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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id 85-v6sm2456868lja.16.2019.02.03.13.42.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 03 Feb 2019 13:42:38 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Tim Harvey , Arnd Bergmann , Olof Johansson , Linus Walleij , Marc Zyngier , Jason Cooper , Thomas Gleixner , devicetree@vger.kernel.org Subject: [PATCH 09/17 v1] irqchip: ixp4xx: Add DT bindings Date: Sun, 3 Feb 2019 22:41:57 +0100 Message-Id: <20190203214205.13594-10-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190203214205.13594-1-linus.walleij@linaro.org> References: <20190203214205.13594-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the IXP4xx interrupt controller. It's a standard 2-cell controller. Cc: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- irqchip maintainers: I am requesting an ACK for this once you're happy with the bindings, as I intend to merge all of this IXP4xx rework through ARM SoC. --- .../intel,ixp4xx-interrupt.txt | 33 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt -- 2.20.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt new file mode 100644 index 000000000000..70ee93b9a6c0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt @@ -0,0 +1,33 @@ +* Intel IXP4xx XScale Networking Processors Interrupt Controller + +This interrupt controller is found in the Intel IXP4xx processors. +Some processors have 32 interrupts, some have up to 64 interrupts. +The exact number of interrupts is determined from the compatible +string. + +The distinct IXP4xx families with different interrupt controller +variations are IXP42x, IXP43x, IXP45x and IXP46x. Those four +families were the only ones to reach the developer and consumer +market. + +Required properties: +- compatible: must be one of + "intel,ixp42x-interrupt" + "intel,ixp43x-interrupt" + "intel,ixp45x-interrupt" + "intel,ixp46x-interrupt" +- reg: The register bank for the interrupt controller. +- interrupt-controller: Identifies the node as an interrupt controller +- #interrupt-cells: The number of cells to define the interrupts. + Must be <2>. The bindings follows the standard binding for controllers + with two cells specified in + interrupt-controller/interrupts.txt + +Example: + +intcon: interrupt-controller@c8003000 { + compatible = "intel,ixp43x-interrupt"; + reg = <0xc8003000 0x100>; + interrupt-controller; + #interrupt-cells = <2>; +}; diff --git a/MAINTAINERS b/MAINTAINERS index a2fb67b75026..ec318f09540c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1650,6 +1650,7 @@ M: Imre Kaloz M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt F: arch/arm/mach-ixp4xx/ F: drivers/clocksource/timer-ixp4xx.c F: drivers/gpio/gpio-ixp4xx.c From patchwork Sun Feb 3 21:41:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 157370 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3199229jaa; Sun, 3 Feb 2019 13:42:47 -0800 (PST) X-Google-Smtp-Source: ALg8bN7ZMCZLsg7fWzWKFuK8w7NCcsKomgHbnqwJMmWqbjUt5VNHF1mMEW4meXFg359LomRZk8aV X-Received: by 2002:a17:902:66e6:: with SMTP id e93mr47698641plk.92.1549230167243; Sun, 03 Feb 2019 13:42:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549230167; cv=none; d=google.com; s=arc-20160816; b=C9GtsiEc/b8E7cBkVAd5o5x1lYvjDo3TK7a/l75LryCYptJ962DVpLAKuPrN07BGoq 4qKTeBoabKll72ZM83hn1W1xauPJ0e6205mkeq1y7+WA25IyMm2BCdTMHDft/ICaHO36 yGsNEweFRy6Z/zYaqivO1f32xixjkmxBpFnHGq73+l7HRb1rJc0v7a1uWOcF9D49kAhj y6rflz3VCutqOFhm/BGZr+ZLL+xZb7shF1WgWc8k9gIL9xPmjGMShPFfsOj5NnXj+zRw zn8M2dBQzwSa1JAMuXblbJZY5iAywNMhjXF2jCxksAucyfbtmxKBMLpMCTqa663pe8G6 vg+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rXBAcdvBpxh0mmOpvAIaV+ZEaPAyDpVqFL3/7RiGnT0=; b=moXl6j//yyy1DRv7JEMIpH1snBT1TGweC5LZ+vpv9Jsx34lMc+1gXJ08NMPPM2yBsq uw5DNESOOBCNNP2dTzd4Nn+6WHBy87GJ8NcA1T+5v6ryGpL66FGh/KZ8wnO6FwAZPra9 RyAi9BSfG46vF+YWdljeW579Wrr2XHon5GLN9fjpZbYkL9dp8Ije/WaS5aJOpeua8Kjt Izi5Uh6n+HehNWM9WV6Gw85Con/PdjoqnezOZXrHvwRagmXZe5MAy9MmokG8wNOR5VUE jcbCDwG0pbt/1pf3arUOlkW1Vqx53pV6AXQEvdB3/IugMHEk0Z4zC+tpwonYkqP/NSrl qxNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YNWH1F0b; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id 85-v6sm2456868lja.16.2019.02.03.13.42.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 03 Feb 2019 13:42:43 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Tim Harvey , Arnd Bergmann , Olof Johansson , Linus Walleij , Daniel Lezcano , Thomas Gleixner , devicetree@vger.kernel.org Subject: [PATCH 11/17 v1] clocksource/drivers/ixp4xx: Add DT bindings Date: Sun, 3 Feb 2019 22:41:59 +0100 Message-Id: <20190203214205.13594-12-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190203214205.13594-1-linus.walleij@linaro.org> References: <20190203214205.13594-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the Intel IXP4xx timers. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- Clocksource/timer maintainers: I am requesting an ACK for this once you're happy with the bindings, as I intend to merge all of this IXP4xx rework through ARM SoC. --- .../bindings/timer/intel,ixp4xx-timer.txt | 18 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.txt -- 2.20.1 Reviewed-by: Rob Herring Acked-by: Daniel Lezcano diff --git a/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.txt b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.txt new file mode 100644 index 000000000000..5b93477bb6ed --- /dev/null +++ b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.txt @@ -0,0 +1,18 @@ +Intel IXP4xx XScale Networking Processors Timers + +This timer is found in the Intel IXP4xx processors. + +Required properties: + +- compatible : Must be + "intel,ixp4xx-timer" +- reg : Should contain registers location and length +- interrupts : Should contain the two timer interrupts + +Example: + +timer@c8005000 { + compatible = "intel,ixp4xx-timer"; + reg = <0xc8005000 0x100>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/MAINTAINERS b/MAINTAINERS index ec318f09540c..775a623dc91d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1651,6 +1651,7 @@ M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt +F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.txt F: arch/arm/mach-ixp4xx/ F: drivers/clocksource/timer-ixp4xx.c F: drivers/gpio/gpio-ixp4xx.c From patchwork Sun Feb 3 21:42:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 157371 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3199262jaa; Sun, 3 Feb 2019 13:42:51 -0800 (PST) X-Google-Smtp-Source: ALg8bN5RhsfkA3SubYb0Xc18aBqupOFJhgI1kDHTkOoxV7Hyzk2PUWAsB6Fz8kf6Qw9b0HofKlG0 X-Received: by 2002:a17:902:28e9:: with SMTP id f96mr49191467plb.169.1549230171242; Sun, 03 Feb 2019 13:42:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549230171; cv=none; d=google.com; s=arc-20160816; b=NUt6WPeg6NXawYOys5LXbrqft9iSUUCZDQXW+rmOwMA6qVKT+fddpC2uXu/0I9KCA6 /rSRopMB8Z8a8VLYGSYutzbZXkTVNEf/c6rk0Vi3qbEEQsY03599avuma/aqCEH90WEL sAz0jOolaCp9/jnQKxK2Rjx0r0brknIK5wbgfi0s3PGwcp3HUHqbuDHY8ivHyFxSW99q SiAZgRRfOgD/jpID4Si6RGGL4DUrduhCPurxjnaZLCBm4c2fjEkU/MCweWdqaSGatXBj m89RZbPYIUGlhrMsBUxIxbmHmQmpr4WsMyUqEBIIQ3iplsJ0dLj+6DTXA+U/evozUHeR EJEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tqkowpPvCE0gZkM+u8f2imx7BQRKOcq+GoRfFNueR54=; b=QCCZlEi5XaF2f9+3SnGlrGCyFektwDM6GFvkCxsWw5xrCXRf9kN2gQrZH+VYK7skZk 0yeNJEwvtsd5xqdksn6BQXFpG3WdWNLBHblFO7V0HS6TlZrbZbrSkYDuEeeHuePK1uV9 q6g3kiKwL+SX1JaCaYR+lJnQBsPvQBNJF04R/5H+Xiul/maHnwNicWhNJrvgH23BJixi b51/GnZuqH3zO3u/yUwL6l7kRk8HqTlu15QZLpf0boDyntgmIi93Z0eoQPA7tDt9Bc2Q LMz8QnXsgFMDfq4laUXXCZEV99rYO7cEbSzamfFZU2+ikMrcSyKOY72GwmVLxc4S79r6 Y2wQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IJwvs9MO; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id 85-v6sm2456868lja.16.2019.02.03.13.42.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 03 Feb 2019 13:42:47 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Tim Harvey , Arnd Bergmann , Olof Johansson , Linus Walleij , Bartosz Golaszewski , devicetree@vger.kernel.org Subject: [PATCH 13/17 v1] gpio: ixp4xx: Add DT bindings Date: Sun, 3 Feb 2019 22:42:01 +0100 Message-Id: <20190203214205.13594-14-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190203214205.13594-1-linus.walleij@linaro.org> References: <20190203214205.13594-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds DT bindings for the IXP4xx GPIO controller. Cc: Bartosz Golaszewski Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- Bartosz: looking for your ACK on this, it'd be good if the other GPIO maintainer is aligned with my ideas here. I intend to merge this through the ARM SoC tree. --- .../bindings/gpio/intel,ixp4xx-gpio.txt | 38 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt -- 2.20.1 Reviewed-by: Bartosz Golaszewski Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt new file mode 100644 index 000000000000..8dc41ed99685 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt @@ -0,0 +1,38 @@ +Intel IXP4xx XScale Networking Processors GPIO + +This GPIO controller is found in the Intel IXP4xx processors. +It supports 16 GPIO lines. + +The interrupt portions of the GPIO controller is hierarchical: +the synchronous edge detector is part of the GPIO block, but the +actual enabling/disabling of the interrupt line is done in the +main IXP4xx interrupt controller which has a 1:1 mapping for +the first 12 GPIO lines to 12 system interrupts. + +The remaining 4 GPIO lines can not be used for receiving +interrupts. + +The interrupt parent of this GPIO controller must be the +IXP4xx interrupt controller. + +Required properties: + +- compatible : Should be + "intel,ixp4xx-gpio" +- reg : Should contain registers location and length +- gpio-controller : marks this as a GPIO controller +- #gpio-cells : Should be 2, see gpio/gpio.txt +- interrupt-controller : marks this as an interrupt controller +- #interrupt-cells : a standard two-cell interrupt, see + interrupt-controller/interrupts.txt + +Example: + +gpio0: gpio@c8004000 { + compatible = "intel,ixp4xx-gpio"; + reg = <0xc8004000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +}; diff --git a/MAINTAINERS b/MAINTAINERS index 775a623dc91d..57d098b85523 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1650,6 +1650,7 @@ M: Imre Kaloz M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.txt F: arch/arm/mach-ixp4xx/ From patchwork Sun Feb 3 21:42:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 157372 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3199311jaa; Sun, 3 Feb 2019 13:42:55 -0800 (PST) X-Google-Smtp-Source: AHgI3IYSIDPTBQ4vxO53j9Cc2JKsLTw/Txnc05dKMpqa/giD3KiEogXzxq0YD612MsgAmBo+Agd/ X-Received: by 2002:a63:2ac9:: with SMTP id q192mr10601323pgq.58.1549230175643; Sun, 03 Feb 2019 13:42:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549230175; cv=none; d=google.com; s=arc-20160816; b=T+PmjDta09/aDYf6dDMR6vuc+BlNaQURi3/HsfcHbzN5siXWwqc3IBkvQdmd5ODC0c xqJfRFBTyUxLOAglkKVkb7t520Nf4pPg7bMyEvgXf53mTAsJXqe0tM34ppmnRyTix9C7 USNM/vFmSqVJ0xO1GVlt/t5UCbFJOYOqwrn0EfHig3mGGTBDCCr3G8GotmRANwWHGiKA oixhZs8cZZUA+RY6zWPjpxDxS+NJdo4Hh87+EMVeHssjDC0Ryg9mgVAk8QnPUjr0k/Bb EbImB2yfTh639kLQHCZ7UM9yjXm49KgT+YxVNzX9itbDFmm3Br7yfvjHbyDPJ1aZoXyB AeHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZXVoeReBcA5qhCvRDJOIchocuRkU673IoSvxfhcDnRc=; b=LkLp0rjShWaRs4u1Jz8CeW3N4c0hMXtKeRHbxxeFb+YCaGbVEwxRLKr5TQw4t/5cMp sa6yUfnpEk7ilayMPuFXklRhDFvGQAqBF7z2etFvBluQjvBJZ6j439VVlE2j5ZlxOhe3 Rh6E9ghUYXmj2dU+5p2UuNA4VMZc/367dnmmwb9WEv8AW0BI35DFzR1BeAtjymljAc1o Q8JG9uZj0snA96AUy/vXg4laqibR+YKaAMBPflC5v7yLhMtwgimbjF3UNVjf3lXEnt7L 5eeR+mTqL5Tnhq9h2fmMWejkRhA9PnnBt2CGlRQeCMvG7gKqYC7AfsxImoxmLe3KbY3h qubA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ECxyQy0x; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id 85-v6sm2456868lja.16.2019.02.03.13.42.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 03 Feb 2019 13:42:51 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Tim Harvey , Arnd Bergmann , Olof Johansson , Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 15/17 v1] ARM: ixp4xx: Add DT bindings Date: Sun, 3 Feb 2019 22:42:03 +0100 Message-Id: <20190203214205.13594-16-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190203214205.13594-1-linus.walleij@linaro.org> References: <20190203214205.13594-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds initial device tree bindings for the IXP4xx machines. This time I tried something wild and crazy and try to make proper JSON-style YAML bindings for the top level. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- I have no clear idea on how to auto-test this schema for validity, since it is a bit of a new thing I hope to figure it out as we go. --- .../devicetree/bindings/arm/intel-ixp4xx.yaml | 22 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml -- 2.20.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml new file mode 100644 index 000000000000..da5f6ffe6f2d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/intel-ixp4xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel IXP4xx Device Tree Bindings + +maintainers: + - Linus Walleij + +properties: + compatible: + oneOf: + - items: + - enum: + - linksys,nslu2 + - const: intel,ixp42x + - items: + - enum: + - gateworks,gw2358-4 + - const: intel,ixp43x diff --git a/MAINTAINERS b/MAINTAINERS index 57d098b85523..c4ca249a2075 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1650,6 +1650,7 @@ M: Imre Kaloz M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.txt