From patchwork Thu Aug 11 20:33:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 596713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 252ACC25B06 for ; Thu, 11 Aug 2022 20:33:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235943AbiHKUd1 (ORCPT ); Thu, 11 Aug 2022 16:33:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235691AbiHKUdY (ORCPT ); Thu, 11 Aug 2022 16:33:24 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68EAA9F0F8 for ; Thu, 11 Aug 2022 13:33:18 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id c187-20020a1c35c4000000b003a30d88fe8eso3269977wma.2 for ; Thu, 11 Aug 2022 13:33:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=44JZfQo8qBDZMgfCdrZJwZLuiR284QlmRSCfMxTvtpo=; b=Rg+2K2aUJR5EC4EzeEhjweVggh3LGAxXDW+n+myh6+YEfAOfixSRbOplNLuQc+hbCh k+KeOqNm6R7kogF4zChBu0vPRB6/t4pC7dpmsahLZa0MR1bkVO2XWKiYhLL+J8YqQUDk ZtKBGxLruXNAffh3BmuL+H6PQwULOjdofcVTtJDehPnCkEwCuYwFQvxMN+8on0EzLv0W 8hG4NzCnIC7nauXERnsjmeIsK9LpEBmZMluKZGrodeAYGFQJLpKQqnVMGITSegeShwjt CAS9qdr1VnbdcCuBIY3JiurrcquUlr5/UocbOVp2P97KWNRvHxATlrQBQ9jfvz51J/Lu zNfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=44JZfQo8qBDZMgfCdrZJwZLuiR284QlmRSCfMxTvtpo=; b=74Is6d9tHiXqBxk8nSHGipTDfNJofGdb9/yIQoQek4Wcj5ywXGuWt5394tPDDiQN2W Vn9ERe5w+Ofl1wBpkGupBiVlnqAK+22HmVgUzfRuQHJDR7+P7r0H8DEuNkmaCRVqNRw5 f3/PvdFBDfL6nTtHhAC2osTcgLVKyaDVh1U8kck+/gpi4Mxqx59oodvVy2Z9VazzR6SF V/XGioiacsE8/rriJgN5rNGKMH4ha5uiNqB5OwbdMwMArfvYROqauxEphOzQMAGm4VDt hGAx85h3Q4JLCb8hlBYencCzHG0VybFPam4NB7bZx9V3kOuoZJ/JbOQh9JUcW0HWCh9I JaiQ== X-Gm-Message-State: ACgBeo1lpHzwl2yRT7pHPNCxEZGeCy7PQxEgWqVqzDx3sdTEaXGobsXs Og9SfXyFEZ52PeQE/Et5CVW3TQ== X-Google-Smtp-Source: AA6agR5N8mHJgZv+snXP8haUdkqppQ+4312cBLsCj598n23ICeGirf1H5+hFJyDA92da/FyY+BkSUQ== X-Received: by 2002:a05:600c:3845:b0:3a3:19e8:829e with SMTP id s5-20020a05600c384500b003a319e8829emr6647580wmr.11.1660249996798; Thu, 11 Aug 2022 13:33:16 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id i12-20020adfefcc000000b0021f1ec8776fsm86643wrp.61.2022.08.11.13.33.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Aug 2022 13:33:16 -0700 (PDT) From: Conor Dooley To: Daire McNamara , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Greentime Hu , Palmer Dabbelt , Albert Ou , Lorenzo Pieralisi , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 1/4] dt-bindings: PCI: fu740-pci: fix missing clock-names Date: Thu, 11 Aug 2022 21:33:04 +0100 Message-Id: <20220811203306.179744-2-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220811203306.179744-1-mail@conchuod.ie> References: <20220811203306.179744-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley The commit in the fixes tag removed the clock-names property from the SiFive FU740 PCI Controller dt-binding, but it was already in the dts for the FU740. dtbs_check was not able to pick up on this at the time but v2022.08 of dt-schema now can: arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dtb: pcie@e00000000: Unevaluated properties are not allowed ('clock-names' was unexpected) From schema: linux/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml The Linux driver does not use this property, but outside of the kernel this property may have users. Re-add the property and its "clocks" dependency. Fixes: b92225b034c0 ("dt-bindings: PCI: designware: Fix 'unevaluatedProperties' warnings") Signed-off-by: Conor Dooley --- I went back and forth on removing the property from the dts, but this seems like the change that is more conservative.. --- .../devicetree/bindings/pci/sifive,fu740-pcie.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml index 195e6afeb169..c7a9a2dc0fa6 100644 --- a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml @@ -51,6 +51,12 @@ properties: description: A phandle to the PCIe power up reset line. maxItems: 1 + clocks: + maxItems: 1 + + clock-names: + const: pcie_aux + pwren-gpios: description: Should specify the GPIO for controlling the PCI bus device power on. maxItems: 1 From patchwork Thu Aug 11 20:33:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 596712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA8BFC25B0F for ; Thu, 11 Aug 2022 20:33:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235363AbiHKUd3 (ORCPT ); Thu, 11 Aug 2022 16:33:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235878AbiHKUd0 (ORCPT ); Thu, 11 Aug 2022 16:33:26 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1DBB9F18E for ; Thu, 11 Aug 2022 13:33:21 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id bs25so4100918wrb.2 for ; Thu, 11 Aug 2022 13:33:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=ClSH5MXXgUZguA19Coz32EYS83xElJy9jIFIyLAmeC4=; b=HHhe+yarKbkwIYZ1mXaOthZ0VXyo310D1cBk8s8PGKXtS+FAnYRo1gNG6ylVj/7gLo BD1+qLMXw3jHjaKmycrt6e1OAv4CCWriwslsnWnsihoR/ceQgpKaw/ZZ6agol8h0tpdV l02Ole49suUd2QEsa7+uNZY+ANEboqWovjQ41L3onQLVlcUDQTarQNGtsJLt8FArM1MM H2MDT+rXQSH4wqI56vlK6Bwt19CVBV2XqoaYwT8ClmSccYovi+z7rS+pap22DWMy7KMA jJBA8lhBOgEw9qEA4SepES7pXBFrOAfewHEorcKXkVi7YaO9c1U7I4skrO+n+EWweBdU rtFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=ClSH5MXXgUZguA19Coz32EYS83xElJy9jIFIyLAmeC4=; b=7kcIBRaI+zwEFCVLioFhLCNykUkg2ESDqH6r1t630f1b7okCrdqwZUY6aZEnn6UQcb JQ8pZBJpeFY8RQptAE4jH78aLglcqthH6zj6zQXICxj6HQMdOTLiHpZfqif0sUyD/YU+ OPFpgnRLDlFiFQFW/NQN9qY3ENsfCMpM0opcqkAU7FzmCRhkBXrsPH7tSOGcGXWB4Tv/ Khx/9Gkg160vp2yHZioUtDVvXGYuayEh8JSu8FVDFDSowuFrAI8tFLV51uvhA7ZwidDP KFCDwDHZLvmshVq2W2yMpFdAoy82RlE3/cvO7k0USWnjyyIkEBNENSWFkxI9d4+WsrV7 KNbQ== X-Gm-Message-State: ACgBeo2OVS23PtZ93U0skzTJqluXyNYemvGSNj5sjXfBXdMrLLTSIDKq kHT4gQt2uRXl6dF0PMkKOynstA== X-Google-Smtp-Source: AA6agR4uUqIg2eHjtpt4HwLt+LlA2AAP/WjAN+bsQ7P2wHGzFMVwBV3+ZG92fs39ZgDOkKMy3JKrZg== X-Received: by 2002:a5d:4345:0:b0:21a:3b82:ad57 with SMTP id u5-20020a5d4345000000b0021a3b82ad57mr361149wrr.176.1660250000231; Thu, 11 Aug 2022 13:33:20 -0700 (PDT) Received: from henark71.. ([109.76.58.63]) by smtp.gmail.com with ESMTPSA id i12-20020adfefcc000000b0021f1ec8776fsm86643wrp.61.2022.08.11.13.33.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Aug 2022 13:33:19 -0700 (PDT) From: Conor Dooley To: Daire McNamara , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Greentime Hu , Palmer Dabbelt , Albert Ou , Lorenzo Pieralisi , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 4/4] dt-bindings: PCI: microchip,pcie-host: fix missing address translation property Date: Thu, 11 Aug 2022 21:33:07 +0100 Message-Id: <20220811203306.179744-5-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220811203306.179744-1-mail@conchuod.ie> References: <20220811203306.179744-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley When the PCI controller node was added to the PolarFire SoC dtsi, dt-schema was not able to detect the presence of some undocumented properties due to how it handled unevaluatedProperties. v2022.08 introduces better validation, producing the following error: arch/riscv/boot/dts/microchip/mpfs-polarberry.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'microchip,axi-m-atr0' were unexpected) From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Signed-off-by: Conor Dooley --- I feel like there's a pretty good chance that this is not the way this should have been done and the property should be marked as deprecated but I don't know enough about PCI to answer that. --- .../devicetree/bindings/pci/microchip,pcie-host.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index 9b123bcd034c..9ac34b33c4b2 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -71,6 +71,17 @@ properties: msi-parent: description: MSI controller the device is capable of using. + microchip,axi-m-atr0: + description: | + Depending on the FPGA bitstream, the AXIM address translation table in the + PCIe controllers bridge layer may need to be configured. Use this property + to set the address offset. For more information, see Section 1.3.3, + "PCIe/AXI4 Address Translation" of the PolarFire SoC PCIe User Guide: + https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 2 + maxItems: 2 + legacy-interrupt-controller: type: object properties: