From patchwork Sat Feb 2 09:43:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 157340 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1522544jaa; Sat, 2 Feb 2019 01:59:43 -0800 (PST) X-Google-Smtp-Source: ALg8bN6Y/5tdLwscrQyLWmnPWiC7x7G8/TcFmfPzjQ3HIxegYLv1KVxR0s/dGCvReFN2HskedLfO X-Received: by 2002:a81:2bc2:: with SMTP id r185mr39218118ywr.425.1549101583894; Sat, 02 Feb 2019 01:59:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549101583; cv=none; d=google.com; s=arc-20160816; b=Rf1bW9xS9bmxhJCCK/UiMq12KYiDdwaXLWwwMn/6Dzd+rrlWFJ+fFdR4ZDRZg26yV6 Fy16sa3WacpI2JNOEUwAkN6lxR3H/7HLgDk1EwWMrUEpSTNb9t9Q0uQ4Egj1kqpApf7X abDdmarK/IYKvO7QTApanynXZibeM/OskjpBfP6OpGz2LqPdmVJzzVgb5x+JIPembEMx Fw2D9sEygbtMkKWJ/1Npvgeo4EATuI5k1sf5nQDcQ4hAgzvHBsHjN8OnrL4h1K1/KBJ+ a0mvk1qede9p/hUXnwgN2ofQifwmdrWSgZofoKQv4rvxikPKjdJhMud2rBBllz/fpYC0 hX1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:to:from:references :in-reply-to:message-id:date:dkim-signature; bh=z6Oe5++7//00+8jf3KOesDxKK2wIxkTBsez1SGK1Kro=; b=Bu5xkHTYmA/D/BGuLV98P/atRcUA6LlHuA3s5TtOZIyvtuyQ9pJfuYintO2wK/DIME ha8gCGa9AetahEXwGyM+Gkley9JBIur+XgydDBU+Tkp7I4HlXX3DvL4hf7sSTEIQYiww 6cIEacOExKyUAh82Tq52jLwSvU28y8o3XqTacmmW4dYPwDt4mEf1OHhThDYtoaGCMG4K iDRgiN27UJaaLOHkkxVblC92NUHe+deOV5boSUkhFEwn3/g09QcN7m19LNCpD/IQY+bv WQSplJZJFPx/3bHcLzT71lIEsens5BmPi2O9TsvmiGQ9u/aDtE3PhbsAnqtChyHWsRT4 3+aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@sifive.com header.s=google header.b=X3l6yNuV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c15si489451ybs.240.2019.02.02.01.59.43 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 02 Feb 2019 01:59:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@sifive.com header.s=google header.b=X3l6yNuV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([127.0.0.1]:40107 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gps5P-0003ZB-F8 for patch@linaro.org; Sat, 02 Feb 2019 04:59:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:55118) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gprzA-000700-JK for qemu-devel@nongnu.org; Sat, 02 Feb 2019 04:53:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gprqD-0005oe-SK for qemu-devel@nongnu.org; Sat, 02 Feb 2019 04:44:03 -0500 Received: from mail-ed1-x541.google.com ([2a00:1450:4864:20::541]:37757) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gprqB-0005Om-Qm for qemu-devel@nongnu.org; Sat, 02 Feb 2019 04:44:00 -0500 Received: by mail-ed1-x541.google.com with SMTP id h15so7475723edb.4 for ; Sat, 02 Feb 2019 01:43:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=z6Oe5++7//00+8jf3KOesDxKK2wIxkTBsez1SGK1Kro=; b=X3l6yNuVoZXHJK+7TqH95EvGY2YZYrcVyI2b1E/ulY6ZzV0JK2tltEwyR+GYWu5L0g l94/Wkg/AovsssjRAbqXZV6mTqn93w2RP62KB+gbeK7uaMX70qKzUHQds7yrKn6HhXji zPQdDWyv3OsZEXRGeZLbXTKixRQ+Qh3FJ2gQUXvRBX/P/O3k2wMzDQy/rdywJanaEC3a DAukFNt8PZoT/ZEjkg48G4oXPn9tsGAbxeCJbsk3RZ2nJaMa6+hccS5PGP4Q66vNbI4g anZsoxrG1WZpsBCLWIuc6s5I9hLwEPrRsp4bAYmoHF+YgxoPhWy/eUFhorQtypE2s9Uu LydQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=z6Oe5++7//00+8jf3KOesDxKK2wIxkTBsez1SGK1Kro=; b=eByi2Sa+YmNKr51+dMqnM05Vb8JUwk+F9uJ2uLjQmW3lZtNgjr9Lz1cguyW7Z9iVBr aIMu/LqZx0byXAeOs1x193akxOI4MXwJJpKXLO/NwOI9mJcXYbrfWuS1rl3CUoEdoXto B9vJhiPxqwLZwQVnVCRRdj1S+tw8B8tG/4iDGRakmgCHP9xk4oNTWWJE9tlEaS7rFNzO l4+W/VRzf2fc883BHVI7/bzCWGGlwyVVQoFzp3jy2UBZvbPqdwQ4OlniDydNBs7BC8If sB0pjYvRWGRJ2iCduiPx9tJqVeGfwsV3rat7K3xVKIfwJ2DmmGwhTVUMR76v+MKhfKVD ff8g== X-Gm-Message-State: AJcUukfmxLB+HcfEwAa2MBTqcMnhPLxA/R0IyHJaK6D/1FXGwHPRgCZf njxh9O/jIWrYMfQ5K4IVTYrscg== X-Received: by 2002:a50:8b26:: with SMTP id l35mr40908322edl.146.1549100619219; Sat, 02 Feb 2019 01:43:39 -0800 (PST) Received: from localhost ([2001:67c:1810:f051:fd32:55e2:f60b:183b]) by smtp.gmail.com with ESMTPSA id c30sm2665260edc.70.2019.02.02.01.43.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 02 Feb 2019 01:43:38 -0800 (PST) Date: Sat, 2 Feb 2019 01:43:20 -0800 Message-Id: <20190202094329.22874-2-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20190202094329.22874-1-palmer@sifive.com> References: <20190202094329.22874-1-palmer@sifive.com> From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::541 Subject: [Qemu-devel] [PULL 01/10] RISC-V: Split out mstatus_fs from tb_flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Richard Henderson , qemu-devel@nongnu.org, Michael Clark , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Michael Clark Reviewed-by: Michael Clark Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 6 +++--- target/riscv/translate.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) -- 2.18.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 743f02c8b95a..681341f5d5a4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -275,8 +275,8 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env, target_ulong cpu_riscv_get_fflags(CPURISCVState *env); void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong); -#define TB_FLAGS_MMU_MASK 3 -#define TB_FLAGS_FP_ENABLE MSTATUS_FS +#define TB_FLAGS_MMU_MASK 3 +#define TB_FLAGS_MSTATUS_FS MSTATUS_FS static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) @@ -284,7 +284,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; #ifdef CONFIG_USER_ONLY - *flags = TB_FLAGS_FP_ENABLE; + *flags = TB_FLAGS_MSTATUS_FS; #else *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 312bf298b3c2..3d07d651b60c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -44,7 +44,7 @@ typedef struct DisasContext { /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; uint32_t opcode; - uint32_t flags; + uint32_t mstatus_fs; uint32_t mem_idx; /* Remember the rounding mode encoded in the previous fp instruction, which we have already installed into env->fp_status. Or -1 for @@ -656,7 +656,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, { TCGv t0; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { gen_exception_illegal(ctx); return; } @@ -686,7 +686,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, { TCGv t0; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { gen_exception_illegal(ctx); return; } @@ -945,7 +945,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, { TCGv t0 = NULL; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { goto do_illegal; } @@ -1818,8 +1818,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) DisasContext *ctx = container_of(dcbase, DisasContext, base); ctx->pc_succ_insn = ctx->base.pc_first; - ctx->flags = ctx->base.tb->flags; ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; + ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; ctx->frm = -1; /* unknown rounding mode */ } From patchwork Sat Feb 2 09:43:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 157339 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1520559jaa; Sat, 2 Feb 2019 01:56:31 -0800 (PST) X-Google-Smtp-Source: ALg8bN4WQyvint17tsZE0mbQfedIxf8hDNEz5bIudviVUqp3l5F7yn869+RyodAJa73WxQOeURTo X-Received: by 2002:a25:258c:: with SMTP id l134mr32655116ybl.65.1549101391154; Sat, 02 Feb 2019 01:56:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549101391; cv=none; d=google.com; s=arc-20160816; b=cp8SEXeFIiqvbkUsz6E0ImPOokMvmC1O3p9ct4uQ1yZLRB6szY+njF+zxJQORlsAmN KI6UxJQN3igNhy/CFCFU/Cc7jH5DmxVuzC+Uhmjzl+vjtE8+KkkUro0Et5WclwBWnveL kdLX04NJBkD1ex2g1QjI8YNZ/tQdQfOmK5y/1VEI+MNwES6z3jW3pPxCvWTFN4l3yyw6 OyOmW62XqwbPCWcy4w1v6oHCM+qWps4iDw1NOyy0JCeE1DaW8HT6bSd5aEfck00+sw0C fLY6J/ys317cCv+eIXPqzZOu/iy+//t6tfmuTdGrc7eoZW9YKiORlgc7d1ArJ5Rk71w5 KpXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:to:from:references :in-reply-to:message-id:date:dkim-signature; bh=m3QyX5GKKen9C2A//gm0itW+Zbw+s4kREoS0dubIg4I=; b=jyDKtAF8l0QqQoJZyPyqSCFsQL+dcLsnyoY2sR9LYTpUE8IUjNogH18Dl+ijx8WFO1 DtD4ktbvh7jtszPyB41jhIhQ48/fFNeAS4arXHDssNKPYW5ZYx9IpxqnOrcNy1yStsd0 jkabFIqnF4NSPGA6EKZJp3r/VrPsi+cx90z9HD48QG2xslPVU0ACceP7IVvN7SdM2IvV m+dRgvbFP9Uv9DzP1brfiSagiXCVOfKbpAkVmVe4TnxGCv6cKLS/GVKJMpuhbstAiBWP 9JjL3rpSPJUQcZWCHLJczMgje6EtdJN+MycEIUyE934oymjGTYacAVCBgSOuzJj4WTB+ GUZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@sifive.com header.s=google header.b="g9s7/vk/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::52b Subject: [Qemu-devel] [PULL 02/10] RISC-V: Mark mstatus.fs dirty X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Richard Henderson , qemu-devel@nongnu.org, Michael Clark , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Modifed from Richard Henderson's patch [1] to integrate with the new control and status register implementation. [1] https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg07034.html Note: the f* CSRs already mark mstatus.FS dirty using env->mstatus |= mstatus.FS so the bug in the first spin of this patch has been fixed in a prior commit. Signed-off-by: Michael Clark Reviewed-by: Michael Clark Signed-off-by: Alistair Francis Co-authored-by: Richard Henderson Co-authored-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 12 ------------ target/riscv/translate.c | 40 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 39 insertions(+), 13 deletions(-) -- 2.18.1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5e7e7d16b8b5..571414768992 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -317,18 +317,6 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) mstatus = (mstatus & ~mask) | (val & mask); - /* Note: this is a workaround for an issue where mstatus.FS - does not report dirty after floating point operations - that modify floating point state. This workaround is - technically compliant with the RISC-V Privileged - specification as it is legal to return only off, or dirty. - at the expense of extra floating point save/restore. */ - - /* FP is always dirty or off */ - if (mstatus & MSTATUS_FS) { - mstatus |= MSTATUS_FS; - } - int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | ((mstatus & MSTATUS_XS) == MSTATUS_XS); mstatus = set_field(mstatus, MSTATUS_SD, dirty); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3d07d651b60c..0581b3c1f7d7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -651,6 +651,31 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, tcg_temp_free(dat); } +#ifndef CONFIG_USER_ONLY +/* The states of mstatus_fs are: + * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty + * We will have already diagnosed disabled state, + * and need to turn initial/clean into dirty. + */ +static void mark_fs_dirty(DisasContext *ctx) +{ + TCGv tmp; + if (ctx->mstatus_fs == MSTATUS_FS) { + return; + } + /* Remember the state change for the rest of the TB. */ + ctx->mstatus_fs = MSTATUS_FS; + + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_temp_free(tmp); +} +#else +static inline void mark_fs_dirty(DisasContext *ctx) { } +#endif + static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, target_long imm) { @@ -679,6 +704,8 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, break; } tcg_temp_free(t0); + + mark_fs_dirty(ctx); } static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, @@ -944,6 +971,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1, int rs2, int rm) { TCGv t0 = NULL; + bool fp_output = true; if (ctx->mstatus_fs == 0) { goto do_illegal; @@ -1006,6 +1034,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_W_S: @@ -1035,6 +1064,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_S_W: @@ -1085,6 +1115,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FMV_S_X: @@ -1177,6 +1208,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_W_D: @@ -1206,6 +1238,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_D_W: @@ -1254,6 +1287,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, default: goto do_illegal; } + fp_output = false; break; #if defined(TARGET_RISCV64) @@ -1271,7 +1305,11 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, tcg_temp_free(t0); } gen_exception_illegal(ctx); - break; + return; + } + + if (fp_output) { + mark_fs_dirty(ctx); } }