From patchwork Tue Aug 2 23:54:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 595043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DEDAC19F2C for ; Tue, 2 Aug 2022 23:54:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235224AbiHBXyx (ORCPT ); Tue, 2 Aug 2022 19:54:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230419AbiHBXyv (ORCPT ); Tue, 2 Aug 2022 19:54:51 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCEB354668; Tue, 2 Aug 2022 16:54:45 -0700 (PDT) X-UUID: 94132bb4d78e43dcbdb1e09a97947496-20220803 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8, REQID:6133c66f-c518-463d-8249-c9328db26a11, OB:0, LO B:10,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:90 X-CID-INFO: VERSION:1.1.8, REQID:6133c66f-c518-463d-8249-c9328db26a11, OB:0, LOB: 10,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:90 X-CID-META: VersionHash:0f94e32, CLOUDID:5c7e1525-a982-4824-82d2-9da3b6056c2a, C OID:050c4078ae47,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 94132bb4d78e43dcbdb1e09a97947496-20220803 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 666857770; Wed, 03 Aug 2022 07:54:42 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 3 Aug 2022 07:54:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 3 Aug 2022 07:54:39 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v5 1/5] scsi: ufs: ufs-mediatek: Remove redundant header files Date: Wed, 3 Aug 2022 07:54:33 +0800 Message-ID: <20220802235437.4547-2-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220802235437.4547-1-stanley.chu@mediatek.com> References: <20220802235437.4547-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Remove redundant header files like Reviewed-by: Bart Van Assche Signed-off-by: Stanley Chu --- drivers/ufs/host/ufs-mediatek.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index c958279bdd8f..ff6fd8f52ebc 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include From patchwork Tue Aug 2 23:54:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 595262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E3A2C19F2B for ; Tue, 2 Aug 2022 23:54:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235284AbiHBXyz (ORCPT ); Tue, 2 Aug 2022 19:54:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231809AbiHBXyv (ORCPT ); Tue, 2 Aug 2022 19:54:51 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1512E54ACD; Tue, 2 Aug 2022 16:54:47 -0700 (PDT) X-UUID: 194c7dff39d041a288cc0765fd2d8e65-20220803 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8, REQID:ede3b625-47fb-4ede-9176-80ed97192ff9, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:90 X-CID-INFO: VERSION:1.1.8, REQID:ede3b625-47fb-4ede-9176-80ed97192ff9, OB:0, LOB: 0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:90 X-CID-META: VersionHash:0f94e32, CLOUDID:fddd1bd0-a6cf-4fb6-be1b-c60094821ca2, C OID:824bbe3a5a70,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 194c7dff39d041a288cc0765fd2d8e65-20220803 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 965615560; Wed, 03 Aug 2022 07:54:43 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 3 Aug 2022 07:54:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 3 Aug 2022 07:54:41 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v5 2/5] scsi: ufs: ufs-mediatek: Provide detailed description for UIC errors Date: Wed, 3 Aug 2022 07:54:34 +0800 Message-ID: <20220802235437.4547-3-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220802235437.4547-1-stanley.chu@mediatek.com> References: <20220802235437.4547-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Provide detailed description in logs for UIC errors for eaiser issue breakdown. Signed-off-by: Stanley Chu --- drivers/ufs/host/ufs-mediatek.c | 58 +++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index ff6fd8f52ebc..62bc3b791b38 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -46,6 +46,44 @@ static const struct of_device_id ufs_mtk_of_match[] = { {}, }; +/* + * Details of UIC Errors + */ +static const char *const ufs_uic_err_str[] = { + "PHY Adapter Layer", + "Data Link Layer", + "Network Link Layer", + "Transport Link Layer", + "DME" +}; + +static const char *const ufs_uic_pa_err_str[] = { + "PHY error on Lane 0", + "PHY error on Lane 1", + "PHY error on Lane 2", + "PHY error on Lane 3", + "Generic PHY Adapter Error. This should be the LINERESET indication" +}; + +static const char *const ufs_uic_dl_err_str[] = { + "NAC_RECEIVED", + "TCx_REPLAY_TIMER_EXPIRED", + "AFCx_REQUEST_TIMER_EXPIRED", + "FCx_PROTECTION_TIMER_EXPIRED", + "CRC_ERROR", + "RX_BUFFER_OVERFLOW", + "MAX_FRAME_LENGTH_EXCEEDED", + "WRONG_SEQUENCE_NUMBER", + "AFC_FRAME_SYNTAX_ERROR", + "NAC_FRAME_SYNTAX_ERROR", + "EOF_SYNTAX_ERROR", + "FRAME_SYNTAX_ERROR", + "BAD_CTRL_SYMBOL_TYPE", + "PA_INIT_ERROR", + "PA_ERROR_IND_RECEIVED", + "PA_INIT" +}; + static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba) { struct ufs_mtk_host *host = ufshcd_get_variant(hba); @@ -1309,8 +1347,28 @@ static void ufs_mtk_event_notify(struct ufs_hba *hba, enum ufs_event_type evt, void *data) { unsigned int val = *(u32 *)data; + unsigned long reg; + u8 bit; trace_ufs_mtk_event(evt, val); + + /* Print details of UIC Errors */ + if (evt <= UFS_EVT_DME_ERR) { + dev_info(hba->dev, + "Host UIC Error Code (%s): %08x\n", + ufs_uic_err_str[evt], val); + reg = val; + } + + if (evt == UFS_EVT_PA_ERR) { + for_each_set_bit(bit, ®, ARRAY_SIZE(ufs_uic_pa_err_str)) + dev_info(hba->dev, "%s\n", ufs_uic_pa_err_str[bit]); + } + + if (evt == UFS_EVT_DL_ERR) { + for_each_set_bit(bit, ®, ARRAY_SIZE(ufs_uic_dl_err_str)) + dev_info(hba->dev, "%s\n", ufs_uic_dl_err_str[bit]); + } } /* From patchwork Tue Aug 2 23:54:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 595261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24D92C00140 for ; Tue, 2 Aug 2022 23:55:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235320AbiHBXy6 (ORCPT ); Tue, 2 Aug 2022 19:54:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235212AbiHBXyw (ORCPT ); Tue, 2 Aug 2022 19:54:52 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFB2F54AEA; Tue, 2 Aug 2022 16:54:50 -0700 (PDT) X-UUID: 07e877c5255b4ac6a3534e91f86e10b4-20220803 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8, REQID:2ace3830-5186-4754-a8da-6a041981e114, OB:0, LO B:10,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.8, REQID:2ace3830-5186-4754-a8da-6a041981e114, OB:0, LOB: 10,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:0f94e32, CLOUDID:37de1bd0-a6cf-4fb6-be1b-c60094821ca2, C OID:71f19a01ffe0,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 07e877c5255b4ac6a3534e91f86e10b4-20220803 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1196140242; Wed, 03 Aug 2022 07:54:46 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 3 Aug 2022 07:54:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 3 Aug 2022 07:54:41 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v5 3/5] scsi: ufs: ufs-mediatek: Dump more registers Date: Wed, 3 Aug 2022 07:54:35 +0800 Message-ID: <20220802235437.4547-4-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220802235437.4547-1-stanley.chu@mediatek.com> References: <20220802235437.4547-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Peter Wang Dump more proprietary UFSHCI status registers for easier issue breakdown. Reviewed-by: Stanley Chu Signed-off-by: Peter Wang Signed-off-by: Stanley Chu --- drivers/ufs/host/ufs-mediatek.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index 62bc3b791b38..2b85d2406714 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -1284,13 +1284,16 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba) { - ufshcd_dump_regs(hba, REG_UFS_REFCLK_CTRL, 0x4, "Ref-Clk Ctrl "); + /* Dump ufshci register 0x140 ~ 0x14C */ + ufshcd_dump_regs(hba, REG_UFS_XOUFS_CTRL, 0x10, + "XOUFS Ctrl (0x140): "); ufshcd_dump_regs(hba, REG_UFS_EXTREG, 0x4, "Ext Reg "); + /* Dump ufshci register 0x2200 ~ 0x22AC */ ufshcd_dump_regs(hba, REG_UFS_MPHYCTRL, REG_UFS_REJECT_MON - REG_UFS_MPHYCTRL + 4, - "MPHY Ctrl "); + "MPHY Ctrl (0x2200): "); /* Direct debugging information to REG_MTK_PROBE */ ufs_mtk_dbg_sel(hba); From patchwork Tue Aug 2 23:54:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 595042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9796BC19F2B for ; Tue, 2 Aug 2022 23:54:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235302AbiHBXy4 (ORCPT ); Tue, 2 Aug 2022 19:54:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234573AbiHBXyv (ORCPT ); Tue, 2 Aug 2022 19:54:51 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A879854AE8; Tue, 2 Aug 2022 16:54:50 -0700 (PDT) X-UUID: 85e546883c8448b99df7b62c713ec1a6-20220803 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8, REQID:af080c16-3fc7-4cb8-acb0-24b29a4a02b7, OB:0, LO B:0,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:0 X-CID-META: VersionHash:0f94e32, CLOUDID:a87e1525-a982-4824-82d2-9da3b6056c2a, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 85e546883c8448b99df7b62c713ec1a6-20220803 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1963949752; Wed, 03 Aug 2022 07:54:47 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 3 Aug 2022 07:54:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 3 Aug 2022 07:54:45 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v5 4/5] scsi: ufs: ufs-mediatek: Fix performance scaling Date: Wed, 3 Aug 2022 07:54:36 +0800 Message-ID: <20220802235437.4547-5-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220802235437.4547-1-stanley.chu@mediatek.com> References: <20220802235437.4547-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Peter Wang If clk-scaling is enabled, performance scaling can be bound to the decision of clk-scaling to avoid unnecessary boosting. Meanwhile, fix missing initialization of pm-qos request. Reviewed-by: Stanley Chu Signed-off-by: Peter Wang Signed-off-by: Stanley Chu --- drivers/ufs/host/ufs-mediatek.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index 2b85d2406714..e1f131a93792 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -635,6 +635,12 @@ static void ufs_mtk_boost_pm_qos(struct ufs_hba *hba, bool boost) boost ? 0 : PM_QOS_DEFAULT_VALUE); } +static void ufs_mtk_scale_perf(struct ufs_hba *hba, bool scale_up) +{ + ufs_mtk_boost_crypt(hba, scale_up); + ufs_mtk_boost_pm_qos(hba, scale_up); +} + static void ufs_mtk_pwr_ctrl(struct ufs_hba *hba, bool on) { struct ufs_mtk_host *host = ufshcd_get_variant(hba); @@ -642,11 +648,11 @@ static void ufs_mtk_pwr_ctrl(struct ufs_hba *hba, bool on) if (on) { phy_power_on(host->mphy); ufs_mtk_setup_ref_clk(hba, on); - ufs_mtk_boost_crypt(hba, on); - ufs_mtk_boost_pm_qos(hba, on); + if (!ufshcd_is_clkscaling_supported(hba)) + ufs_mtk_scale_perf(hba, on); } else { - ufs_mtk_boost_pm_qos(hba, on); - ufs_mtk_boost_crypt(hba, on); + if (!ufshcd_is_clkscaling_supported(hba)) + ufs_mtk_scale_perf(hba, on); ufs_mtk_setup_ref_clk(hba, on); phy_power_off(host->mphy); } @@ -870,6 +876,10 @@ static int ufs_mtk_init(struct ufs_hba *hba) host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER); + /* Initialize pm-qos request */ + cpu_latency_qos_add_request(&host->pm_qos_req, PM_QOS_DEFAULT_VALUE); + host->pm_qos_init = true; + goto out; out_variant_clear: From patchwork Tue Aug 2 23:54:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanley Chu X-Patchwork-Id: 595041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A71D2C00140 for ; Tue, 2 Aug 2022 23:55:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235386AbiHBXzB (ORCPT ); Tue, 2 Aug 2022 19:55:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235246AbiHBXyx (ORCPT ); Tue, 2 Aug 2022 19:54:53 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D31AA5464E; Tue, 2 Aug 2022 16:54:51 -0700 (PDT) X-UUID: 083ad263bb40484cb1308f5ed11994a2-20220803 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8, REQID:07cee150-814b-4527-b489-c9f3f96c1b59, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:0f94e32, CLOUDID:a97e1525-a982-4824-82d2-9da3b6056c2a, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 083ad263bb40484cb1308f5ed11994a2-20220803 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 227284621; Wed, 03 Aug 2022 07:54:47 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 3 Aug 2022 07:54:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 3 Aug 2022 07:54:45 +0800 From: Stanley Chu To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v5 5/5] scsi: ufs: ufs-mediatek: Support clk-scaling to optimize power consumption Date: Wed, 3 Aug 2022 07:54:37 +0800 Message-ID: <20220802235437.4547-6-stanley.chu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220802235437.4547-1-stanley.chu@mediatek.com> References: <20220802235437.4547-1-stanley.chu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Po-Wen Kao Provide clk-scaling feature in MediaTek UFS platforms. MediaTek platform supports clk-scaling by switching parent clock mux of UFSHCI main clocks: ufs_sel. The driver needs to prevent changing the rate of ufs_sel because its parent PLL clock may be shared between multiple IPs. In order to achieve this goal, the maximum and minimum clock rates of ufs_sel defined in dts should match the rate of "ufs_sel_max_src" and "ufs_sel_min_src" respectively. Reviewed-by: Stanley Chu Signed-off-by: Po-Wen Kao Signed-off-by: Stanley Chu --- drivers/ufs/host/ufs-mediatek-trace.h | 27 +++++- drivers/ufs/host/ufs-mediatek.c | 121 ++++++++++++++++++++++++++ drivers/ufs/host/ufs-mediatek.h | 7 ++ 3 files changed, 153 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek-trace.h b/drivers/ufs/host/ufs-mediatek-trace.h index 7e010848dc99..b5f2ec314074 100644 --- a/drivers/ufs/host/ufs-mediatek-trace.h +++ b/drivers/ufs/host/ufs-mediatek-trace.h @@ -24,9 +24,32 @@ TRACE_EVENT(ufs_mtk_event, __entry->data = data; ), - TP_printk("ufs:event=%u data=%u", + TP_printk("ufs: event=%u data=%u", __entry->type, __entry->data) - ); +); + +TRACE_EVENT(ufs_mtk_clk_scale, + TP_PROTO(const char *name, bool scale_up, unsigned long clk_rate), + TP_ARGS(name, scale_up, clk_rate), + + TP_STRUCT__entry( + __field(const char*, name) + __field(bool, scale_up) + __field(unsigned long, clk_rate) + ), + + TP_fast_assign( + __entry->name = name; + __entry->scale_up = scale_up; + __entry->clk_rate = clk_rate; + ), + + TP_printk("ufs: clk (%s) scaled %s @ %lu", + __entry->name, + __entry->scale_up ? "up" : "down", + __entry->clk_rate) +); + #endif #undef TRACE_INCLUDE_PATH diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index e1f131a93792..7309f3f87eac 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -738,6 +738,46 @@ static u32 ufs_mtk_get_ufs_hci_version(struct ufs_hba *hba) return hba->ufs_version; } +/** + * ufs_mtk_init_clocks - Init mtk driver private clocks + * + * @hba: per adapter instance + */ +static void ufs_mtk_init_clocks(struct ufs_hba *hba) +{ + struct ufs_mtk_host *host = ufshcd_get_variant(hba); + struct list_head *head = &hba->clk_list_head; + struct ufs_mtk_clk *mclk = &host->mclk; + struct ufs_clk_info *clki, *clki_tmp; + + /* + * Find private clocks and store them in struct ufs_mtk_clk. + * Remove "ufs_sel_min_src" and "ufs_sel_min_src" from list to avoid + * being switched on/off in clock gating. + */ + list_for_each_entry_safe(clki, clki_tmp, head, list) { + if (!strcmp(clki->name, "ufs_sel")) { + host->mclk.ufs_sel_clki = clki; + } else if (!strcmp(clki->name, "ufs_sel_max_src")) { + host->mclk.ufs_sel_max_clki = clki; + clk_disable_unprepare(clki->clk); + list_del(&clki->list); + } else if (!strcmp(clki->name, "ufs_sel_min_src")) { + host->mclk.ufs_sel_min_clki = clki; + clk_disable_unprepare(clki->clk); + list_del(&clki->list); + } + } + + if (!mclk->ufs_sel_clki || !mclk->ufs_sel_max_clki || + !mclk->ufs_sel_min_clki) { + hba->caps &= ~UFSHCD_CAP_CLK_SCALING; + dev_info(hba->dev, + "%s: Clk-scaling not ready. Feature disabled.", + __func__); + } +} + #define MAX_VCC_NAME 30 static int ufs_mtk_vreg_fix_vcc(struct ufs_hba *hba) { @@ -858,12 +898,18 @@ static int ufs_mtk_init(struct ufs_hba *hba) /* Enable WriteBooster */ hba->caps |= UFSHCD_CAP_WB_EN; + + /* Enable clk scaling*/ + hba->caps |= UFSHCD_CAP_CLK_SCALING; + hba->quirks |= UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL; hba->vps->wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(80); if (host->caps & UFS_MTK_CAP_DISABLE_AH8) hba->caps |= UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; + ufs_mtk_init_clocks(hba); + /* * ufshcd_vops_init() is invoked after * ufshcd_setup_clock(true) in ufshcd_hba_init() thus @@ -1384,6 +1430,79 @@ static void ufs_mtk_event_notify(struct ufs_hba *hba, } } +static void ufs_mtk_config_scaling_param(struct ufs_hba *hba, + struct devfreq_dev_profile *profile, + struct devfreq_simple_ondemand_data *data) +{ + /* Customize min gear in clk scaling */ + hba->clk_scaling.min_gear = UFS_HS_G4; + + hba->vps->devfreq_profile.polling_ms = 200; + hba->vps->ondemand_data.upthreshold = 50; + hba->vps->ondemand_data.downdifferential = 20; +} + +/** + * ufs_mtk_clk_scale - Internal clk scaling operation + * + * MTK platform supports clk scaling by switching parent of ufs_sel(mux). + * The ufs_sel downstream to ufs_ck which feeds directly to UFS hardware. + * Max and min clocks rate of ufs_sel defined in dts should match rate of + * "ufs_sel_max_src" and "ufs_sel_min_src" respectively. + * This prevent changing rate of pll clock that is shared between modules. + * + * @hba: per adapter instance + * @scale_up: True for scaling up and false for scaling down + */ +static void ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up) +{ + struct ufs_mtk_host *host = ufshcd_get_variant(hba); + struct ufs_mtk_clk *mclk = &host->mclk; + struct ufs_clk_info *clki = mclk->ufs_sel_clki; + int ret = 0; + + ret = clk_prepare_enable(clki->clk); + if (ret) { + dev_info(hba->dev, + "clk_prepare_enable() fail, ret: %d\n", ret); + return; + } + + if (scale_up) { + ret = clk_set_parent(clki->clk, mclk->ufs_sel_max_clki->clk); + clki->curr_freq = clki->max_freq; + } else { + ret = clk_set_parent(clki->clk, mclk->ufs_sel_min_clki->clk); + clki->curr_freq = clki->min_freq; + } + + if (ret) { + dev_info(hba->dev, + "Failed to set ufs_sel_clki, ret: %d\n", ret); + } + + clk_disable_unprepare(clki->clk); + + trace_ufs_mtk_clk_scale(clki->name, scale_up, clk_get_rate(clki->clk)); +} + +static int ufs_mtk_clk_scale_notify(struct ufs_hba *hba, bool scale_up, + enum ufs_notify_change_status status) +{ + if (!ufshcd_is_clkscaling_supported(hba)) + return 0; + + if (status == PRE_CHANGE) { + /* Switch parent before clk_set_rate() */ + ufs_mtk_clk_scale(hba, scale_up); + } else { + /* Request interrupt latency QoS accordingly */ + ufs_mtk_scale_perf(hba, scale_up); + } + + return 0; +} + /* * struct ufs_hba_mtk_vops - UFS MTK specific variant operations * @@ -1405,6 +1524,8 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = { .dbg_register_dump = ufs_mtk_dbg_register_dump, .device_reset = ufs_mtk_device_reset, .event_notify = ufs_mtk_event_notify, + .config_scaling_param = ufs_mtk_config_scaling_param, + .clk_scale_notify = ufs_mtk_clk_scale_notify, }; /** diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h index aa26d415527b..2fc6d7b87694 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -124,6 +124,12 @@ struct ufs_mtk_crypt_cfg { int vcore_volt; }; +struct ufs_mtk_clk { + struct ufs_clk_info *ufs_sel_clki; /* Mux */ + struct ufs_clk_info *ufs_sel_max_clki; /* Max src */ + struct ufs_clk_info *ufs_sel_min_clki; /* Min src */ +}; + struct ufs_mtk_hw_ver { u8 step; u8 minor; @@ -139,6 +145,7 @@ struct ufs_mtk_host { struct reset_control *crypto_reset; struct ufs_hba *hba; struct ufs_mtk_crypt_cfg *crypt; + struct ufs_mtk_clk mclk; struct ufs_mtk_hw_ver hw_ver; enum ufs_mtk_host_caps caps; bool mphy_powered_on;