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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020a5d4bd0000000b0022059422255sm7109295wrt.69.2022.08.01.08.36.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Aug 2022 08:36:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features Date: Mon, 1 Aug 2022 16:36:03 +0100 Message-Id: <20220801153605.3051778-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220801153605.3051778-1-peter.maydell@linaro.org> References: <20220801153605.3051778-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Indication for support for SVE will not depend on whether we perform the query on the main kvm_state or the temp vcpu. Signed-off-by: Richard Henderson Message-id: 20220726045828.53697-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index d16d4ea2500..bb1516b3d5a 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -675,7 +675,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) } } - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; + sve_supported = kvm_arm_sve_supported(); /* Add feature bits that can't appear until after VCPU init. */ if (sve_supported) { From patchwork Mon Aug 1 15:36:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 594718 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:b345:0:0:0:0 with SMTP id w5csp3573141maz; Mon, 1 Aug 2022 08:39:00 -0700 (PDT) X-Google-Smtp-Source: AA6agR4uq59AvFSBlfyQCELnS9u6W9KnelVBx1WA9tPjM4DrZw9z4jAATyQ8Zv4Gmwr7/bO6QYMJ X-Received: by 2002:ad4:5d41:0:b0:473:f990:dad4 with SMTP id jk1-20020ad45d41000000b00473f990dad4mr14603207qvb.78.1659368340883; Mon, 01 Aug 2022 08:39:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1659368340; cv=none; d=google.com; s=arc-20160816; b=0cjAJnT59EeCEYm1GNoR8K3jgauwPoIJlVirGcjMBQEw8CVxnSrjZGm6w0T4wnzaXu SBlcwmfhIs9LbETZdUPfppDVRdP9gV983tH0l9vlnCX2Ye2OgMmN2p97pEVPVAYqo/0m pBa+QnM+CdtVEnNqC8C2il3laX9iKibu2iOW8QGptt9o3kgdVY6Cf5TblEV/Hw95Alvx dcf1Y6hC5iSIrzkDhX6WJLMtxsFwdjhhOD9ZUhDt9MkNX1/f4pg1ZFPbUqNZIEoonGEK s8uZWOVxiYwYGS1P1oRUoP9J+FwQwpjCdDN/BXgQ5FXRv32nelaLPK2Gcm5YSqR027+J jl6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zlTomEsC6jgfuL5E2VJ8p507QO9XDvOULRxbbhKQdX4=; b=hc/dWk2OK+K6ICfMvLeGH8Kw2mi7iDZh3cwuvegimXk1zT+AxgKu/dk/PcaxL/iyDb 8Ydwkn48vD3nMfir2Q7waSWcmiw+5xe9lX85qwxQ6tU8t1d1Hn2R9rC4NyN1W+6tDgKP kM2RgyXSc8Ls3BnMKgiB3pmSVkzvuw5HZ1tGvBze9YXOj3jwVayVk9zgFoXg6Ae7pgzj vtFmwPhWa2pUhgxV5hKCwxdAvtWTICJknjvzd8N1Vth+IVdgPijvb1CAG9QwKSTtmYow 0i1+4i/Xm0kNCvbt7qamNEZ0Ec44CkIm+quTQ4IgVXhivWI0pQI3l+MQshFM9XuFMONY Uk/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QBIcLC5H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020a5d4bd0000000b0022059422255sm7109295wrt.69.2022.08.01.08.36.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Aug 2022 08:36:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host Date: Mon, 1 Aug 2022 16:36:04 +0100 Message-Id: <20220801153605.3051778-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220801153605.3051778-1-peter.maydell@linaro.org> References: <20220801153605.3051778-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Because we weren't setting this flag, our probe of ID_AA64ZFR0 was always returning zero. This also obviates the adjustment of ID_AA64PFR0, which had sanitized the SVE field. The effects of the bug are not visible, because the only thing that ID_AA64ZFR0 is used for within qemu at present is tcg translation. The other tests for SVE within KVM are via ID_AA64PFR0.SVE. Reported-by: Zenghui Yu Signed-off-by: Richard Henderson Message-id: 20220726045828.53697-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index bb1516b3d5a..43cd7eb8904 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -507,7 +507,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) bool sve_supported; bool pmu_supported = false; uint64_t features = 0; - uint64_t t; int err; /* Old kernels may not know about the PREFERRED_TARGET ioctl: however @@ -528,10 +527,17 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) struct kvm_vcpu_init init = { .target = -1, }; /* - * Ask for Pointer Authentication if supported. We can't play the - * SVE trick of synthesising the ID reg as KVM won't tell us - * whether we have the architected or IMPDEF version of PAuth, so - * we have to use the actual ID regs. + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, + * which is otherwise RAZ. + */ + sve_supported = kvm_arm_sve_supported(); + if (sve_supported) { + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; + } + + /* + * Ask for Pointer Authentication if supported, so that we get + * the unsanitized field values for AA64ISAR1_EL1. */ if (kvm_arm_pauth_supported()) { init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | @@ -675,20 +681,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) } } - sve_supported = kvm_arm_sve_supported(); - - /* Add feature bits that can't appear until after VCPU init. */ if (sve_supported) { - t = ahcf->isar.id_aa64pfr0; - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - ahcf->isar.id_aa64pfr0 = t; - /* * There is a range of kernels between kernel commit 73433762fcae * and f81cb2c3ad41 which have a bug where the kernel doesn't expose * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled - * SVE support, so we only read it here, rather than together with all - * the other ID registers earlier. + * SVE support, which resulted in an error rather than RAZ. + * So only read the register if we set KVM_ARM_VCPU_SVE above. */ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, ARM64_SYS_REG(3, 0, 0, 4, 4)); From patchwork Mon Aug 1 15:36:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 594717 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:b345:0:0:0:0 with SMTP id w5csp3572766maz; Mon, 1 Aug 2022 08:38:27 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uURLuVTwnnulQC2cJWV+1FEaVBNL0bxFRH2p16DU+jA3QUYJJm/p3SzqbWqdfkrY1D4PUj X-Received: by 2002:a05:622a:5d89:b0:31e:e5c5:d84c with SMTP id fu9-20020a05622a5d8900b0031ee5c5d84cmr14877481qtb.84.1659368307238; Mon, 01 Aug 2022 08:38:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1659368307; cv=none; d=google.com; s=arc-20160816; b=Xg9Z6mwYogXo4QR4O9ro/+bW15cCwaisYPsL8kLrYARWY7TRo0yRrVTz8KtVBYIz7F BPxaKzVNxaDjiVnw34z2I4Xycsc+MyRBC+1pp8LiAvw8CsLR6H2ViNPreT/eKB6DDy5m HkWS2o1ioWYQf47iA/mwMmr4nPtrctLsCbUfzfrLABwHsW7Q95JESYhVQbnjhsKv4f8H X0Oa0foszvkYkPbbp6szhC7VzsuXLh8NWcHccklXdKOIVuiAMSmDIUgu6cKU9EStIAsw VRMw/9KtW1Dc5h52Jxd0Tm1r/ek9+lQVpM3xsHXxvmMMSHvBYnhoyByi5GdFyeiV1JE5 AR2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7TrRZP89XydMUNpJE0vVRKRxKhZa4Vn1cfpQMOwzXNY=; b=uDCE+DQffBG4ynaZ2KPRQ1pO701NvgcCWUuyLtGs0SgKmVCN/x2vOg2j8svEAESuRT OZNYOs16BCTNorLAONAVEdxExdJ8c4sQMX4eiexDHSoqu/kfqqiVBj9SADFyILdyOXN8 4GLcH6SrN87bGkZaTZ+874FNmTGWGCj/Mj0ViQv97IJwoR+R+AfFEVfQUjQdCir3Cgg3 HFOdIX2B/x23TaniIlLUiIkbeO8quaoJIowpdAzr/KBQ5a6idNhHtqP1Jv9NbwnUvW4Y HXVk0v9CBpudjmxUgP/j258XwjgJ4K0Ml3JfEGiRHN56/Jq04dLTFImWH7LP+VijJhOf GbIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ziGjG+Zz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id l16-20020a5d4bd0000000b0022059422255sm7109295wrt.69.2022.08.01.08.36.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Aug 2022 08:36:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch Date: Mon, 1 Aug 2022 16:36:05 +0100 Message-Id: <20220801153605.3051778-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220801153605.3051778-1-peter.maydell@linaro.org> References: <20220801153605.3051778-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The test for the IF block indicates no ID registers are exposed, much less host support for SVE. Move the SVE probe into the ELSE block. Signed-off-by: Richard Henderson Message-id: 20220726045828.53697-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 43cd7eb8904..9b9dd46d782 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -679,18 +679,18 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, ARM64_SYS_REG(3, 3, 9, 12, 0)); } - } - if (sve_supported) { - /* - * There is a range of kernels between kernel commit 73433762fcae - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled - * SVE support, which resulted in an error rather than RAZ. - * So only read the register if we set KVM_ARM_VCPU_SVE above. - */ - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, - ARM64_SYS_REG(3, 0, 0, 4, 4)); + if (sve_supported) { + /* + * There is a range of kernels between kernel commit 73433762fcae + * and f81cb2c3ad41 which have a bug where the kernel doesn't + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has + * enabled SVE support, which resulted in an error rather than RAZ. + * So only read the register if we set KVM_ARM_VCPU_SVE above. + */ + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, + ARM64_SYS_REG(3, 0, 0, 4, 4)); + } } kvm_arm_destroy_scratch_host_vcpu(fdarray);