From patchwork Thu Jan 31 00:39:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 157103 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp6587292jaa; Wed, 30 Jan 2019 16:40:46 -0800 (PST) X-Google-Smtp-Source: ALg8bN6QgDtH+266blb1PGI3YtIGB0AJkVq8jHtc1OxKyJpkb8Bw3rJMj6W9xu/GwP9XA7ANaTHG X-Received: by 2002:a63:4c04:: with SMTP id z4mr29756587pga.312.1548895246205; Wed, 30 Jan 2019 16:40:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548895246; cv=none; d=google.com; s=arc-20160816; b=tuA1nQ8udlzEIhxfySTR+edxRM0mwGWbgsTz18x58hZAAC2IrHcYrNfRdYVLWcsq/C aSyvcu8fGUzrKJOy6P5gkw7R4lKhb++Y+Kv6oABxRcENbz+gMTh3n3gQmanhkxONkjw0 f2zdsFTc144sIMqGalhWzifzhwfk5PF1BebS9n2nJbCOI4ZsBhysegFTjFM1A0c72c2i T84Qu3BhpHPlJ/HKCHHSt9prtujDoMTJPydwcNsGrVlxMRIXy2sC6BKnuxXx6FOKf98e 3yerqMV/oDhDsKS7JtqRhAIwRICiFGHvpXTHICssTNUjzDEnJPLd87ozcs5+oA3VqThu hbrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Rku1BaWpLuzz+j+NKPgUgAkxtH2UnE4qdz465ne+ekY=; b=snoglLapxH4rWQLnPsxdVZOxQ1m85NwKyNkUgz92PMGXKXyFee+sF6c05mPCW2QWZI f7PtDxvRtBVTn+mrn7IIcTqJlWWPjsESK2fgyObkkZHJi55iwpf24ZSaPECFMEsL5in2 LBOAWtcmqLMwmjmm/14fO9BIBEmLeAEcLns2+fe8iwZ38FGEPocN6bonIsbqQ4Yt0uts DVD3wWdCgEm9OHaOKBQe/jbD1vasiAT0HQUL+f8AjikvGI0GCyjaNDVqBtO8Ur9g+Jam Og5ltMv0nR1OINdbUjs4/T9oxi95Aa7Wx91xX+DxlmXXIOoM6r62rThRZvRVW06PpY3Q 1lgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kQ+DOyoG; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z12si3019566plk.90.2019.01.30.16.40.45; Wed, 30 Jan 2019 16:40:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kQ+DOyoG; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728841AbfAaAjy (ORCPT + 15 others); Wed, 30 Jan 2019 19:39:54 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:43569 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728812AbfAaAjy (ORCPT ); Wed, 30 Jan 2019 19:39:54 -0500 Received: by mail-pg1-f196.google.com with SMTP id v28so574498pgk.10 for ; Wed, 30 Jan 2019 16:39:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Rku1BaWpLuzz+j+NKPgUgAkxtH2UnE4qdz465ne+ekY=; b=kQ+DOyoGl9amjlhKsWQX11UEQ/ST1ykM8cDg06n85E+OiO+nk/ISg3sJzZX89C39SR cw8ry+mLvsFnXdrFwxI7ZtXNxvvGG/S0bk79yG7rb2QPD0QO6BYKf2S2aFGcdq9HGKBn 6R2jJNpSUfC5TPpDkLyuvShRfrgVydyg5hgYo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Rku1BaWpLuzz+j+NKPgUgAkxtH2UnE4qdz465ne+ekY=; b=hOAM7deSvJUHJFUK4cHsqjz963byBGu0Wg3mHlxajK8PjtxkM2s9tr3vWqQpeGqXib CYM6OQa1RO/omHtqhMSSnvCCm4C4Si/VQ8RQBWPUIGjkluA/JTTEUBSYRhtXwfCRdXQ8 q5ZVNhtil815xFrKsQtvCIX+mubqoiiFTgM5mEFy0z1Rm5qqCliFKIuLe40djVwQTk5q 6/x60IF56rBkpaY7BIGFLNZ6R8aDyCj7/wWf1lV7UCfjDCzPoOOHUVtzTekgDOZqlqXr 8EcBJzjS68yYRDgnZ1l9OFIShf4NyT16u34TYbGuZuiDdUwXAx11+8ZiYcHcMyv5w5Fp ZwhQ== X-Gm-Message-State: AJcUukcIM1BJEM97utnxMvV9D4Wr56hcK0gwjJ6/eETsjXtm0VpH6ei2 +Hv9PI22s0tnaw0XNjYjkNsl2g== X-Received: by 2002:a65:4784:: with SMTP id e4mr28990086pgs.12.1548895193337; Wed, 30 Jan 2019 16:39:53 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id k15sm4357928pfb.147.2019.01.30.16.39.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Jan 2019 16:39:52 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , Ohad Ben-Cohen , Arun Kumar Neelakantam , Sibi Sankar , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org Subject: [PATCH v5 02/10] arm64: dts: qcom: sdm845: Define rmtfs memory Date: Wed, 30 Jan 2019 16:39:25 -0800 Message-Id: <20190131003933.11436-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190131003933.11436-1-bjorn.andersson@linaro.org> References: <20190131003933.11436-1-bjorn.andersson@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Define the rmtfs memory node. As the memory region specified in version 10 of the memory map is only 1MB a chunk of unallocated memory is chosen. Signed-off-by: Bjorn Andersson --- Changes since v4: - Moved rmtfs_mem, to not collide with xbl_mem Changes since v3: - Labeled the node arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 45b1616392aa..d19486ba1e5e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -104,6 +104,15 @@ no-map; }; + rmtfs_mem: memory@88f0000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0x88f00000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + qseecom_mem: memory@8ab00000 { reg = <0 0x8ab00000 0 0x1400000>; no-map; From patchwork Thu Jan 31 00:39:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 157096 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp6586723jaa; Wed, 30 Jan 2019 16:40:01 -0800 (PST) X-Google-Smtp-Source: ALg8bN63yRAHe3TaCmJ4YcDc/vEtIfmNidEE9/u7wDUuAxiIAOw/Xo+HmKtzhldwUe14QvsS2tzM X-Received: by 2002:a63:ea15:: with SMTP id c21mr28082122pgi.361.1548895201372; Wed, 30 Jan 2019 16:40:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548895201; cv=none; d=google.com; s=arc-20160816; b=DkoJzv6Wns+tT0JIFG/oOe33bVgFvG/3ym+xLigEKusxOsnSN0yr5wF3itnA72KM3H lbwHh89Q5w18SYNkQGlit/6nxCsqYxgZCtCI6r25KqgOMzmTtVWMbeKojWCETim34ucI NZ66+yC3xmtJKoZ1OAaxxEegSS1IdPEFyAh51KKuwrOEpFKk8Tf9l//OJZE+StCDTDdu wfKCJEB0nxnvWSQUAHoFtRMynmPTUsK7VM7Pnf+jKMGicPC7jjP1q4FtkY3oRaIcS/dH OP43ntdyC4rsk8LKVz7k/QB3Xku0Xn/rAIFkj3YfX8/pvpCT8xRd5rBLxTOzvU1hBmTc vUig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=3q4IQ689Cb4SrReAZYPihH6dgW8kkZFdx3ckm+KAsiw=; b=talVi5PV5NZ6FMugbaq2qvXRtn+iSO8SPMr+PNE/3RaoC5zm7qvN/TCJQHh0Bj+XFl 7HKEdgfOLAqQJbcGYvNNHTv0Pg/sKBYZ6tYcChuKuE6y7BbRD3HPaAg2Q2lrKR2NTb/B B2UD1EiBcLJiw415Z7V8aXULwPfBRv/VBNj3FyCEDt5HPw93EAdy0itjC0Y3YBYHsmy6 cB4s/o6gMPXgJ33WhXT3+IfirNWekpQNrM8OiF125AFQ9T9QEl59d6OtbcEO8z9Qbwm8 qCCPhJdrP/dUMwlsCwjHTwv1BlnUhs5npNqLHeEeXjAFIOHFZvoEcmUK8jr/3dSGb+7u ibVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SgMXupv7; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y123si2893881pfy.18.2019.01.30.16.40.00; Wed, 30 Jan 2019 16:40:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SgMXupv7; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729725AbfAaAj6 (ORCPT + 15 others); Wed, 30 Jan 2019 19:39:58 -0500 Received: from mail-pl1-f195.google.com ([209.85.214.195]:33175 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729486AbfAaAj6 (ORCPT ); Wed, 30 Jan 2019 19:39:58 -0500 Received: by mail-pl1-f195.google.com with SMTP id z23so649334plo.0 for ; Wed, 30 Jan 2019 16:39:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3q4IQ689Cb4SrReAZYPihH6dgW8kkZFdx3ckm+KAsiw=; b=SgMXupv71M01ZZnxmcOBn3FPh6jhTDettERGUrMucbisid9HA1y8EBEE/ySVJMDkPZ 4cGD2gFU9dqeze3phrzHPOtOkl4JF/HdeY8sE6nMiL375Vve5ke8tz55l98z5BKjB9lc mVCHhBqoz8IC+Ymi24tr0DAvw9P7tNsy5W+PI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3q4IQ689Cb4SrReAZYPihH6dgW8kkZFdx3ckm+KAsiw=; b=BAuRxKv1QnVYNTTifT5LLb/4eiJ3LeQoY+fCcYS3mO5VVP3LCPIXoZX8c2UkAzVWxj xaMm1hxAalJ1qVCIGVVVUgO/PtnIhjlSg/xK7JnMsueC8brf9hWL5puHuyBkpZZNcCO2 KIct+ppCA4RDzqaMNWctD3mFgggc+Er8tssRYgCXD5atdeDKFMpWTRx1VxvMSztosebn 3k2QNbYlvPQXn3pVp/ErPHoMOl9XLBu2TCu5ZN67P7BXAirosZ+ZbkQx9QF7hVNTW39V DU50XD0l4ZpBR2eKAP8Clxr4uuRUhK30BAtcFtHPYf2TY1Usj3jA70Ms6fQQ4P4+zil5 z2xQ== X-Gm-Message-State: AJcUukfuDydUM1YOrAlKwtWqCaYBuBKXcoiQdvbz40xCgEoHVbP8XS6K OMtXnmHuGcqMoL48WquRW2Y50A== X-Received: by 2002:a17:902:24a2:: with SMTP id w31mr31988757pla.216.1548895197417; Wed, 30 Jan 2019 16:39:57 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id k15sm4357928pfb.147.2019.01.30.16.39.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Jan 2019 16:39:56 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , Ohad Ben-Cohen , Arun Kumar Neelakantam , Sibi Sankar , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org Subject: [PATCH v5 05/10] soc: qcom: Add AOSS QMP communication driver Date: Wed, 30 Jan 2019 16:39:28 -0800 Message-Id: <20190131003933.11436-6-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190131003933.11436-1-bjorn.andersson@linaro.org> References: <20190131003933.11436-1-bjorn.andersson@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The AOSS QMP driver is used to communicate with the AOSS for certain side-channel requests, that are not enabled through the RPMh interface. The communication is a very simple synchronous mechanism of messages being written in message RAM and a doorbell in the AOSS is rung. As the AOSS has processed the message length is cleared and an interrupt is fired by the AOSS as acknowledgment. Reviewed-by: Arun Kumar Neelakantam Signed-off-by: Bjorn Andersson --- Changes since v4: - None Changes since v3: - None drivers/soc/qcom/Kconfig | 9 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/aoss-qmp.c | 317 ++++++++++++++++++++++++++++++ include/linux/soc/qcom/aoss-qmp.h | 14 ++ 4 files changed, 341 insertions(+) create mode 100644 drivers/soc/qcom/aoss-qmp.c create mode 100644 include/linux/soc/qcom/aoss-qmp.h -- 2.18.0 diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 1ee298f6bf17..28ab19bf8c98 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -3,6 +3,15 @@ # menu "Qualcomm SoC drivers" +config QCOM_AOSS_QMP + tristate "Qualcomm AOSS Messaging Driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on MAILBOX + help + This driver provides the means for communicating with the + micro-controller in the AOSS, using QMP, to control certain resource + that are not exposed through RPMh. + config QCOM_COMMAND_DB bool "Qualcomm Command DB" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index ffe519b0cb66..2c04d27fbf9e 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 CFLAGS_rpmh-rsc.o := -I$(src) +obj-$(CONFIG_QCOM_AOSS_QMP) += aoss-qmp.o obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o obj-$(CONFIG_QCOM_GLINK_SSR) += glink_ssr.o diff --git a/drivers/soc/qcom/aoss-qmp.c b/drivers/soc/qcom/aoss-qmp.c new file mode 100644 index 000000000000..86ee622cdadf --- /dev/null +++ b/drivers/soc/qcom/aoss-qmp.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, Linaro Ltd + */ +#include +#include +#include +#include +#include +#include + +#define QMP_DESC_MAGIC 0x0 +#define QMP_DESC_VERSION 0x4 +#define QMP_DESC_FEATURES 0x8 + +#define QMP_DESC_UCORE_LINK_STATE 0xc +#define QMP_DESC_UCORE_LINK_STATE_ACK 0x10 +#define QMP_DESC_UCORE_CH_STATE 0x14 +#define QMP_DESC_UCORE_CH_STATE_ACK 0x18 +#define QMP_DESC_UCORE_MBOX_SIZE 0x1c +#define QMP_DESC_UCORE_MBOX_OFFSET 0x20 + +#define QMP_DESC_MCORE_LINK_STATE 0x24 +#define QMP_DESC_MCORE_LINK_STATE_ACK 0x28 +#define QMP_DESC_MCORE_CH_STATE 0x2c +#define QMP_DESC_MCORE_CH_STATE_ACK 0x30 +#define QMP_DESC_MCORE_MBOX_SIZE 0x34 +#define QMP_DESC_MCORE_MBOX_OFFSET 0x38 + +#define QMP_STATE_UP 0x0000ffff +#define QMP_STATE_DOWN 0xffff0000 + +#define QMP_MAGIC 0x4d41494c +#define QMP_VERSION 1 + +/** + * struct qmp - driver state for QMP implementation + * @msgram: iomem referencing the message RAM used for communication + * @dev: reference to QMP device + * @mbox_client: mailbox client used to ring the doorbell on transmit + * @mbox_chan: mailbox channel used to ring the doorbell on transmit + * @offset: offset within @msgram where messages should be written + * @size: maximum size of the messages to be transmitted + * @event: wait_queue for synchronization with the IRQ + * @tx_lock: provides syncrhonization between multiple callers of qmp_send() + * @pd_pdev: platform device for the power-domain child device + */ +struct qmp { + void __iomem *msgram; + struct device *dev; + + struct mbox_client mbox_client; + struct mbox_chan *mbox_chan; + + size_t offset; + size_t size; + + wait_queue_head_t event; + + struct mutex tx_lock; + + struct platform_device *pd_pdev; +}; + +static void qmp_kick(struct qmp *qmp) +{ + mbox_send_message(qmp->mbox_chan, NULL); + mbox_client_txdone(qmp->mbox_chan, 0); +} + +static bool qmp_magic_valid(struct qmp *qmp) +{ + return readl(qmp->msgram + QMP_DESC_MAGIC) == QMP_MAGIC; +} + +static bool qmp_link_acked(struct qmp *qmp) +{ + return readl(qmp->msgram + QMP_DESC_MCORE_LINK_STATE_ACK) == QMP_STATE_UP; +} + +static bool qmp_mcore_channel_acked(struct qmp *qmp) +{ + return readl(qmp->msgram + QMP_DESC_MCORE_CH_STATE_ACK) == QMP_STATE_UP; +} + +static bool qmp_ucore_channel_up(struct qmp *qmp) +{ + return readl(qmp->msgram + QMP_DESC_UCORE_CH_STATE) == QMP_STATE_UP; +} + +static int qmp_open(struct qmp *qmp) +{ + int ret; + u32 val; + + ret = wait_event_timeout(qmp->event, qmp_magic_valid(qmp), HZ); + if (!ret) { + dev_err(qmp->dev, "QMP magic doesn't match\n"); + return -ETIMEDOUT; + } + + val = readl(qmp->msgram + QMP_DESC_VERSION); + if (val != QMP_VERSION) { + dev_err(qmp->dev, "unsupported QMP version %d\n", val); + return -EINVAL; + } + + qmp->offset = readl(qmp->msgram + QMP_DESC_MCORE_MBOX_OFFSET); + qmp->size = readl(qmp->msgram + QMP_DESC_MCORE_MBOX_SIZE); + if (!qmp->size) { + dev_err(qmp->dev, "invalid mailbox size 0x%zx\n", qmp->size); + return -EINVAL; + } + + /* Ack remote core's link state */ + val = readl(qmp->msgram + QMP_DESC_UCORE_LINK_STATE); + writel(val, qmp->msgram + QMP_DESC_UCORE_LINK_STATE_ACK); + + /* Set local core's link state to up */ + writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_MCORE_LINK_STATE); + + qmp_kick(qmp); + + ret = wait_event_timeout(qmp->event, qmp_link_acked(qmp), HZ); + if (!ret) { + dev_err(qmp->dev, "ucore didn't ack link\n"); + goto timeout_close_link; + } + + writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_MCORE_CH_STATE); + + ret = wait_event_timeout(qmp->event, qmp_ucore_channel_up(qmp), HZ); + if (!ret) { + dev_err(qmp->dev, "ucore didn't open channel\n"); + goto timeout_close_channel; + } + + /* Ack remote core's channel state */ + val = readl(qmp->msgram + QMP_DESC_UCORE_CH_STATE); + writel(val, qmp->msgram + QMP_DESC_UCORE_CH_STATE_ACK); + + qmp_kick(qmp); + + ret = wait_event_timeout(qmp->event, qmp_mcore_channel_acked(qmp), HZ); + if (!ret) { + dev_err(qmp->dev, "ucore didn't ack channel\n"); + goto timeout_close_channel; + } + + return 0; + +timeout_close_channel: + writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_CH_STATE); + +timeout_close_link: + writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_LINK_STATE); + qmp_kick(qmp); + + return -ETIMEDOUT; +} + +static void qmp_close(struct qmp *qmp) +{ + writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_CH_STATE); + writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_LINK_STATE); + qmp_kick(qmp); +} + +static irqreturn_t qmp_intr(int irq, void *data) +{ + struct qmp *qmp = data; + + wake_up_interruptible_all(&qmp->event); + + return IRQ_HANDLED; +} + +static bool qmp_message_empty(struct qmp *qmp) +{ + return readl(qmp->msgram + qmp->offset) == 0; +} + +/** + * qmp_send() - send a message to the AOSS + * @qmp: qmp context + * @data: message to be sent + * @len: length of the message + * + * Transmit @data to AOSS and wait for the AOSS to acknowledge the message. + * @len must be a multiple of 4 and not longer than the mailbox size. Access is + * synchronized by this implementation. + * + * Return: 0 on success, negative errno on failure + */ +int qmp_send(struct qmp *qmp, const void *data, size_t len) +{ + int ret; + + if (WARN_ON(len + sizeof(u32) > qmp->size)) + return -EINVAL; + + if (WARN_ON(len % sizeof(u32))) + return -EINVAL; + + mutex_lock(&qmp->tx_lock); + + /* The message RAM only implements 32-bit accesses */ + __iowrite32_copy(qmp->msgram + qmp->offset + sizeof(u32), + data, len / sizeof(u32)); + writel(len, qmp->msgram + qmp->offset); + qmp_kick(qmp); + + ret = wait_event_interruptible_timeout(qmp->event, + qmp_message_empty(qmp), HZ); + if (!ret) { + dev_err(qmp->dev, "ucore did not ack channel\n"); + ret = -ETIMEDOUT; + + /* Clear message from buffer */ + writel(0, qmp->msgram + qmp->offset); + } else { + ret = 0; + } + + mutex_unlock(&qmp->tx_lock); + + return ret; +} +EXPORT_SYMBOL(qmp_send); + +static int qmp_probe(struct platform_device *pdev) +{ + struct resource *res; + struct qmp *qmp; + int irq; + int ret; + + qmp = devm_kzalloc(&pdev->dev, sizeof(*qmp), GFP_KERNEL); + if (!qmp) + return -ENOMEM; + + qmp->dev = &pdev->dev; + init_waitqueue_head(&qmp->event); + mutex_init(&qmp->tx_lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + qmp->msgram = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(qmp->msgram)) + return PTR_ERR(qmp->msgram); + + qmp->mbox_client.dev = &pdev->dev; + qmp->mbox_client.knows_txdone = true; + qmp->mbox_chan = mbox_request_channel(&qmp->mbox_client, 0); + if (IS_ERR(qmp->mbox_chan)) { + dev_err(&pdev->dev, "failed to acquire ipc mailbox\n"); + return PTR_ERR(qmp->mbox_chan); + } + + irq = platform_get_irq(pdev, 0); + ret = devm_request_irq(&pdev->dev, irq, qmp_intr, IRQF_ONESHOT, + "aoss-qmp", qmp); + if (ret < 0) { + dev_err(&pdev->dev, "failed to request interrupt\n"); + mbox_free_channel(qmp->mbox_chan); + return ret; + } + + ret = qmp_open(qmp); + if (ret < 0) { + mbox_free_channel(qmp->mbox_chan); + return ret; + } + + platform_set_drvdata(pdev, qmp); + + if (of_property_read_bool(pdev->dev.of_node, "#power-domain-cells")) { + qmp->pd_pdev = platform_device_register_data(&pdev->dev, + "aoss_qmp_pd", + PLATFORM_DEVID_NONE, + NULL, 0); + if (IS_ERR(qmp->pd_pdev)) + dev_err(&pdev->dev, "failed to register AOSS PD\n"); + } + + return 0; +} + +static int qmp_remove(struct platform_device *pdev) +{ + struct qmp *qmp = platform_get_drvdata(pdev); + + platform_device_unregister(qmp->pd_pdev); + + mbox_free_channel(qmp->mbox_chan); + qmp_close(qmp); + + return 0; +} + +static const struct of_device_id qmp_dt_match[] = { + { .compatible = "qcom,sdm845-aoss-qmp", }, + {} +}; +MODULE_DEVICE_TABLE(of, qmp_dt_match); + +static struct platform_driver qmp_driver = { + .driver = { + .name = "aoss_qmp", + .of_match_table = qmp_dt_match, + }, + .probe = qmp_probe, + .remove = qmp_remove, +}; +module_platform_driver(qmp_driver); + +MODULE_DESCRIPTION("Qualcomm AOSS QMP driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/soc/qcom/aoss-qmp.h b/include/linux/soc/qcom/aoss-qmp.h new file mode 100644 index 000000000000..a2ac891d7fd4 --- /dev/null +++ b/include/linux/soc/qcom/aoss-qmp.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, Linaro Ltd + */ +#ifndef __AOP_QMP_H__ +#define __AOP_QMP_H__ + +#include + +struct qmp; + +int qmp_send(struct qmp *qmp, const void *data, size_t len); + +#endif From patchwork Thu Jan 31 00:39:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 157101 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp6587009jaa; Wed, 30 Jan 2019 16:40:23 -0800 (PST) X-Google-Smtp-Source: ALg8bN6CKw3vP2WbQLvQe5lljs3EJIew3iJimi4rFBLitSh5y5XR1P/0Xw3TVz14h4gtqjRL2mSG X-Received: by 2002:a62:44d8:: with SMTP id m85mr33128368pfi.164.1548895223903; Wed, 30 Jan 2019 16:40:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548895223; cv=none; d=google.com; s=arc-20160816; b=Rjhym3CGNJ5fb6w6XVVpO7CifW7xS6cCu8vE5ir13iqD3Mb6DS38ghTDv/w1nbf/Ks Grw9LBARRk1GHo8+bduyZYVFTEo4Lh43QS5WBp7/7BaVTyScvgRPKH5Ws5ZnFI5OEAVP WM9xPLxTP3WTUqyO1oq0b5IU9m/+52YxLebedHqepMDykE15EI4pki6uONmWFSnsL/nA ogE5btKAO+dj9DqVXuIVZX4djwyy05oQ2LOJeOTFuwDNL9O+rbaFc5fqbStxVwRVeRKm ZS7T1Wok/N+91TcIvJwzHuC6bN7M9LcBvFmHboTqUuN6Sm6DHNX5FBDvauDZTz+7swTh OcrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Q9ixFk4EI7syC1y3QXe8jfTn6KfD24gFIztErYAZrg8=; b=WrH8UR8i8XwHZ+QPeRFeqdfm5W+0ijs8fBfH9VM94jmmOJMvhjUrSoqdu1cqqksNFA EKFhsVBsKiM1lJLw8o2E7DUAa3pN2uAzo6HY5yG4tqNjcJVqTLmXCjn86gr4xyx4BjhW mP2tgelhNGNCGY7CRj0f7j4LHJZicvyHyHIS2pQrB+E24DGlcIm4wZvF5qT+HV6ROwIM vTAfQznt+h5/QizcfDPVQXKmJ/jne6DppSsywaUd92WfJBwVDvHCO/j3U926ZDm15lCR h54HogSAS8FDGy4giDHuA+ultzZ8xVj6mtEoHa7uzI67ainU4GnKXlURyqGaWFzfDYK0 cq2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=coalg0v7; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i1si3009203pfj.276.2019.01.30.16.40.23; Wed, 30 Jan 2019 16:40:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=coalg0v7; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730088AbfAaAkB (ORCPT + 15 others); Wed, 30 Jan 2019 19:40:01 -0500 Received: from mail-pl1-f193.google.com ([209.85.214.193]:36618 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729830AbfAaAkB (ORCPT ); Wed, 30 Jan 2019 19:40:01 -0500 Received: by mail-pl1-f193.google.com with SMTP id g9so642454plo.3 for ; Wed, 30 Jan 2019 16:40:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Q9ixFk4EI7syC1y3QXe8jfTn6KfD24gFIztErYAZrg8=; b=coalg0v7IJaPO62rKXqNeDw18IKRXjMf3m4DZYQ/K30rkIpQp8oWuKbnDIZ3Dyaoxi mwg3piqJOxHNbieRI3V+ko9mghQuyxs1NRydUspHU2rJ818tdicGRa5PV//HD/97NAD8 uRI6S+7FOU0HSQmLzHe8cMfwpudpTfrkqnh1M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Q9ixFk4EI7syC1y3QXe8jfTn6KfD24gFIztErYAZrg8=; b=qAEa3+Tfxor5b4grilSu+7s4uUi/B0ZviS9pCqZv5nHep37VW6QccAHGPGsItxywdT nYpMAEpdlv0xV+a4h34592uTFubxMpY9o3E3R5C4T44gWa6KHBLsF8HUdZuWNx0VOZcp Fk8iwHc4D7SSX0GYfa0GiOFxYQ7F8SxMvV+ktkYwZM1rpnhkZmHZd4xIN6n55WkGQuKw UzUhHKdj09sOQzEUopviwsDIrNMJ3J6DmCtzwYXRfvxi+wgULXewQvLfHvkvnqepIfTe 1nQfiJu95M7aIGacTrJaeg3US88t1aVtChNLiiuVd1BPbBhmaQzplGuY4sZPIe4iG9/V aQjg== X-Gm-Message-State: AJcUukdh6qVGnEE08RSXD9cFln+D4g0LB5THsPcMYmeNxmubVTZslAWi 8h5GW4HKeL+nJ8U0qDHyCf1w/w== X-Received: by 2002:a17:902:5ac2:: with SMTP id g2mr32740574plm.313.1548895200423; Wed, 30 Jan 2019 16:40:00 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id k15sm4357928pfb.147.2019.01.30.16.39.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Jan 2019 16:39:59 -0800 (PST) From: Bjorn Andersson To: Ohad Ben-Cohen , Bjorn Andersson Cc: Andy Gross , David Brown , Rob Herring , Mark Rutland , Arun Kumar Neelakantam , Sibi Sankar , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org Subject: [PATCH v5 07/10] remoteproc: q6v5-mss: Vote for rpmh power domains Date: Wed, 30 Jan 2019 16:39:30 -0800 Message-Id: <20190131003933.11436-8-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190131003933.11436-1-bjorn.andersson@linaro.org> References: <20190131003933.11436-1-bjorn.andersson@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rajendra Nayak With rpmh ARC resources being modelled as power domains with performance state, we need to proxy vote on these for SDM845. Add support to vote on multiple of them, now that genpd supports associating mutliple power domains to a device. Tested-by: Sibi Sankar Reviewed-by: Sibi Sankar Signed-off-by: Rajendra Nayak [bjorn: Drop device link, improve error handling, name things "proxy"] Signed-off-by: Bjorn Andersson --- Changes since v4: - None Changes since v3: - Rebased upon latest remoteproc branch drivers/remoteproc/qcom_q6v5_mss.c | 119 +++++++++++++++++++++++++++-- 1 file changed, 114 insertions(+), 5 deletions(-) -- 2.18.0 diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c index 07d1cc52a647..c32c63e351a0 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include #include #include @@ -131,6 +133,7 @@ struct rproc_hexagon_res { char **proxy_clk_names; char **reset_clk_names; char **active_clk_names; + char **proxy_pd_names; int version; bool need_mem_protection; bool has_alt_reset; @@ -156,9 +159,11 @@ struct q6v5 { struct clk *active_clks[8]; struct clk *reset_clks[4]; struct clk *proxy_clks[4]; + struct device *proxy_pds[3]; int active_clk_count; int reset_clk_count; int proxy_clk_count; + int proxy_pd_count; struct reg_info active_regs[1]; struct reg_info proxy_regs[3]; @@ -321,6 +326,41 @@ static void q6v5_clk_disable(struct device *dev, clk_disable_unprepare(clks[i]); } +static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds, + size_t pd_count) +{ + int ret; + int i; + + for (i = 0; i < pd_count; i++) { + dev_pm_genpd_set_performance_state(pds[i], INT_MAX); + ret = pm_runtime_get_sync(pds[i]); + if (ret < 0) + goto unroll_pd_votes; + } + + return 0; + +unroll_pd_votes: + for (i--; i >= 0; i--) { + dev_pm_genpd_set_performance_state(pds[i], 0); + pm_runtime_put(pds[i]); + } + + return ret; +}; + +static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds, + size_t pd_count) +{ + int i; + + for (i = 0; i < pd_count; i++) { + dev_pm_genpd_set_performance_state(pds[i], 0); + pm_runtime_put(pds[i]); + } +} + static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm, bool remote_owner, phys_addr_t addr, size_t size) @@ -690,11 +730,17 @@ static int q6v5_mba_load(struct q6v5 *qproc) qcom_q6v5_prepare(&qproc->q6v5); + ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); + if (ret < 0) { + dev_err(qproc->dev, "failed to enable proxy power domains\n"); + goto disable_irqs; + } + ret = q6v5_regulator_enable(qproc, qproc->proxy_regs, qproc->proxy_reg_count); if (ret) { dev_err(qproc->dev, "failed to enable proxy supplies\n"); - goto disable_irqs; + goto disable_proxy_pds; } ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks, @@ -791,6 +837,8 @@ static int q6v5_mba_load(struct q6v5 *qproc) disable_proxy_reg: q6v5_regulator_disable(qproc, qproc->proxy_regs, qproc->proxy_reg_count); +disable_proxy_pds: + q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); disable_irqs: qcom_q6v5_unprepare(&qproc->q6v5); @@ -841,6 +889,8 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc) ret = qcom_q6v5_unprepare(&qproc->q6v5); if (ret) { + q6v5_pds_disable(qproc, qproc->proxy_pds, + qproc->proxy_pd_count); q6v5_clk_disable(qproc->dev, qproc->proxy_clks, qproc->proxy_clk_count); q6v5_regulator_disable(qproc, qproc->proxy_regs, @@ -1121,6 +1171,7 @@ static void qcom_msa_handover(struct qcom_q6v5 *q6v5) qproc->proxy_clk_count); q6v5_regulator_disable(qproc, qproc->proxy_regs, qproc->proxy_reg_count); + q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); } static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev) @@ -1181,6 +1232,45 @@ static int q6v5_init_clocks(struct device *dev, struct clk **clks, return i; } +static int q6v5_pds_attach(struct device *dev, struct device **devs, + char **pd_names) +{ + size_t num_pds = 0; + int ret; + int i; + + if (!pd_names) + return 0; + + while (pd_names[num_pds]) + num_pds++; + + for (i = 0; i < num_pds; i++) { + devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]); + if (IS_ERR(devs[i])) { + ret = PTR_ERR(devs[i]); + goto unroll_attach; + } + } + + return num_pds; + +unroll_attach: + for (i--; i >= 0; i--) + dev_pm_domain_detach(devs[i], false); + + return ret; +}; + +static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds, + size_t pd_count) +{ + int i; + + for (i = 0; i < pd_count; i++) + dev_pm_domain_detach(pds[i], false); +} + static int q6v5_init_reset(struct q6v5 *qproc) { qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev, @@ -1322,10 +1412,18 @@ static int q6v5_probe(struct platform_device *pdev) } qproc->active_reg_count = ret; + ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds, + desc->proxy_pd_names); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to init power domains\n"); + goto free_rproc; + } + qproc->proxy_pd_count = ret; + qproc->has_alt_reset = desc->has_alt_reset; ret = q6v5_init_reset(qproc); if (ret) - goto free_rproc; + goto detach_proxy_pds; qproc->version = desc->version; qproc->need_mem_protection = desc->need_mem_protection; @@ -1333,7 +1431,7 @@ static int q6v5_probe(struct platform_device *pdev) ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, qcom_msa_handover); if (ret) - goto free_rproc; + goto detach_proxy_pds; qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS); qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS); @@ -1343,15 +1441,17 @@ static int q6v5_probe(struct platform_device *pdev) qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12); if (IS_ERR(qproc->sysmon)) { ret = PTR_ERR(qproc->sysmon); - goto free_rproc; + goto detach_proxy_pds; } ret = rproc_add(rproc); if (ret) - goto free_rproc; + goto detach_proxy_pds; return 0; +detach_proxy_pds: + q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count); free_rproc: rproc_free(rproc); @@ -1368,6 +1468,9 @@ static int q6v5_remove(struct platform_device *pdev) qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev); qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev); qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev); + + q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count); + rproc_free(qproc->rproc); return 0; @@ -1392,6 +1495,12 @@ static const struct rproc_hexagon_res sdm845_mss = { "mnoc_axi", NULL }, + .proxy_pd_names = (char*[]){ + "cx", + "mx", + "mss", + NULL + }, .need_mem_protection = true, .has_alt_reset = true, .version = MSS_SDM845,