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[209.132.180.67]) by mx.google.com with ESMTP id 89si2914842pfr.242.2019.01.30.16.39.55; Wed, 30 Jan 2019 16:39:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HPzZ0xkt; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726783AbfAaAjy (ORCPT + 7 others); Wed, 30 Jan 2019 19:39:54 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:33964 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728394AbfAaAjw (ORCPT ); Wed, 30 Jan 2019 19:39:52 -0500 Received: by mail-pf1-f195.google.com with SMTP id h3so646860pfg.1 for ; Wed, 30 Jan 2019 16:39:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X9drpPMa6oVd5Osj3ji7IrS++uZ13uDxuVy5Mx8gZLY=; b=HPzZ0xktXeT9m0z6Y+Kc0NGCckMSJAEBmBSiDFcYWvHwLw/FjbZ7FmGvvEfUDu5tOQ gZ9wqUQJ5mIAYk0fdq77PpbUJ4Flf42eh2CaZryTe7ytkZ1ph9M14C9C5NL6cZLxgiEQ pQAJY+FTjQLgFoH8icULZAM/89lzEiejE/vDA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=X9drpPMa6oVd5Osj3ji7IrS++uZ13uDxuVy5Mx8gZLY=; b=lTHaj+/iDpxBs7+bDqMW7Lk4bg0bCPKjrLcEAvlfApKjOlQPS9jE2EynEbaGeHEQO6 MI09I27PZCewlXJksUcZyhIYSaInmqpeJuV+nvYItLX5ImiT7UuaqtEW8l6BPZu+TWsY dz7Yn5wb8XdEAdrb+XHFrx1t2/JZxnnlUlAOH6NUZz6+mPo8udOOvWzitWkt9Axv8Kgw odkb3YfwDe6QCJ4CG1MrMxCRUggQAz0j0VYoSXF49syBDySAWy2bNrS3EWsE/BQ2sjI9 UMsbOjlgK6fr0NpwJzUl0hAGfl/Swi9o9odNJif83P5w6t0TkZ//VV43EMX89wWNuIKr +H8w== X-Gm-Message-State: AJcUukcXQBTMKeffMWQCL0e1sxSCL1dh1wxbomWExL+F0JsxbymDSupu wC/j6H4ACSC0hTL6QMRlhjoJfQ== X-Received: by 2002:a63:4187:: with SMTP id o129mr27482466pga.370.1548895191885; Wed, 30 Jan 2019 16:39:51 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id k15sm4357928pfb.147.2019.01.30.16.39.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Jan 2019 16:39:50 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , Ohad Ben-Cohen , Arun Kumar Neelakantam , Sibi Sankar , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org Subject: [PATCH v5 01/10] arm64: dts: qcom: sdm845: Update reserved memory map Date: Wed, 30 Jan 2019 16:39:24 -0800 Message-Id: <20190131003933.11436-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190131003933.11436-1-bjorn.andersson@linaro.org> References: <20190131003933.11436-1-bjorn.andersson@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update existing and add missing regions to the reserved memory map, as described in version 10. Signed-off-by: Bjorn Andersson --- Changes since v4: - Labeled aop_mem, aop_cmd_db_mem and made tz_mem span the last TZ related segment Changes since v3: - Added hyp and xbl memory nodes. - Labeled all PIL nodes arch/arm64/boot/dts/qcom/sdm845.dtsi | 72 +++++++++++++++++++++++++--- 1 file changed, 66 insertions(+), 6 deletions(-) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 33f5f4ba6160..45b1616392aa 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -73,12 +73,22 @@ #size-cells = <2>; ranges; - memory@85fc0000 { + hyp_mem: memory@85700000 { + reg = <0x0 0x85700000 0 0x600000>; + no-map; + }; + + xbl_mem: memory@85e00000 { + reg = <0x0 0x85e00000 0 0x100000>; + no-map; + }; + + aop_mem: memory@85fc0000 { reg = <0 0x85fc0000 0 0x20000>; no-map; }; - memory@85fe0000 { + aop_cmd_db_mem: memory@85fe0000 { compatible = "qcom,cmd-db"; reg = <0x0 0x85fe0000 0x0 0x20000>; no-map; @@ -89,13 +99,43 @@ no-map; }; - memory@86200000 { - reg = <0 0x86200000 0 0x2d00000>; + tz_mem: memory@86200000 { + reg = <0 0x86200000 0 0x3c00000>; + no-map; + }; + + qseecom_mem: memory@8ab00000 { + reg = <0 0x8ab00000 0 0x1400000>; + no-map; + }; + + camera_mem: memory@8bf00000 { + reg = <0 0x8bf00000 0 0x500000>; + no-map; + }; + + ipa_fw_mem: memory@8c400000 { + reg = <0 0x8c400000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: memory@8c410000 { + reg = <0 0x8c410000 0 0x5000>; no-map; }; - wlan_msa_mem: memory@96700000 { - reg = <0 0x96700000 0 0x100000>; + gpu_mem: memory@8c415000 { + reg = <0 0x8c415000 0 0x2000>; + no-map; + }; + + adsp_mem: memory@8c500000 { + reg = <0 0x8c500000 0 0x1a00000>; + no-map; + }; + + wlan_msa_mem: memory@8df00000 { + reg = <0 0x8df00000 0 0x100000>; no-map; }; @@ -104,10 +144,30 @@ no-map; }; + venus_mem: memory@95800000 { + reg = <0 0x95800000 0 0x500000>; + no-map; + }; + + cdsp_mem: memory@95d00000 { + reg = <0 0x95d00000 0 0x800000>; + no-map; + }; + mba_region: memory@96500000 { reg = <0 0x96500000 0 0x200000>; no-map; }; + + slpi_mem: memory@96700000 { + reg = <0 0x96700000 0 0x1400000>; + no-map; + }; + + spss_mem: memory@97b00000 { + reg = <0 0x97b00000 0 0x100000>; + no-map; + }; }; cpus { From patchwork Thu Jan 31 00:39:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 157102 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp6587076jaa; Wed, 30 Jan 2019 16:40:29 -0800 (PST) X-Google-Smtp-Source: ALg8bN5jqWuFHcplSZB+h0snAoWCG6bbSfrpqOyPykON+QbA7D77LGcyt+vRG4xxhC0x6H6F0QT5 X-Received: by 2002:a62:3811:: with SMTP id f17mr33357231pfa.206.1548895229671; Wed, 30 Jan 2019 16:40:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548895229; cv=none; d=google.com; s=arc-20160816; b=pVhYFBOUNkfI1BHschIUofZ/Zw11QxeSPoMh4cAX5kZSugjo3OfZeh9FtAn1mIikSR meJ5b7Ekdf4He4e8MstJpa7OeIp7B/DKpL1PKD4Gi6SRLJ8Ccul7HK6pPigJUHBb52i9 WPyh02aJIFB65VkvdMXwA4b9UbxJ6ZZXwyIHCxnhVgEHRbg9vSgzGBh8azLpC6xSQcQd AMhvhkTsDu+9V1VEUulgLCZfuWX5KtCZYY6RMdYm9gDrSup7No9JvAUIFGrp3PMdocGk P1BjR4ZsCBSbwe8Su7D7qYzzOB6aXD4agkZeoFBUOxhm3Hg2lzBHPPdMl0jrLzu8qD32 pxVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=JJQe2lLdTM2hsTFb5II1fbwAeKRwdoCX1Mx+YzheR7s=; b=x3U/k0vRu3PaGrNw5GvsYppXTnfvXZHZusR4Ib3TzOG6xl4XYkZyvEnYNoygVA9rCv rPTAQoDsXiKAbIWAxzM7+QwTkTHPp59O+Rauk6xth7Y60Lnw/4B5T8DV1sq4P1vNuFDb urL60zul78VuaRlwhnCf6YjH5THYm4P4MaYWTVfEpuCeSeVSrL+M8fXfv4Rn3x3jsWbY n3zKECBwn+xV9ebnqHq6RMsO2aMpI74yE6x2Sn34ICl20pUHQyEPAgjda+OJ4YDh8Pmg jG7GWyeJFUKJBAnKwbGfSPLNhgLq71cylGNO3H9JfaDyNMo66+8wP6+kZhEp40IzJt6w A2gQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZfR6oWnI; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id k15sm4357928pfb.147.2019.01.30.16.39.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Jan 2019 16:39:55 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , Ohad Ben-Cohen , Arun Kumar Neelakantam , Sibi Sankar , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org Subject: [PATCH v5 04/10] dt-bindings: soc: qcom: Add AOSS QMP binding Date: Wed, 30 Jan 2019 16:39:27 -0800 Message-Id: <20190131003933.11436-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190131003933.11436-1-bjorn.andersson@linaro.org> References: <20190131003933.11436-1-bjorn.andersson@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding for the QMP based side-channel communication mechanism to the AOSS, which is used to control resources not exposed through the RPMh interface. Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson --- Changes since v4: - None Changes since v3: - Spelled out QMP .../bindings/soc/qcom/qcom,aoss-qmp.txt | 76 +++++++++++++++++++ include/dt-bindings/power/qcom-aoss-qmp.h | 15 ++++ 2 files changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt create mode 100644 include/dt-bindings/power/qcom-aoss-qmp.h -- 2.18.0 diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt new file mode 100644 index 000000000000..9ce6c42192ad --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt @@ -0,0 +1,76 @@ +Qualcomm Always-On Subsystem side channel binding + +This binding describes the hardware component responsible for side channel +requests to the always-on subsystem (AOSS), used for certain power management +requests that is not handled by the standard RPMh interface. Each client in the +SoC has it's own block of message RAM and IRQ for communication with the AOSS. +The protocol used to communicate in the message RAM is known as Qualcomm +Messagin Protocol (QMP) + +The AOSS side channel exposes control over a set of resources, used to control +a set of debug related clocks and to affect the low power state of resources +related to the secondary subsystems. These resources are exposed as a set of +power-domains. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdm845-aoss-qmp" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the message RAM for this + client's communication with the AOSS + +- interrupts: + Usage: required + Value type: + Definition: should specify the AOSS message IRQ for this client + +- mboxes: + Usage: required + Value type: + Definition: reference to the mailbox representing the outgoing doorbell + in APCS for this client, as described in mailbox/mailbox.txt + +- #power-domain-cells: + Usage: optional + Value type: + Definition: must be 1 + The provided power-domains are: + QDSS clock-domain (0), CDSP state (1), LPASS state (2), + modem state (3), SLPI state (4), SPSS state (5) and Venus + state (6). + += SUBNODES +The AOSS side channel also provides the controls for three cooling devices, +these are expressed as subnodes of the QMP node. The name of the node is used +to identify the resource and must therefor be "cx", "mx" or "ebi". + +- #cooling-cells: + Usage: optional + Value type: + Definition: must be 2 + += EXAMPLE + +The following example represents the AOSS side-channel message RAM and the +mechanism exposing the power-domains, as found in SDM845. + + aoss_qmp: qmp@c300000 { + compatible = "qcom,sdm845-aoss-qmp"; + reg = <0x0c300000 0x100000>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #power-domain-cells = <1>; + + cx_cdev: cx { + #cooling-cells = <2>; + }; + + mx_cdev: mx { + #cooling-cells = <2>; + }; + }; diff --git a/include/dt-bindings/power/qcom-aoss-qmp.h b/include/dt-bindings/power/qcom-aoss-qmp.h new file mode 100644 index 000000000000..7d8ac1a4f90c --- /dev/null +++ b/include/dt-bindings/power/qcom-aoss-qmp.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, Linaro Ltd. */ + +#ifndef __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H +#define __DT_BINDINGS_POWER_QCOM_AOSS_QMP_H + +#define AOSS_QMP_QDSS_CLK 0 +#define AOSS_QMP_LS_CDSP 1 +#define AOSS_QMP_LS_LPASS 2 +#define AOSS_QMP_LS_MODEM 3 +#define AOSS_QMP_LS_SLPI 4 +#define AOSS_QMP_LS_SPSS 5 +#define AOSS_QMP_LS_VENUS 6 + +#endif From patchwork Thu Jan 31 00:39:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 157098 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp6586761jaa; Wed, 30 Jan 2019 16:40:05 -0800 (PST) X-Google-Smtp-Source: ALg8bN4EYxUFkWdIsTi0diJZjOtC232PtyMZk6g4JnWcGovY+X+z2J4g5s8kyGY75TrqcKb+6X7c X-Received: by 2002:a63:a41:: with SMTP id z1mr29390131pgk.117.1548895205185; Wed, 30 Jan 2019 16:40:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548895205; cv=none; d=google.com; s=arc-20160816; b=b8isXXXwxeW3TYqrCx0ImyrLIIu0o3a98m2HG1u/opUJDbAqx0rQVG4GlxAe3Do0Ji jHMTQxHB7B7MMm8h9/sen82aumBnS3lgZytImcQwamXQy8mZjrqpERuXT+AFfNS78dUx MQzQtkqrz3tHHzKexPOsoLC3bKb2K2RczgGzmvMgIM+Mu0eo520UKDQ1u0XTWRVYP/tp BNhnSaovfeXGxlM+5gcQbPoX0Vx6byMix93uzfM4uNSXtGBh9TINnWz0nVpKWq/wdvnW VBiKXL2Iu+LbTkvfEHaXEsObQkdkea+zNswGhIUS84GM+O7I1fUOAmO/9kbNsq1462Qz j6dA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=ceyOt+Ii5BmCJVNixxOHlvttbK+fclQyqSbGF7lj+b0=; b=C6Ve4/wWqziwcB5cAQb0chzsZZTzrYXW7a15Nhn71Su0aAJ+PvHXwPpNB2qTUJ9QUj Q5JtYQKuSKcAvyq9jDgADQgMTDP4xINEGaW7xipuwt4Eu1VmjDHtDExJjfbX2Fgu+RP1 LAA2Pv5h13RtvMBqYUZaytDHaX3pkESd38wl48numotZyXq+zNSYZKP/4ebK30/uqM+U OVL/wHxGqpO7NgtIrCURfONDUPNMKO9XfHpNjc4e6DFJXd7yBXIG5yXIgWNUcbBNiw81 vBPn7oJm13SzN+zfAKIwCnMd83J6M5EgNN+DezZFDPp7qljoKGaxrcglJAFMRplVWDdQ 20AQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZnX9kKcE; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id k15sm4357928pfb.147.2019.01.30.16.40.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Jan 2019 16:40:01 -0800 (PST) From: Bjorn Andersson To: Ohad Ben-Cohen , Bjorn Andersson Cc: Andy Gross , David Brown , Rob Herring , Mark Rutland , Arun Kumar Neelakantam , Sibi Sankar , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org Subject: [PATCH v5 08/10] remoteproc: q6v5-mss: Active powerdomain for SDM845 Date: Wed, 30 Jan 2019 16:39:31 -0800 Message-Id: <20190131003933.11436-9-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190131003933.11436-1-bjorn.andersson@linaro.org> References: <20190131003933.11436-1-bjorn.andersson@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SDM845 MSS needs the load_state powerdomain voted for during the duration of the MSS being powered on, to let the AOSS know that it may not perform certain power save measures. So vote for this. Tested-by: Sibi Sankar Reviewed-by: Sibi Sankar Signed-off-by: Bjorn Andersson --- Changes since v4: - None Changes since v3: - None drivers/remoteproc/qcom_q6v5_mss.c | 31 ++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) -- 2.18.0 diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c index c32c63e351a0..e30f5486fd20 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -133,6 +133,7 @@ struct rproc_hexagon_res { char **proxy_clk_names; char **reset_clk_names; char **active_clk_names; + char **active_pd_names; char **proxy_pd_names; int version; bool need_mem_protection; @@ -159,10 +160,12 @@ struct q6v5 { struct clk *active_clks[8]; struct clk *reset_clks[4]; struct clk *proxy_clks[4]; + struct device *active_pds[1]; struct device *proxy_pds[3]; int active_clk_count; int reset_clk_count; int proxy_clk_count; + int active_pd_count; int proxy_pd_count; struct reg_info active_regs[1]; @@ -730,10 +733,16 @@ static int q6v5_mba_load(struct q6v5 *qproc) qcom_q6v5_prepare(&qproc->q6v5); + ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count); + if (ret < 0) { + dev_err(qproc->dev, "failed to enable active power domains\n"); + goto disable_irqs; + } + ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); if (ret < 0) { dev_err(qproc->dev, "failed to enable proxy power domains\n"); - goto disable_irqs; + goto disable_active_pds; } ret = q6v5_regulator_enable(qproc, qproc->proxy_regs, @@ -839,6 +848,8 @@ static int q6v5_mba_load(struct q6v5 *qproc) qproc->proxy_reg_count); disable_proxy_pds: q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count); +disable_active_pds: + q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count); disable_irqs: qcom_q6v5_unprepare(&qproc->q6v5); @@ -878,6 +889,7 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc) qproc->active_clk_count); q6v5_regulator_disable(qproc, qproc->active_regs, qproc->active_reg_count); + q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count); /* In case of failure or coredump scenario where reclaiming MBA memory * could not happen reclaim it here. @@ -1412,11 +1424,19 @@ static int q6v5_probe(struct platform_device *pdev) } qproc->active_reg_count = ret; + ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds, + desc->active_pd_names); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to attach active power domains\n"); + goto free_rproc; + } + qproc->active_pd_count = ret; + ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds, desc->proxy_pd_names); if (ret < 0) { dev_err(&pdev->dev, "Failed to init power domains\n"); - goto free_rproc; + goto detach_active_pds; } qproc->proxy_pd_count = ret; @@ -1452,6 +1472,8 @@ static int q6v5_probe(struct platform_device *pdev) detach_proxy_pds: q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count); +detach_active_pds: + q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count); free_rproc: rproc_free(rproc); @@ -1469,6 +1491,7 @@ static int q6v5_remove(struct platform_device *pdev) qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev); qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev); + q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count); q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count); rproc_free(qproc->rproc); @@ -1495,6 +1518,10 @@ static const struct rproc_hexagon_res sdm845_mss = { "mnoc_axi", NULL }, + .active_pd_names = (char*[]){ + "load_state", + NULL + }, .proxy_pd_names = (char*[]){ "cx", "mx", From patchwork Thu Jan 31 00:39:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 157099 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp6586775jaa; Wed, 30 Jan 2019 16:40:05 -0800 (PST) X-Google-Smtp-Source: ALg8bN5hWyOhRPssPJCvhm1Nl7WYzL8EFCozC/3Z4nVrvyCkAuUiUk0D+doGCJa4TE97kMOiWrsi X-Received: by 2002:a17:902:2887:: with SMTP id f7mr31895868plb.176.1548895205873; Wed, 30 Jan 2019 16:40:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548895205; cv=none; d=google.com; s=arc-20160816; b=x5at0m+5yByBaZXnIBJb/5H/JeH4E3o+DdH3loWlHJXLnhsSFqJVuAcq9IMntA8cGu 1wu+AlJfOdAfbzh+z6WIZ8p9CmQqRmayllAqJiiDk8EFHZSN0UoWGU0PTIe4Xe99J3+e sZT2itS6p8myny/GhRDtgyOIJ3D7GVfHRxzz4pq+0xAtHQ3VdaMMo887PplmTu739i8A gvjCl4jfx14pfmX+95RM7qUT1oYVNniHu6KqVAB4AvUV82yoMnkZG9uMLK68oK683Rde 0jKkorfsbth4Qp/RrveYhpwey1uPLSIcntI5ViZgtOVYxu9r0/lIknX6v3fVo5qRZXB5 b66g== ARC-Message-Signature: i=1; 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id k15sm4357928pfb.147.2019.01.30.16.40.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Jan 2019 16:40:02 -0800 (PST) From: Bjorn Andersson To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , Ohad Ben-Cohen , Arun Kumar Neelakantam , Sibi Sankar , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org Subject: [PATCH v5 09/10] arm64: dts: qcom: Add AOSS QMP node Date: Wed, 30 Jan 2019 16:39:32 -0800 Message-Id: <20190131003933.11436-10-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190131003933.11436-1-bjorn.andersson@linaro.org> References: <20190131003933.11436-1-bjorn.andersson@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The AOSS QMP provides a number of power domains, used for QDSS and PIL, add the node for this. Signed-off-by: Bjorn Andersson --- Changes since v4: - None Changes since v3: - None arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 07d9cd6fba7d..dc43fee8bb90 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -2076,6 +2077,15 @@ #reset-cells = <1>; }; + aoss_qmp: qmp@c300000 { + compatible = "qcom,sdm845-aoss-qmp"; + reg = <0 0x0c300000 0 0x100000>; + interrupts = ; + mboxes = <&apss_shared 0>; + + #power-domain-cells = <1>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>,