From patchwork Fri Jul 29 10:44:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 594431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DC8DC19F2D for ; Fri, 29 Jul 2022 10:45:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235713AbiG2Ko6 (ORCPT ); Fri, 29 Jul 2022 06:44:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233101AbiG2Ko5 (ORCPT ); Fri, 29 Jul 2022 06:44:57 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A40E8321F; Fri, 29 Jul 2022 03:44:54 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id EF54D6601B55; Fri, 29 Jul 2022 11:44:51 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1659091493; bh=g+LcCft8DaAa9BeWpNJbD1ov3XINszU+afPtdnzNVwE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UuLkRXbNOEtS+yPogV3R63b1wH6QZVeIf9Fz44BXMMQUk4ChORyyAYVBXhFTrYT+y /x+lY/0lg6luBq6l9rj+BTLNh+X+p7gYS5ehcMwCUaFYK/WE1fGmzBLn8CUTOp1lmM TFCGRVp0IQRJAWpveTh/qg4Spg93s5H5tkqdLcSRrAwAq87JAcrK6uq4xn+c5Tx8Rl ypwKYULbYpFL2Ue+JN9c9bTOxZ0cslT0JndPC0NSeqMfT0HtIt+s9FaVnr75zwbYJs pazkRs4/gFK1wjoQ63V3NFI60nOMUPJ3CQirf8qRRBHEpsA/lycnbyK8PDrhH9ak5j Z4uSN0yqnlPDg== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, fparent@baylibre.com, sam.shih@mediatek.com, sean.wang@mediatek.com, long.cheng@mediatek.com, wenbin.mei@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Subject: [PATCH 1/8] dt-bindings: dma: mediatek,uart-dma: Add binding for MT6795 SoC Date: Fri, 29 Jul 2022 12:44:33 +0200 Message-Id: <20220729104441.39177-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> References: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add mediatek,mt6795-uart-dma to the compatibles list to support the MT6795 Helio X10 SoC's UART APDMA. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml index 19ea8dcbcbce..9ab4d81ead35 100644 --- a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml +++ b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml @@ -22,6 +22,7 @@ properties: - items: - enum: - mediatek,mt2712-uart-dma + - mediatek,mt6795-uart-dma - mediatek,mt8365-uart-dma - mediatek,mt8516-uart-dma - const: mediatek,mt6577-uart-dma From patchwork Fri Jul 29 10:44:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 594430 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F0EFC25B0C for ; Fri, 29 Jul 2022 10:45:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231706AbiG2KpA (ORCPT ); Fri, 29 Jul 2022 06:45:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234698AbiG2Ko5 (ORCPT ); Fri, 29 Jul 2022 06:44:57 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78E8383222; Fri, 29 Jul 2022 03:44:55 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2DE3C6601B5B; Fri, 29 Jul 2022 11:44:53 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1659091494; bh=FjoMUwROjlB7ASGVOB0J6z6l9OQcUOCW/N0yhWPHg8c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JTTLJwKZozKdOax4mnSZj1zRid9azn4xnWvYLuiriwzApy5olMOYbMeRPWujTXxCA j0TWzrjZeqO8NuwizjAbvJMzFDjBd/bd2e7073MobSqCT1Ijo81DgIwW1zTkumyQ3v oTB2esiYJz438D0/6mppzZCJjz5xGbvh8wSkFQMkH8OG9QdIMhy75SXFo6hV1jq5Ka pjX8XXqlXnLmJJnSV3ySOvLOYjju4dHsFw7t/RKtYkHQqNPtk5ccLKuurUe+pS2fOE cZfn9Z+Llto+30h2RpEsTLQyAXUnWkMvijaV9fsX73aRHd7I0pOmUAklkB/giEe0Ts VYnIc74fgHJbw== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, fparent@baylibre.com, sam.shih@mediatek.com, sean.wang@mediatek.com, long.cheng@mediatek.com, wenbin.mei@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Subject: [PATCH 2/8] dt-bindings: mmc: Add compatible for MT6795 Helio X10 SoC Date: Fri, 29 Jul 2022 12:44:34 +0200 Message-Id: <20220729104441.39177-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> References: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add a compatible string for the MT6795 SoC's mtk-sd mmc controllers. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index be366cefffc2..e1ceefe0ae48 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -20,6 +20,7 @@ properties: - mediatek,mt2701-mmc - mediatek,mt2712-mmc - mediatek,mt6779-mmc + - mediatek,mt6795-mmc - mediatek,mt7620-mmc - mediatek,mt7622-mmc - mediatek,mt8135-mmc From patchwork Fri Jul 29 10:44:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 594428 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4524DC25B07 for ; Fri, 29 Jul 2022 10:45:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235803AbiG2KpC (ORCPT ); Fri, 29 Jul 2022 06:45:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235820AbiG2KpB (ORCPT ); Fri, 29 Jul 2022 06:45:01 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2507E83223; Fri, 29 Jul 2022 03:44:57 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 74E196601B66; Fri, 29 Jul 2022 11:44:54 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1659091495; bh=TA74QxJMdtjbhlYPI6ogd09Z8LzPo3IXxmpuJNWStt8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NAe69YGjki0F5pOABZw7N7isdxhWy81tV+oAU2rC2q+u/l4xSJGwvnjCmz1vPHpIa rA9bMPoiDIqNarvYBSJaH89J5/7EmB1GGp5PqlNLq50/TqwjV0xpb8BgfKuY6lnYX7 QdLPz6/pIeqlzMWxyTWaDtxuVu0MzsmP4nz/9vRi2myY3ZeZDiVbTuKvs3f5fMyK6H KyU89Xze+3VjsSa8BIW9kg7xQuXUyKFThy59ej1f6+AlP1SROSzIr0zE2958XJ735E 3JaxbkDq67zPK7JOVTSV0OfLEoE1N2VoBDoiRQDT2xAQc7moQV5TLNSlXL7kxh25aF eUcTq7GCvjw+w== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, fparent@baylibre.com, sam.shih@mediatek.com, sean.wang@mediatek.com, long.cheng@mediatek.com, wenbin.mei@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Subject: [PATCH 3/8] arm64: dts: mediatek: mt6795: Add topckgen, infra, peri clocks/resets Date: Fri, 29 Jul 2022 12:44:35 +0200 Message-Id: <20220729104441.39177-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> References: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add nodes for topckgen, infracfg and pericfg, providing various clocks and resets and needed to support basic IPs of this SoC. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 46f0e54be766..9166d481a366 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -192,6 +192,26 @@ soc { compatible = "simple-bus"; ranges; + topckgen: syscon@10000000 { + compatible = "mediatek,mt6795-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt6795-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt6795-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + pio: pinctrl@10005000 { compatible = "mediatek,mt6795-pinctrl"; reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; From patchwork Fri Jul 29 10:44:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 594603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52B6FC19F2B for ; Fri, 29 Jul 2022 10:45:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231218AbiG2KpA (ORCPT ); Fri, 29 Jul 2022 06:45:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235742AbiG2Ko7 (ORCPT ); Fri, 29 Jul 2022 06:44:59 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1171083211; Fri, 29 Jul 2022 03:44:58 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B1F976601B67; Fri, 29 Jul 2022 11:44:55 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1659091496; bh=yVmhhT/qx+tW3CwtsNMyM1l565LqcHdXD5WPr7UhHvw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IAY6rFWWe4TWdsu6dYjxm9mvBCzXlLn949L17cmUizMmPbLMDKq7fOdlugwx2wB/y FNWW4BNaZ1TsF32t3jztQX0+00XsR/OIJidBhdy4UCfnesSEcAmEjzWKerWBpvXZBX EfeRj9TNfW4pmDeBZ1MIv//2YQqu/dvlz1kcwg8qUy6aNbxpnvj0W1bJPOiAdCK8jT KBRqaEd3MjStG4xu5EPf252jg6ChlHcdcr3E7vL9Y0ZgfV5TtPWpOmkvnwopFULyGr dXdRWC1aWRQp+8zEvYnsHvHqdGkferWs4G6EzI8dWc74eRnWmSN8W0VgjW9x7ClXmG 4ztQmf85X8law== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, fparent@baylibre.com, sam.shih@mediatek.com, sean.wang@mediatek.com, long.cheng@mediatek.com, wenbin.mei@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Subject: [PATCH 4/8] arm64: dts: mediatek: mt6795: Replace UART dummy clocks with pericfg Date: Fri, 29 Jul 2022 12:44:36 +0200 Message-Id: <20220729104441.39177-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> References: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The UART nodes had a dummy clock for early bringup, as it is expected that these are left on by the bootloader: now that the pericfg clock controller is supported, we can replace them with the real clocks. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 9166d481a366..559fec1ee123 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -312,7 +312,8 @@ uart0: serial@11002000 { "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -321,7 +322,8 @@ uart1: serial@11003000 { "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = ; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -330,7 +332,8 @@ uart2: serial@11004000 { "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = ; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -339,7 +342,8 @@ uart3: serial@11005000 { "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = ; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; status = "disabled"; }; }; From patchwork Fri Jul 29 10:44:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 594429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CE58C28B2C for ; Fri, 29 Jul 2022 10:45:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235782AbiG2KpB (ORCPT ); Fri, 29 Jul 2022 06:45:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234856AbiG2KpA (ORCPT ); Fri, 29 Jul 2022 06:45:00 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 317BC8321F; Fri, 29 Jul 2022 03:44:59 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id F038D6601B68; Fri, 29 Jul 2022 11:44:56 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1659091498; bh=QeRJz0RuJnUHLQciSaPN8Icqa2P19dEJD9UBWVAvvwk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J28iktrnjebj17ZFhJh7/p44DmgfY9pGQY8X8C8WU8Eiejc0k0T7c8BedGhoxvRRu 8YwSCakgQI+YA1LsmHgzoPV3dX1RbyNJLIFiZOuViSXU2zkmsN9l+2CCLfAW2LNnQB PHPWXC13HqPdCER2bIzNZyoW9rRFt3MbbSvDY6n0/YKVZllb7Lq496FY7Nz3qnc9qQ TwC1N1ezKmYYHllHxx45eD0w8oqAMEx6qX6aokQZdDTMaHuwhemoG4CLpfrToXnP1p p8Z/9p8TrcJ8n/n8AdQSy9HzDSOAf2mdDMU/eskVyP4drSlnCHX4kuCvZVC+a01Rmd M5VM6U/dsZHEA== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, fparent@baylibre.com, sam.shih@mediatek.com, sean.wang@mediatek.com, long.cheng@mediatek.com, wenbin.mei@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Subject: [PATCH 5/8] arm64: dts: mediatek: mt6795: Add support for APDMA and wire up UART DMAs Date: Fri, 29 Jul 2022 12:44:37 +0200 Message-Id: <20220729104441.39177-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> References: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org This SoC has a DMA controller with tx/rx channels for all of the UART controller IPs: add the apdma node and wire up the DMAs on all controllers. When one of the UART controllers is used as a serial console, the DMA will be automatically ignored. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 559fec1ee123..687e0ee63503 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -314,6 +314,8 @@ uart0: serial@11002000 { interrupts = ; clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -324,9 +326,37 @@ uart1: serial@11003000 { interrupts = ; clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; + apdma: dma-controller@11000380 { + compatible = "mediatek,mt6795-uart-dma", + "mediatek,mt6577-uart-dma"; + reg = <0 0x11000380 0 0x60>, + <0 0x11000400 0 0x60>, + <0 0x11000480 0 0x60>, + <0 0x11000500 0 0x60>, + <0 0x11000580 0 0x60>, + <0 0x11000600 0 0x60>, + <0 0x11000680 0 0x60>, + <0 0x11000700 0 0x60>; + interrupts = , + , + , + , + , + , + , + ; + dma-requests = <8>; + clocks = <&pericfg CLK_PERI_AP_DMA>; + clock-names = "apdma"; + mediatek,dma-33bits; + #dma-cells = <1>; + }; + uart2: serial@11004000 { compatible = "mediatek,mt6795-uart", "mediatek,mt6577-uart"; @@ -334,6 +364,8 @@ uart2: serial@11004000 { interrupts = ; clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -344,6 +376,8 @@ uart3: serial@11005000 { interrupts = ; clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; clock-names = "baud", "bus"; + dmas = <&apdma 6>, <&apdma 7>; + dma-names = "tx", "rx"; status = "disabled"; }; }; From patchwork Fri Jul 29 10:44:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 594602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17F3FC2BBC5 for ; Fri, 29 Jul 2022 10:45:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235875AbiG2KpD (ORCPT ); Fri, 29 Jul 2022 06:45:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235856AbiG2KpB (ORCPT ); Fri, 29 Jul 2022 06:45:01 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B04DC83F19; Fri, 29 Jul 2022 03:45:00 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 3BEC66601B69; Fri, 29 Jul 2022 11:44:58 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1659091499; bh=FJUOyAwho3bbWQ8PWvLe4wxYoMHlf01l8/jYVjXf2r0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QWzukmMRpP7N16ie/C/7kSNSqJO07cZHNsvoFBDgJhi6Jjb4ih+LGXpW+zMgi6YPm yXEG0q1bVhbdTw4t12e8DySfifvBcCbnizCcFiOC5yi45hG9P4kn9+Y0ENLimm8C53 RRLXIpVmXy3Qk73sDFdkiSFB8ADTzIGo+VIasHg9KY7c1npOVBFSh1S3aXIFw8JH9h IcEIV0LLbzCdUtxCUZ4FLuuNywYyPAZ5ep8d8HAwvGd1vG/DvIZDQjxZkxIzQYVv5V nctcrZCXvoNSokM7OGhX4p7WnBHkPA48W3Sng1skXJGNpR4XQmD2IzRZigtGyTjkHg HpxjTnK7IDaNA== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, fparent@baylibre.com, sam.shih@mediatek.com, sean.wang@mediatek.com, long.cheng@mediatek.com, wenbin.mei@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Subject: [PATCH 6/8] arm64: dts: mediatek: mt6795: Add support for eMMC/SD/SDIO controllers Date: Fri, 29 Jul 2022 12:44:38 +0200 Message-Id: <20220729104441.39177-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> References: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add the mmc nodes to support all of the four controllers, used for eMMC, SD/MicroSD and SDIO storage. All of these controller nodes are left disabled by default, as usage is board dependent. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 687e0ee63503..2548bfcf9755 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -380,5 +380,46 @@ uart3: serial@11005000 { dma-names = "tx", "rx"; status = "disabled"; }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt6795-mmc", "mediatek,mt8173-mmc"; + reg = <0 0x11230000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_0>, + <&topckgen CLK_TOP_MSDC50_0_H_SEL>, + <&topckgen CLK_TOP_MSDC50_0_SEL>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt6795-mmc", "mediatek,mt8173-mmc"; + reg = <0 0x11240000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_1>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt6795-mmc", "mediatek,mt8173-mmc"; + reg = <0 0x11250000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_2>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc3: mmc@11260000 { + compatible = "mediatek,mt6795-mmc", "mediatek,mt8173-mmc"; + reg = <0 0x11260000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_3>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; }; }; From patchwork Fri Jul 29 10:44:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 594427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF5D8C25B0F for ; Fri, 29 Jul 2022 10:45:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235923AbiG2KpH (ORCPT ); Fri, 29 Jul 2022 06:45:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235871AbiG2KpD (ORCPT ); Fri, 29 Jul 2022 06:45:03 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5CA483F34; Fri, 29 Jul 2022 03:45:01 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 805A16601B6A; Fri, 29 Jul 2022 11:44:59 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1659091500; bh=0QqxLKrVrFujWkJ9DfNf1cxn6EG01MDTs5MXelKFVVI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SzrBYnrYJGRifz/98IYnmb50FiMX0iJ1APYI8Ev83ulPV5S1YgZdl9urEQa+hqsbb d1LGyLGyjbmrMgVT49tTGetbMvtA+Zy8FYqEKW70wuZW1gxpxpO4vEo2CHkbG1gEKS WUqpamW3QzPbfyY/zhbQx4C4Vp5k6bTWCV32XXnr6TT/a3gJW/kUKiqmcW39YeVN8J E6OR36oigizyIVlIxKbMLk5pgAYYg78X6XyoE/fByCty8wOlm7E9QPC68DTu5+6jqU V4pvaBQPukkf8VOAKGrQAXDgKPGt4+YI+P6oBh4VFWKVL34mPADF7VGhOaWv0ngNRr n7ACfawIluOQg== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, fparent@baylibre.com, sam.shih@mediatek.com, sean.wang@mediatek.com, long.cheng@mediatek.com, wenbin.mei@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Subject: [PATCH 7/7] arm64: dts: mediatek: Add support for MT6795 Sony Xperia M5 smartphone Date: Fri, 29 Jul 2022 12:44:39 +0200 Message-Id: <20220729104441.39177-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> References: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add a basic support for the Sony Xperia M5 (codename "Holly") smartphone, powered by a MediaTek Helio X10 SoC. This achieves a console boot. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt6795-sony-xperia-m5.dts | 90 +++++++++++++++++++ 2 files changed, 91 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index af362a085a02..72fd683c9264 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-sony-xperia-m5.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts new file mode 100644 index 000000000000..94d011c4126c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Collabora Ltd + * Author: AngeloGioacchino Del Regno + */ + +/dts-v1/; +#include "mt6795.dtsi" + +#include + +/ { + model = "Sony Xperia M5"; + compatible = "sony,xperia-m5", "mediatek,mt6795"; + chassis-type = "handset"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + serial0 = &uart0; + serial1 = &uart1; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1E800000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + no-map; + reg = <0 0x43000000 0 0x30000>; + }; + + /* preloader and bootloader regions cannot be touched */ + preloader-region@44800000 { + no-map; + reg = <0 0x44800000 0 0x100000>; + }; + + bootloader-region@46000000 { + no-map; + reg = <0 0x46000000 0 0x400000>; + }; + }; +}; + +&pio { + uart0_pins: uart0-pins { + pins-rx { + pinmux = ; + bias-pull-up; + input-enable; + }; + pins-tx { + pinmux = ; + output-high; + }; + }; + + uart2_pins: uart2-pins { + pins-rx { + pinmux = ; + bias-pull-up; + input-enable; + }; + pins-tx { + pinmux = ; + }; + }; +}; + +&uart0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; From patchwork Fri Jul 29 10:44:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 594600 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E17BC19F2C for ; Fri, 29 Jul 2022 10:45:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235937AbiG2KpL (ORCPT ); Fri, 29 Jul 2022 06:45:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235839AbiG2KpG (ORCPT ); Fri, 29 Jul 2022 06:45:06 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 653B783222; Fri, 29 Jul 2022 03:45:04 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 0CA486601B6D; Fri, 29 Jul 2022 11:45:02 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1659091503; bh=0QqxLKrVrFujWkJ9DfNf1cxn6EG01MDTs5MXelKFVVI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iT15RnhyxjpR5pnSE8GfqFPQeCidfxclnzPstf+2HMcwDU+HEh4piDVGsrFFs0G6z ozGBSuXB2g0umlDpsGVJEJi6TPMaFd83jzq1RoEQzJ6NVjIZLTulf5yy/Cg7hty7h4 GHAj+MJogHlxXjOgzo01tWd70HybWQysIvjXKbRDXPaP6JLMCm/+doqK5ba0a2Ckw3 e2Bq1imDDPkNTXAoUGS+aXAy0ASA4VpxHwVAiXmMoh+kSFTgkD5d5r525AYkW2SdKQ xI9zObLHtfrk03u7CGLsw/NwJCh6ICzAJrwSGm/VjxUh44D+v65v7LznhJAKH9hdZ9 AVkcOaCuHP64g== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, chaotian.jing@mediatek.com, ulf.hansson@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, fparent@baylibre.com, sam.shih@mediatek.com, sean.wang@mediatek.com, long.cheng@mediatek.com, wenbin.mei@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Subject: [PATCH 8/8] arm64: dts: mediatek: Add support for MT6795 Sony Xperia M5 smartphone Date: Fri, 29 Jul 2022 12:44:41 +0200 Message-Id: <20220729104441.39177-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> References: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add a basic support for the Sony Xperia M5 (codename "Holly") smartphone, powered by a MediaTek Helio X10 SoC. This achieves a console boot. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt6795-sony-xperia-m5.dts | 90 +++++++++++++++++++ 2 files changed, 91 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index af362a085a02..72fd683c9264 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-sony-xperia-m5.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts new file mode 100644 index 000000000000..94d011c4126c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Collabora Ltd + * Author: AngeloGioacchino Del Regno + */ + +/dts-v1/; +#include "mt6795.dtsi" + +#include + +/ { + model = "Sony Xperia M5"; + compatible = "sony,xperia-m5", "mediatek,mt6795"; + chassis-type = "handset"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + serial0 = &uart0; + serial1 = &uart1; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1E800000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + no-map; + reg = <0 0x43000000 0 0x30000>; + }; + + /* preloader and bootloader regions cannot be touched */ + preloader-region@44800000 { + no-map; + reg = <0 0x44800000 0 0x100000>; + }; + + bootloader-region@46000000 { + no-map; + reg = <0 0x46000000 0 0x400000>; + }; + }; +}; + +&pio { + uart0_pins: uart0-pins { + pins-rx { + pinmux = ; + bias-pull-up; + input-enable; + }; + pins-tx { + pinmux = ; + output-high; + }; + }; + + uart2_pins: uart2-pins { + pins-rx { + pinmux = ; + bias-pull-up; + input-enable; + }; + pins-tx { + pinmux = ; + }; + }; +}; + +&uart0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +};