From patchwork Wed Jan 30 17:35:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 157078 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp6218381jaa; Wed, 30 Jan 2019 09:42:49 -0800 (PST) X-Google-Smtp-Source: ALg8bN6DVvftnNSYOlsRCuKqn9NW5cvFzng3U0rk3fl807sSsNI0c3eXu3hj8BBqykjSbHnhLw3D X-Received: by 2002:a25:b6c8:: with SMTP id f8mr29906407ybm.430.1548870169375; Wed, 30 Jan 2019 09:42:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548870169; cv=none; d=google.com; s=arc-20160816; b=xSs/vOybntFmxMXU3UA/5ch8IZ+gn+BuNDLjM6YXzHcwOfuVtZoZeTatJslyqQejVJ V2AhU2IRWG7NnfbXTIiguv/phqpTvbapb8hjEbQ8YKyk/eqNV2THxtFCVHURawHuLxwE GWKDbHAjSoiYfci4XQqOLqRZsddCgqS6YJk98cv+tuO/tJsVM2m9IBDBdtw6IZwMrdjE BOTmReoJfSO5lkc+BIYOp0AQMd6gbkW0FlZyAdAimgegTYb7pTO8OMHB+pgg4mkZiIH9 EBzXjiExzid2pllFTwP3BdFln8t640gaXb+Pbxje/FpIaAVlDv8M/XS8nAwfcJpSFrPT CzPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:to:from:references :in-reply-to:message-id:date:dkim-signature; bh=z6Oe5++7//00+8jf3KOesDxKK2wIxkTBsez1SGK1Kro=; b=hC491HdlmnRwqb/9IaHWObbmTTr+YrC3SeXkSyAhtdKxhN7y9C8Fm8YBa+PMqRFLlN C3IXPBRfu3jJSTG7gOkteNpTLRidnragQ9/4NCzSGovc/aWaNc6D+LnT11NfurtVO2kg m2wTLnH2hD/CLaLDYYqLA2iKNuBlwVXrm0iN2El7N8zihDGs9vdNhRIoripwj/s7EiXA KRds0Dx7EbEeUcFOEKU9fMY0FlujJlB8vmomRjV8RBcxZ4K4Zc5fbYsyoexZVtrigN6a nIkAsBJPC9ViwSRKknTa7fEbobqPRf5eliccVXTXUYY2ZkvHfGul5kRghnPeP+QGwBWQ 2etw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@sifive.com header.s=google header.b=nRfzzAnk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c124si1220329ywf.270.2019.01.30.09.42.49 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 30 Jan 2019 09:42:49 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@sifive.com header.s=google header.b=nRfzzAnk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([127.0.0.1]:41898 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gotsu-0000bo-TL for patch@linaro.org; Wed, 30 Jan 2019 12:42:48 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38440) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gotn6-0004gY-N1 for qemu-devel@nongnu.org; Wed, 30 Jan 2019 12:36:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gotn4-00007P-7O for qemu-devel@nongnu.org; Wed, 30 Jan 2019 12:36:47 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:36878) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gotn3-0008LX-VS for qemu-devel@nongnu.org; Wed, 30 Jan 2019 12:36:46 -0500 Received: by mail-pl1-x62c.google.com with SMTP id b5so139199plr.4 for ; Wed, 30 Jan 2019 09:36:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=z6Oe5++7//00+8jf3KOesDxKK2wIxkTBsez1SGK1Kro=; b=nRfzzAnkouDPf2j8nlOXvdxjBjsytYVjH1HZJbUb0ju2YicxBUsJwJiZX5saYhFdIi /9FGP0Q/WKWeOiiFoeNGIRcRXfgTF0vERsD4Zrwh2ODsy2KXv0kq9g71XJXYR4m/VoAD +6pEYLJ+gAcsSnpbokU0kxIbf7IIQBU1X3pwb8yY2s4ZsWpbOyV16ew4bp+r6vuGWtT7 py91UD67VWu1nDHGvqKtnCePXv97ZS4nnDmIqerlU2Hm3nFsMQALI3tSln43jY+uug+V Wef/bUvp0tUV+QdQVHjw82LRBTVYflX4T4L5klG6ZUAmdmHRikuFfENsSsJgHRiqPcdh 2t0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=z6Oe5++7//00+8jf3KOesDxKK2wIxkTBsez1SGK1Kro=; b=Aca7Y6YGlsSvESO9bX37Pui+4KPhlxOzqgSyUBUhIFh3dM4O4ZlUQjHm4ahY6x7trC yabm2PdWtKjqKXYh29e6iPwMM4R9/qBpNCBqoDeu33kMWL+e6rEg0S/6gQyPSXPF9K/K Vpi++Dk7iGThEYNKKt9rvUcfVLX6iYrfYgBoob8SkyMyzn/hxqlNSr4hUBroLvIyHxNu 3LgvNdRXcFyFsXutuY1zU1KOf9qmPtc3ZN/vtB9LSd99CCZPByfXPl6IOhk8iKd2E7p7 SMjoeCTuadv9ppWBXef17z0QGQVEoMcZkMF7EH0KxywjNHcjIpuqShiGFGPuzAXZ23wK aLQg== X-Gm-Message-State: AJcUukebp5QZcCg3dingmV+px4Tat0d9zLnFz27z5LBDZCB5g5tWIcAk dRmQEAH27fEoLQ91qqSXw+Go7jr3bfs= X-Received: by 2002:a17:902:5a86:: with SMTP id r6mr30174442pli.301.1548869776430; Wed, 30 Jan 2019 09:36:16 -0800 (PST) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id j21sm3409734pfn.175.2019.01.30.09.36.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Jan 2019 09:36:15 -0800 (PST) Date: Wed, 30 Jan 2019 09:35:52 -0800 Message-Id: <20190130173601.3268-2-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20190130173601.3268-1-palmer@sifive.com> References: <20190130173601.3268-1-palmer@sifive.com> From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62c Subject: [Qemu-devel] [PULL 01/10] RISC-V: Split out mstatus_fs from tb_flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Michael Clark , Richard Henderson , qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Michael Clark Reviewed-by: Michael Clark Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 6 +++--- target/riscv/translate.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) -- 2.18.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 743f02c8b95a..681341f5d5a4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -275,8 +275,8 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env, target_ulong cpu_riscv_get_fflags(CPURISCVState *env); void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong); -#define TB_FLAGS_MMU_MASK 3 -#define TB_FLAGS_FP_ENABLE MSTATUS_FS +#define TB_FLAGS_MMU_MASK 3 +#define TB_FLAGS_MSTATUS_FS MSTATUS_FS static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) @@ -284,7 +284,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; #ifdef CONFIG_USER_ONLY - *flags = TB_FLAGS_FP_ENABLE; + *flags = TB_FLAGS_MSTATUS_FS; #else *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 312bf298b3c2..3d07d651b60c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -44,7 +44,7 @@ typedef struct DisasContext { /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; uint32_t opcode; - uint32_t flags; + uint32_t mstatus_fs; uint32_t mem_idx; /* Remember the rounding mode encoded in the previous fp instruction, which we have already installed into env->fp_status. Or -1 for @@ -656,7 +656,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, { TCGv t0; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { gen_exception_illegal(ctx); return; } @@ -686,7 +686,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, { TCGv t0; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { gen_exception_illegal(ctx); return; } @@ -945,7 +945,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, { TCGv t0 = NULL; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { goto do_illegal; } @@ -1818,8 +1818,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) DisasContext *ctx = container_of(dcbase, DisasContext, base); ctx->pc_succ_insn = ctx->base.pc_first; - ctx->flags = ctx->base.tb->flags; ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; + ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; ctx->frm = -1; /* unknown rounding mode */ } From patchwork Wed Jan 30 17:35:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 157077 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp6213061jaa; Wed, 30 Jan 2019 09:37:13 -0800 (PST) X-Google-Smtp-Source: ALg8bN6lkLz3BaDx+r0WJP4pth5rXz6FDdzaIICUl2TkNe8BzAOtIAKJbfExILFXJYDBqsVd9E3G X-Received: by 2002:a81:27c9:: with SMTP id n192mr29615185ywn.504.1548869833632; Wed, 30 Jan 2019 09:37:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548869833; cv=none; d=google.com; s=arc-20160816; b=c3x9sKThCj9tHiv0ew6HSC/QmScImq7bcqZrT/N+kfcT37Jq+6HLsM9BQ+5UR0FxZS eb8+wOIl9aNXGjZso9sL/9K66aH/bw22UKOplvvxoyv9Sfqnegrjn7eroS0eI+cAdfln oqm+av9XHqlkiFTGCQxeKScmbSXH+yRVf1XmxIx3hC86+n3j7OtsMbPIN+VHE0SRW37y lUlp10HFeiXPatxZrNVi93B08h5Gi4NghZ4sueI87DNzmvy4T0IKMi1f/BMyXB0Xu7W7 HuLqQiRRV+MXlA+kGfOwP4nbeitVO/m9dbba2dhQfEKUtT4s7iQcOsGe5Cb6IEPTIiUN lBUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:to:from:references :in-reply-to:message-id:date:dkim-signature; bh=m3QyX5GKKen9C2A//gm0itW+Zbw+s4kREoS0dubIg4I=; b=iuIF1e7alcxSiUmevf9fjAjI1+YP9+2SvWUDgWZJxKq7SgoLZ8pXRxXV8buQSJgx1Q zymLEknSEtpvxam12U5A2MSyVrUyRxxYC/SOy9fA+ANJLJ0aKars0dMctEcZlL3wdfYg t948lvhbIoJ5CuTO10WIQBp8LYCV0G9ZNBk2PFdTT5nNQXIbCjWG6Sb4KPIH+6quMnYZ SfhPV0zV2jARUgKj8AU5NhLwPs1dSiE6N+nvnjT/qKd5v+Mf54MLbfCrqiCd8JwCl5DQ OvCiqTQnG6l29eUQJxlEJurpFrwuUD5qDL/pH1r9iFID5WY9Gn+KptkBMicClwBAgQ+g icWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@sifive.com header.s=google header.b=bCst0i9M; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::531 Subject: [Qemu-devel] [PULL 02/10] RISC-V: Mark mstatus.fs dirty X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Michael Clark , Richard Henderson , qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Modifed from Richard Henderson's patch [1] to integrate with the new control and status register implementation. [1] https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg07034.html Note: the f* CSRs already mark mstatus.FS dirty using env->mstatus |= mstatus.FS so the bug in the first spin of this patch has been fixed in a prior commit. Signed-off-by: Michael Clark Reviewed-by: Michael Clark Signed-off-by: Alistair Francis Co-authored-by: Richard Henderson Co-authored-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 12 ------------ target/riscv/translate.c | 40 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 39 insertions(+), 13 deletions(-) -- 2.18.1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5e7e7d16b8b5..571414768992 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -317,18 +317,6 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) mstatus = (mstatus & ~mask) | (val & mask); - /* Note: this is a workaround for an issue where mstatus.FS - does not report dirty after floating point operations - that modify floating point state. This workaround is - technically compliant with the RISC-V Privileged - specification as it is legal to return only off, or dirty. - at the expense of extra floating point save/restore. */ - - /* FP is always dirty or off */ - if (mstatus & MSTATUS_FS) { - mstatus |= MSTATUS_FS; - } - int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | ((mstatus & MSTATUS_XS) == MSTATUS_XS); mstatus = set_field(mstatus, MSTATUS_SD, dirty); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3d07d651b60c..0581b3c1f7d7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -651,6 +651,31 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, tcg_temp_free(dat); } +#ifndef CONFIG_USER_ONLY +/* The states of mstatus_fs are: + * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty + * We will have already diagnosed disabled state, + * and need to turn initial/clean into dirty. + */ +static void mark_fs_dirty(DisasContext *ctx) +{ + TCGv tmp; + if (ctx->mstatus_fs == MSTATUS_FS) { + return; + } + /* Remember the state change for the rest of the TB. */ + ctx->mstatus_fs = MSTATUS_FS; + + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_temp_free(tmp); +} +#else +static inline void mark_fs_dirty(DisasContext *ctx) { } +#endif + static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, target_long imm) { @@ -679,6 +704,8 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, break; } tcg_temp_free(t0); + + mark_fs_dirty(ctx); } static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, @@ -944,6 +971,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1, int rs2, int rm) { TCGv t0 = NULL; + bool fp_output = true; if (ctx->mstatus_fs == 0) { goto do_illegal; @@ -1006,6 +1034,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_W_S: @@ -1035,6 +1064,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_S_W: @@ -1085,6 +1115,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FMV_S_X: @@ -1177,6 +1208,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_W_D: @@ -1206,6 +1238,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_D_W: @@ -1254,6 +1287,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, default: goto do_illegal; } + fp_output = false; break; #if defined(TARGET_RISCV64) @@ -1271,7 +1305,11 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, tcg_temp_free(t0); } gen_exception_illegal(ctx); - break; + return; + } + + if (fp_output) { + mark_fs_dirty(ctx); } }