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Wed, 27 Jul 2022 15:06:12 +0900 (KST) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas2p3.samsung.com (KnoxPortal) with ESMTPA id 20220727060612epcas2p355e7f9ca3700cad4778e944cbdbf2d50~Fmo4GIq8a1065410654epcas2p35; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20220727060612epsmtrp2afb298f10c3de36e2af79f2c4e5d3bfa~Fmo4EPVt72781327813epsmtrp2z; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) X-AuditID: b6c32a47-5f7ff700000025aa-c3-62e0d5d4f2d2 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 41.50.08802.4D5D0E26; Wed, 27 Jul 2022 15:06:12 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220727060612epsmtip192d252485799370b0828d5fb9f19fdea~Fmo32WL6B2680226802epsmtip1S; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) From: Chanho Park To: Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Krzysztof Kozlowski , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski Cc: Sam Protsenko , Alim Akhtar , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCH 1/6] dt-bindings: clk: exynosautov9: add fys0 clock definitions Date: Wed, 27 Jul 2022 15:01:41 +0900 Message-Id: <20220727060146.9228-2-chanho61.park@samsung.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220727060146.9228-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrDJsWRmVeSWpSXmKPExsWy7bCmqe6Vqw+SDM48M7d4MG8bm8Xl/doW 1788Z7WYf+Qcq0Xfi4fMFntfb2W32PT4GqvFx557rBYzzu9jsrh4ytWide8RdovDb9pZLf5d 28hi8bwPKL5q1x9GB36P9zda2T12zrrL7rFpVSebx51re9g8Ni+p9+jbsorR4/MmuQD2qGyb jNTElNQihdS85PyUzLx0WyXv4HjneFMzA0NdQ0sLcyWFvMTcVFslF58AXbfMHKCrlRTKEnNK gUIBicXFSvp2NkX5pSWpChn5xSW2SqkFKTkF5gV6xYm5xaV56Xp5qSVWhgYGRqZAhQnZGauX z2Qq+C5ccXbfIsYGxpeCXYycHBICJhKrTz9m62Lk4hAS2MEocW7eGyYI5xOjxK4l65ghnM+M Ev2NU9lhWr6cfscOkdjFKPFiZQ9YQkjgI6PEo3d6IDabgK7EluevGEGKRAQeM0kcPtIGtoRZ oI1JYtqzjawgVcICgRI/H59gA7FZBFQlvhxqYQGxeQVsJfre7meBWCcvcf1mGzOIzSlgJ7Fj zU4miBpBiZMzn4DVMAPVNG+dDXarhMBaDolTp7ZBNbtIbFt3mxnCFpZ4dXwL1A9SEp/f7WWD sIslls76xATR3MAocXnbL6iEscSsZ+1AP3AAbdCUWL9LH8SUEFCWOHILai+fRMfhv+wQYV6J jjYhiEZ1iQPbp0NdICvRPeczK4TtIdH2aSULJLAmMkpMehk4gVFhFpJvZiH5ZhbC3gWMzKsY xVILinPTU4uNCozhUZycn7uJEZyMtdx3MM54+0HvECMTB+MhRgkOZiUR3oTo+0lCvCmJlVWp RfnxRaU5qcWHGE2BYT2RWUo0OR+YD/JK4g1NLA1MzMwMzY1MDcyVxHm9UjYkCgmkJ5akZqem FqQWwfQxcXBKNTCJ2wa/N2CQjn85/a/uszKJhIAmeYuu2q2zX5rYbVV6NYd/45of3PdWdzt9 PsN1kJeJeUniJL7DS5V0pm77+qvsVlmHhuWWSV6h1aXObq9LyyS/Bv69HeQp9NyuYIqA7vNS cffHBxyTxNn3q/3/L168dZNtYfW+10J5DoEa+RNTz67k8+laxiWdvKMte/n05erys4qlPHJl XrOe+7hjlaLFAfNcp98qSaffvtvVuoFn7o7gjLW8Nqfz5nlGh0w6vdLR7cLF8nescqlPFHbb uHj67j+v9ta8aW7Lrxl8fU+LDTwbIp4/vC1R+tgmLVRrQ5Sy2DoLP8NzvexPPkv7X2U+nBlk dGgy5ytdPqGCp0osxRmJhlrMRcWJAH670P9PBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBLMWRmVeSWpSXmKPExsWy7bCSnO6Vqw+SDOb8F7d4MG8bm8Xl/doW 1788Z7WYf+Qcq0Xfi4fMFntfb2W32PT4GqvFx557rBYzzu9jsrh4ytWide8RdovDb9pZLf5d 28hi8bwPKL5q1x9GB36P9zda2T12zrrL7rFpVSebx51re9g8Ni+p9+jbsorR4/MmuQD2KC6b lNSczLLUIn27BK6M1ctnMhV8F644u28RYwPjS8EuRk4OCQETiS+n37F3MXJxCAnsYJT4+mQV M0RCVuLZux3sELawxP2WI6wQRe8ZJdZs3QRWxCagK7Hl+StGkISIwHMmiSkrDoI5zAJdTBJ3 2j6BtQsL+EtsPP+IDcRmEVCV+HKohQXE5hWwleh7u58FYoW8xPWbbWBTOQXsJHas2ckEYgsB 1cx81QRVLyhxcuYTMJsZqL5562zmCYwCs5CkZiFJLWBkWsUomVpQnJueW2xYYJSXWq5XnJhb XJqXrpecn7uJERw5Wlo7GPes+qB3iJGJg/EQowQHs5IIb0L0/SQh3pTEyqrUovz4otKc1OJD jNIcLErivBe6TsYLCaQnlqRmp6YWpBbBZJk4OKUamOxnKOy1ZL/dKl30NVTUqfSzAeuKeQe6 5sQk2P/8JZ+qdfZj2tfVghf288ftKVbw1P+u9vTqioPff+habl128WZJtbVyQlWzy4aLN7YI Fz6ZFX3bM1ro6V/3TAX998F2S0zVJ8/8u2NrzNwVWi+NnVyu3dFat2mjspbuQpuCc3wWTyYL GTgVMzJ3zWie2cBxXPtu9NdnLQ5c7wREdcRM8gNn21nmXf6/wdTg9tEvLF9P2/OZB5fzxDE7 Bx6uvavTeidpgbTxvW8LnBf/7n8kdOLvzWPz734rr5v5yqr5/Y31c2awiaU5u/gan30ac3nG 5R/S61NPBypdbRHMk55/qai2+tf8lYzqbUKT13xv8FViKc5INNRiLipOBAD7+/LgCwMAAA== X-CMS-MailID: 20220727060612epcas2p355e7f9ca3700cad4778e944cbdbf2d50 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220727060612epcas2p355e7f9ca3700cad4778e944cbdbf2d50 References: <20220727060146.9228-1-chanho61.park@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add fsys0(for PCIe) clock definitions. Signed-off-by: Chanho Park Acked-by: Chanwoo Choi Acked-by: Krzysztof Kozlowski --- .../dt-bindings/clock/samsung,exynosautov9.h | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h index ea9f91b4eb1a..6305a84396ce 100644 --- a/include/dt-bindings/clock/samsung,exynosautov9.h +++ b/include/dt-bindings/clock/samsung,exynosautov9.h @@ -185,6 +185,49 @@ #define CORE_NR_CLK 6 +/* CMU_FSYS0 */ +#define CLK_MOUT_FSYS0_BUS_USER 1 +#define CLK_MOUT_FSYS0_PCIE_USER 2 +#define CLK_GOUT_FSYS0_BUS_PCLK 3 + +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK 4 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK 5 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK 6 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK 7 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK 8 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK 9 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK 10 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK 11 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_PIPE_CLK 12 +#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK 13 +#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK 14 + +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK 15 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK 16 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK 17 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK 18 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK 19 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK 20 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK 21 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK 22 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_PIPE_CLK 23 +#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK 24 +#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK 25 + +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK 26 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK 27 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK 28 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK 29 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK 30 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK 31 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK 32 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK 33 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_PIPE_CLK 34 +#define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK 35 +#define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK 36 + +#define FSYS0_NR_CLK 37 + /* CMU_FSYS2 */ #define CLK_MOUT_FSYS2_BUS_USER 1 #define CLK_MOUT_FSYS2_UFS_EMBD_USER 2 From patchwork Wed Jul 27 06:01:42 2022 Content-Type: text/plain; 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Wed, 27 Jul 2022 15:06:13 +0900 (KST) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas2p3.samsung.com (KnoxPortal) with ESMTPA id 20220727060612epcas2p34e861279ece7fbd3c7c87ce02c7d795c~Fmo4IE9ux1302313023epcas2p3Y; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20220727060612epsmtrp29d5b3647de825907be6df8843b263fa8~Fmo4HM_7a2776027760epsmtrp2D; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) X-AuditID: b6c32a47-dff43a80000025aa-c4-62e0d5d4a6d1 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 20.EB.08905.4D5D0E26; Wed, 27 Jul 2022 15:06:12 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220727060612epsmtip19856a6dc2d80f9c20e7910e43548404e~Fmo36-Ipi2960929609epsmtip1M; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) From: Chanho Park To: Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Krzysztof Kozlowski , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski Cc: Sam Protsenko , Alim Akhtar , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCH 2/6] dt-bindings: clock: exynosautov9: add fsys1 clock definitions Date: Wed, 27 Jul 2022 15:01:42 +0900 Message-Id: <20220727060146.9228-3-chanho61.park@samsung.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220727060146.9228-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrDJsWRmVeSWpSXmKPExsWy7bCmqe7Vqw+SDK50MFo8mLeNzeLyfm2L 61+es1rMP3KO1aLvxUNmi72vt7JbbHp8jdXiY889VosZ5/cxWVw85WrRuvcIu8XhN+2sFv+u bWSxeN4HFF+16w+jA7/H+xut7B47Z91l99i0qpPN4861PWwem5fUe/RtWcXo8XmTXAB7VLZN RmpiSmqRQmpecn5KZl66rZJ3cLxzvKmZgaGuoaWFuZJCXmJuqq2Si0+ArltmDtDVSgpliTml QKGAxOJiJX07m6L80pJUhYz84hJbpdSClJwC8wK94sTc4tK8dL281BIrQwMDI1OgwoTsjJdz jrAULOWumPj/GHMD4y3OLkZODgkBE4lTJw6xdDFycQgJ7GCUWDnnERuE84lR4uPkuewQzjdG iWm7zjDDtJxvXMIIkdjLKPHz+kt2kISQwEdGiesvZEBsNgFdiS3PX4EViQg8ZpI4fKQNbC6z QBuTxLRnG1lBqoQFQiRuTnjEBGKzCKhKvLn8CGgSBwevgK3EobXiENvkJa7fbAPbzClgJ7Fj zU6wcl4BQYmTM5+wgNjMQDXNW2czg8yXEFjLIfHv0RZGiGYXiTvvzrBB2MISr45vYYewpSQ+ v9sLFS+WWDrrExNEcwOjxOVtv6ASxhKznrUzghzELKApsX6XPogpIaAsceQW1F4+iY7Df9kh wrwSHW1CEI3qEge2T2eBsGUluud8ZoWwPSRWHF/ICgm4iYwS3xousUxgVJiF5J1ZSN6ZhbB4 ASPzKkax1ILi3PTUYqMCY3gUJ+fnbmIEJ2Mt9x2MM95+0DvEyMTBeIhRgoNZSYQ3Ifp+khBv SmJlVWpRfnxRaU5q8SFGU2BYT2SWEk3OB+aDvJJ4QxNLAxMzM0NzI1MDcyVxXq+UDYlCAumJ JanZqakFqUUwfUwcnFINTOXvlLfvS09jnPTg6YHuw3udX4mLbD+R988s94nww3yHH++7pszl u7lQfE5aDNfl5litOX3BRhNsNz2YpHQ93Sw4OnZTk2EXq//hv6dFK//e1HwpZB1qeXNy2NOk Buf3rN+b/RjaQ/031/l+zM+On8217Ur3Rd3YiVs5P3sUcbG2uXL2WMbVLf+8pSE2s9y8/M3s xzFxJtU8d62zxc8u+79+tfjRZ1x9hn3S9wKOXTis9OzYjAkTN2tu5JgVfTt9zy/n+rs3vbnO 9BkYJZUfk3C+21/IHq+7pPW3bUKRu/PS76l3b0evdd57eBG7ZmOj3fPgU83xwWLHDGPmfY+J YdZ1tnTcf2rG6zLhU4+PKrEUZyQaajEXFScCABpOU15PBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrOLMWRmVeSWpSXmKPExsWy7bCSnO6Vqw+SDFa/krF4MG8bm8Xl/doW 1788Z7WYf+Qcq0Xfi4fMFntfb2W32PT4GqvFx557rBYzzu9jsrh4ytWide8RdovDb9pZLf5d 28hi8bwPKL5q1x9GB36P9zda2T12zrrL7rFpVSebx51re9g8Ni+p9+jbsorR4/MmuQD2KC6b lNSczLLUIn27BK6Ml3OOsBQs5a6Y+P8YcwPjLc4uRk4OCQETifONSxi7GLk4hAR2M0rs2v+U BSIhK/Hs3Q52CFtY4n7LEVaIoveMEuuXbgdLsAnoSmx5/gqsW0TgOZPElBUHwRxmgS4miTtt n8CqhAWCJN48msUIYrMIqEq8ufwIKM7BwStgK3ForTjEBnmJ6zfbmEFsTgE7iR1rdjKB2EJA JTNfNYFdxCsgKHFy5hMwmxmovnnrbOYJjAKzkKRmIUktYGRaxSiZWlCcm55bbFhgmJdarlec mFtcmpeul5yfu4kRHDdamjsYt6/6oHeIkYmD8RCjBAezkghvQvT9JCHelMTKqtSi/Pii0pzU 4kOM0hwsSuK8F7pOxgsJpCeWpGanphakFsFkmTg4pRqYZC6JXv2/zrjqoItx10wBsWvv0vPm HunV4Ep8flPGN/qYMYPWj1nHmPrfa+4918359Gx7IlvzZye+r9zhAZtf7FdcWLtT8qMms6nS mV8SHddeu674s3qD0aFX0m+9v+wId7YquSf+iJPjR0nG/Vky/oIF3wvF9V3Lpr9d88StXKVS pCZl0uobASfOf9gb/zU6mNPr64usxd8bn2e9vh/8pKSl4oKZ/QHub5UhrKzfpN5Mtk65eKqy XSq+xGZmgxJHz/PYZ67sU3jW+a/f9G/Jpod3mpPvTeDfe67x+3czlw2mLaLx/Qeaz1wp2zBR vOnq8RNlxaWeRsLtIc/sLDYU9Xy/32B4lbPGfIGx56tTSizFGYmGWsxFxYkA7onKkgoDAAA= X-CMS-MailID: 20220727060612epcas2p34e861279ece7fbd3c7c87ce02c7d795c X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220727060612epcas2p34e861279ece7fbd3c7c87ce02c7d795c References: <20220727060146.9228-1-chanho61.park@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add fsys1(for usb and mmc) clock definitions. Signed-off-by: Chanho Park --- .../dt-bindings/clock/samsung,exynosautov9.h | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h index 6305a84396ce..7e11e681da5c 100644 --- a/include/dt-bindings/clock/samsung,exynosautov9.h +++ b/include/dt-bindings/clock/samsung,exynosautov9.h @@ -228,6 +228,31 @@ #define FSYS0_NR_CLK 37 +/* CMU_FSYS1 */ +#define FOUT_MMC_PLL 1 + +#define CLK_MOUT_FSYS1_BUS_USER 2 +#define CLK_MOUT_MMC_PLL 3 +#define CLK_MOUT_FSYS1_MMC_CARD_USER 4 +#define CLK_MOUT_FSYS1_USBDRD_USER 5 +#define CLK_MOUT_FSYS1_MMC_CARD 6 + +#define CLK_DOUT_FSYS1_MMC_CARD 7 + +#define CLK_GOUT_FSYS1_PCLK 8 +#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN 9 +#define CLK_GOUT_FSYS1_MMC_CARD_ACLK 10 +#define CLK_GOUT_FSYS1_USB20DRD_0_REFCLK 11 +#define CLK_GOUT_FSYS1_USB20DRD_1_REFCLK 12 +#define CLK_GOUT_FSYS1_USB30DRD_0_REFCLK 13 +#define CLK_GOUT_FSYS1_USB30DRD_1_REFCLK 14 +#define CLK_GOUT_FSYS1_USB20_0_ACLK 15 +#define CLK_GOUT_FSYS1_USB20_1_ACLK 16 +#define CLK_GOUT_FSYS1_USB30_0_ACLK 17 +#define CLK_GOUT_FSYS1_USB30_1_ACLK 18 + +#define FSYS1_NR_CLK 19 + /* CMU_FSYS2 */ #define CLK_MOUT_FSYS2_BUS_USER 1 #define CLK_MOUT_FSYS2_UFS_EMBD_USER 2 From patchwork Wed Jul 27 06:01:43 2022 Content-Type: text/plain; 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Wed, 27 Jul 2022 15:06:13 +0900 (KST) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas2p4.samsung.com (KnoxPortal) with ESMTPA id 20220727060612epcas2p4b844ea92fe11c302337a320b222947d3~Fmo4M4gws2914429144epcas2p4p; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20220727060612epsmtrp1b06bdaedca7577c55e7da4e91d52d58b~Fmo4L0At90521005210epsmtrp1r; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) X-AuditID: b6c32a47-5e1ff700000025aa-c5-62e0d5d52f40 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 33.50.08802.4D5D0E26; Wed, 27 Jul 2022 15:06:12 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220727060612epsmtip1aef76668bddfa03250c2d9a7bc8953a4~Fmo3-rpj52961129611epsmtip1N; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) From: Chanho Park To: Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Krzysztof Kozlowski , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski Cc: Sam Protsenko , Alim Akhtar , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCH 3/6] dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1 Date: Wed, 27 Jul 2022 15:01:43 +0900 Message-Id: <20220727060146.9228-4-chanho61.park@samsung.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220727060146.9228-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrNJsWRmVeSWpSXmKPExsWy7bCmue7Vqw+SDA50sFk8mLeNzeLyfm2L 61+es1rMP3KO1aLvxUNmi72vt7JbbHp8jdXiY889VosZ5/cxWVw85WrRuvcIu8XhN+2sFv+u bWSxeN4HFF+16w+jA7/H+xut7B47Z91l99i0qpPN4861PWwem5fUe/RtWcXo8XmTXAB7VLZN RmpiSmqRQmpecn5KZl66rZJ3cLxzvKmZgaGuoaWFuZJCXmJuqq2Si0+ArltmDtDVSgpliTml QKGAxOJiJX07m6L80pJUhYz84hJbpdSClJwC8wK94sTc4tK8dL281BIrQwMDI1OgwoTsjDkX XjAXvBGq2H+ji72BcSNvFyMnh4SAicSVw1MYQWwhgR2MEneX2HQxcgHZnxglNvTdYodwPjNK LG5dxQrTMaV/GhtEYhejRHP3VWYI5yOjxNYVV5lAqtgEdCW2PH/FCJIQEXjMJHH4SBtYC7NA G5PEtGcbwWYJCwRLfJz4ACjBwcEioCrROSMcJMwrYCvRevotE8Q6eYnrN9uYQWxOATuJHWt2 MkHUCEqcnPmEBcRmBqpp3jqbGaJ+LYfEvGZVCNtFYuKZdWwQtrDEq+Nb2CFsKYmX/W1QdrHE 0lmfmEBukxBoYJS4vO0XVIOxxKxn7YwgtzELaEqs36UPYkoIKEscuQW1lk+i4/Bfdogwr0RH mxBEo7rEge3TWSBsWYnuOZ+hAech8fjXOVZIWE0EBtzyBUwTGBVmIflmFpJvZiEsXsDIvIpR LLWgODc9tdiowBgew8n5uZsYwalYy30H44y3H/QOMTJxMB5ilOBgVhLhTYi+nyTEm5JYWZVa lB9fVJqTWnyI0RQY1BOZpUST84HZIK8k3tDE0sDEzMzQ3MjUwFxJnNcrZUOikEB6Yklqdmpq QWoRTB8TB6dUA5NLj0fFrHLpPyphzyX0ds7rDjoaUjr1tNyDH8b5/wSfykTNk7ybENfdMvHb /GrJlfqvE7f5la/VtTukL2rZfKlePeW7UiGf+tLHnQdCJtl2rtYXu9oxcatT286PHSfF3u60 nxu9oWiKvpjZocDiu9eKzVYpume9eX1oa0KHM1fN04pTjkf6/37fcT6xwvxc4+RpEf7PJy4s XBLxJ+nNPgEt1+r16ck2e5KLdt92SpaZ/eOyWVd8DseRQyrCf1N/e3C/Lz6vMmfanT8rD7v5 d3S7rK7N/z/bZoona/Ka1O27+4KmzL6ebn8w0UBtc6B81zmRtaq8c+oWT9EMiS9z3XHD5Pzq iz4LmFdVHryTlqjEUpyRaKjFXFScCAD4AqL8TgQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGLMWRmVeSWpSXmKPExsWy7bCSnO6Vqw+SDLZuUrR4MG8bm8Xl/doW 1788Z7WYf+Qcq0Xfi4fMFntfb2W32PT4GqvFx557rBYzzu9jsrh4ytWide8RdovDb9pZLf5d 28hi8bwPKL5q1x9GB36P9zda2T12zrrL7rFpVSebx51re9g8Ni+p9+jbsorR4/MmuQD2KC6b lNSczLLUIn27BK6MORdeMBe8EarYf6OLvYFxI28XIyeHhICJxJT+aWwgtpDADkaJC5ekIOKy Es/e7WCHsIUl7rccYe1i5AKqec8ocatlPSNIgk1AV2LL81eMIAkRgedMElNWHARzmAW6mCTu tH0CaxcWCJTovXCZuYuRg4NFQFWic0Y4SJhXwFai9fRbJogN8hLXb7Yxg9icAnYSO9bsZIK4 yFZi5qsmFoh6QYmTM5+A2cxA9c1bZzNPYBSYhSQ1C0lqASPTKkbJ1ILi3PTcYsMCo7zUcr3i xNzi0rx0veT83E2M4KjR0trBuGfVB71DjEwcjIcYJTiYlUR4E6LvJwnxpiRWVqUW5ccXleak Fh9ilOZgURLnvdB1Ml5IID2xJDU7NbUgtQgmy8TBKdXAZL5ruqLERcnkXeEKm8V+s+yoZeD+ 5SYj4Bux5vIky7RvVw8cjFkZePv1p3CTn2fPWbvE2czW6/W472L1hOHGVflOvo5vt/bXLFi7 dkr950CF7mIW7wjz3bMO1yUrrGFSYUl4re1Rs0xVYZ96zZrWaWafFzLtu7Bf23jK+4N5eV0p jX8lvPofv7mpq5yTzsWlnWV3vnf7BSH7wAmS23auK0nZ9SRrV2v93c/NbyaJdEkydOpKhv3K qQlQ7mxYtCFfyCl54/mNwtcePlto3DPBYt3dle/jp3E4W+wSWVUwO0Xzm9X1f3rbT69ZMNOn /3VeXKZcg59ZXE6z6PkwjkM9vKvlfuws04t+nWKzb6ufEktxRqKhFnNRcSIAQZQCegkDAAA= X-CMS-MailID: 20220727060612epcas2p4b844ea92fe11c302337a320b222947d3 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220727060612epcas2p4b844ea92fe11c302337a320b222947d3 References: <20220727060146.9228-1-chanho61.park@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add "samsung,exynosautov9-cmu-fsys0/1" compatibles to illustrate cmu_fsys0 and fsys1 for Exynos Auto v9 SoC. Signed-off-by: Chanho Park --- .../clock/samsung,exynosautov9-clock.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml index eafc715d2d02..2ab4642679c0 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml @@ -35,6 +35,8 @@ properties: - samsung,exynosautov9-cmu-top - samsung,exynosautov9-cmu-busmc - samsung,exynosautov9-cmu-core + - samsung,exynosautov9-cmu-fsys0 + - samsung,exynosautov9-cmu-fsys1 - samsung,exynosautov9-cmu-fsys2 - samsung,exynosautov9-cmu-peric0 - samsung,exynosautov9-cmu-peric1 @@ -107,6 +109,48 @@ allOf: - const: oscclk - const: dout_clkcmu_core_bus + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-fsys0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS0 bus clock (from CMU_TOP) + - description: CMU_FSYS0 pcie clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_fsys0_bus + - const: dout_clkcmu_fsys0_pcie + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-fsys1 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS1 bus clock (from CMU_TOP) + - description: CMU_FSYS1 mmc card clock (from CMU_TOP) + - description: CMU_FSYS1 usb clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_fsys1_bus + - const: dout_clkcmu_fsys1_mmc_card + - const: dout_clkcmu_fsys1_usbdrd + - if: properties: compatible: From patchwork Wed Jul 27 06:01:44 2022 Content-Type: text/plain; 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Wed, 27 Jul 2022 15:06:13 +0900 (KST) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas2p3.samsung.com (KnoxPortal) with ESMTPA id 20220727060612epcas2p3fa8d9a1e8ab3db929b3518ac8aca770c~Fmo4RxR401806418064epcas2p3K; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20220727060612epsmtrp2d14efc8ad93ca696bd4d2c4c8162d05d~Fmo4QEQ082781327813epsmtrp20; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) X-AuditID: b6c32a47-5e1ff700000025aa-c7-62e0d5d5ed0c Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 43.50.08802.4D5D0E26; Wed, 27 Jul 2022 15:06:12 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220727060612epsmtip18ebb240c6309f29e4af4d8dff505d180~Fmo4EOAeW2960929609epsmtip1N; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) From: Chanho Park To: Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Krzysztof Kozlowski , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski Cc: Sam Protsenko , Alim Akhtar , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCH 4/6] arm64: dts: exynosautov9: add fsys0/1 clock DT nodes Date: Wed, 27 Jul 2022 15:01:44 +0900 Message-Id: <20220727060146.9228-5-chanho61.park@samsung.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220727060146.9228-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrHJsWRmVeSWpSXmKPExsWy7bCmhe7Vqw+SDC6e4LZ4MG8bm8Xl/doW 1788Z7WYf+Qcq0Xfi4fMFntfb2W32PT4GqvFx557rBYzzu9jsrh4ytWide8RdovDb9pZLf5d 28hi8bwPKL5q1x9GB36P9zda2T12zrrL7rFpVSebx51re9g8Ni+p9+jbsorR4/MmuQD2qGyb jNTElNQihdS85PyUzLx0WyXv4HjneFMzA0NdQ0sLcyWFvMTcVFslF58AXbfMHKCrlRTKEnNK gUIBicXFSvp2NkX5pSWpChn5xSW2SqkFKTkF5gV6xYm5xaV56Xp5qSVWhgYGRqZAhQnZGV0H /rIX7OOp6JnSydbA2MbVxcjJISFgIjHt53yWLkYuDiGBHYwSu5Y+ZoNwPjFK7L/ewwrhfGaU WLN1AxNMy+Q5S6GqdjFKNO+bB1X1kVFi4uVOZpAqNgFdiS3PXzGCJEQEHjNJHD7SBtbCLNDG JDHt2UZWkCphAU+J1jdrWEBsFgFVib6Wr+wgNq+ArcS0P7vYIfbJS1y/2QY2lVPATmLHmp1M EDWCEidnPgHrZQaqad46mxlkgYTASg6JFX1XoJpdJB5t+s0GYQtLvDq+BSouJfH53V6oeLHE 0lmfmCCaGxglLm/7BZUwlpj1rB3oBw6gDZoS63fpg5gSAsoSR25B7eWT6Dj8lx0izCvR0SYE 0agucWD7dBYIW1aie85nVgjbQ2L79PfMkNCayCjxvm8K6wRGhVlI3pmF5J1ZCIsXMDKvYhRL LSjOTU8tNiowhkdycn7uJkZwQtZy38E44+0HvUOMTByMhxglOJiVRHgTou8nCfGmJFZWpRbl xxeV5qQWH2I0BQb2RGYp0eR8YE7IK4k3NLE0MDEzMzQ3MjUwVxLn9UrZkCgkkJ5YkpqdmlqQ WgTTx8TBKdXAtPJicueBnNxyL/nIqzdnVx6KZ5NTL6g4cYrfo1VykpSQkvDy+32Oih3fuxqN l6053rnGSD7j+XuHV8eKfcqsaj9LVM29fuLWos7ttTGTXl/yF5y2SrHlZsuqw0mtc5d+YM1x O+ZePute+df6leofg59H6i3Vat/Mq1S/xCxphf3GqO98Ey6YblosXb+P/9IMfeVZx+/Ptu0w PHP49PS0rxxWk+/rLn2ryiWUOOmR+XnTlx9lmaf0HFjonXeLMf/Zsu9a0lxzWcV+WPtaKpsw /z8QzHcl6qqFKPcN5WAtn8S6Ktno9ZsFedmKf3fOuvFEKu5exte+fS9PtE+P7HjLfrTlKasB gw7zJ66tDFrySizFGYmGWsxFxYkAEL+GZVEEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBLMWRmVeSWpSXmKPExsWy7bCSnO6Vqw+SDGbNUrN4MG8bm8Xl/doW 1788Z7WYf+Qcq0Xfi4fMFntfb2W32PT4GqvFx557rBYzzu9jsrh4ytWide8RdovDb9pZLf5d 28hi8bwPKL5q1x9GB36P9zda2T12zrrL7rFpVSebx51re9g8Ni+p9+jbsorR4/MmuQD2KC6b lNSczLLUIn27BK6MrgN/2Qv28VT0TOlka2Bs4+pi5OSQEDCRmDxnKVsXIxeHkMAORolFh3vY IRKyEs/e7YCyhSXutxxhhSh6zyjxctMDFpAEm4CuxJbnrxhBEiICz5kkpqw4COYwC3QxSdxp +wTWLizgKdH6Zg1YB4uAqkRfy1ewOK+ArcS0P7ugVshLXL/ZxgxicwrYSexYs5MJxBYCqpn5 qokFol5Q4uTMJ2A2M1B989bZzBMYBWYhSc1CklrAyLSKUTK1oDg3PbfYsMAoL7Vcrzgxt7g0 L10vOT93EyM4crS0djDuWfVB7xAjEwfjIUYJDmYlEd6E6PtJQrwpiZVVqUX58UWlOanFhxil OViUxHkvdJ2MFxJITyxJzU5NLUgtgskycXBKNTB1cU269emPm1uL7aHKjTWfNxzebDlz/YJ5 Xsnmm3SL2XU+COx//1L5YNz9o10+H80/71F0enSizHGKs1vjbvWVH2q57t3lsntcqGX2OiWP LVhDxIl3+aWogg9SRp82s/7Mjyu2MF28kE0q+KRoh8LOfQJMsvZ2p0X9edSmddyLLBdnfGk7 Rddra7HR2vXPsw4+/6S14MSGtG6mS4X+p/uS9vbOud24qNffpKdE4/T9ZEXzja/j0hYt6p6w RP1s8F95002PHjL37ozLTQm8Kt+T9IP93vXTkbJmc7JtTiz1yXyXemrnDMnFFQ96V3XF5P7M TVndJBt7oyjRuWhW+pdKj1cuKY6mcVs2BrsYGCuxFGckGmoxFxUnAgCx8UJXCwMAAA== X-CMS-MailID: 20220727060612epcas2p3fa8d9a1e8ab3db929b3518ac8aca770c X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220727060612epcas2p3fa8d9a1e8ab3db929b3518ac8aca770c References: <20220727060146.9228-1-chanho61.park@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add cmu_fsys0 and cmu_fsys1 for PCIe clocks and USB/MMC clocks respectively. Signed-off-by: Chanho Park Reviewed-by: Chanwoo Choi --- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 28 ++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 2013718532f3..58b3b0c5d3fc 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -207,6 +207,34 @@ cmu_peric1: clock-controller@10800000 { "dout_clkcmu_peric1_ip"; }; + cmu_fsys0: clock-controller@17700000 { + compatible = "samsung,exynosautov9-cmu-fsys0"; + reg = <0x17700000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_FSYS0_BUS>, + <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>; + clock-names = "oscclk", + "dout_clkcmu_fsys0_bus", + "dout_clkcmu_fsys0_pcie"; + }; + + cmu_fsys1: clock-controller@17040000 { + compatible = "samsung,exynosautov9-cmu-fsys1"; + reg = <0x17040000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_FSYS1_BUS>, + <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>, + <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>; + clock-names = "oscclk", + "dout_clkcmu_fsys1_bus", + "gout_clkcmu_fsys1_mmc_card", + "dout_clkcmu_fsys1_usbdrd"; + }; + cmu_fsys2: clock-controller@17c00000 { compatible = "samsung,exynosautov9-cmu-fsys2"; reg = <0x17c00000 0x8000>; From patchwork Wed Jul 27 06:01:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanho Park X-Patchwork-Id: 594611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3BFAC25B06 for ; Wed, 27 Jul 2022 06:06:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229924AbiG0GGZ (ORCPT ); Wed, 27 Jul 2022 02:06:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229914AbiG0GGW (ORCPT ); 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Wed, 27 Jul 2022 15:06:12 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220727060612epsmtip17ebe1cdd3ac9239002b00faaefca3231~Fmo4JDxlu2961129611epsmtip1O; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) From: Chanho Park To: Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Krzysztof Kozlowski , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski Cc: Sam Protsenko , Alim Akhtar , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCH 5/6] clk: samsung: exynosautov9: add fsys0 clock support Date: Wed, 27 Jul 2022 15:01:45 +0900 Message-Id: <20220727060146.9228-6-chanho61.park@samsung.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220727060146.9228-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrHJsWRmVeSWpSXmKPExsWy7bCmue7Vqw+SDM4f4rJ4MG8bm8Xl/doW 1788Z7WYf+Qcq0Xfi4fMFntfb2W32PT4GqvFx557rBYzzu9jsrh4ytWide8RdovDb9pZLf5d 28hi8bwPKL5q1x9GB36P9zda2T12zrrL7rFpVSebx51re9g8Ni+p9+jbsorR4/MmuQD2qGyb jNTElNQihdS85PyUzLx0WyXv4HjneFMzA0NdQ0sLcyWFvMTcVFslF58AXbfMHKCrlRTKEnNK gUIBicXFSvp2NkX5pSWpChn5xSW2SqkFKTkF5gV6xYm5xaV56Xp5qSVWhgYGRqZAhQnZGR86 7jMXtGZW/Po5kbGB8XZMFyMnh4SAicS813fYuxi5OIQEdjBKTOxohHI+MUp82H+eFcL5xijR 8GY7G0zL1h0bmSESexkl/nw/xAbhfGSUeHhjITtIFZuArsSW568YQRIiAo+ZJA4faQOrYhZo Y5KY9mwjK0iVsICHxIXWV2A2i4CqxJsb/8G6eQVsJU6da2eG2Ccvcf1mG5jNKWAnsWPNTiaI GkGJkzOfsIDYzEA1zVtng90kIbCSQ2J+31WoY10kjty+zwphC0u8Or6FHcKWknjZ3wZlF0ss nfWJCaK5gVHi8rZfUM3GErOetQP9wAG0QVNi/S59EFNCQFniyC2ovXwSHYf/skOEeSU62oQg GtUlDmyfzgJhy0p0z/kMdYGHRNfHnYyQ0JrIKDFt7h7mCYwKs5C8MwvJO7MQFi9gZF7FKJZa UJybnlpsVGAEj+Tk/NxNjOCErOW2g3HK2w96hxiZOBgPMUpwMCuJ8CZE308S4k1JrKxKLcqP LyrNSS0+xGgKDOyJzFKiyfnAnJBXEm9oYmlgYmZmaG5kamCuJM7rlbIhUUggPbEkNTs1tSC1 CKaPiYNTqoFpcU1/As/tx/O2Mv/NYOf7wTt708SC1YHv5bmEmqxyrzXzNiedUHpw/7Pyxkl8 4c4N7/nmiU3m6JOeXlj37eTvzw6TmJbc5n77v1VGcObHpVqhlV5W0xX2/HLQ8C2s4546l5n3 Ej9DwqaCOP/pfPdNvdUPMyQobe/6PWeffURCyv6EX9e2cDHaHb6Sa/SJ//ii+dx77nJ+W2Re eHdXvQXrj/0lHnk5EyrMmyr1HT5fd2Ca3/1xfYUtH6vp8y0XBTannohes9k5+nuiu5zAigbG Vddy3A6smX/ruo7MwRMJx+5Ovz39mXL3+Qm3JjZb9XkcNPqyTfmBtY52SeRuudc3xGPWxqTG Be2a/Y03XXaeEktxRqKhFnNRcSIALpH0FlEEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrOLMWRmVeSWpSXmKPExsWy7bCSnO6Vqw+SDO5f0rZ4MG8bm8Xl/doW 1788Z7WYf+Qcq0Xfi4fMFntfb2W32PT4GqvFx557rBYzzu9jsrh4ytWide8RdovDb9pZLf5d 28hi8bwPKL5q1x9GB36P9zda2T12zrrL7rFpVSebx51re9g8Ni+p9+jbsorR4/MmuQD2KC6b lNSczLLUIn27BK6MDx33mQtaMyt+/ZzI2MB4O6aLkZNDQsBEYuuOjcxdjFwcQgK7GSUWH7zF DpGQlXj2bgeULSxxv+UIK4gtJPCeUWL1ak8Qm01AV2LL81eMIM0iAs+ZJKasOAjmMAt0MUnc afsE1i0s4CFxofUVWDeLgKrEmxv/weK8ArYSp861M0NskJe4frMNzOYUsJPYsWYnE8Q2W4mZ r5pYIOoFJU7OfAJmMwPVN2+dzTyBUWAWktQsJKkFjEyrGCVTC4pz03OLDQsM81LL9YoTc4tL 89L1kvNzNzGC40ZLcwfj9lUf9A4xMnEwHmKU4GBWEuFNiL6fJMSbklhZlVqUH19UmpNafIhR moNFSZz3QtfJeCGB9MSS1OzU1ILUIpgsEwenVAPT6l2+T0oSdRQTGs8/WPQ59PSShSEuUyvY jPZE8+y96BQbu8/ITvci27svcgZhOTyLTx7Z8SHG+fC80u+zO6PjrYIKqia2nvn01SfNX+HJ zL4TxTzJ7CmB72y3HPYOir7LtWCaQ8trwejnSZJfVbatqhLVn77yhHZ7bMo75o7bRntLJ/7P 0FCXdt3Rs1hiW9VpbsUj/2JnLp58rPra5V8njJYy5EpfDrs4T1QqNjTjvP2SK/2dea8a0ry1 mL/7SPO7HEuPzNga9ljfvyviNTtPghHjqyUahg9frF/9KNovqtJ8xtqtJ4MLzoc8FvjzU7LC vn639bcnrw0/l2zLvev38NjZuz4WOwze2HfEJJgqsRRnJBpqMRcVJwIARYfnoQoDAAA= X-CMS-MailID: 20220727060612epcas2p1e79b8d8bfb9e8a3ea351c4dbd7c42b7d X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220727060612epcas2p1e79b8d8bfb9e8a3ea351c4dbd7c42b7d References: <20220727060146.9228-1-chanho61.park@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2 Lanes. Signed-off-by: Chanho Park --- drivers/clk/samsung/clk-exynosautov9.c | 243 +++++++++++++++++++++++++ 1 file changed, 243 insertions(+) diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c index d9e1f8e4a7b4..527a6837661e 100644 --- a/drivers/clk/samsung/clk-exynosautov9.c +++ b/drivers/clk/samsung/clk-exynosautov9.c @@ -1067,6 +1067,246 @@ static const struct samsung_cmu_info core_cmu_info __initconst = { .clk_name = "dout_clkcmu_core_bus", }; +/* ---- CMU_FSYS0 ---------------------------------------------------------- */ + +/* Register Offset definitions for CMU_FSYS2 (0x17700000) */ +#define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER 0x0600 +#define PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER 0x0610 +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x2000 + +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN 0x2004 +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN 0x2008 +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN 0x200c +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN 0x2010 +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN 0x2014 +#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN 0x2018 + +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK 0x205c +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK 0x2060 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK 0x2064 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK 0x206c +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK 0x2070 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK 0x2074 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK 0x207c + +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK 0x2084 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK 0x2088 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK 0x208c +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK 0x2094 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK 0x2098 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK 0x209c +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK 0x20a4 + +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK 0x20ac +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK 0x20b0 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK 0x20b4 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK 0x20bc +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK 0x20c0 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK 0x20c4 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK 0x20cc + +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK 0x20d4 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK 0x20d8 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK 0x20dc +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK 0x20e0 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK 0x20e4 +#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK 0x20e8 + + +static const unsigned long fsys0_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, + PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER, + CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN, + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN, + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN, + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN, + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN, + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK, + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK, +}; + +/* List of parent clocks for Muxes in CMU_FSYS0 */ +PNAME(mout_fsys0_bus_user_p) = { "oscclk", "dout_clkcmu_fsys0_bus" }; +PNAME(mout_fsys0_pcie_user_p) = { "oscclk", "dout_clkcmu_fsys0_pcie" }; + +static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = { + MUX(CLK_MOUT_FSYS0_BUS_USER, "mout_fsys0_bus_user", + mout_fsys0_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, 4, 1), + MUX(CLK_MOUT_FSYS0_PCIE_USER, "mout_fsys0_pcie_user", + mout_fsys0_pcie_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER, 4, 1), +}; + +static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = { + GATE(CLK_GOUT_FSYS0_BUS_PCLK, "gout_fsys0_bus_pclk", + "mout_fsys0_bus_user", + CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + + /* Gen3 2L0 */ + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK, + "gout_fsys0_pcie_gen3_2l0_x1_refclk", "mout_fsys0_pcie_user", + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK, + "gout_fsys0_pcie_gen3_2l0_x2_refclk", "mout_fsys0_pcie_user", + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK, + "gout_fsys0_pcie_gen3_2l0_x1_dbi_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK, + "gout_fsys0_pcie_gen3_2l0_x1_mstr_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK, + "gout_fsys0_pcie_gen3_2l0_x1_slv_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK, + "gout_fsys0_pcie_gen3_2l0_x2_dbi_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK, + "gout_fsys0_pcie_gen3_2l0_x2_mstr_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK, + "gout_fsys0_pcie_gen3_2l0_x2_slv_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK, + "gout_fsys0_pcie_gen3a_2l0_clk", "mout_fsys0_pcie_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK, + "gout_fsys0_pcie_gen3b_2l0_clk", "mout_fsys0_pcie_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK, + 21, 0, 0), + + /* Gen3 2L1 */ + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK, + "gout_fsys0_pcie_gen3_2l1_x1_refclk", "mout_fsys0_pcie_user", + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK, + "gout_fsys0_pcie_gen3_2l1_x2_refclk", "mout_fsys0_pcie_user", + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK, + "gout_fsys0_pcie_gen3_2l1_x1_dbi_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK, + "gout_fsys0_pcie_gen3_2l1_x1_mstr_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK, + "gout_fsys0_pcie_gen3_2l1_x1_slv_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK, + "gout_fsys0_pcie_gen3_2l1_x2_dbi_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK, + "gout_fsys0_pcie_gen3_2l1_x2_mstr_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK, + "gout_fsys0_pcie_gen3_2l1_x2_slv_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK, + "gout_fsys0_pcie_gen3a_2l1_clk", "mout_fsys0_pcie_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK, + "gout_fsys0_pcie_gen3b_2l1_clk", "mout_fsys0_pcie_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK, + 21, 0, 0), + + /* Gen3 4L */ + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK, + "gout_fsys0_pcie_gen3_4l_x2_refclk", "mout_fsys0_pcie_user", + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK, + "gout_fsys0_pcie_gen3_4l_x4_refclk", "mout_fsys0_pcie_user", + CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK, + "gout_fsys0_pcie_gen3_4l_x2_dbi_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK, + "gout_fsys0_pcie_gen3_4l_x2_mstr_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK, + "gout_fsys0_pcie_gen3_4l_x2_slv_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK, + "gout_fsys0_pcie_gen3_4l_x4_dbi_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK, + "gout_fsys0_pcie_gen3_4l_x4_mstr_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK, + "gout_fsys0_pcie_gen3_4l_x4_slv_aclk", "mout_fsys0_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK, + "gout_fsys0_pcie_gen3a_4l_clk", "mout_fsys0_pcie_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK, + "gout_fsys0_pcie_gen3b_4l_clk", "mout_fsys0_pcie_user", + CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK, + 21, 0, 0), +}; + +static const struct samsung_cmu_info fsys0_cmu_info __initconst = { + .mux_clks = fsys0_mux_clks, + .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), + .gate_clks = fsys0_gate_clks, + .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), + .nr_clk_ids = FSYS0_NR_CLK, + .clk_regs = fsys0_clk_regs, + .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), + .clk_name = "dout_clkcmu_fsys0_bus", +}; + /* ---- CMU_FSYS2 ---------------------------------------------------------- */ /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */ @@ -1701,6 +1941,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = { }, { .compatible = "samsung,exynosautov9-cmu-core", .data = &core_cmu_info, + }, { + .compatible = "samsung,exynosautov9-cmu-fsys0", + .data = &fsys0_cmu_info, }, { .compatible = "samsung,exynosautov9-cmu-fsys2", .data = &fsys2_cmu_info, From patchwork Wed Jul 27 06:01:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanho Park X-Patchwork-Id: 594610 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on 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20220727060612epsmtip13635d045e510301425adf80aae590188~Fmo4N7sJm2961429614epsmtip1G; Wed, 27 Jul 2022 06:06:12 +0000 (GMT) From: Chanho Park To: Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Krzysztof Kozlowski , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski Cc: Sam Protsenko , Alim Akhtar , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chanho Park Subject: [PATCH 6/6] clk: samsung: exynosautov9: add fsys1 clock support Date: Wed, 27 Jul 2022 15:01:46 +0900 Message-Id: <20220727060146.9228-7-chanho61.park@samsung.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220727060146.9228-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrNJsWRmVeSWpSXmKPExsWy7bCmqe7Vqw+SDLb/EbF4MG8bm8Xl/doW 1788Z7WYf+Qcq0Xfi4fMFntfb2W32PT4GqvFx557rBYzzu9jsrh4ytWide8RdovDb9pZLf5d 28hi8bwPKL5q1x9GB36P9zda2T12zrrL7rFpVSebx51re9g8Ni+p9+jbsorR4/MmuQD2qGyb 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Vs38HHVBo7Zxxnkx0TmpjbMeivkW2Vo911qUqCaY3fii+cMacwGPf29jGhSKu9LrtGaYPQm6 6Dtv1rHTbolz+Q/d3fi5pTjxQo3Gd90YLfM9K6L+nHtmJjrx/wy9Y16CUp/P3kt8zlYal757 R8+MkoRfGy+IqNpcPVueXV1+7VzkV/38PTJpDqmFu9ZW21Xsc98gYnN4jjPfyXATpqrUPuYH 8f6+cY/uPTe5vtAq20p/WQ+HaI1S0vyJC1UvVyixFGckGmoxFxUnAgCi7u1zCgMAAA== X-CMS-MailID: 20220727060612epcas2p47e21a2545b686d536de47518f7b5c199 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220727060612epcas2p47e21a2545b686d536de47518f7b5c199 References: <20220727060146.9228-1-chanho61.park@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1, 2 x USB 2.0) and mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also supported as a PLL source clock provider. Signed-off-by: Chanho Park --- drivers/clk/samsung/clk-exynosautov9.c | 129 +++++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c index 527a6837661e..b61eec1244cc 100644 --- a/drivers/clk/samsung/clk-exynosautov9.c +++ b/drivers/clk/samsung/clk-exynosautov9.c @@ -1307,6 +1307,132 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = { .clk_name = "dout_clkcmu_fsys0_bus", }; +/* ---- CMU_FSYS1 ---------------------------------------------------------- */ + +/* Register Offset definitions for CMU_FSYS1 (0x17040000) */ +#define PLL_LOCKTIME_PLL_MMC 0x0000 +#define PLL_CON0_PLL_MMC 0x0100 +#define PLL_CON3_PLL_MMC 0x010c +#define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0600 +#define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0610 +#define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0x0620 + +#define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0x1000 +#define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0x1800 + +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x202c +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2028 + +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0x204c +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0x2058 +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0x2064 +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0x2070 + +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0x2074 +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0x2078 +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0x207c +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0x2080 + +static const unsigned long fsys1_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, +}; + +static const struct samsung_pll_clock fsys1_pll_clks[] __initconst = { + PLL(pll_0831x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", + PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), +}; + +/* List of parent clocks for Muxes in CMU_FSYS1 */ +PNAME(mout_fsys1_bus_user_p) = { "oscclk", "dout_clkcmu_fsys1_bus" }; +PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; +PNAME(mout_fsys1_mmc_card_user_p) = { "oscclk", "gout_clkcmu_fsys1_mmc_card" }; +PNAME(mout_fsys1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_fsys1_usbdrd" }; +PNAME(mout_fsys1_mmc_card_p) = { "mout_fsys1_mmc_card_user", "mout_mmc_pll" }; + +static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = { + MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user", + mout_fsys1_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 4, 1), + MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, + PLL_CON0_PLL_MMC, 4, 1), + MUX(CLK_MOUT_FSYS1_MMC_CARD_USER, "mout_fsys1_mmc_card_user", + mout_fsys1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER, + 4, 1), + MUX(CLK_MOUT_FSYS1_USBDRD_USER, "mout_fsys1_usbdrd_user", + mout_fsys1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER, + 4, 1), + MUX(CLK_MOUT_FSYS1_MMC_CARD, "mout_fsys1_mmc_card", + mout_fsys1_mmc_card_p, CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD, + 0, 1), +}; + +static const struct samsung_div_clock fsys1_div_clks[] __initconst = { + DIV(CLK_DOUT_FSYS1_MMC_CARD, "dout_fsys1_mmc_card", + "mout_fsys1_mmc_card", + CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9), +}; + +static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = { + GATE(CLK_GOUT_FSYS1_PCLK, "gout_fsys1_pclk", "mout_fsys1_bus_user", + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN, "gout_fsys1_mmc_card_sdclkin", + "dout_fsys1_mmc_card", + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN, + 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS1_MMC_CARD_ACLK, "gout_fsys1_mmc_card_aclk", + "dout_fsys1_mmc_card", + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS1_USB20DRD_0_REFCLK, "gout_fsys1_usb20drd_0_refclk", + "mout_fsys1_usbdrd_user", + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40, + 21, 0, 0), + GATE(CLK_GOUT_FSYS1_USB20DRD_1_REFCLK, "gout_fsys1_usb20drd_1_refclk", + "mout_fsys1_usbdrd_user", + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40, + 21, 0, 0), + GATE(CLK_GOUT_FSYS1_USB30DRD_0_REFCLK, "gout_fsys1_usb30drd_0_refclk", + "mout_fsys1_usbdrd_user", + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40, + 21, 0, 0), + GATE(CLK_GOUT_FSYS1_USB30DRD_1_REFCLK, "gout_fsys1_usb30drd_1_refclk", + "mout_fsys1_usbdrd_user", + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40, + 21, 0, 0), + GATE(CLK_GOUT_FSYS1_USB20_0_ACLK, "gout_fsys1_usb20_0_aclk", + "mout_fsys1_usbdrd_user", + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS1_USB20_1_ACLK, "gout_fsys1_usb20_1_aclk", + "mout_fsys1_usbdrd_user", + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS1_USB30_0_ACLK, "gout_fsys1_usb30_0_aclk", + "mout_fsys1_usbdrd_user", + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_FSYS1_USB30_1_ACLK, "gout_fsys1_usb30_1_aclk", + "mout_fsys1_usbdrd_user", + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK, + 21, 0, 0), +}; + +static const struct samsung_cmu_info fsys1_cmu_info __initconst = { + .pll_clks = fsys1_pll_clks, + .nr_pll_clks = ARRAY_SIZE(fsys1_pll_clks), + .mux_clks = fsys1_mux_clks, + .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), + .div_clks = fsys1_div_clks, + .nr_div_clks = ARRAY_SIZE(fsys1_div_clks), + .gate_clks = fsys1_gate_clks, + .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), + .nr_clk_ids = FSYS1_NR_CLK, + .clk_regs = fsys1_clk_regs, + .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), + .clk_name = "dout_clkcmu_fsys1_bus", +}; + /* ---- CMU_FSYS2 ---------------------------------------------------------- */ /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */ @@ -1944,6 +2070,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = { }, { .compatible = "samsung,exynosautov9-cmu-fsys0", .data = &fsys0_cmu_info, + }, { + .compatible = "samsung,exynosautov9-cmu-fsys1", + .data = &fsys1_cmu_info, }, { .compatible = "samsung,exynosautov9-cmu-fsys2", .data = &fsys2_cmu_info,