From patchwork Tue Jul 26 14:22:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 593513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE034C04A68 for ; Tue, 26 Jul 2022 14:23:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239199AbiGZOXt (ORCPT ); Tue, 26 Jul 2022 10:23:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239149AbiGZOXt (ORCPT ); Tue, 26 Jul 2022 10:23:49 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4985F27CE8 for ; Tue, 26 Jul 2022 07:23:45 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id k12so2659190wrm.13 for ; Tue, 26 Jul 2022 07:23:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iN4g8Q0MhfeR/u597UBROPVWFRobvvZk7geE/5YXWMo=; b=AmybggQ/afwLbYKutEwikc3w0YLeHJQvVO81EIa5bCBowVO0mViSM+LX8xqbgeCwLc 4G2OkRdKPPUQtonPOAkYMx0+0V6oyBKvP/9+1UgTyl2GA3fWu1ZJ0ETAcqwf+ybIIrjK OiSj+VD5HtJjH3W2qYldwcTZGjVtVHAKeH9bd2//J7r9FKhG1CIBsXoJUqkEuWLOhQax 8miUjFDD/jMfUW6ZmRxS3wyCA+5LQvWq1ZuGVNzl1+nn+6qNHZgkPFnBGbuIwo6w3jCb jD3VmWu15x6xA2Az+bv1TvTKjwnGgVbVBslli8NBtF7xqm2e34wD79JaLQDIMele9cxY Y4og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iN4g8Q0MhfeR/u597UBROPVWFRobvvZk7geE/5YXWMo=; b=lX1ckS432U3WdoRKN390ZksNkoH+PSx5E5e1OdpuJJtboYfST/GIAwz6YaGf+L2Z4p Lov/wUE3AHP7lJkM+Alyi6ckazp55h2hgazzukbnelZDQn8R07hfjPx0bAJbYiXOO+0l NzTzSOTg+OLCwU4KXAiZY5uWTuw7kS7zy5JQ4HlYIwjgJMRkc4ADQGsflku4tEMjtqCo Rs0w2LSusK5L/u252x50jkbFkydcdgHkUUkr2d8JvCwLY5fNTTsbMCifuuz0rE+Mq7iN HGu6No+ohsj4y6Le/U6wCRT7DIVR3v9Nj4w8WjiFNkt69gopJuOe0xr8JMUt8FYn5VEF KS/Q== X-Gm-Message-State: AJIora/td9x+Hgfy8yM1AmzzAcHukhLmIVahQestkbbpBdsZq1mYPbCc SXr/c9DLM1TMCXI7zZrY2hDnVQ== X-Google-Smtp-Source: AGRyM1tov4IGbHdLhoHIVZ1JTGggwsyOjMaENX4QMjzTNb/yYyfyp9LzGNuW+Pxx31lkOrgMF6dd+g== X-Received: by 2002:adf:ea8c:0:b0:21e:463e:7480 with SMTP id s12-20020adfea8c000000b0021e463e7480mr11131837wrm.171.1658845423762; Tue, 26 Jul 2022 07:23:43 -0700 (PDT) Received: from localhost.localdomain ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id t21-20020a1c7715000000b003a331c6bffdsm17017119wmi.47.2022.07.26.07.23.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 07:23:43 -0700 (PDT) From: Abel Vesa To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Mike Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Linux Kernel Mailing List , Abel Vesa Subject: [RFC 1/9] clk: qcom: qcc-sdm845: Collapse gdsc structs into macros Date: Tue, 26 Jul 2022 17:22:55 +0300 Message-Id: <20220726142303.4126434-2-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.3 In-Reply-To: <20220726142303.4126434-1-abel.vesa@linaro.org> References: <20220726142303.4126434-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Collapse gdsc structs definitions into macros to make them more compact visually. Signed-off-by: Abel Vesa --- drivers/clk/qcom/gcc-sdm845.c | 129 ++++------------------------------ drivers/clk/qcom/gdsc.h | 10 +++ 2 files changed, 23 insertions(+), 116 deletions(-) diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index 58aa3ec9a7fc..8529e9c8c90c 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -3191,122 +3191,19 @@ static struct clk_branch gcc_lpass_sway_clk = { }; #endif -static struct gdsc pcie_0_gdsc = { - .gdscr = 0x6b004, - .pd = { - .name = "pcie_0_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc pcie_1_gdsc = { - .gdscr = 0x8d004, - .pd = { - .name = "pcie_1_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc ufs_card_gdsc = { - .gdscr = 0x75004, - .pd = { - .name = "ufs_card_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc ufs_phy_gdsc = { - .gdscr = 0x77004, - .pd = { - .name = "ufs_phy_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc usb30_prim_gdsc = { - .gdscr = 0xf004, - .pd = { - .name = "usb30_prim_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc usb30_sec_gdsc = { - .gdscr = 0x10004, - .pd = { - .name = "usb30_sec_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, -}; - -static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = { - .gdscr = 0x7d030, - .pd = { - .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, -}; - -static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = { - .gdscr = 0x7d03c, - .pd = { - .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, -}; - -static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = { - .gdscr = 0x7d034, - .pd = { - .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, -}; - -static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = { - .gdscr = 0x7d038, - .pd = { - .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, -}; - -static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { - .gdscr = 0x7d040, - .pd = { - .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, -}; - -static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { - .gdscr = 0x7d048, - .pd = { - .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, -}; - -static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = { - .gdscr = 0x7d044, - .pd = { - .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, -}; +DEFINE_QCOM_CC_GDSC(pcie_0_gdsc, 0x6b004, "pcie_0_gdsc", PWRSTS_OFF_ON, POLL_CFG_GDSCR); +DEFINE_QCOM_CC_GDSC(pcie_1_gdsc, 0x8d004, "pcie_1_gdsc", PWRSTS_OFF_ON, POLL_CFG_GDSCR); +DEFINE_QCOM_CC_GDSC(ufs_card_gdsc, 0x75004, "ufs_card_gdsc", PWRSTS_OFF_ON, POLL_CFG_GDSCR); +DEFINE_QCOM_CC_GDSC(ufs_phy_gdsc, 0x77004, "ufs_phy_gdsc", PWRSTS_OFF_ON, POLL_CFG_GDSCR); +DEFINE_QCOM_CC_GDSC(usb30_prim_gdsc, 0xf004, "usb30_prim_gdsc", PWRSTS_OFF_ON, POLL_CFG_GDSCR); +DEFINE_QCOM_CC_GDSC(usb30_sec_gdsc, 0x10004, "usb30_sec_gdsc", PWRSTS_OFF_ON, POLL_CFG_GDSCR); +DEFINE_QCOM_CC_GDSC(hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc, 0x7d030, "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc", PWRSTS_OFF_ON, VOTABLE); +DEFINE_QCOM_CC_GDSC(hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc, 0x7d03c, "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc", PWRSTS_OFF_ON, VOTABLE); +DEFINE_QCOM_CC_GDSC(hlos1_vote_aggre_noc_mmu_tbu1_gdsc, 0x7d034, "hlos1_vote_aggre_noc_mmu_tbu1_gdsc", PWRSTS_OFF_ON, VOTABLE); +DEFINE_QCOM_CC_GDSC(hlos1_vote_aggre_noc_mmu_tbu2_gdsc, 0x7d038, "hlos1_vote_aggre_noc_mmu_tbu2_gdsc", PWRSTS_OFF_ON, VOTABLE); +DEFINE_QCOM_CC_GDSC(hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, 0x7d040, "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", PWRSTS_OFF_ON, VOTABLE); +DEFINE_QCOM_CC_GDSC(hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, 0x7d048, "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", PWRSTS_OFF_ON, VOTABLE); +DEFINE_QCOM_CC_GDSC(hlos1_vote_mmnoc_mmu_tbu_sf_gdsc, 0x7d044, "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc", PWRSTS_OFF_ON, VOTABLE); static struct clk_regmap *gcc_sdm845_clocks[] = { [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 5de48c9439b2..c0e616b49dee 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -78,6 +78,16 @@ struct gdsc_desc { size_t num; }; +#define DEFINE_QCOM_CC_GDSC(_name, _gdscr, _pd_name, _pwrsts, _flags) \ + static struct gdsc _name = { \ + .gdscr = _gdscr, \ + .pd = { \ + .name = _pd_name, \ + }, \ + .pwrsts = _pwrsts, \ + .flags = _flags, \ + } + #ifdef CONFIG_QCOM_GDSC int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *, struct regmap *); From patchwork Tue Jul 26 14:22:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 593512 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68F8DC00144 for ; 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Tue, 26 Jul 2022 07:23:47 -0700 (PDT) From: Abel Vesa To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Mike Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Linux Kernel Mailing List , Abel Vesa Subject: [RFC 4/9] clk: qcom: alpha-pll: Add macros to collapse definition Date: Tue, 26 Jul 2022 17:22:58 +0300 Message-Id: <20220726142303.4126434-5-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.3 In-Reply-To: <20220726142303.4126434-1-abel.vesa@linaro.org> References: <20220726142303.4126434-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add macros for a visually more compact alpha-pll clocks definition, one for alpha-pll and one for alpha-pll postdiv. These are only the ones used by gcc-sdm845 driver. More will be added later on. Signed-off-by: Abel Vesa --- drivers/clk/qcom/clk-alpha-pll.h | 61 ++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 447efb82fe59..1bf7a3ecb7f1 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -127,6 +127,67 @@ struct alpha_pll_config { u32 vco_mask; }; +#define __DEFINE_QCOM_CC_CLK_ALPHA_PLL(_name, _offset, _regs, \ + _enable_reg, _enable_mask, \ + _parent_fw_name, _flags, _ops) \ + static struct clk_alpha_pll _name = { \ + .offset = _offset, \ + .regs = _regs, \ + .clkr = { \ + .enable_reg = _enable_reg, \ + .enable_mask = _enable_mask, \ + .hw.init = &(struct clk_init_data){ \ + .name = #_name, \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = _parent_fw_name, \ + .name = _parent_fw_name, \ + }, \ + .num_parents = 1, \ + .ops = _ops, \ + .flags = _flags, \ + }, \ + }, \ + } + +#define __DEFINE_QCOM_CC_CLK_ALPHA_PLL_POSTDIV(_name, _offset, \ + _post_div_shift, _post_div_table, \ + _width, _regs, \ + _parent_hws, _flags, _ops) \ + static struct clk_alpha_pll_postdiv _name = { \ + .offset = _offset, \ + .post_div_shift = _post_div_shift, \ + .post_div_table = _post_div_table, \ + .num_post_div = ARRAY_SIZE(_post_div_table), \ + .width = _width, \ + .regs = _regs, \ + .clkr.hw.init = &(struct clk_init_data){ \ + .name = #_name, \ + .parent_hws = (const struct clk_hw*[]){ \ + _parent_hws, \ + }, \ + .num_parents = 1, \ + .ops = _ops, \ + .flags = _flags, \ + }, \ + } + +#define DEFINE_QCOM_CC_CLK_ALPHA_PLL(_name, _offset, \ + _enable_reg, _enable_mask, \ + _parent_fw_name) \ + __DEFINE_QCOM_CC_CLK_ALPHA_PLL(_name, _offset, \ + clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], \ + _enable_reg, _enable_mask, \ + _parent_fw_name, 0, \ + &clk_alpha_pll_fixed_fabia_ops) + +#define DEFINE_QCOM_CC_CLK_ALPHA_PLL_POSTDIV(_name, _offset, \ + _post_div_shift, _post_div_table, \ + _width, _parent_hws) \ + __DEFINE_QCOM_CC_CLK_ALPHA_PLL_POSTDIV(_name, _offset, \ + _post_div_shift, _post_div_table, _width, \ + clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], \ + _parent_hws, 0, &clk_alpha_pll_postdiv_fabia_ops) + extern const struct clk_ops clk_alpha_pll_ops; extern const struct clk_ops clk_alpha_pll_fixed_ops; extern const struct clk_ops clk_alpha_pll_hwfsm_ops; From patchwork Tue Jul 26 14:23:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 593511 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4DA5C00140 for ; Tue, 26 Jul 2022 14:23:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239271AbiGZOX4 (ORCPT ); Tue, 26 Jul 2022 10:23:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239253AbiGZOXx (ORCPT ); Tue, 26 Jul 2022 10:23:53 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA7FD2873B for ; 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Tue, 26 Jul 2022 07:23:50 -0700 (PDT) Received: from localhost.localdomain ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id t21-20020a1c7715000000b003a331c6bffdsm17017119wmi.47.2022.07.26.07.23.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 07:23:49 -0700 (PDT) From: Abel Vesa To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Mike Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Linux Kernel Mailing List , Abel Vesa Subject: [RFC 6/9] clk: qcom: common: Add macro wrapper for all clock types Date: Tue, 26 Jul 2022 17:23:00 +0300 Message-Id: <20220726142303.4126434-7-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.3 In-Reply-To: <20220726142303.4126434-1-abel.vesa@linaro.org> References: <20220726142303.4126434-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a generic macro that uses the clk_type to figure out which clock type specific macro to call. Signed-off-by: Abel Vesa --- drivers/clk/qcom/common.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index 9c8f7b798d9f..475febd19dba 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -19,6 +19,9 @@ struct clk_hw; #define PLL_VOTE_FSM_ENA BIT(20) #define PLL_VOTE_FSM_RESET BIT(21) +#define DEFINE_QCOM_CC_CLK(clk_type, ...) \ + DEFINE_QCOM_CC_CLK_##clk_type(__VA_ARGS__) + struct qcom_cc_desc { const struct regmap_config *config; struct clk_regmap **clks; From patchwork Tue Jul 26 14:23:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 593509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B9E7C04A68 for ; Tue, 26 Jul 2022 14:24:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239211AbiGZOYP (ORCPT ); Tue, 26 Jul 2022 10:24:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239285AbiGZOX7 (ORCPT ); Tue, 26 Jul 2022 10:23:59 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B37982983F for ; Tue, 26 Jul 2022 07:23:54 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id l15so16335615wro.11 for ; Tue, 26 Jul 2022 07:23:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v7i/uQ3DjdzEQt9s+bjB4ZzmhQ5Ksdu2J2iSUOzx3xk=; b=VlExN11m/xKEq6RFZyFwqCm718lldPuvAc6HVpMi/5/h+DaMSpAhxFoFZm9wlYWdPC mLYeO1btAPFHCLtM7JyiqDazfmfAGvy5D/cAgiHpn43q/LtdojNgYcFFgk3MnXkPLU72 94v/39sulSTDebkiaJcZVRSmeFNjAFVukmwsLTdrK5Ev/RZaLBPl2RTnKUOahSOLgGqo djalSCBUaASFFHxGVkZLI64jWZO21/hNI4FjQBfJpziVfgjY2M+L4mvRThOwsvkHY3ej hPha7ITJyh7tAyJd+wRGByWeL2B+ITLqvuHYIIpcru0mSWp6ygP4W5Df1uQR7nUQ67Rx 3o6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v7i/uQ3DjdzEQt9s+bjB4ZzmhQ5Ksdu2J2iSUOzx3xk=; b=24RH+r9GJRczTqgFnOGoKb1UOgQKl+dZNn427PqIQ8pER4EzHwU4GV5cUYw0vhxvG/ mzzkXv4pikJyxp2/3TgbjYrIH76W9CGVGJJiQOAc10juIFFI+ZBMZ/2mbmjvsaQV37wk /Hlhu4VJJk4LULfLrdtTRMb11zRKNR0cGUCvQA59/7JAUDyEB3H7UZh3rtVLXhzZmz3h pvM5nLpLTntK7iL8SAo7FUccGcEcf3Qw9u3a4sSBmpoV//LlF4Rg0DGKOT9u3/Nk7hf0 tPE1v7EgBwWd8VZHFO/seuTFlrMMHVREecRgZAWZUoFgFT50V5l60fVhrgQlXWGIvSil QqBw== X-Gm-Message-State: AJIora9U6jCQADJvb4nBvkKMAy7pQwvoTfXoxhoY2Tg+6ZNnWxo6646c iKI/GOInawtMHvrASYKpT43TJyfYff+o3A== X-Google-Smtp-Source: AGRyM1ssWbDVP8KtCaTsELE8oiR0zedtzDuwa0zZbYxnUqO2A7hPAE4VoEG8Bq55+p6xbz4rS1+xtQ== X-Received: by 2002:a05:6000:18af:b0:21d:93a5:2d2 with SMTP id b15-20020a05600018af00b0021d93a502d2mr10909154wri.301.1658845433165; Tue, 26 Jul 2022 07:23:53 -0700 (PDT) Received: from localhost.localdomain ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id t21-20020a1c7715000000b003a331c6bffdsm17017119wmi.47.2022.07.26.07.23.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jul 2022 07:23:52 -0700 (PDT) From: Abel Vesa To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Mike Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Linux Kernel Mailing List , Abel Vesa Subject: [RFC 8/9] clk: qcom: gcc-sdm845: Switch to macros to collapse rcg2 clocks definitions Date: Tue, 26 Jul 2022 17:23:02 +0300 Message-Id: <20220726142303.4126434-9-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.3 In-Reply-To: <20220726142303.4126434-1-abel.vesa@linaro.org> References: <20220726142303.4126434-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Switch from the expanded rcg2 clocks definitions to the more compact macros. Signed-off-by: Abel Vesa --- drivers/clk/qcom/gcc-sdm845.c | 712 +++------------------------------- 1 file changed, 51 insertions(+), 661 deletions(-) diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index 2e66256599d3..d9751d7e617c 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -200,39 +200,11 @@ static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { { } }; -static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { - .cmd_rcgr = 0x48014, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_ahb_clk_src", - .parent_data = gcc_parent_data_7_ao, - .num_parents = ARRAY_SIZE(gcc_parent_data_7_ao), - .ops = &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), { } }; -static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { - .cmd_rcgr = 0x4815c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_3, - .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_rbcpr_clk_src", - .parent_data = gcc_parent_data_8_ao, - .num_parents = ARRAY_SIZE(gcc_parent_data_8_ao), - .ops = &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), @@ -242,102 +214,18 @@ static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { { } }; -static struct clk_rcg2 gcc_gp1_clk_src = { - .cmd_rcgr = 0x64004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp1_clk_src", - .parent_data = gcc_parent_data_1, - .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_gp2_clk_src = { - .cmd_rcgr = 0x65004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp2_clk_src", - .parent_data = gcc_parent_data_1, - .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_gp3_clk_src = { - .cmd_rcgr = 0x66004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp3_clk_src", - .parent_data = gcc_parent_data_1, - .num_parents = ARRAY_SIZE(gcc_parent_data_1), - .ops = &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { F(9600000, P_BI_TCXO, 2, 0, 0), F(19200000, P_BI_TCXO, 1, 0, 0), { } }; -static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { - .cmd_rcgr = 0x6b028, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_0_aux_clk_src", - .parent_data = gcc_parent_data_2, - .num_parents = ARRAY_SIZE(gcc_parent_data_2), - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { - .cmd_rcgr = 0x8d028, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_1_aux_clk_src", - .parent_data = gcc_parent_data_2, - .num_parents = ARRAY_SIZE(gcc_parent_data_2), - .ops = &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), { } }; -static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { - .cmd_rcgr = 0x6f014, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pcie_phy_refgen_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), @@ -346,20 +234,6 @@ static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { { } }; -static struct clk_rcg2 gcc_qspi_core_clk_src = { - .cmd_rcgr = 0x4b008, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qspi_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_core_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_floor_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { F(9600000, P_BI_TCXO, 2, 0, 0), F(19200000, P_BI_TCXO, 1, 0, 0), @@ -367,20 +241,6 @@ static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { { } }; -static struct clk_rcg2 gcc_pdm2_clk_src = { - .cmd_rcgr = 0x33010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_pdm2_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pdm2_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), @@ -400,262 +260,6 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { { } }; -static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { - .name = "gcc_qupv3_wrap0_s0_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { - .cmd_rcgr = 0x17034, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { - .name = "gcc_qupv3_wrap0_s1_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { - .cmd_rcgr = 0x17164, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { - .name = "gcc_qupv3_wrap0_s2_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { - .cmd_rcgr = 0x17294, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { - .name = "gcc_qupv3_wrap0_s3_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { - .cmd_rcgr = 0x173c4, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { - .name = "gcc_qupv3_wrap0_s4_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { - .cmd_rcgr = 0x174f4, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { - .name = "gcc_qupv3_wrap0_s5_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { - .cmd_rcgr = 0x17624, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { - .name = "gcc_qupv3_wrap0_s6_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { - .cmd_rcgr = 0x17754, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { - .name = "gcc_qupv3_wrap0_s7_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { - .cmd_rcgr = 0x17884, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { - .name = "gcc_qupv3_wrap1_s0_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { - .cmd_rcgr = 0x18018, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { - .name = "gcc_qupv3_wrap1_s1_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { - .cmd_rcgr = 0x18148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { - .name = "gcc_qupv3_wrap1_s2_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { - .cmd_rcgr = 0x18278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { - .name = "gcc_qupv3_wrap1_s3_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { - .cmd_rcgr = 0x183a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { - .name = "gcc_qupv3_wrap1_s4_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { - .cmd_rcgr = 0x184d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { - .name = "gcc_qupv3_wrap1_s5_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { - .cmd_rcgr = 0x18608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { - .name = "gcc_qupv3_wrap1_s6_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { - .cmd_rcgr = 0x18738, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, -}; - -static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { - .name = "gcc_qupv3_wrap1_s7_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { - .cmd_rcgr = 0x18868, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, -}; - static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { F(400000, P_BI_TCXO, 12, 1, 4), F(9600000, P_BI_TCXO, 2, 0, 0), @@ -667,20 +271,6 @@ static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { { } }; -static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { - .cmd_rcgr = 0x1400c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_10, - .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_apps_clk_src", - .parent_data = gcc_parent_data_10, - .num_parents = ARRAY_SIZE(gcc_parent_data_10), - .ops = &clk_rcg2_floor_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { F(400000, P_BI_TCXO, 12, 1, 4), F(9600000, P_BI_TCXO, 2, 0, 0), @@ -691,39 +281,11 @@ static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { { } }; -static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { - .cmd_rcgr = 0x1600c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc4_apps_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_floor_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { F(105495, P_BI_TCXO, 2, 1, 91), { } }; -static struct clk_rcg2 gcc_tsif_ref_clk_src = { - .cmd_rcgr = 0x36010, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_6, - .freq_tbl = ftbl_gcc_tsif_ref_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_tsif_ref_clk_src", - .parent_data = gcc_parent_data_6, - .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .ops = &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), @@ -733,20 +295,6 @@ static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { { } }; -static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { - .cmd_rcgr = 0x7501c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_axi_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), @@ -755,34 +303,6 @@ static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { { } }; -static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { - .cmd_rcgr = 0x7505c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_ice_core_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { - .cmd_rcgr = 0x75090, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_phy_aux_clk_src", - .parent_data = gcc_parent_data_4, - .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .ops = &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), @@ -790,20 +310,6 @@ static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { { } }; -static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { - .cmd_rcgr = 0x75074, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_card_unipro_core_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), @@ -813,62 +319,6 @@ static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { { } }; -static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { - .cmd_rcgr = 0x7701c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { - .cmd_rcgr = 0x7705c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { - .cmd_rcgr = 0x77090, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_clk_src", - .parent_data = gcc_parent_data_4, - .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { - .cmd_rcgr = 0x77074, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), @@ -878,20 +328,6 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { { } }; -static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { - .cmd_rcgr = 0xf018, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_master_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), @@ -900,90 +336,6 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { { } }; -static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { - .cmd_rcgr = 0xf030, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_mock_utmi_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { - .cmd_rcgr = 0x10018, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_master_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { - .cmd_rcgr = 0x10030, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sec_mock_utmi_clk_src", - .parent_data = gcc_parent_data_0, - .num_parents = ARRAY_SIZE(gcc_parent_data_0), - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { - .cmd_rcgr = 0xf05c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_aux_clk_src", - .parent_data = gcc_parent_data_2, - .num_parents = ARRAY_SIZE(gcc_parent_data_2), - .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { - .cmd_rcgr = 0x1005c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_sec_phy_aux_clk_src", - .parent_data = gcc_parent_data_2, - .num_parents = ARRAY_SIZE(gcc_parent_data_2), - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 gcc_vs_ctrl_clk_src = { - .cmd_rcgr = 0x7a030, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_3, - .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_vs_ctrl_clk_src", - .parent_data = gcc_parent_data_3, - .num_parents = ARRAY_SIZE(gcc_parent_data_3), - .ops = &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), @@ -991,19 +343,57 @@ static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = { { } }; -static struct clk_rcg2 gcc_vsensor_clk_src = { - .cmd_rcgr = 0x7a018, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_3, - .freq_tbl = ftbl_gcc_vsensor_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_vsensor_clk_src", - .parent_data = gcc_parent_data_8, - .num_parents = ARRAY_SIZE(gcc_parent_data_8), - .ops = &clk_rcg2_ops, - }, -}; +DEFINE_QCOM_CC_CLK(RCG2, gcc_cpuss_ahb_clk_src, 0x48014, 0, 5, gcc_parent_map_0, ftbl_gcc_cpuss_ahb_clk_src, gcc_parent_data_7_ao); +DEFINE_QCOM_CC_CLK(RCG2, gcc_cpuss_rbcpr_clk_src, 0x4815c, 0, 5, gcc_parent_map_3, ftbl_gcc_cpuss_rbcpr_clk_src, gcc_parent_data_8_ao); +DEFINE_QCOM_CC_CLK(RCG2, gcc_gp1_clk_src, 0x64004, 8, 5, gcc_parent_map_1, ftbl_gcc_gp1_clk_src, gcc_parent_data_1); +DEFINE_QCOM_CC_CLK(RCG2, gcc_gp2_clk_src, 0x65004, 8, 5, gcc_parent_map_1, ftbl_gcc_gp1_clk_src, gcc_parent_data_1); +DEFINE_QCOM_CC_CLK(RCG2, gcc_gp3_clk_src, 0x6b028, 8, 5, gcc_parent_map_1, ftbl_gcc_gp1_clk_src, gcc_parent_data_1); +DEFINE_QCOM_CC_CLK(RCG2, gcc_pcie_0_aux_clk_src, 0x6b028, 16, 5, gcc_parent_map_2, ftbl_gcc_pcie_0_aux_clk_src, gcc_parent_data_2); +DEFINE_QCOM_CC_CLK(RCG2, gcc_pcie_1_aux_clk_src, 0x8d028, 16, 5, gcc_parent_map_2, ftbl_gcc_pcie_0_aux_clk_src, gcc_parent_data_2); +DEFINE_QCOM_CC_CLK(RCG2, gcc_pcie_phy_refgen_clk_src, 0x6f014, 0, 5, gcc_parent_map_0, ftbl_gcc_pcie_phy_refgen_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_FLOOR, gcc_qspi_core_clk_src, 0x4b008, 0, 5, gcc_parent_map_0, ftbl_gcc_qspi_core_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2, gcc_pdm2_clk_src, 0x33010, 0, 5, gcc_parent_map_0, ftbl_gcc_pdm2_clk_src, gcc_parent_data_0); + +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s0_clk_src, 0x17034, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s1_clk_src, 0x17164, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s2_clk_src, 0x17294, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s3_clk_src, 0x173c4, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s4_clk_src, 0x174f4, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s5_clk_src, 0x17624, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s6_clk_src, 0x17754, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap0_s7_clk_src, 0x17884, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); + +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s0_clk_src, 0x18018, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s1_clk_src, 0x18148, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s2_clk_src, 0x18278, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s3_clk_src, 0x183a8, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s4_clk_src, 0x184d8, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s5_clk_src, 0x18608, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s6_clk_src, 0x18738, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_qupv3_wrap1_s7_clk_src, 0x18868, 16, 5, gcc_parent_map_0, ftbl_gcc_qupv3_wrap0_s0_clk_src, gcc_parent_data_0); + +DEFINE_QCOM_CC_CLK(RCG2_FLOOR, gcc_sdcc2_apps_clk_src, 0x1400c, 8, 5, gcc_parent_map_10, ftbl_gcc_sdcc2_apps_clk_src, gcc_parent_data_10); +DEFINE_QCOM_CC_CLK(RCG2_FLOOR, gcc_sdcc4_apps_clk_src, 0x1600c, 8, 5, gcc_parent_map_0, ftbl_gcc_sdcc4_apps_clk_src, gcc_parent_data_0); + +DEFINE_QCOM_CC_CLK(RCG2, gcc_tsif_ref_clk_src, 0x36010, 8, 5, gcc_parent_map_6, ftbl_gcc_tsif_ref_clk_src, gcc_parent_data_6); + +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_ufs_card_axi_clk_src, 0x7501c, 8, 5, gcc_parent_map_0, ftbl_gcc_ufs_card_axi_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_ufs_card_ice_core_clk_src, 0x7505c, 0, 5, gcc_parent_map_0, ftbl_gcc_ufs_card_ice_core_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2, gcc_ufs_card_phy_aux_clk_src, 0x75090, 0, 5, gcc_parent_map_4, ftbl_gcc_cpuss_rbcpr_clk_src, gcc_parent_data_4); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_ufs_card_unipro_core_clk_src, 0x75074, 0, 5, gcc_parent_map_0, ftbl_gcc_ufs_card_unipro_core_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_ufs_phy_axi_clk_src, 0x7701c, 8, 5, gcc_parent_map_0, ftbl_gcc_ufs_phy_axi_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_ufs_phy_ice_core_clk_src, 0x7705c, 0, 5, gcc_parent_map_0, ftbl_gcc_ufs_card_ice_core_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_ufs_phy_phy_aux_clk_src, 0x77090, 0, 5, gcc_parent_map_4, ftbl_gcc_pcie_0_aux_clk_src, gcc_parent_data_4); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_ufs_phy_unipro_core_clk_src, 0x77074, 0, 5, gcc_parent_map_0, ftbl_gcc_ufs_card_ice_core_clk_src, gcc_parent_data_0); + +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_usb30_prim_master_clk_src, 0xf018, 8, 5, gcc_parent_map_0, ftbl_gcc_usb30_prim_master_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_usb30_prim_mock_utmi_clk_src, 0xf030, 8, 5, gcc_parent_map_0, ftbl_gcc_usb30_prim_mock_utmi_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2, gcc_usb30_sec_master_clk_src, 0x10018, 8, 5, gcc_parent_map_0, ftbl_gcc_usb30_prim_master_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2, gcc_usb30_sec_mock_utmi_clk_src, 0x10030, 0, 5, gcc_parent_map_0, ftbl_gcc_usb30_prim_master_clk_src, gcc_parent_data_0); +DEFINE_QCOM_CC_CLK(RCG2, gcc_usb3_prim_phy_aux_clk_src, 0xf05c, 0, 5, gcc_parent_map_2, ftbl_gcc_cpuss_rbcpr_clk_src, gcc_parent_data_2); +DEFINE_QCOM_CC_CLK(RCG2_SHARED, gcc_usb3_sec_phy_aux_clk_src, 0x1005c, 8, 5, gcc_parent_map_2, ftbl_gcc_cpuss_rbcpr_clk_src, gcc_parent_data_2); +DEFINE_QCOM_CC_CLK(RCG2, gcc_vs_ctrl_clk_src, 0x7a030, 0, 5, gcc_parent_map_3, ftbl_gcc_cpuss_rbcpr_clk_src, gcc_parent_data_3); +DEFINE_QCOM_CC_CLK(RCG2, gcc_vsensor_clk_src, 0x7a018, 0, 5, gcc_parent_map_3, ftbl_gcc_vsensor_clk_src, gcc_parent_data_3); DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_aggre_noc_pcie_tbu_clk, 0, 0x90014, 0, 0, 0x90014, BIT(0), 0); DEFINE_QCOM_CC_CLK(BRANCH, HALT, gcc_aggre_ufs_card_axi_clk, 1, 0x82028, 0x82028, 1, 0x82028, BIT(0), CLK_SET_RATE_PARENT, &gcc_ufs_card_axi_clk_src.clkr.hw); From patchwork Tue Jul 26 14:23:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 593510 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0925C00144 for ; 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Tue, 26 Jul 2022 07:23:53 -0700 (PDT) From: Abel Vesa To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Mike Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Linux Kernel Mailing List , Abel Vesa Subject: [RFC 9/9] clk: qcom: gcc-sdm845: Switch to macros to collapse alpha-pll clocks definitions Date: Tue, 26 Jul 2022 17:23:03 +0300 Message-Id: <20220726142303.4126434-10-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.3 In-Reply-To: <20220726142303.4126434-1-abel.vesa@linaro.org> References: <20220726142303.4126434-1-abel.vesa@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Switch from the expanded alpha-pll clocks definitions to the more compact macros. Signed-off-by: Abel Vesa --- drivers/clk/qcom/gcc-sdm845.c | 54 +++-------------------------------- 1 file changed, 4 insertions(+), 50 deletions(-) diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index d9751d7e617c..ed85d3ba771a 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -34,40 +34,6 @@ enum { P_SLEEP_CLK, }; -static struct clk_alpha_pll gpll0 = { - .offset = 0x0, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_fabia_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll4 = { - .offset = 0x76000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gpll4", - .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", .name = "bi_tcxo", - }, - .num_parents = 1, - .ops = &clk_alpha_pll_fixed_fabia_ops, - }, - }, -}; - static const struct clk_div_table post_div_table_fabia_even[] = { { 0x0, 1 }, { 0x1, 2 }, @@ -76,22 +42,10 @@ static const struct clk_div_table post_div_table_fabia_even[] = { { } }; -static struct clk_alpha_pll_postdiv gpll0_out_even = { - .offset = 0x0, - .post_div_shift = 8, - .post_div_table = post_div_table_fabia_even, - .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), - .width = 4, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll0_out_even", - .parent_hws = (const struct clk_hw*[]){ - &gpll0.clkr.hw, - }, - .num_parents = 1, - .ops = &clk_alpha_pll_postdiv_fabia_ops, - }, -}; +DEFINE_QCOM_CC_CLK(ALPHA_PLL, gpll0, 0x0, 0x52000, BIT(0), "bi_tcxo"); +DEFINE_QCOM_CC_CLK(ALPHA_PLL, gpll4, 0x76000, 0x52000, BIT(4), "bi_tcxo"); + +DEFINE_QCOM_CC_CLK(ALPHA_PLL_POSTDIV, gpll0_out_even, 0x0, 8, post_div_table_fabia_even, 4, &gpll0.clkr.hw); static const struct parent_map gcc_parent_map_0[] = { { P_BI_TCXO, 0 },