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([2602:ae:1549:801:673b:b40:a955:bc1b]) by smtp.gmail.com with ESMTPSA id o19-20020aa79793000000b00525343b5047sm10550460pfp.76.2022.07.25.21.58.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jul 2022 21:58:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: yuzenghui@huawei.com, qemu-arm@nongnu.org Subject: [PATCH v2 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features Date: Mon, 25 Jul 2022 21:58:26 -0700 Message-Id: <20220726045828.53697-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220726045828.53697-1-richard.henderson@linaro.org> References: <20220726045828.53697-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Indication for support for SVE will not depend on whether we perform the query on the main kvm_state or the temp vcpu. Signed-off-by: Richard Henderson --- target/arm/kvm64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index d16d4ea250..bb1516b3d5 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -675,7 +675,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) } } - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; + sve_supported = kvm_arm_sve_supported(); /* Add feature bits that can't appear until after VCPU init. */ if (sve_supported) { From patchwork Tue Jul 26 04:58:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 593442 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:b811:0:0:0:0 with SMTP id fc17csp3240923mab; Mon, 25 Jul 2022 22:01:23 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sKaUY+R2o5vzqO1LGrQJQ4WRN1l6AKRF9tVDdfRuf1EA3CiC3VO9vcG6mJom9STtHEBzDp X-Received: by 2002:ac8:4b48:0:b0:31e:fa8c:8555 with SMTP id e8-20020ac84b48000000b0031efa8c8555mr12988062qts.416.1658811683513; Mon, 25 Jul 2022 22:01:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658811683; cv=none; d=google.com; s=arc-20160816; b=V5Q6ssOj7BdTN1fgD6fJdktCrcaWPsmLyy3aSebkFEMG/RJ6F5VX7fjwCOhozb0I9f PosYypSrbsSnJhwvnN3yggctPBt0Z9aSbA/7pqe8ekJ4BNuIA4TQxLCsm4nuH3gRNV03 TYxEZfnqq2BeFcUk/4PtWQI0kYOBQ/APi3gWorHYkAJH1AJ7qDpXnN+xPdb8eFtPT3Au PzafJk3huATuSjpnVM0khTcNB+J/J7QCvKtSjlyYCtuf9yep4U1Ul/waKdwLcfElUJ5Z XFeu4Z0yoSNHRqn/VKIfRNX38yNfW4S6MozeHOIiu83ZhGkNao8tvmlUw/X4B+KJIvGw BWUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KDVN6nTJJe7rCbQUwyIy/u753J7JpZeC4VTwUN/cZno=; b=iEg1lobV0qw9DzZb5mJZLJSOR5V04WAKFqW8nIeXU0eA3ODY7jWPMnSbibr2Ck4XEy EJxonjCOBi0Zz7JuJiIcY6eJHA6Ak9rgC2uaZnAlA61DgQGBu1xmTsWmxC8gGzqJ29Cg tp5Joh8TTW2KLCsSrxogFcwFhXV1Q4KDjgYzyJcDqXLSCBHJ0+m2E26NqHVYbvT9nBn2 B9Obuk47Qvar/muBb2GlA5qgORh5oQnXj8EdgVQZ4Ie37wPh7M17RAtfK0ISSURpqYSa S1bgrx//lqcJ8KwyfyvK/UYNAfwGOVXyHUCGQE1LmuOO1aEsWqiLCnwsu0W95Y/1bz8l QsSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=APhM1Irp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1549:801:673b:b40:a955:bc1b]) by smtp.gmail.com with ESMTPSA id o19-20020aa79793000000b00525343b5047sm10550460pfp.76.2022.07.25.21.58.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jul 2022 21:58:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: yuzenghui@huawei.com, qemu-arm@nongnu.org Subject: [PATCH v2 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host Date: Mon, 25 Jul 2022 21:58:27 -0700 Message-Id: <20220726045828.53697-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220726045828.53697-1-richard.henderson@linaro.org> References: <20220726045828.53697-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because we weren't setting this flag, our probe of ID_AA64ZFR0 was always returning zero. This also obviates the adjustment of ID_AA64PFR0, which had sanitized the SVE field. The effects of the bug are not visible, because the only thing that ID_AA64ZFR0 is used for within qemu at present is tcg translation. The other tests for SVE within KVM are via ID_AA64PFR0.SVE. Reported-by: Zenghui Yu Signed-off-by: Richard Henderson --- target/arm/kvm64.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index bb1516b3d5..43cd7eb890 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -507,7 +507,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) bool sve_supported; bool pmu_supported = false; uint64_t features = 0; - uint64_t t; int err; /* Old kernels may not know about the PREFERRED_TARGET ioctl: however @@ -528,10 +527,17 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) struct kvm_vcpu_init init = { .target = -1, }; /* - * Ask for Pointer Authentication if supported. We can't play the - * SVE trick of synthesising the ID reg as KVM won't tell us - * whether we have the architected or IMPDEF version of PAuth, so - * we have to use the actual ID regs. + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, + * which is otherwise RAZ. + */ + sve_supported = kvm_arm_sve_supported(); + if (sve_supported) { + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; + } + + /* + * Ask for Pointer Authentication if supported, so that we get + * the unsanitized field values for AA64ISAR1_EL1. */ if (kvm_arm_pauth_supported()) { init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | @@ -675,20 +681,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) } } - sve_supported = kvm_arm_sve_supported(); - - /* Add feature bits that can't appear until after VCPU init. */ if (sve_supported) { - t = ahcf->isar.id_aa64pfr0; - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - ahcf->isar.id_aa64pfr0 = t; - /* * There is a range of kernels between kernel commit 73433762fcae * and f81cb2c3ad41 which have a bug where the kernel doesn't expose * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled - * SVE support, so we only read it here, rather than together with all - * the other ID registers earlier. + * SVE support, which resulted in an error rather than RAZ. + * So only read the register if we set KVM_ARM_VCPU_SVE above. */ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, ARM64_SYS_REG(3, 0, 0, 4, 4)); From patchwork Tue Jul 26 04:58:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 593443 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:b811:0:0:0:0 with SMTP id fc17csp3240931mab; Mon, 25 Jul 2022 22:01:24 -0700 (PDT) X-Google-Smtp-Source: AGRyM1s8ZNe2d3gviCuMp9Z6098aHBECPfYT74uLstKe+R3yu99rX6E1uUwkvqS4+sJV0RxRFl/t X-Received: by 2002:ac8:5b93:0:b0:31e:f963:4f4b with SMTP id a19-20020ac85b93000000b0031ef9634f4bmr13254024qta.461.1658811684043; Mon, 25 Jul 2022 22:01:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658811684; cv=none; d=google.com; s=arc-20160816; b=KB/lFlT9s4qPG7Grg67GxmcyLQiD/mEZNFrzfC9zV/7jDNFygp4qW2QU5GhGAQVKWs Y1FiYxwJgwOPNptguNLyrTgbwwsc5lRyFR8LxHhcgzcdpKuXm0vhKBXjNYqB+BuMKY48 dvonZvI+0MCv9zRTv03TRQDhI13e6bTiXkd+YIvQad0HlPK1nwGWyhA+OmkX5dPLk7hC WEwLJmmaqmfqDXIZU25Dn3nuRIk6eck52Ep19XEOTPFWFVkzAHvukIjoFm/8clzBwxMu NDwpltVX+/5XKxUtd3caQA/UZ4cOr5S6bdXmnZxOLw4E8tJ+zYItzCHtFXnVtBtNJNBC a97A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=emSFyLsiKiz9IhTW6WmW8M3rFKM7w+1zQzDRk8176ug=; b=npW9Z85xjqHjF/BGjRVrFiEgAXkOLNMKv5DY7t1rmP4wMlWjOry3xH+4whCLYdAQ0J jZJKoP+sevpKeGqjS2adxQrkQlR0fJ3efD1LXUcMD3BP+GvgPKH+qY5Z1pJeuBjgVibx DsCzwJlBuxJ8thXKn6kQyX0moNUqJsmHSzGIWvAEiroMN288fESOh5djtNtxxdpsB3cH 1axC6yRt2yEvlRs30DsHBiMiIP+i3W4EiHn9QlOchq60T2Mf3jJw/k3hG+eG0PAGnqmH X3JQtj8JWBmum56VVhUqfsFQWyQEGnKDEl5AKw3KiSOivGEaZtKuBbv4esqUftagpmar q0sg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JVkZgxXg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1549:801:673b:b40:a955:bc1b]) by smtp.gmail.com with ESMTPSA id o19-20020aa79793000000b00525343b5047sm10550460pfp.76.2022.07.25.21.58.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jul 2022 21:58:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: yuzenghui@huawei.com, qemu-arm@nongnu.org Subject: [PATCH v2 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch Date: Mon, 25 Jul 2022 21:58:28 -0700 Message-Id: <20220726045828.53697-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220726045828.53697-1-richard.henderson@linaro.org> References: <20220726045828.53697-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The test for the IF block indicates no ID registers are exposed, much less host support for SVE. Move the SVE probe into the ELSE block. Signed-off-by: Richard Henderson --- target/arm/kvm64.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 43cd7eb890..9b9dd46d78 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -679,18 +679,18 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, ARM64_SYS_REG(3, 3, 9, 12, 0)); } - } - if (sve_supported) { - /* - * There is a range of kernels between kernel commit 73433762fcae - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled - * SVE support, which resulted in an error rather than RAZ. - * So only read the register if we set KVM_ARM_VCPU_SVE above. - */ - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, - ARM64_SYS_REG(3, 0, 0, 4, 4)); + if (sve_supported) { + /* + * There is a range of kernels between kernel commit 73433762fcae + * and f81cb2c3ad41 which have a bug where the kernel doesn't + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has + * enabled SVE support, which resulted in an error rather than RAZ. + * So only read the register if we set KVM_ARM_VCPU_SVE above. + */ + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, + ARM64_SYS_REG(3, 0, 0, 4, 4)); + } } kvm_arm_destroy_scratch_host_vcpu(fdarray);