From patchwork Tue Jan 29 13:23:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 156987 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp4657507jaa; Tue, 29 Jan 2019 05:23:54 -0800 (PST) X-Google-Smtp-Source: ALg8bN7MwVdmUS1IbguSFedfevlLKr/UtyoIK7CQzqJfKNFnego+l/3Jwu7dI1JW0CxeMXdUzxms X-Received: by 2002:a63:e247:: with SMTP id y7mr22606496pgj.84.1548768234357; Tue, 29 Jan 2019 05:23:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548768234; cv=none; d=google.com; s=arc-20160816; b=hgeKFxUf+ArgShyWeaexwuyvuUOgtQpzbl1zi5p5I9vTEMpJPj8tm3kNwGLXS8DRUb iSkX1bVVk6WfQkrJdnebvhgV+gR5DiZlaXtweUT72N2FuRgl2n/iaKVY39efdJ21EtDk jEdz79fm3njRBGmYB6OzYEkhjWo+dMQ+G3LhyU8SwSKCHPF4CRxgqZH6lTE2ExTkePBG Cu3jnppc//ml4OU2cVgYzMRRS/ussBeEoBd2VS5c43pmvFHtyhxm8mPS15qdLW7Jc8z8 IfmHf6VrX3EFj8qbG4A/qrQPzZ9P6vGZ4o6IgK1yvNGolR2w/VpXUlNHF7wqNSyV98vj TqBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=C9cOt5ITDVopsgviHrr1V3PGSqn/anQnP2GxQeP5Cxg=; b=KphQQ8v8iFJcokO/PX7sd1ZFcE6d1EiaGD/qoS2Sfljwk8wjPHAeEGXz9IPJhjkGLu w97NSx/BYmgrZ/jX/WKjrJ/BUvjM6P1pj+j0bNh2l4f3ZJsJccMJZ5PIUIfAOSf5q+X+ epOjwnXaLD+Eo4MwM/gSCVwdyHW/o3oxesTYlDgEIdDhVpcGtiSVMzrE0h8Ycex+RUIu pKynQC+R/jYQ/xmNo8x6ps0cun8jznHP2maPNoi3SQ5rvdJbpZC6eJhcbZ1mE8RIez5F K6y0YT6JLDN5n3MxXXgBBVXLf0gvfUnsAVEesFd5fA2a5YA4EAaKg83VTsygwEdMwBYF Ydlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=V5DWwx0n; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[86.30.250.44]) by smtp.gmail.com with ESMTPSA id w80sm3739628wme.38.2019.01.29.05.23.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Jan 2019 05:23:50 -0800 (PST) From: Srinivas Kandagatla To: andy.gross@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Jordan Crouse , Vivek Gautam , Srinivas Kandagatla Subject: [PATCH 1/6] arm64: dts: msm8996: Add graphics smmu node Date: Tue, 29 Jan 2019 13:23:30 +0000 Message-Id: <20190129132335.30695-2-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190129132335.30695-1-srinivas.kandagatla@linaro.org> References: <20190129132335.30695-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jordan Crouse Add device node for graphics smmu, aka. adreno_smmu. Signed-off-by: Jordan Crouse Signed-off-by: Vivek Gautam Signed-off-by: Srinivas Kandagatla --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.20.1 diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 6ba96916c66d..c9b80d175fd4 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1138,6 +1138,23 @@ }; }; + adreno_smmu: arm,smmu@b40000 { + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; + reg = <0xb40000 0x10000>; + + #global-interrupts = <1>; + interrupts = , + , + ; + #iommu-cells = <1>; + + clocks = <&mmcc GPU_AHB_CLK>, + <&gcc GCC_MMSS_BIMC_GFX_CLK>; + clock-names = "iface", "bus"; + + power-domains = <&mmcc GPU_GDSC>; + }; + agnoc@0 { power-domains = <&gcc AGGRE0_NOC_GDSC>; compatible = "simple-pm-bus"; From patchwork Tue Jan 29 13:23:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 156989 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp4657552jaa; Tue, 29 Jan 2019 05:23:56 -0800 (PST) X-Google-Smtp-Source: ALg8bN46a21zuls8ZgSIgS+b9pXT8Nl0mpm2sibIRdRGDywmsPvG56xLqEHX2zhN06s1bOQLtEVz X-Received: by 2002:a63:fd53:: with SMTP id m19mr23939829pgj.340.1548768236924; Tue, 29 Jan 2019 05:23:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548768236; cv=none; d=google.com; s=arc-20160816; b=O4cDIFc+K0LW6x5zOeEHaDYbCvK7qXYE11xeWfn/Wbbm98uhv2cDXBNnE3+0e9U9wF JXozW8aarOPp1bz9x1zQNU9BeDCAOxaahDcJUsKp5OZMUxCh6+kMnOK7xlymuGWrCHHZ egH5C1SA96NmZSkg8TgD5H+Bb/uEnWJb8veiz02MgF2taFN7UvdIysX+r1PSWZMyCpVT Xvs7g/eco+PM7U3yeKVLeSUdd5u+MQ9x2rTl6CBqlAufaJlHmP84IE2aOTQ1n3+tf2Gh g2IkIZ2csL4LgFAIFFkLqA66Cz0a5gWW3XBqmHQOZcsvRXArbB6WKUjXgSGZk4U5pqQ1 squw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cJVPwkmiIQelbKGNm2p5QIWk1VCEgPV2Jz4v/peH4c0=; b=SqJAW4hEi8xWj/rZfAG4Te6OupyBqtEKBhaMlZwS3xJPsm8FrbdWrLB4SmIjuECcp1 vhJlzno7ZREvSZYzLdFaAl08KDjR4zbFtcPlcnmIZ5EZ3Jq5oNS8CK9nlWkast6+vOTo zVfwYdyS5mr530BJLgTPh+HWGqa4Z+RYXh//537/gpQpPGSaq24XBRxjQIbsHS1rm3uR ITcRkDg3qYQ6r3l/WfkOGA7Ibi3n4NVQXwx2LFRCpQ/iOoS9OKpSRpguWdHqOQmGM6cn IvRasE3JHZzDFnA9FExcIymI7w3l1fzSq679rdNIvHMg1A/GfGclTOuehh4kyj+kjeWB rr8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=imGOnd4x; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[86.30.250.44]) by smtp.gmail.com with ESMTPSA id w80sm3739628wme.38.2019.01.29.05.23.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Jan 2019 05:23:53 -0800 (PST) From: Srinivas Kandagatla To: andy.gross@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Archit Taneja , Vivek Gautam , Srinivas Kandagatla Subject: [PATCH 3/6] arm64: qcom: msm8996.dtsi: Add Display nodes Date: Tue, 29 Jan 2019 13:23:32 +0000 Message-Id: <20190129132335.30695-4-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190129132335.30695-1-srinivas.kandagatla@linaro.org> References: <20190129132335.30695-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Archit Taneja Signed-off-by: Archit Taneja [Removed instances of mmagic clocks; Use qcom,msm8996-smmu-v2 bindings] Signed-off-by: Vivek Gautam Signed-off-by: Srinivas Kandagatla --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 120 ++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) -- 2.20.1 diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 96adda520bd5..0d0b9482aa4d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1337,6 +1337,126 @@ "bus_slave"; }; }; + + mdss: mdss@900000 { + compatible = "qcom,mdss"; + + reg = <0x900000 0x1000>, + <0x9b0000 0x1040>, + <0x9b8000 0x1040>; + reg-names = "mdss_phys", + "vbif_phys", + "vbif_nrt_phys"; + + power-domains = <&mmcc MDSS_GDSC>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&mmcc MDSS_AHB_CLK>; + clock-names = "iface_clk"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdp: mdp@901000 { + compatible = "qcom,mdp5"; + reg = <0x901000 0x90000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc SMMU_MDP_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface_clk", + "bus_clk", + "core_clk", + "iommu_clk", + "vsync_clk"; + + iommus = <&mdp_smmu 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf3_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; + }; + + hdmi: hdmi-tx@9a0000 { + compatible = "qcom,hdmi-tx-8996"; + reg = <0x009a0000 0x50c>, + <0x00070000 0x6158>, + <0x009e0000 0xfff>; + reg-names = "core_physical", + "qfprom_physical", + "hdcp_physical"; + + interrupt-parent = <&mdss>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_HDMI_CLK>, + <&mmcc MDSS_HDMI_AHB_CLK>, + <&mmcc MDSS_EXTPCLK_CLK>; + clock-names = + "mdp_core_clk", + "iface_clk", + "core_clk", + "alt_iface_clk", + "extp_clk"; + + phys = <&hdmi_phy>; + phy-names = "hdmi_phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hdmi_in: endpoint { + remote-endpoint = <&mdp5_intf3_out>; + }; + }; + }; + }; + + hdmi_phy: hdmi-phy@9a0600 { + #phy-cells = <0>; + compatible = "qcom,hdmi-phy-8996"; + reg = <0x9a0600 0x1c4>, + <0x9a0a00 0x124>, + <0x9a0c00 0x124>, + <0x9a0e00 0x124>, + <0x9a1000 0x124>, + <0x9a1200 0x0c8>; + reg-names = "hdmi_pll", + "hdmi_tx_l0", + "hdmi_tx_l1", + "hdmi_tx_l2", + "hdmi_tx_l3", + "hdmi_phy"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&gcc GCC_HDMI_CLKREF_CLK>; + clock-names = "iface_clk", + "ref_clk"; + }; + }; }; adsp-pil { From patchwork Tue Jan 29 13:23:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 156990 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp4657584jaa; Tue, 29 Jan 2019 05:23:58 -0800 (PST) X-Google-Smtp-Source: ALg8bN40h2inI5mIY0hyk/AGwODdRM4X0ikbrrqelBsTGLLjNhsrXoDLPo1LmM20lIyx7spOl+2F X-Received: by 2002:a63:60cf:: with SMTP id u198mr23853375pgb.323.1548768238328; Tue, 29 Jan 2019 05:23:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548768238; cv=none; d=google.com; s=arc-20160816; b=o1puSsLGhWNvyuqCJu32UYRmd4XDTCjbCGNQSTXZUJk2iMtmtQuErDEqBpm3uAy/nV xJUILBiDfuCdy6bG8SMrRc6haygxpH16vXpKXOdGlMFeWSdJdES+Fu8YwUHZjaiWOnK7 4sqtiMauWfPOT2wxfyZ8Isyp7o6DFtE95kNl2chFPKJOePCLHMuPz7OQQNDyf2jdBGXX kNHMOW6t2sFuvGqmCjZ4RjxUzU3G2nXCAlKFmMfjwYTP8lfPnf0e3IBJU8JPjExcx4tg fcVn2HOJeKJ/ZPDiLGqcIsM6JE7p7Qlylsy43JsvqrbyZqxGii9WDwywn9lo3tUZWBZ6 5ZEg== ARC-Message-Signature: i=1; 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[86.30.250.44]) by smtp.gmail.com with ESMTPSA id w80sm3739628wme.38.2019.01.29.05.23.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Jan 2019 05:23:54 -0800 (PST) From: Srinivas Kandagatla To: andy.gross@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Jordan Crouse , Vivek Gautam , Srinivas Kandagatla Subject: [PATCH 4/6] arm64: dts: Add Adreno GPU and GPU smmu definitions Date: Tue, 29 Jan 2019 13:23:33 +0000 Message-Id: <20190129132335.30695-5-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190129132335.30695-1-srinivas.kandagatla@linaro.org> References: <20190129132335.30695-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jordan Crouse Add an initial node for the Adreno GPU and it's companion SMMU. The GPU node is mostly complete except for a bare bones power table that will be filled out more completely later. Signed-off-by: Jordan Crouse [Remove mmagic clocks from GPU/smmu nodes] Signed-off-by: Vivek Gautam Signed-off-by: Srinivas Kandagatla --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 52 +++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) -- 2.20.1 diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 0d0b9482aa4d..b5f23594905c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -84,6 +84,12 @@ qcom,client-id = <1>; qcom,vmid = <15>; }; + + zap_shader_region: gpu@8f200000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x90b00000 0x0 0xa00000>; + no-map; + }; }; cpus { @@ -1338,6 +1344,52 @@ }; }; + gpu@b00000 { + compatible = "qcom,adreno-530.2", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0xb00000 0x3f000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&mmcc GPU_GX_GFX3D_CLK>, + <&mmcc GPU_AHB_CLK>, + <&mmcc GPU_GX_RBBMTIMER_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_MMSS_BIMC_GFX_CLK>; + + clock-names = "core", + "iface", + "rbbmtimer", + "mem", + "mem_iface"; + + power-domains = <&mmcc GPU_GDSC>; + iommus = <&adreno_smmu 0>; + + qcom,gpu-quirk-two-pass-use-wfi; + qcom,gpu-quirk-fault-detect-mask; + + /* This is a safe speed for bring up in all bin levels. + * This isn't the fastest the chip can go, but we can + * get there eventually */ + qcom,gpu-pwrlevels { + compatible = "qcom,gpu-pwrlevels"; + qcom,gpu-pwrlevel@0 { + qcom,gpu-freq = <510000000>; + }; + qcom,gpu-pwrlevel@1 { + qcom,gpu-freq = <27000000>; + }; + }; + + zap-shader { + memory-region = <&zap_shader_region>; + }; + }; + mdss: mdss@900000 { compatible = "qcom,mdss";