From patchwork Mon Jul 25 07:52:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alain Volmat X-Patchwork-Id: 593356 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96891CCA473 for ; Mon, 25 Jul 2022 07:53:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232082AbiGYHxh (ORCPT ); Mon, 25 Jul 2022 03:53:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231387AbiGYHxa (ORCPT ); Mon, 25 Jul 2022 03:53:30 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC7F712AD7; Mon, 25 Jul 2022 00:53:29 -0700 (PDT) Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 26P7FAwf006147; Mon, 25 Jul 2022 09:53:19 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=6razgSe0W2c3Jx+HKO5kPTMtBrHCoPC0SPCdLXo7BWw=; b=sdYSfLRwuIhHV0AMaExjlCQ7MlJ3z8UNHpzTzQnSLc/S0wbW9dtRBdfKCjWTnJvDSh5E yV1DbhZQl7ZuS1fIelRpkQSM0QAtj4w0/GanZTCTB/RX2ATxNvsQzzllNNj3kVOACS9y l3/tQVV+6kzeRx5IVQ+zkJLVBnCUJp1w70OYGXqaixNF2yBrDfnneCDzrDdw2XwjFvgK diDe2pE8Gkk5cv46bpQ3q21OPeGl5LwV9SHFkK62F/EATneh/yci62Bovj+u1WIe67tP evLZnQ5+LpKNSD92W3e2HXGS3qpwYpzhdJel8KyEf8Lr32TKmKMcQYO82Il1h7M6oA7L WA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3hg8b0qu3g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Jul 2022 09:53:19 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6E993100039; Mon, 25 Jul 2022 09:53:19 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 691602122FA; Mon, 25 Jul 2022 09:53:19 +0200 (CEST) Received: from localhost (10.75.127.48) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2308.20; Mon, 25 Jul 2022 09:53:19 +0200 From: Alain Volmat To: CC: , , , , , , , Subject: [PATCH v2 2/2] ARM: dts: stm32: add pinctrl and disabled spi5 node in stm32mp135f-dk Date: Mon, 25 Jul 2022 09:52:55 +0200 Message-ID: <20220725075255.429869-3-alain.volmat@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220725075255.429869-1-alain.volmat@foss.st.com> References: <20220725075255.429869-1-alain.volmat@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-23_02,2022-07-21_02,2022-06-22_01 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pinctrl information and a disabled spi5 node within stm32mp135f-dk.dts in order to use the spi5 bus which is available via the GPIO expansion pins of the STM32MP135 Discovery board. Signed-off-by: Alain Volmat --- arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 23 +++++++++++++++++++++++ arch/arm/boot/dts/stm32mp135f-dk.dts | 7 +++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index 749078ba9d42..efdd163eba30 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -142,6 +142,29 @@ pins { }; }; + spi5_pins_a: spi5-0 { + pins1 { + pinmux = , /* SPI5_SCK */ + ; /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI5_MISO */ + bias-disable; + }; + }; + + spi5_sleep_pins_a: spi5-sleep-0 { + pins { + pinmux = , /* SPI5_SCK */ + , /* SPI5_MISO */ + ; /* SPI5_MOSI */ + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index 3e2823332d51..de341d17e87d 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -116,6 +116,13 @@ &sdmmc1 { status = "okay"; }; +&spi5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi5_pins_a>; + pinctrl-1 = <&spi5_sleep_pins_a>; + status = "disabled"; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>;