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([2602:ae:1549:801:30c1:2484:a853:233d]) by smtp.gmail.com with ESMTPSA id bg5-20020a1709028e8500b0016d8d277c02sm1125004plb.25.2022.07.25.11.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jul 2022 11:15:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: yuzenghui@huawei.com, qemu-arm@nongnu.org Subject: [PATCH 1/3] target/arm: Create kvm_arm_svm_supported Date: Mon, 25 Jul 2022 11:14:55 -0700 Message-Id: <20220725181457.41083-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220725181457.41083-1-richard.henderson@linaro.org> References: <20220725181457.41083-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Indication for support for SVE will not depend on whether we perform the query on the main kvm_state or the temp vcpu. Mirror kvm_arm_pauth_supported. Signed-off-by: Richard Henderson --- target/arm/kvm64.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index d16d4ea250..36ff20c9e3 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -496,6 +496,11 @@ static bool kvm_arm_pauth_supported(void) kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); } +static bool kvm_arm_svm_supported(void) +{ + return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); +} + bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and @@ -675,7 +680,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) } } - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; + sve_supported = kvm_arm_svm_supported(); /* Add feature bits that can't appear until after VCPU init. */ if (sve_supported) { From patchwork Mon Jul 25 18:14:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 593289 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:b811:0:0:0:0 with SMTP id fc17csp2898813mab; Mon, 25 Jul 2022 11:21:51 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sIYJo93HbqC7ef5iSiHE6d3QlpoOhSNkb6IX6JwC2jh3wDNRnqRS3tIWy1Y7mENo7zeS2z X-Received: by 2002:a05:620a:4381:b0:6b5:da97:fe0f with SMTP id a1-20020a05620a438100b006b5da97fe0fmr10074990qkp.84.1658773311208; Mon, 25 Jul 2022 11:21:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658773311; cv=none; d=google.com; s=arc-20160816; b=pIP7FwdqnMd4+/AeIuBjRZ3tfnsGhw/y0OdAwaGf+Pb2liKgjymmgFuFsELlVhmcq4 TbrZWqjhZv7sYYYhbS46M9ykpfkpJtw8NKgiR2dHKawxCwy+/EMdb2I2E1zB09xgSY6W IUMzLOAsn/HbxgybLtHLZueN2bXuHN+t3/qvUBaK0ZTzRqqVLsG4QtUb7Iw88Qx8o3oS to4MnWglDSS1MfVYdrQofIXJWhhxbUuQJG9SZQJpc15R5o2ZwXWc2Ubi4whOodwMNhmf S9Y5sqzvFgtygQeWDnuJrkcSRQDXkhC4FqvXtgeNV0jtTWbHyrIqvCf2UkonA/dskkk0 3S1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=N2OJQKKwRLRjFx/fh9iTaEVWiqAoFPuSiTt6AYqCB48=; b=BHKKRbAxEPGN7nGGJvQiW0o9Nk/ZMS2hK+Ar+tA2ZEV5VkgU2IKvxP0LXBXuNYd0dE Pb61S0LpVwZ4UpJOnZzixfPfVhSIalPXHQ4xW9+XQoa2gFr9jaYH9eMn8RClZuNRU7uK 4DjSGw9ZqXPq8ai6R5SFUWfS8uorvHVGoKSro+2zqlMiopEnPUlOE8U+1n6enKrdMFfO 4nTK5JN8pzsczTBBMZ6sGU5UuvaXCvhlS+UxlCceYlxJj2c+x+EJeLgTCxDemov/tjJ6 0crT4pWG0J3/+Uz2irw3ULoUJ/r3wWquVpYZ32jex+YVsrguWF5VVapbi0++uNpAl5yZ EI4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=k4z62w5I; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1549:801:30c1:2484:a853:233d]) by smtp.gmail.com with ESMTPSA id bg5-20020a1709028e8500b0016d8d277c02sm1125004plb.25.2022.07.25.11.15.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jul 2022 11:15:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: yuzenghui@huawei.com, qemu-arm@nongnu.org Subject: [PATCH 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host Date: Mon, 25 Jul 2022 11:14:56 -0700 Message-Id: <20220725181457.41083-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220725181457.41083-1-richard.henderson@linaro.org> References: <20220725181457.41083-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Because we weren't setting this flag, our probe of ID_AA64ZFR0 was always returning zero. This also obviates the adjustment of ID_AA64PFR0, which had sanitized the SVE field. Reported-by: Zenghui Yu Signed-off-by: Richard Henderson --- target/arm/kvm64.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 36ff20c9e3..8b2ae9948a 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -512,7 +512,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) bool sve_supported; bool pmu_supported = false; uint64_t features = 0; - uint64_t t; int err; /* Old kernels may not know about the PREFERRED_TARGET ioctl: however @@ -533,10 +532,17 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) struct kvm_vcpu_init init = { .target = -1, }; /* - * Ask for Pointer Authentication if supported. We can't play the - * SVE trick of synthesising the ID reg as KVM won't tell us - * whether we have the architected or IMPDEF version of PAuth, so - * we have to use the actual ID regs. + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, + * which is otherwise RAZ. + */ + sve_supported = kvm_arm_svm_supported(); + if (sve_supported) { + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; + } + + /* + * Ask for Pointer Authentication if supported, so that we get + * the unsanitized field values for AA64ISAR1_EL1. */ if (kvm_arm_pauth_supported()) { init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | @@ -680,20 +686,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) } } - sve_supported = kvm_arm_svm_supported(); - - /* Add feature bits that can't appear until after VCPU init. */ if (sve_supported) { - t = ahcf->isar.id_aa64pfr0; - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - ahcf->isar.id_aa64pfr0 = t; - /* * There is a range of kernels between kernel commit 73433762fcae * and f81cb2c3ad41 which have a bug where the kernel doesn't expose * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled - * SVE support, so we only read it here, rather than together with all - * the other ID registers earlier. + * SVE support, which resulted in an error rather than RAZ. + * So only read the register if we set KVM_ARM_VCPU_SVE above. */ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, ARM64_SYS_REG(3, 0, 0, 4, 4)); From patchwork Mon Jul 25 18:14:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 593288 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:b811:0:0:0:0 with SMTP id fc17csp2898704mab; Mon, 25 Jul 2022 11:21:41 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vTkAZbF9IRXIYGgajsWqnXhQ9H+3fjm9FnSnXmQHhFWHKPAmozyjqxL6bPBwWOOrbxLpls X-Received: by 2002:a05:620a:28c9:b0:6b5:d74e:5cf8 with SMTP id l9-20020a05620a28c900b006b5d74e5cf8mr10171634qkp.505.1658773301830; Mon, 25 Jul 2022 11:21:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658773301; cv=none; d=google.com; s=arc-20160816; b=pdlEeQIhBTKltXxDsAnFOO7PzvMbEJ/loBJ4lQBCuDRIlrYtnzzWeavO88VI9XKkxj 3a0h7h2sQIGB/Kr2kLUcCIYpvkxpL0k1UnAQBXjZp+U3zeR2plSGw4E/jDVKLH6cbyjz trDuQ1jOO3XDxbuxfsKDiKZ8nQbFVS+rRu6d3WRAyKYYMZWT1YrAiGZrgtYx1WIRu1as MvPwTVmdAsV6rFcTXimnDBACN446USlrdE3kvcqQ7LRh+qdUKhO2eipf2d9dAwQixjrm 48peiE1Z/j32RHcoDquhFMOme0kPdd04+RuDDOxNjM/ugf7oFww0Cqtrm/1ZYQCGZxX4 wEww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RMuYv4EVFHYkxhumjJ2SxEr+kwKlkg7raeV+cD/IvUA=; b=LtijrT79IZePWieGJHtyiKCglUulXRrqHitHJD0ov+gPlHb+HFAsx+W++BOtYQidG/ KDGiwfLdcrKlPhkDn2jUqVWe6+hMFM+jFl4S2FNT0hXnrJPGuM8hP84zhzsOUNCoSoy8 qdCLtbsbGz1gf7Bv/R1Kyrtc8b53TpWCoQhDVbg+ry1MYakbussuPCdt4Bt/+Rtc0DC0 YbsklWtqZik3M/T+7j9afWNasuHahzGGJUj1Kh+5+UuJLCw/3YOyaJHDTdlvaEC5Citu llxCKAqdNHPbFLFo5ZYtgz3S80Szq8u487dHtSUAkkvrmGyI3ypR0lJkqvPtsEhcjkyT 5i6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gdkKLSsn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1549:801:30c1:2484:a853:233d]) by smtp.gmail.com with ESMTPSA id bg5-20020a1709028e8500b0016d8d277c02sm1125004plb.25.2022.07.25.11.15.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jul 2022 11:15:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: yuzenghui@huawei.com, qemu-arm@nongnu.org Subject: [PATCH 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch Date: Mon, 25 Jul 2022 11:14:57 -0700 Message-Id: <20220725181457.41083-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220725181457.41083-1-richard.henderson@linaro.org> References: <20220725181457.41083-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The test for the IF block indicates no ID registers are exposed, much less host support for SVE. Move the SVE probe into the ELSE block. Signed-off-by: Richard Henderson --- target/arm/kvm64.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 8b2ae9948a..bc3d7d9883 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -684,18 +684,18 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, ARM64_SYS_REG(3, 3, 9, 12, 0)); } - } - if (sve_supported) { - /* - * There is a range of kernels between kernel commit 73433762fcae - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled - * SVE support, which resulted in an error rather than RAZ. - * So only read the register if we set KVM_ARM_VCPU_SVE above. - */ - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, - ARM64_SYS_REG(3, 0, 0, 4, 4)); + if (sve_supported) { + /* + * There is a range of kernels between kernel commit 73433762fcae + * and f81cb2c3ad41 which have a bug where the kernel doesn't + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has + * enabled SVE support, which resulted in an error rather than RAZ. + * So only read the register if we set KVM_ARM_VCPU_SVE above. + */ + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, + ARM64_SYS_REG(3, 0, 0, 4, 4)); + } } kvm_arm_destroy_scratch_host_vcpu(fdarray);