From patchwork Sun Jul 24 22:49:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 594175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8B4DC43334 for ; Sun, 24 Jul 2022 22:50:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231775AbiGXWuG (ORCPT ); Sun, 24 Jul 2022 18:50:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229618AbiGXWuF (ORCPT ); Sun, 24 Jul 2022 18:50:05 -0400 Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1275ADEC7 for ; Sun, 24 Jul 2022 15:50:04 -0700 (PDT) Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 1B0C7840B8; Mon, 25 Jul 2022 00:50:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1658703001; bh=23j0cMeP76LtcOutso881U3wO9sI79SMtd8DydDjECg=; h=From:To:Cc:Subject:Date:From; b=O9wW3YRykhP3BG4Vg0A01L3k7okKl1Q/dSmn7iS+QbfLhgDEGL3VVVFC8gDEKz5Yj p8St4jSIz2V8DS2Qmjds9C53dkA21IQe2rKPrIPMtAksoT34MhX+v/JVkW7VrGpXI9 cY7gt+RVVH3AaHHe0zNuzqpVD9LGrxBrHZGySfw8dHTNFuVrPAt+eWrlZr+i77Lco8 DYFq4jcX9GsYa8USgikRY2HFyZmE5fyh2fiWpMMBtW6w4drivpcw2TczGsEj3C67RO 3LsNV/Uc5aTMlHvsuimw0DZ0HMqi86vgJjEstnT9fTMaoOU00MWyiEl2ldPvpidNzO 049I54A2EA6Ww== From: Marek Vasut To: linux-gpio@vger.kernel.org Cc: Marek Vasut , Bartosz Golaszewski , Linus Walleij , Loic Poulain , Marc Zyngier , NXP Linux Team , Peng Fan , Shawn Guo Subject: [PATCH v4 1/2] gpio: mxc: Protect GPIO irqchip RMW with bgpio spinlock Date: Mon, 25 Jul 2022 00:49:42 +0200 Message-Id: <20220724224943.294057-1-marex@denx.de> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The driver currently performs register read-modify-write without locking in its irqchip part, this could lead to a race condition when configuring interrupt mode setting. Add the missing bgpio spinlock lock/unlock around the register read-modify-write. Fixes: 07bd1a6cc7cbb ("MXC arch: Add gpio support for the whole platform") Signed-off-by: Marek Vasut Cc: Bartosz Golaszewski Cc: Linus Walleij Cc: Loic Poulain Cc: Marc Zyngier Cc: NXP Linux Team Cc: Peng Fan Cc: Shawn Guo Reported-by: kernel test robot --- V3: New patch V4: Include linux/spinlock.h --- drivers/gpio/gpio-mxc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index c871602fc5ba9..75e7aceecac0a 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -147,6 +148,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct mxc_gpio_port *port = gc->private; + unsigned long flags; u32 bit, val; u32 gpio_idx = d->hwirq; int edge; @@ -185,6 +187,8 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) return -EINVAL; } + spin_lock_irqsave(&port->gc.bgpio_lock, flags); + if (GPIO_EDGE_SEL >= 0) { val = readl(port->base + GPIO_EDGE_SEL); if (edge == GPIO_INT_BOTH_EDGES) @@ -204,15 +208,20 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) writel(1 << gpio_idx, port->base + GPIO_ISR); + spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); + return 0; } static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) { void __iomem *reg = port->base; + unsigned long flags; u32 bit, val; int edge; + spin_lock_irqsave(&port->gc.bgpio_lock, flags); + reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ bit = gpio & 0xf; val = readl(reg); @@ -230,6 +239,8 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) return; } writel(val | (edge << (bit << 1)), reg); + + spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); } /* handle 32 interrupts in one status register */ From patchwork Sun Jul 24 22:49:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 593217 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F804C433EF for ; Sun, 24 Jul 2022 22:50:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231805AbiGXWuF (ORCPT ); Sun, 24 Jul 2022 18:50:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231775AbiGXWuF (ORCPT ); Sun, 24 Jul 2022 18:50:05 -0400 Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12355CE30 for ; Sun, 24 Jul 2022 15:50:04 -0700 (PDT) Received: from tr.lan (ip-86-49-12-201.bb.vodafone.cz [86.49.12.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 6FE10840FC; Mon, 25 Jul 2022 00:50:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1658703001; bh=P3P7zX7DArAnzm2f9Qx+o5BGy+s0OX4lOObHIR/g+9g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hCmMhW+Arp3JT0gl+yUl5wpjy3wd9+1taUwGlJmwboGC0wd+dNmG2zNRX7NpWIG2R pQrEbDuWGFA/jpwXaaQNpMMDjeW0GJuXyDUZrj/qtwCwRf5lNlQEH3KSut5nj3Ulcu 6HESWc/3GaWs+jWKRqkjAt8NHD1zuHPBcFvbAOUD3L6TwdFxF4t0uJUzC/3ktqLDYX XF+PG9GOd1QTpW2CRXaKHV0v21cv92ow/sCPyuSMqBgIaOaoNPVCRsMF6y2odZSY/E NUVAMWgLFmzkfQoLZoxkhpiPYi0S3/zn2XJeNRXsi8xLewtA9dnpw7t8Si3Ya5DIO5 9RU3hHgK9Lx/A== From: Marek Vasut To: linux-gpio@vger.kernel.org Cc: Marek Vasut , Bartosz Golaszewski , Linus Walleij , Loic Poulain , Marc Zyngier , NXP Linux Team , Peng Fan , Shawn Guo Subject: [PATCH v4 2/2] gpio: mxc: Always set GPIOs used as interrupt source to INPUT mode Date: Mon, 25 Jul 2022 00:49:43 +0200 Message-Id: <20220724224943.294057-2-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220724224943.294057-1-marex@denx.de> References: <20220724224943.294057-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Always configure GPIO pins which are used as interrupt source as INPUTs. In case the default pin configuration is OUTPUT, or the prior stage does configure the pins as OUTPUT, then Linux will not reconfigure the pin as INPUT and no interrupts are received. Always configure interrupt source GPIO pin as input to fix the above case. Fixes: 07bd1a6cc7cbb ("MXC arch: Add gpio support for the whole platform") Signed-off-by: Marek Vasut Cc: Bartosz Golaszewski Cc: Linus Walleij Cc: Loic Poulain Cc: Marc Zyngier Cc: NXP Linux Team Cc: Peng Fan Cc: Shawn Guo Reviewed-by: Linus Walleij --- V2: Actually update and clear bits in GDIR register V3: Rebase on top of new patch 1/2, expand CC list, add Fixes tag V4: No change --- drivers/gpio/gpio-mxc.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 75e7aceecac0a..f4cadbf30c6b8 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -149,7 +149,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct mxc_gpio_port *port = gc->private; unsigned long flags; - u32 bit, val; + u32 bit, val, dir; u32 gpio_idx = d->hwirq; int edge; void __iomem *reg = port->base; @@ -208,6 +208,10 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) writel(1 << gpio_idx, port->base + GPIO_ISR); + dir = readl(port->base + GPIO_GDIR); + dir &= ~BIT(gpio_idx); + writel(dir, port->base + GPIO_GDIR); + spin_unlock_irqrestore(&port->gc.bgpio_lock, flags); return 0;