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[209.51.188.17]) by mx.google.com with ESMTPS id m12si79703259wrn.358.2019.01.28.09.43.36 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 28 Jan 2019 09:43:36 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gAuz06FK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:35967 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goAwZ-0004Ip-52 for patch@linaro.org; Mon, 28 Jan 2019 12:43:35 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60152) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goAst-00024b-QO for qemu-devel@nongnu.org; Mon, 28 Jan 2019 12:39:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goAss-0003Wm-5z for qemu-devel@nongnu.org; Mon, 28 Jan 2019 12:39:47 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:52761) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goAsr-0003Ty-HL for qemu-devel@nongnu.org; Mon, 28 Jan 2019 12:39:45 -0500 Received: by mail-wm1-x342.google.com with SMTP id m1so14933824wml.2 for ; Mon, 28 Jan 2019 09:39:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4Ma4KyFZWMZDWKwrBGwmM0xc8BBD1DkWp6hR/NBgppo=; b=gAuz06FKTv9Y8r9Da05CsvEAmSMjpl8j8HcIrtT9DshKG2mT3OAF9rzXpyStPlRL+a U+4795imPXuovl0bqoeHeqAsYYT8kfGxl4ug5zf4Y7Ag5H4MJWAzpBtHKEWpicxHhb06 9fEucmscjteZp9q3BNn8pEcvTMZsfhmK5Uc/4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4Ma4KyFZWMZDWKwrBGwmM0xc8BBD1DkWp6hR/NBgppo=; b=BgUM+z7cpPINT00fB47d6YGtFQjWR6TKaqsbY8bioWecH1hqBirwjwtvdAQuQkNgwm jWHIr4GiHs/ZEorAbPTpLPPVMbMEa+FpbkEbp+AxhKMGypZ1aAxY4T9cHsKAcO+j2Zkm 01cGH/WAVsuEz9UjNgf3BpZtRZ3PZSRDoK4l36NBJ/bWnICaJN2LIIDHCVmUsJUV8umY FIOx2s9rJUPPh58oikeoz94zqxJ2jaaIQZTYGrULDigH4PUIalDRPXVazOX51MoU23hA qHZr5osMoa0eN8paZrlRn8rQprFIAfcmQ4DAyOK1ojipJlVR3sd9rpY2IeLvtBdLVJ+M 97xA== X-Gm-Message-State: AJcUukeCVTVKPD7sDYyfq/dyzZ4s+HgreTrYerFeV1AHiTJrFsAo7Atz V+9DrKGAlqoYtIy3X7FfnYkI2A== X-Received: by 2002:a7b:ce84:: with SMTP id q4mr18921037wmj.105.1548697182179; Mon, 28 Jan 2019 09:39:42 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id t199sm348163wmt.1.2019.01.28.09.39.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 09:39:40 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 8D6913E050B; Mon, 28 Jan 2019 17:39:40 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 17:39:37 +0000 Message-Id: <20190128173940.25813-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190128173940.25813-1-alex.bennee@linaro.org> References: <20190128173940.25813-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH v1 1/4] target/arm: relax permission checks for HWCAP_CPUID registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Although technically not visible to userspace the kernel does make them visible via a trap and emulate ABI. We provide a new permission mask (PL0U_R) which maps to PL0_R for CONFIG_USER builds and adjust the minimum permission check accordingly. Signed-off-by: Alex Bennée --- target/arm/cpu.h | 12 ++++++++++++ target/arm/helper.c | 6 +++++- 2 files changed, 17 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ff81db420d..3b3c359cca 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2202,6 +2202,18 @@ static inline bool cptype_valid(int cptype) #define PL0_R (0x02 | PL1_R) #define PL0_W (0x01 | PL1_W) +/* + * For user-mode some registers are accessible to EL0 via a kernel + * trap-and-emulate ABI. In this case we define the read permissions + * as actually being PL0_R. However some bits of any given register + * may still be masked. + */ +#ifdef CONFIG_USER_ONLY +#define PL0U_R PL0_R +#else +#define PL0U_R PL1_R +#endif + #define PL3_RW (PL3_R | PL3_W) #define PL2_RW (PL2_R | PL2_W) #define PL1_RW (PL1_R | PL1_W) diff --git a/target/arm/helper.c b/target/arm/helper.c index 92666e5208..42c1c0b144 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6731,7 +6731,11 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, if (r->state != ARM_CP_STATE_AA32) { int mask = 0; switch (r->opc1) { - case 0: case 1: case 2: + case 0: + /* min_EL EL1, but some accessible to EL0 via kernel ABI */ + mask = PL0U_R | PL1_RW; + break; + case 1: case 2: /* min_EL EL1 */ mask = PL1_RW; break; From patchwork Mon Jan 28 17:39:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 156808 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3696343jaa; Mon, 28 Jan 2019 09:40:30 -0800 (PST) X-Google-Smtp-Source: ALg8bN6M1s4QtQIKJ3XVMWowayDHu8MzJS6xsk07WPTh6UUYcxripiDvzVJ7vQzObU3iWBbSjWgA X-Received: by 2002:adf:f1cb:: with SMTP id z11mr22463407wro.35.1548697230737; Mon, 28 Jan 2019 09:40:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548697230; cv=none; d=google.com; s=arc-20160816; b=qjwRJzUCDjukL8WUN7jNBP1L/O67WKYNHNpy63/dqfuv8y4UiqowhJWe1tELz2KScv tLQpN6ZbVul+WpR9m10jUd3O5pIVnOAzEygSaXe4dngBXxTmFEzW/lwO89dbuJRi44fK oLXm4v55A93TjpeXUtuJW4AdkwY5ocx9ArbtvhC6OymFb3CV8h4ORAIODt6UFkohC+0i 0ja1EQCHRH6sVQyNWQfokkUupfZUPPiLX+DDn9vXeulDfNB9wI1di+/Ab3PemQjdFE/z +mttN9UQ9HL4Bii7PRBbqZR6p4+nMxVqvAM7Ugb+D0x2L7MKYLGWaGFHPoQq8j2wK6lZ tGqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=rtKjTx0NfXwlZhYnnXHxQ+aJeket67uwad3MWD6/3qo=; b=m4PLqExhba+SrJyxkQQEXmfkn60qOcE5N882aP6KBqkEqL7RGp2wVel32bagh0evMm n2IESqGbrOK8U+4l7stvn2npMqnShtnwHQVzVsLsRQS7tQsXn+mTaEMTewL92F35Ls9g LFdwVNMK88mKp5hG7CVytQmy+pGfA+l1nAPE2BzM/17YZVeUTUErTPqotv2FxkX775ni lI0O3askWkqytXoN7/yHAB0tTQJOgW61lfgOjNkCTBoPLsmKmXBz06IcPbbJD+At6oi4 /BrnS+5b27mPKKQKWqbKNan2gpey8OkgOMZWn9eV4or22H0zI8Ei2v+zLePaG9OWf0qb irfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=iuoXdebq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::32e Subject: [Qemu-devel] [PATCH v1 2/4] target/arm: expose CPUID registers to userspace X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A number of CPUID registers are exposed to userspace by modern Linux kernels thanks to the "ARM64 CPU Feature Registers" ABI. For QEMU's user-mode emulation we don't need to emulate the kernels trap but just return the value the trap would have done. For this we use the PL0U_R permission mask which allows this access in CONFIG_USER mode. Some registers only return a subset of their contents so we need specific CONFIG_USER_ONLY logic to do this. Signed-off-by: Alex Bennée --- v4 - tweak commit message - use PL0U_R instead of PL1U_R to be less confusing - more CONFIG_USER logic for special cases - mask a bunch of bits for some registers --- target/arm/helper.c | 51 ++++++++++++++++++++++++++++++++------------- 1 file changed, 36 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 42c1c0b144..68808e7293 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3543,7 +3543,7 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) static const ARMCPRegInfo mpidr_cp_reginfo[] = { { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, - .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, + .access = PL0U_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, REGINFO_SENTINEL }; @@ -5488,6 +5488,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) return pfr1; } +#ifndef CONFIG_USER_ONLY static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = arm_env_get_cpu(env); @@ -5498,6 +5499,7 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) } return pfr0; } +#endif /* Shared logic between LORID and the rest of the LOR* registers. * Secure state has already been delt with. @@ -5799,18 +5801,26 @@ void register_cp_regs_for_features(ARMCPU *cpu) * define new registers here. */ ARMCPRegInfo v8_idregs[] = { - /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't - * know the right value for the GIC field until after we - * define these regs. + /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST for system + * emulation because we don't know the right value for the + * GIC field until after we define these regs. For + * user-mode HWCAP_CPUID emulation the GIC bits are masked + * anyway. */ { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, +#ifndef CONFIG_USER_ONLY .access = PL1_R, .type = ARM_CP_NO_RAW, .readfn = id_aa64pfr0_read, - .writefn = arm_cp_write_ignore }, + .writefn = arm_cp_write_ignore +#else + .access = PL0U_R, .type = ARM_CP_CONST, + .resetvalue = cpu->isar.id_aa64pfr0 & 0x000f000f0ff0000ULL +#endif + }, { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, - .access = PL1_R, .type = ARM_CP_CONST, + .access = PL0U_R, .type = ARM_CP_CONST, .resetvalue = cpu->isar.id_aa64pfr1}, { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, @@ -5839,11 +5849,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue = 0 }, { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, - .access = PL1_R, .type = ARM_CP_CONST, + .access = PL0U_R, .type = ARM_CP_CONST, .resetvalue = cpu->id_aa64dfr0 }, { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, - .access = PL1_R, .type = ARM_CP_CONST, + .access = PL0U_R, .type = ARM_CP_CONST, .resetvalue = cpu->id_aa64dfr1 }, { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, @@ -5871,11 +5881,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue = 0 }, { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, - .access = PL1_R, .type = ARM_CP_CONST, - .resetvalue = cpu->isar.id_aa64isar0 }, + .access = PL0U_R, .type = ARM_CP_CONST, +#ifdef CONFIG_USER_ONLY + .resetvalue = cpu->isar.id_aa64isar0 & 0x000fffffff0ffff0ULL +#else + .resetvalue = cpu->isar.id_aa64isar0 +#endif + }, { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, - .access = PL1_R, .type = ARM_CP_CONST, + .access = PL0U_R, .type = ARM_CP_CONST, .resetvalue = cpu->isar.id_aa64isar1 }, { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, @@ -5903,11 +5918,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue = 0 }, { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, - .access = PL1_R, .type = ARM_CP_CONST, + .access = PL0U_R, .type = ARM_CP_CONST, .resetvalue = cpu->isar.id_aa64mmfr0 }, { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, - .access = PL1_R, .type = ARM_CP_CONST, + .access = PL0U_R, .type = ARM_CP_CONST, .resetvalue = cpu->isar.id_aa64mmfr1 }, { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, @@ -6211,7 +6226,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo id_v8_midr_cp_reginfo[] = { { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, - .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, + .access = PL0U_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), .readfn = midr_read }, /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ @@ -6223,7 +6238,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .resetvalue = cpu->midr }, { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, - .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, +#ifdef CONFIG_USER_ONLY + .access = PL0U_R, .type = ARM_CP_CONST, + .resetvalue = 0 /* HW_CPUID IMPDEF fields are 0 */ }, +#else + .access = PL1_R, .type = ARM_CP_CONST, + .resetvalue = cpu->revidr }, +#endif REGINFO_SENTINEL }; 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X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH v1 3/4] linux-user/elfload: enable HWCAP_CPUID for AArch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Riku Voipio , qemu-arm@nongnu.org, =?utf-8?q?Alex_?= =?utf-8?q?Benn=C3=A9e?= , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Userspace programs should (in theory) query the ELF HWCAP before probing these registers. Now we have implemented them all make it public. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- linux-user/elfload.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 Acked-by: Laurent Vivier diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 4cff9e1a31..e95c162097 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -571,6 +571,7 @@ static uint32_t get_elf_hwcap(void) hwcaps |= ARM_HWCAP_A64_FP; hwcaps |= ARM_HWCAP_A64_ASIMD; + hwcaps |= ARM_HWCAP_A64_CPUID; /* probe for the extra features */ #define GET_FEATURE_ID(feat, hwcap) \ From patchwork Mon Jan 28 17:39:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 156813 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3700330jaa; Mon, 28 Jan 2019 09:44:29 -0800 (PST) X-Google-Smtp-Source: ALg8bN5JIQ8fI5Lyr/N6H841/o5za3AL7AVYzl2/+05WukiWMRWhoyAtJJZZX+bXOXiw1fqlz7ca X-Received: by 2002:adf:d0c9:: with SMTP id z9mr21711406wrh.317.1548697469741; Mon, 28 Jan 2019 09:44:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548697469; cv=none; d=google.com; s=arc-20160816; b=AD8ovp63sefj74lpcXORBpUGGW7vGKQ2CHjy8loe5NiiNEbwGftMSxWEPLnUKyto9p Bh1EOYl63Mucl/acjwjaH2s4opmeHnSrXUSYpeWrN4yc8X/T78tQicTunssgLaU4nAk7 9iYBYb32fvaa/0+Stzmss/fq7oll4L1AclY4tfafFahQHg/6iiY0sN9Ykqj/FRjzocqF uhR0FlntiUwa3JUB2EWmnwV3UDcYCRRbYoW96fTDYmmrL07V6KPVgmPNli9Z6hljzIV+ BJB7KHaUOlzLkui9G85HOPrbpQL65N3RHEzkEnbtcCTM9qUksQIGZ40kn7IFQeG5Yxqb kolw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=uNZOim1otVCdMzCZrGI3QsadJO/8xlW0Xrr3vFSwptQ=; b=uliKUePlVJ7NGHUkg0WTRySQ0axatbaIcBUFMMB96KlyQgylIsUbqSFyZopAn7LBrV VeFSZmc+RENPmrYr5jgPpVVL4Yh12hjy3rgfcEpmbWBAMVewrP/1QntDw77tBbNlBFN0 imleW083CrTFA+HWNXlrTvBjqytQf8gSconcgQMfW1z8xnY2bst0JIgey5yd6UwMC7yx IP0za1LGvA+7Pb/85dDnMdpgygUsew/pPhejq3NXOBPgsLUOGt+qRXds96A+ALAQppfB lXZ6AYrZ+i+M8pztFqNmzWLHwK/eGT/Cm0rY35CHDF4VF4VHqahLLJIpIwtZ8de9OcvR 261w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ip5aWhzi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v1 4/4] tests/tcg/aarch64: userspace system register test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This tests a bunch of registers that the kernel allows userspace to read including the CPUID registers. Signed-off-by: Alex Bennée --- v4 - also test for extra bits that shouldn't be exposed --- tests/tcg/aarch64/Makefile.target | 2 +- tests/tcg/aarch64/sysregs.c | 120 ++++++++++++++++++++++++++++++ 2 files changed, 121 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/sysregs.c -- 2.17.1 diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 08c45b8470..cc1a7eb486 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -7,7 +7,7 @@ VPATH += $(AARCH64_SRC) # we don't build any of the ARM tests AARCH64_TESTS=$(filter-out $(ARM_TESTS), $(TESTS)) -AARCH64_TESTS+=fcvt +AARCH64_TESTS+=fcvt sysregs TESTS:=$(AARCH64_TESTS) fcvt: LDFLAGS+=-lm diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c new file mode 100644 index 0000000000..8e11288ee3 --- /dev/null +++ b/tests/tcg/aarch64/sysregs.c @@ -0,0 +1,120 @@ +/* + * Check emulated system register access for linux-user mode. + * + * See: https://www.kernel.org/doc/Documentation/arm64/cpu-feature-registers.txt + */ + +#include +#include +#include +#include +#include +#include + +int failed_mask_count; + +#define get_cpu_reg(id) ({ \ + unsigned long __val = 0xdeadbeef; \ + asm("mrs %0, "#id : "=r" (__val)); \ + printf("%-20s: 0x%016lx\n", #id, __val); \ + __val; \ + }) + +#define get_cpu_reg_check_mask(id, mask) ({ \ + unsigned long __cval = get_cpu_reg(id); \ + unsigned long __extra = __cval & ~mask; \ + if (__extra) { \ + printf("%-20s: 0x%016lx\n", " !!extra bits!!", __extra); \ + failed_mask_count++; \ + } \ +}) + +bool should_fail; +int should_fail_count; +int should_not_fail_count; +uintptr_t failed_pc[10]; + +void sigill_handler(int signo, siginfo_t *si, void *data) +{ + ucontext_t *uc = (ucontext_t *)data; + + if (should_fail) { + should_fail_count++; + } else { + uintptr_t pc = (uintptr_t) uc->uc_mcontext.pc; + failed_pc[should_not_fail_count++] = pc; + } + uc->uc_mcontext.pc += 4; +} + +int main(void) +{ + struct sigaction sa; + + /* Hook in a SIGILL handler */ + memset(&sa, 0, sizeof(struct sigaction)); + sa.sa_flags = SA_SIGINFO; + sa.sa_sigaction = &sigill_handler; + sigemptyset(&sa.sa_mask); + + if (sigaction(SIGILL, &sa, 0) != 0) { + perror("sigaction"); + return 1; + } + + /* since 4.12 */ + printf("Checking CNT registers\n"); + + get_cpu_reg(ctr_el0); + get_cpu_reg(cntvct_el0); + get_cpu_reg(cntfrq_el0); + + /* when (getauxval(AT_HWCAP) & HWCAP_CPUID), since 4.11*/ + if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) { + printf("CPUID registers unavailable\n"); + return 1; + } else { + printf("Checking CPUID registers\n"); + } + + /* + * Some registers only expose some bits to user-space. Anything + * that is IMDEF is exported as 0 to user-space. + */ + get_cpu_reg_check_mask(id_aa64isar0_el1, 0x000fffffff0ffff0ULL); + get_cpu_reg_check_mask(id_aa64isar1_el1, 0x00000000ffffffffULL); + get_cpu_reg(id_aa64mmfr0_el1); + get_cpu_reg(id_aa64mmfr1_el1); + get_cpu_reg_check_mask(id_aa64pfr0_el1, 0x000f000f0ff0000ULL); + get_cpu_reg(id_aa64pfr1_el1); + get_cpu_reg(id_aa64dfr0_el1); + get_cpu_reg(id_aa64dfr1_el1); + + get_cpu_reg_check_mask(midr_el1, 0x00000000ffffffffULL); + get_cpu_reg(mpidr_el1); + /* REVIDR is all IMPDEF so should be all zeros to user-space */ + get_cpu_reg_check_mask(revidr_el1, 0x0); + + printf("Remaining registers should fail\n"); + should_fail = true; + + /* Unexposed register access causes SIGILL */ + get_cpu_reg(id_mmfr0_el1); + + if (should_not_fail_count > 0) { + int i; + for (i = 0; i < should_not_fail_count; i++) { + uintptr_t pc = failed_pc[i]; + uint32_t insn = *(uint32_t *) pc; + printf("insn %#x @ %#lx unexpected FAIL\n", insn, pc); + } + return 1; + } + + if (failed_mask_count > 0) { + printf("Extra information leaked to user-space!\n"); + return 1; + } + + return should_fail_count == 1 ? 0 : 1; +}