From patchwork Thu Jul 21 13:40:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 592197 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EF09CCA48B for ; Thu, 21 Jul 2022 13:44:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230230AbiGUNoI (ORCPT ); Thu, 21 Jul 2022 09:44:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229982AbiGUNnW (ORCPT ); Thu, 21 Jul 2022 09:43:22 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3610C83F26 for ; Thu, 21 Jul 2022 06:43:00 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id t1so2842517lft.8 for ; Thu, 21 Jul 2022 06:42:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pmSASrhJHn6ivFdlVEJYXb7R4srgTjTFkdflVpjygv8=; b=IdFYhGuUDDZtzDwEay5CBmdNBTQm0pTARSgLybdSal4/UR7uz4/ls4vEupVLwS5ZMS wJIZIZaxIwDThGwx21tAtohhZoXkccszD+nED/NGp+Vp1u1HOU32FzT1udkepuxGsRFH huubjJDVVIYC3hizzYjeJ24clq80YQWecxgeadDabHBddkuXoT6Veibu8zU2aWYn+w38 L4zBYSxMs3fHJlhnYl+fqsGcDtDVwflBpZ3RNPQN8US7ErTT6ChuQcD1XiOiFUUD7QvD IfGCJJISou1GTkA7VmMuQomGadNAxKDhaELBm8SCYzYVN2ZH/q4/SWc/Zpi4mXV/c0b1 npkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pmSASrhJHn6ivFdlVEJYXb7R4srgTjTFkdflVpjygv8=; b=O/NXcPqOUIJsT74buLmgjuBOSdKT/+QzHeHXNqWQMiCgEH2igP4ViOHKPtvuhHa7mi 3Q3Ynnrog6HgYh8kzowv/vGYB2tNdfPtAf+oUT08LTjlRhqGhbLbsuei5IljGW6qyraC p1tdgc/VvvJD1f1hKPOpHz5gNxQ5x3WBVe5KglITEnkAvqT35Pg5wwUFm9g+YUkCQ+PM n3lWPv0sAc0W7xljCvqFWBqyC4EqUjlzX88n/HiPgV0704giTqLNvaw9W5tbrH//SPEJ Lo+0WqM6jgFC/1BrjCbAU5X8EL4fOVKBwNSJGbkFczGpPqmiPb2jkuyV7IbUI4W4EzQQ 64oA== X-Gm-Message-State: AJIora/LJDzqcHZX+n10XDw0oELIQZSj1bAZe8+Q/BCZ6uZnAvFLAn8q T72LVSjv6suJl0ryAs0hCeXXGQs+xlGTrA== X-Google-Smtp-Source: AGRyM1sFV4rNCGoH1/mlb2Jg+Y6/gMWTCs6jaIazqSvm5Af7YyfWmAGFiUE0aQb3Pao0wQr5rfEgvg== X-Received: by 2002:a05:6512:3d11:b0:489:d28c:10d9 with SMTP id d17-20020a0565123d1100b00489d28c10d9mr21653956lfv.467.1658410977675; Thu, 21 Jul 2022 06:42:57 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.42.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:42:57 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 01/15] crypto: ux500/hash: Pass ctx to hash_setconfiguration() Date: Thu, 21 Jul 2022 15:40:36 +0200 Message-Id: <20220721134050.1047866-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org This function was dereferencing device_data->current_ctx to get the context. This is not a good idea, the device_data is serialized with an awkward semaphore construction and fragile. Also fix a checkpatch warning about putting compared constants to the right in an expression. Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_alg.h | 2 +- drivers/crypto/ux500/hash/hash_core.c | 15 ++++++++------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h index 7c9bcc15125f..26e8b7949d7c 100644 --- a/drivers/crypto/ux500/hash/hash_alg.h +++ b/drivers/crypto/ux500/hash/hash_alg.h @@ -380,7 +380,7 @@ struct hash_device_data { int hash_check_hw(struct hash_device_data *device_data); int hash_setconfiguration(struct hash_device_data *device_data, - struct hash_config *config); + struct hash_ctx *ctx); void hash_begin(struct hash_device_data *device_data, struct hash_ctx *ctx); diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index 265ef3e96fdd..dfdf3e35d94f 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -473,7 +473,7 @@ static int init_hash_hw(struct hash_device_data *device_data, { int ret = 0; - ret = hash_setconfiguration(device_data, &ctx->config); + ret = hash_setconfiguration(device_data, ctx); if (ret) { dev_err(device_data->dev, "%s: hash_setconfiguration() failed!\n", __func__); @@ -672,11 +672,12 @@ static void hash_incrementlength(struct hash_req_ctx *ctx, u32 incr) * hash_setconfiguration - Sets the required configuration for the hash * hardware. * @device_data: Structure for the hash device. - * @config: Pointer to a configuration structure. + * @ctx: Current context */ int hash_setconfiguration(struct hash_device_data *device_data, - struct hash_config *config) + struct hash_ctx *ctx) { + struct hash_config *config = &ctx->config; int ret = 0; if (config->algorithm != HASH_ALGO_SHA1 && @@ -711,12 +712,12 @@ int hash_setconfiguration(struct hash_device_data *device_data, * MODE bit. This bit selects between HASH or HMAC mode for the * selected algorithm. 0b0 = HASH and 0b1 = HMAC. */ - if (HASH_OPER_MODE_HASH == config->oper_mode) + if (config->oper_mode == HASH_OPER_MODE_HASH) { HASH_CLEAR_BITS(&device_data->base->cr, HASH_CR_MODE_MASK); - else if (HASH_OPER_MODE_HMAC == config->oper_mode) { + } else if (config->oper_mode == HASH_OPER_MODE_HMAC) { HASH_SET_BITS(&device_data->base->cr, HASH_CR_MODE_MASK); - if (device_data->current_ctx->keylen > HASH_BLOCK_SIZE) { + if (ctx->keylen > HASH_BLOCK_SIZE) { /* Truncate key to blocksize */ dev_dbg(device_data->dev, "%s: LKEY set\n", __func__); HASH_SET_BITS(&device_data->base->cr, @@ -878,7 +879,7 @@ static int hash_dma_final(struct ahash_request *req) goto out; } } else { - ret = hash_setconfiguration(device_data, &ctx->config); + ret = hash_setconfiguration(device_data, ctx); if (ret) { dev_err(device_data->dev, "%s: hash_setconfiguration() failed!\n", From patchwork Thu Jul 21 13:40:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 592907 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54BBBC43334 for ; Thu, 21 Jul 2022 13:44:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229994AbiGUNob (ORCPT ); Thu, 21 Jul 2022 09:44:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229846AbiGUNnX (ORCPT ); Thu, 21 Jul 2022 09:43:23 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 181D884EC6 for ; Thu, 21 Jul 2022 06:43:03 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id a10so1875238ljj.5 for ; Thu, 21 Jul 2022 06:43:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N27Ramn+YqqyrLto5WZmvzxeHJl8LdGFZ7o1ehX5d0g=; b=Aj2RZx+BtPq43qjmJeYcG65C3ORcEYXJmMD0o9dHUht5BVZ1xvEter3Dgc2PkXP1tW F08X77ydrrUV5FamWBLaYDtCy/NZkBQeKtem3NaRCTiuwetsr6WEHEkMKCEzuwDLeWf7 EXnGBDAwX2VTePyXm8BMq0t05AZJupK1zUGDkJAZKUGaP+ceQrp4BT64AV/1Y+MqRiRt d5F8nXHOIGjqbxOXnubxq6sk3JsB6p8JSrQmdh1evXIOek1NQG45OPuJSH3qk6TDLqr9 Bu8gctO7UDvo14AhzGpqCjAuIi0h945Y9X78kbqTIyfo8fN5jVmQlV4AQloI+9thQrC/ 5bGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N27Ramn+YqqyrLto5WZmvzxeHJl8LdGFZ7o1ehX5d0g=; b=ESeT0+RtS6ErZaF+PZigk+KRsSgrp1teYN2pidUHsyWR6bAEXDdiYVPP2KJiFFPBbM tSLDOMy79kIQ7MB67qG2uShFaBEV6LPjleoxg3Qy7Ny5b0EEsCvwfW7pXKPZVfbm2hrQ JHIJQDgJ5oTunRJixbn+sm4JkaWHiUjoF62N5lIgI6M/Gn9Odfr7dm4IOlr8foncq3D3 CC6llZFpDUWCjKIh1KSQYBp6HLnE+0SSLYzYWyaheqpxRZhAtGTjI5xRLo3cDO1nE7E5 KRpysZn1wUJEKMAz6+7s1lR+GpYV+U8GRC6mkaxBQ+mA2/XvN79KLa4akWQvSNsI43an XP6g== X-Gm-Message-State: AJIora/5i7LUvkohu1zjK97nzRc7sAgwI7a4K4xMz/2xAlIGMu9+CVwJ 3diG5mte8UOii1CdkprpD2V8phjnd8AwwQ== X-Google-Smtp-Source: AGRyM1u92ayUn0LLsVEAfP1XV6Zas7RxYuKTfJXzgD8uPvEvHdacue3k3rl0I2+Mfr3tmAibsTcNMg== X-Received: by 2002:a2e:7c01:0:b0:25d:7734:5a79 with SMTP id x1-20020a2e7c01000000b0025d77345a79mr18873926ljc.252.1658410979327; Thu, 21 Jul 2022 06:42:59 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.42.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:42:59 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 02/15] crypto: ux500/hash: Get rid of custom device list Date: Thu, 21 Jul 2022 15:40:37 +0200 Message-Id: <20220721134050.1047866-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The Ux500 hash driver builds a list with one (1) hash engine as it is all it has, then goes to great lengths to lock the one device using a semaphore. Instead do what other drivers do: trust the core to do the right thing, add the device state to the algorithm template, fill it in when registering the algorithms and assign the device state to the context when intializing each context. This saves us from a lot of complex code. Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_core.c | 194 +++----------------------- 1 file changed, 17 insertions(+), 177 deletions(-) diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index dfdf3e35d94f..fd7a862244ac 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -59,19 +58,6 @@ static const u8 zero_message_hmac_sha256[SHA256_DIGEST_SIZE] = { 0xc6, 0xc7, 0x12, 0x14, 0x42, 0x92, 0xc5, 0xad }; -/** - * struct hash_driver_data - data specific to the driver. - * - * @device_list: A list of registered devices to choose from. - * @device_allocation: A semaphore initialized with number of devices. - */ -struct hash_driver_data { - struct klist device_list; - struct semaphore device_allocation; -}; - -static struct hash_driver_data driver_data; - /* Declaration of functions */ /** * hash_messagepad - Pads a message and write the nblw bits. @@ -86,24 +72,6 @@ static struct hash_driver_data driver_data; static void hash_messagepad(struct hash_device_data *device_data, const u32 *message, u8 index_bytes); -/** - * release_hash_device - Releases a previously allocated hash device. - * @device_data: Structure for the hash device. - * - */ -static void release_hash_device(struct hash_device_data *device_data) -{ - spin_lock(&device_data->ctx_lock); - device_data->current_ctx->device = NULL; - device_data->current_ctx = NULL; - spin_unlock(&device_data->ctx_lock); - - /* - * The down_interruptible part for this semaphore is called in - * cryp_get_device_data. - */ - up(&driver_data.device_allocation); -} static void hash_dma_setup_channel(struct hash_device_data *device_data, struct device *dev) @@ -354,65 +322,6 @@ static int hash_enable_power(struct hash_device_data *device_data, return ret; } -/** - * hash_get_device_data - Checks for an available hash device and return it. - * @ctx: Structure for the hash context. - * @device_data: Structure for the hash device. - * - * This function check for an available hash device and return it to - * the caller. - * Note! Caller need to release the device, calling up(). - */ -static int hash_get_device_data(struct hash_ctx *ctx, - struct hash_device_data **device_data) -{ - int ret; - struct klist_iter device_iterator; - struct klist_node *device_node; - struct hash_device_data *local_device_data = NULL; - - /* Wait until a device is available */ - ret = down_interruptible(&driver_data.device_allocation); - if (ret) - return ret; /* Interrupted */ - - /* Select a device */ - klist_iter_init(&driver_data.device_list, &device_iterator); - device_node = klist_next(&device_iterator); - while (device_node) { - local_device_data = container_of(device_node, - struct hash_device_data, list_node); - spin_lock(&local_device_data->ctx_lock); - /* current_ctx allocates a device, NULL = unallocated */ - if (local_device_data->current_ctx) { - device_node = klist_next(&device_iterator); - } else { - local_device_data->current_ctx = ctx; - ctx->device = local_device_data; - spin_unlock(&local_device_data->ctx_lock); - break; - } - spin_unlock(&local_device_data->ctx_lock); - } - klist_iter_exit(&device_iterator); - - if (!device_node) { - /** - * No free device found. - * Since we allocated a device with down_interruptible, this - * should not be able to happen. - * Number of available devices, which are contained in - * device_allocation, is therefore decremented by not doing - * an up(device_allocation). - */ - return -EBUSY; - } - - *device_data = local_device_data; - - return 0; -} - /** * hash_hw_write_key - Writes the key to the hardware registries. * @@ -859,14 +768,10 @@ static int hash_dma_final(struct ahash_request *req) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct hash_ctx *ctx = crypto_ahash_ctx(tfm); struct hash_req_ctx *req_ctx = ahash_request_ctx(req); - struct hash_device_data *device_data; + struct hash_device_data *device_data = ctx->device; u8 digest[SHA256_DIGEST_SIZE]; int bytes_written = 0; - ret = hash_get_device_data(ctx, &device_data); - if (ret) - return ret; - dev_dbg(device_data->dev, "%s: (ctx=0x%lx)!\n", __func__, (unsigned long)ctx); @@ -944,8 +849,6 @@ static int hash_dma_final(struct ahash_request *req) memcpy(req->result, digest, ctx->digestsize); out: - release_hash_device(device_data); - /** * Allocated in setkey, and only used in HMAC. */ @@ -964,13 +867,9 @@ static int hash_hw_final(struct ahash_request *req) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct hash_ctx *ctx = crypto_ahash_ctx(tfm); struct hash_req_ctx *req_ctx = ahash_request_ctx(req); - struct hash_device_data *device_data; + struct hash_device_data *device_data = ctx->device; u8 digest[SHA256_DIGEST_SIZE]; - ret = hash_get_device_data(ctx, &device_data); - if (ret) - return ret; - dev_dbg(device_data->dev, "%s: (ctx=0x%lx)!\n", __func__, (unsigned long)ctx); @@ -1047,7 +946,6 @@ static int hash_hw_final(struct ahash_request *req) memcpy(req->result, digest, ctx->digestsize); out: - release_hash_device(device_data); /** * Allocated in setkey, and only used in HMAC. @@ -1068,36 +966,29 @@ int hash_hw_update(struct ahash_request *req) int ret = 0; u8 index = 0; u8 *buffer; - struct hash_device_data *device_data; u8 *data_buffer; struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct hash_ctx *ctx = crypto_ahash_ctx(tfm); struct hash_req_ctx *req_ctx = ahash_request_ctx(req); + struct hash_device_data *device_data = ctx->device; struct crypto_hash_walk walk; int msg_length; index = req_ctx->state.index; buffer = (u8 *)req_ctx->state.buffer; - ret = hash_get_device_data(ctx, &device_data); - if (ret) - return ret; - msg_length = crypto_hash_walk_first(req, &walk); /* Empty message ("") is correct indata */ - if (msg_length == 0) { - ret = 0; - goto release_dev; - } + if (msg_length == 0) + return 0; /* Check if ctx->state.length + msg_length overflows */ if (msg_length > (req_ctx->state.length.low_word + msg_length) && HASH_HIGH_WORD_MAX_VAL == req_ctx->state.length.high_word) { pr_err("%s: HASH_MSG_LENGTH_OVERFLOW!\n", __func__); - ret = crypto_hash_walk_done(&walk, -EPERM); - goto release_dev; + return crypto_hash_walk_done(&walk, -EPERM); } /* Main loop */ @@ -1110,7 +1001,7 @@ int hash_hw_update(struct ahash_request *req) dev_err(device_data->dev, "%s: hash_internal_hw_update() failed!\n", __func__); crypto_hash_walk_done(&walk, ret); - goto release_dev; + return ret; } msg_length = crypto_hash_walk_done(&walk, 0); @@ -1120,10 +1011,7 @@ int hash_hw_update(struct ahash_request *req) dev_dbg(device_data->dev, "%s: indata length=%d, bin=%d\n", __func__, req_ctx->state.index, req_ctx->state.bit_index); -release_dev: - release_hash_device(device_data); - - return ret; + return 0; } /** @@ -1495,6 +1383,7 @@ static int hmac_sha256_setkey(struct crypto_ahash *tfm, struct hash_algo_template { struct hash_config conf; struct ahash_alg hash; + struct hash_device_data *device; }; static int hash_cra_init(struct crypto_tfm *tfm) @@ -1507,6 +1396,8 @@ static int hash_cra_init(struct crypto_tfm *tfm) struct hash_algo_template, hash); + ctx->device = hash_alg->device; + crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), sizeof(struct hash_req_ctx)); @@ -1623,6 +1514,7 @@ static int ahash_algs_register_all(struct hash_device_data *device_data) int count; for (i = 0; i < ARRAY_SIZE(hash_algs); i++) { + hash_algs[i].device = device_data; ret = crypto_register_ahash(&hash_algs[i].hash); if (ret) { count = i; @@ -1723,11 +1615,6 @@ static int ux500_hash_probe(struct platform_device *pdev) platform_set_drvdata(pdev, device_data); - /* Put the new device into the device list... */ - klist_add_tail(&device_data->list_node, &driver_data.device_list); - /* ... and signal that a new device is available. */ - up(&driver_data.device_allocation); - ret = ahash_algs_register_all(device_data); if (ret) { dev_err(dev, "%s: ahash_algs_register_all() failed!\n", @@ -1766,10 +1653,6 @@ static int ux500_hash_remove(struct platform_device *pdev) return -ENOMEM; } - /* Try to decrease the number of available devices. */ - if (down_trylock(&driver_data.device_allocation)) - return -EBUSY; - /* Check that the device is free */ spin_lock(&device_data->ctx_lock); /* current_ctx allocates a device, NULL = unallocated */ @@ -1777,19 +1660,12 @@ static int ux500_hash_remove(struct platform_device *pdev) /* The device is busy */ spin_unlock(&device_data->ctx_lock); /* Return the device to the pool. */ - up(&driver_data.device_allocation); return -EBUSY; } spin_unlock(&device_data->ctx_lock); - /* Remove the device from the list */ - if (klist_node_attached(&device_data->list_node)) - klist_remove(&device_data->list_node); - - /* If this was the last device, remove the services */ - if (list_empty(&driver_data.device_list.k_list)) - ahash_algs_unregister_all(device_data); + ahash_algs_unregister_all(device_data); if (hash_disable_power(device_data, false)) dev_err(dev, "%s: hash_disable_power() failed\n", @@ -1820,9 +1696,6 @@ static void ux500_hash_shutdown(struct platform_device *pdev) spin_lock(&device_data->ctx_lock); /* current_ctx allocates a device, NULL = unallocated */ if (!device_data->current_ctx) { - if (down_trylock(&driver_data.device_allocation)) - dev_dbg(&pdev->dev, "%s: Cryp still in use! Shutting down anyway...\n", - __func__); /** * (Allocate the device) * Need to set this to non-null (dummy) value, @@ -1832,13 +1705,7 @@ static void ux500_hash_shutdown(struct platform_device *pdev) } spin_unlock(&device_data->ctx_lock); - /* Remove the device from the list */ - if (klist_node_attached(&device_data->list_node)) - klist_remove(&device_data->list_node); - - /* If this was the last device, remove the services */ - if (list_empty(&driver_data.device_list.k_list)) - ahash_algs_unregister_all(device_data); + ahash_algs_unregister_all(device_data); if (hash_disable_power(device_data, false)) dev_err(&pdev->dev, "%s: hash_disable_power() failed\n", @@ -1868,9 +1735,6 @@ static int ux500_hash_suspend(struct device *dev) spin_unlock(&device_data->ctx_lock); if (device_data->current_ctx == ++temp_ctx) { - if (down_interruptible(&driver_data.device_allocation)) - dev_dbg(dev, "%s: down_interruptible() failed\n", - __func__); ret = hash_disable_power(device_data, false); } else { @@ -1904,9 +1768,7 @@ static int ux500_hash_resume(struct device *dev) device_data->current_ctx = NULL; spin_unlock(&device_data->ctx_lock); - if (!device_data->current_ctx) - up(&driver_data.device_allocation); - else + if (device_data->current_ctx) ret = hash_enable_power(device_data, true); if (ret) @@ -1924,7 +1786,7 @@ static const struct of_device_id ux500_hash_match[] = { }; MODULE_DEVICE_TABLE(of, ux500_hash_match); -static struct platform_driver hash_driver = { +static struct platform_driver ux500_hash_driver = { .probe = ux500_hash_probe, .remove = ux500_hash_remove, .shutdown = ux500_hash_shutdown, @@ -1934,29 +1796,7 @@ static struct platform_driver hash_driver = { .pm = &ux500_hash_pm, } }; - -/** - * ux500_hash_mod_init - The kernel module init function. - */ -static int __init ux500_hash_mod_init(void) -{ - klist_init(&driver_data.device_list, NULL, NULL); - /* Initialize the semaphore to 0 devices (locked state) */ - sema_init(&driver_data.device_allocation, 0); - - return platform_driver_register(&hash_driver); -} - -/** - * ux500_hash_mod_fini - The kernel module exit function. - */ -static void __exit ux500_hash_mod_fini(void) -{ - platform_driver_unregister(&hash_driver); -} - -module_init(ux500_hash_mod_init); -module_exit(ux500_hash_mod_fini); +module_platform_driver(ux500_hash_driver); MODULE_DESCRIPTION("Driver for ST-Ericsson UX500 HASH engine."); MODULE_LICENSE("GPL"); From patchwork Thu Jul 21 13:40:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 592908 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17277C43334 for ; Thu, 21 Jul 2022 13:44:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229948AbiGUNoI (ORCPT ); Thu, 21 Jul 2022 09:44:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229964AbiGUNnR (ORCPT ); Thu, 21 Jul 2022 09:43:17 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CF3282F98 for ; Thu, 21 Jul 2022 06:43:02 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id p6so1860510ljc.8 for ; Thu, 21 Jul 2022 06:43:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KTtKtpahYRj5RrvQ3U2GaLKtIGWmV90iOPLY5xwmgyQ=; b=t7AnqB2RV3V6BS2xjRZKiX3uRPu8cnMe5JDuwFXelSwR/3GatO5Q5VZ7RzajZ2qyQu A6ZT6B7I4pbWADQutw3FmF2q0QMcCd6DtMjpoq5ACBMgvjsARtBfUL+m7zn6L2QJgtKH 7nJxhuJP1vhZ/MNJ8nLgwit364aJXwzIbCAkDITDMlerwI4+2LOBZgJyF6oFtp4ZLpXG DNvNnlwqT9p/x6ElGPd+qIDXNR01DYG2CcoQlhSdzaWecLLNd84/eyjZxkp7wmsdy46J v3QA+pnoXokBSYgLplf1EsUIBhACMTE+MB8WXeB100kMEJ4utBucXJPhD6EATF5gYBjF s7UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KTtKtpahYRj5RrvQ3U2GaLKtIGWmV90iOPLY5xwmgyQ=; b=L7+m8SrF2+eEUjPSxzD5O7XbGHMua/IV/Wks92qaO+lhte6OaJWIJfQjhbJQwcuMy3 HKLicCGHlbNNwwgiifxj6SulveWN9XeEdwwNIEwc15XYZ2Vge4PoSmF+NNkMJfPV5wsp p4nHeRwGHWYUZ8jlpPrPyrXMiXAgHUoifEQkNgjKTDCQlAGSO4c5unckA5XOXPlRH10C rtnR12rAAIxeoqNMwFpLjU3Eye5hLTq2SOwZF9bueQGLyCwFBk9kvYwykMnF/EN7+XDY GJoWNd/TaYPacx8s0daWssQOr+l0Rf0PSo8X02MGaDW6yWuVWfzL63arLEgui31l1QQi p+Bw== X-Gm-Message-State: AJIora/Tc6GgSupkC8ns4ZrnJoo+ZZa5z23s4HDNneEDRj0LiSCYDvzf kUHVddGEiCcOaiLOh32OFarYbrn83JMj/w== X-Google-Smtp-Source: AGRyM1tyyylXEb8hvr6ScBCQEhjqYd1WYVb1G8WydKAzGjpNztUbbcKBRYpMlMrNlb6DqquPbu90fA== X-Received: by 2002:a2e:8954:0:b0:25d:6936:849a with SMTP id b20-20020a2e8954000000b0025d6936849amr19723517ljk.370.1658410980632; Thu, 21 Jul 2022 06:43:00 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.43.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:43:00 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 03/15] crypto: ux500/hash: Pass context to zero message digest Date: Thu, 21 Jul 2022 15:40:38 +0200 Message-Id: <20220721134050.1047866-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org This function obtains the current context from the device state pointer, which is fragile. Pass the context explicitly instead. Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_core.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index fd7a862244ac..884046e87262 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -183,11 +183,10 @@ static int hash_dma_write(struct hash_ctx *ctx, * @zero_digest: True if zero_digest returned. */ static int get_empty_message_digest( - struct hash_device_data *device_data, + struct hash_device_data *device_data, struct hash_ctx *ctx, u8 *zero_hash, u32 *zero_hash_size, bool *zero_digest) { int ret = 0; - struct hash_ctx *ctx = device_data->current_ctx; *zero_digest = false; /** @@ -889,7 +888,7 @@ static int hash_hw_final(struct ahash_request *req) * Use a pre-calculated empty message digest * (workaround since hw return zeroes, hw bug!?) */ - ret = get_empty_message_digest(device_data, &zero_hash[0], + ret = get_empty_message_digest(device_data, ctx, &zero_hash[0], &zero_hash_size, &zero_digest); if (!ret && likely(zero_hash_size == ctx->digestsize) && zero_digest) { From patchwork Thu Jul 21 13:40:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 592196 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6B86C433EF for ; Thu, 21 Jul 2022 13:44:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230243AbiGUNoe (ORCPT ); Thu, 21 Jul 2022 09:44:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230007AbiGUNnX (ORCPT ); Thu, 21 Jul 2022 09:43:23 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EA3784ECB for ; Thu, 21 Jul 2022 06:43:04 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id a9so2823324lfk.11 for ; Thu, 21 Jul 2022 06:43:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rVMziS2gK6F8Ul17CTqouVgo6gQ0LapeQ4hzWQIcyy4=; b=SYjOlPf1cAqlODqUyBPXO//eShu/N3znxopvhxE+fjSvrd8flnJQbwRNHX1U6DbMxy HMonZjgigfdxiVWbbZ1cFxgn9kIOnIAOovdO6csGRjmyauyUMth4iRqkp2ISuNetZ4/x EZ47kmLdrap0zd8sb5avVQ1woj6B1Id3UcjYXGm3ZceWIPeRQhn+67r8zVuh4izqbVs1 VCy12E9rtnR2EjUV9xrDomrAew+kHwFYh4zdpRH/TSA+g0M9FjMYWVd3rmKQndNkoNrP DGJq/Ucb2Azyqv9/15Ss1L3810LKLJTw2e9cWdA017CS0GGYJZSE5lLQDTS7Yy7+nT6R Gu6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rVMziS2gK6F8Ul17CTqouVgo6gQ0LapeQ4hzWQIcyy4=; b=ZyIOeJOfZ+Fz5rdepllP7hNLlImRXqmsExDVrDGBWBb696tNUUgc9O3RUsSbM39MxO oX8w2+soCq3lc//6Ozd3O+BJGIiXr7vLO1FgjbRiSFxVjlcBsrFOZ6PN9UvZ9QEOnXNG zWv1xK6cdt5R8yN6c4ElmZQpgv4yX9Wz8HTwkHsmNB+LaPOEyYQJtD2JrYApHq60Y76t Cg7C8/oGoE5Q3SZOiJWHqgTQj1qz0Z573GTj1fDNC7CV2uK/WlWSalHYUh4fKKM0boz1 X9A3Mu8hlDSbsAFoKYcsHPgAiWD6AjO48+UajCG2NzGq3cOHWk5Mx1fm0uEllRUKFgND 8Yhw== X-Gm-Message-State: AJIora9bl4svYusAL4uqCCcie1lp6MyaQ8K5ArBS7ySuLvXI/EjGEudZ H0p1epJgVc7eDFTuDmkbENio/Z2s409qkg== X-Google-Smtp-Source: AGRyM1uy1ncvXrCVToQw4cQD0wfxojkoilzylRtCF1kLNmDdLVeSbqJhQYapplH7JF0p4tGXCOOQXg== X-Received: by 2002:a05:6512:2527:b0:489:ec08:7ada with SMTP id be39-20020a056512252700b00489ec087adamr21822553lfb.621.1658410981954; Thu, 21 Jul 2022 06:43:01 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.43.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:43:01 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 04/15] crypto: ux500/hash: Drop custom state save/restore Date: Thu, 21 Jul 2022 15:40:39 +0200 Message-Id: <20220721134050.1047866-5-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Drop the code that is saving and restoring the device state as part of the PM operations: this is the job of .import and .export, do not try to work around the framework. Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_core.c | 52 +++++---------------------- 1 file changed, 8 insertions(+), 44 deletions(-) diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index 884046e87262..e6e3a91ae795 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -243,13 +243,11 @@ static int get_empty_message_digest( /** * hash_disable_power - Request to disable power and clock. * @device_data: Structure for the hash device. - * @save_device_state: If true, saves the current hw state. * * This function request for disabling power (regulator) and clock, * and could also save current hw state. */ -static int hash_disable_power(struct hash_device_data *device_data, - bool save_device_state) +static int hash_disable_power(struct hash_device_data *device_data) { int ret = 0; struct device *dev = device_data->dev; @@ -258,12 +256,6 @@ static int hash_disable_power(struct hash_device_data *device_data, if (!device_data->power_state) goto out; - if (save_device_state) { - hash_save_state(device_data, - &device_data->state); - device_data->restore_dev_state = true; - } - clk_disable(device_data->clk); ret = regulator_disable(device_data->regulator); if (ret) @@ -280,13 +272,11 @@ static int hash_disable_power(struct hash_device_data *device_data, /** * hash_enable_power - Request to enable power and clock. * @device_data: Structure for the hash device. - * @restore_device_state: If true, restores a previous saved hw state. * * This function request for enabling power (regulator) and clock, * and could also restore a previously saved hw state. */ -static int hash_enable_power(struct hash_device_data *device_data, - bool restore_device_state) +static int hash_enable_power(struct hash_device_data *device_data) { int ret = 0; struct device *dev = device_data->dev; @@ -309,12 +299,6 @@ static int hash_enable_power(struct hash_device_data *device_data, device_data->power_state = true; } - if (device_data->restore_dev_state) { - if (restore_device_state) { - device_data->restore_dev_state = false; - hash_resume_state(device_data, &device_data->state); - } - } out: spin_unlock(&device_data->power_state_lock); @@ -1597,7 +1581,7 @@ static int ux500_hash_probe(struct platform_device *pdev) } /* Enable device power (and clock) */ - ret = hash_enable_power(device_data, false); + ret = hash_enable_power(device_data); if (ret) { dev_err(dev, "%s: hash_enable_power() failed!\n", __func__); goto out_clk_unprepare; @@ -1625,7 +1609,7 @@ static int ux500_hash_probe(struct platform_device *pdev) return 0; out_power: - hash_disable_power(device_data, false); + hash_disable_power(device_data); out_clk_unprepare: clk_unprepare(device_data->clk); @@ -1666,7 +1650,7 @@ static int ux500_hash_remove(struct platform_device *pdev) ahash_algs_unregister_all(device_data); - if (hash_disable_power(device_data, false)) + if (hash_disable_power(device_data)) dev_err(dev, "%s: hash_disable_power() failed\n", __func__); @@ -1706,7 +1690,7 @@ static void ux500_hash_shutdown(struct platform_device *pdev) ahash_algs_unregister_all(device_data); - if (hash_disable_power(device_data, false)) + if (hash_disable_power(device_data)) dev_err(&pdev->dev, "%s: hash_disable_power() failed\n", __func__); } @@ -1720,7 +1704,6 @@ static int ux500_hash_suspend(struct device *dev) { int ret; struct hash_device_data *device_data; - struct hash_ctx *temp_ctx = NULL; device_data = dev_get_drvdata(dev); if (!device_data) { @@ -1728,18 +1711,7 @@ static int ux500_hash_suspend(struct device *dev) return -ENOMEM; } - spin_lock(&device_data->ctx_lock); - if (!device_data->current_ctx) - device_data->current_ctx++; - spin_unlock(&device_data->ctx_lock); - - if (device_data->current_ctx == ++temp_ctx) { - ret = hash_disable_power(device_data, false); - - } else { - ret = hash_disable_power(device_data, true); - } - + ret = hash_disable_power(device_data); if (ret) dev_err(dev, "%s: hash_disable_power()\n", __func__); @@ -1754,7 +1726,6 @@ static int ux500_hash_resume(struct device *dev) { int ret = 0; struct hash_device_data *device_data; - struct hash_ctx *temp_ctx = NULL; device_data = dev_get_drvdata(dev); if (!device_data) { @@ -1762,14 +1733,7 @@ static int ux500_hash_resume(struct device *dev) return -ENOMEM; } - spin_lock(&device_data->ctx_lock); - if (device_data->current_ctx == ++temp_ctx) - device_data->current_ctx = NULL; - spin_unlock(&device_data->ctx_lock); - - if (device_data->current_ctx) - ret = hash_enable_power(device_data, true); - + ret = hash_enable_power(device_data); if (ret) dev_err(dev, "%s: hash_enable_power() failed!\n", __func__); From patchwork Thu Jul 21 13:40:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 592906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20EDECCA488 for ; Thu, 21 Jul 2022 13:44:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229867AbiGUNou (ORCPT ); Thu, 21 Jul 2022 09:44:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229776AbiGUNnm (ORCPT ); Thu, 21 Jul 2022 09:43:42 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3374F84ED6 for ; Thu, 21 Jul 2022 06:43:05 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id j26so1889130lji.1 for ; Thu, 21 Jul 2022 06:43:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tfNmd4/2AJvSA9Ov5LFupfzA3mhbd15BtcA4LqxtVDQ=; b=xCi7mg5zJUJnI3q6au2Agii2IITR+WTcn8cVbMnz22QTZF2te2pfCfUDMYOaHV/mFJ QtC9YYygS3cX2o7CaSUds9G8nmOUPy1z6EDVtwxjG9jn0eLVvk/6ktJuucUG883JbL0i 0rrUK7ETchOEIGl80Jje1lUTGgG96uem2UOVnSqLVoGQDOVJzHeMl6QFfefNVfMvD7Qe Sm/tSiQbFy98C90/O0OWlrAZ+DuqaxlK9mdj0P7OyWT42deMm16y79c81mW3g2QBqm0B MiRvzgRH5dhnRcq3C6c4te4tOEF1qYs/Bwq+nXIzpDMk6Ys35066eprzLTw7cvJnThMZ 0+Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tfNmd4/2AJvSA9Ov5LFupfzA3mhbd15BtcA4LqxtVDQ=; b=uN3ATAHJ7rEkoA81QbKFsW0cHYLvnd4yqKd5cKGkD2PdA1faNPSY4I/VcGO6Hr4+5a TKT/NWuLAHzb7kHeKH9fy5QkrBXDtVJoVmohWfkmZz2tn7UtJhz8oV714EElaGvnyPpZ isLERRed+hY6Lc3hpe+60Ms1QJrdEQyJTZoCH8QMBos5Go4RLtdV9XUp2FRpEAVD7zyP XZGd/SjR64ugfpKFdxZz1+PsgLG8jq6AXgsOP9Ei6GPZ355+bFqhVFxV04CTNEQZCpWO BIZe1kiVduwrc6/SA8o4pcvE1qWxw+qDERYoOvhwTIFVhf1xPJhMIXQufUWRb+ByQE6J 7sfA== X-Gm-Message-State: AJIora/G74IXQ4Zqp0AJpa/If+CXKvqCbTgxE+ihSNlG/LX/YptMFqEh mF0PLHIHt8UlxqK/LdshLZRSg2lb2htPaQ== X-Google-Smtp-Source: AGRyM1vT847rpqEEKE3v4I46Q8btuhYW6R5OaM5+2qU2VIPqksarcjcAm36zkTwZkOIf+ZvEnqGo2Q== X-Received: by 2002:a2e:9857:0:b0:25d:d722:b492 with SMTP id e23-20020a2e9857000000b0025dd722b492mr3331528ljj.218.1658410983222; Thu, 21 Jul 2022 06:43:03 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.43.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:43:02 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 05/15] crypto: ux500/hash: Drop bit index Date: Thu, 21 Jul 2022 15:40:40 +0200 Message-Id: <20220721134050.1047866-6-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org This is some leftover code because the field is only referenced in a debug print and never assigned. Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_alg.h | 4 ---- drivers/crypto/ux500/hash/hash_core.c | 4 ++-- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h index 26e8b7949d7c..00730c0090ae 100644 --- a/drivers/crypto/ux500/hash/hash_alg.h +++ b/drivers/crypto/ux500/hash/hash_alg.h @@ -217,7 +217,6 @@ struct hash_register { * @buffer: Working buffer for messages going to the hardware. * @length: Length of the part of message hashed so far (floor(N/64) * 64). * @index: Valid number of bytes in buffer (N % 64). - * @bit_index: Valid number of bits in buffer (N % 8). * * This structure is used between context switches, i.e. when ongoing jobs are * interupted with new jobs. When this happens we need to store intermediate @@ -237,7 +236,6 @@ struct hash_state { u32 buffer[HASH_BLOCK_SIZE / sizeof(u32)]; struct uint64 length; u8 index; - u8 bit_index; }; /** @@ -358,7 +356,6 @@ struct hash_req_ctx { * @power_state_lock: Spinlock for power_state. * @regulator: Pointer to the device's power control. * @clk: Pointer to the device's clock control. - * @restore_dev_state: TRUE = saved state, FALSE = no saved state. * @dma: Structure used for dma. */ struct hash_device_data { @@ -372,7 +369,6 @@ struct hash_device_data { spinlock_t power_state_lock; struct regulator *regulator; struct clk *clk; - bool restore_dev_state; struct hash_state state; /* Used for saving and resuming state */ struct hash_dma dma; }; diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index e6e3a91ae795..e9962c8a29bd 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -991,8 +991,8 @@ int hash_hw_update(struct ahash_request *req) } req_ctx->state.index = index; - dev_dbg(device_data->dev, "%s: indata length=%d, bin=%d\n", - __func__, req_ctx->state.index, req_ctx->state.bit_index); + dev_dbg(device_data->dev, "%s: indata length=%d\n", + __func__, req_ctx->state.index); return 0; } From patchwork Thu Jul 21 13:40:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 592195 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 124CDC433EF for ; Thu, 21 Jul 2022 13:44:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229634AbiGUNoy (ORCPT ); Thu, 21 Jul 2022 09:44:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230047AbiGUNnn (ORCPT ); Thu, 21 Jul 2022 09:43:43 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F21D84EDF for ; Thu, 21 Jul 2022 06:43:06 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id e11so1876418ljl.4 for ; Thu, 21 Jul 2022 06:43:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m7UqmZ0Jv14B5vRscyamwS43czlrxOV9Csm1EJ3FYWU=; b=C66TCTDJ7sKyxBua7YeGhp0UufcNjmOLPVT+lKUSM3PfJVXUtTSyz0z9fFTx6a0DMc 6E7A5v7nDyMulMGb82MwytsLJ3sjTbkz+pj8gAszy7aL6fd5FcXjKxsQ7PHiIireySfA 9uDpe5hENNACo3v4ynkAnKMKN0C+s7CbAKJS/+VFUr/nkBi4wMf+4fQzEAnPdKcaejH2 vEIhqDC68m4fcZ30CiZtFOClyLyppFcKapIyNnkl8jY/i72Ct/jzXUITY21TWfRnbsoJ X2pV5iONDWXYY0uJHPSZ6KYu1OyBltt8KOGAoj8nWtFC4Qli3v62CSWQo1IDlU8Uazsv Bcqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m7UqmZ0Jv14B5vRscyamwS43czlrxOV9Csm1EJ3FYWU=; b=6O7QbFAs0kkm3C1leUlVkIsIQdu2mA78CvoeHeQ52coBuOr5ywBeD9mEw/ia03KfsU GzK+D6O8mfpamGK8elxXUDjFH4DF/Ygfs8QRPeC/lHNUGPgUEz7HbZTsq0DxOUK3S5l1 1ZA4lNOzGSeCJ02NZJu/pm/9V/FIXGxU+bpQirVJdMuF/cTkTW0LMmcZkXv1Qdkw5GJO cZlIuKf0qMwRs6uMzBK21+1K9YV1Yc0WnkbI4UQnqKmbn+Vnn1lvevlRPo8LPnN6EmaZ teUAX8iwGjVk1s+Y4Q25Ioj2+yiWbyX45iel+XhfZ5T/rROrSWWmN6q8Gq+dBq+Vg6Vp o/Qw== X-Gm-Message-State: AJIora/nLOROd33X9H1XQa/FG7ptEAcqjWSUlq6JrL0X6fWj2ca0avqK +7rhDqqbY67H6hkiyuIZJrbYgveFch5OZg== X-Google-Smtp-Source: AGRyM1v5HtaWUCdRjprp+311OVnYsxtYnVkgdBxadGqmDdj6hWN0pPmoSSmDorNJUwM3k8uLiu9WiA== X-Received: by 2002:a2e:a608:0:b0:25d:5363:35a4 with SMTP id v8-20020a2ea608000000b0025d536335a4mr19906611ljp.132.1658410984484; Thu, 21 Jul 2022 06:43:04 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.43.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:43:04 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 06/15] crypto: ux500/hash: Break while/do instead of if/else Date: Thu, 21 Jul 2022 15:40:41 +0200 Message-Id: <20220721134050.1047866-7-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Instead of a deeply nested if/else inside the while/do loop, just break the loop as we know the termination requirement was just established (msg_length == 0). Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_core.c | 115 +++++++++++++------------- 1 file changed, 58 insertions(+), 57 deletions(-) diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index e9962c8a29bd..c9ceaa0b1778 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -671,69 +671,70 @@ static int hash_process_data(struct hash_device_data *device_data, } *index += msg_length; msg_length = 0; - } else { - if (req_ctx->updated) { - ret = hash_resume_state(device_data, - &device_data->state); - memmove(req_ctx->state.buffer, - device_data->state.buffer, - HASH_BLOCK_SIZE); - if (ret) { - dev_err(device_data->dev, - "%s: hash_resume_state() failed!\n", - __func__); - goto out; - } - } else { - ret = init_hash_hw(device_data, ctx); - if (ret) { - dev_err(device_data->dev, - "%s: init_hash_hw() failed!\n", - __func__); - goto out; - } - req_ctx->updated = 1; - } - /* - * If 'data_buffer' is four byte aligned and - * local buffer does not have any data, we can - * write data directly from 'data_buffer' to - * HW peripheral, otherwise we first copy data - * to a local buffer - */ - if (IS_ALIGNED((unsigned long)data_buffer, 4) && - (0 == *index)) - hash_processblock(device_data, - (const u32 *)data_buffer, - HASH_BLOCK_SIZE); - else { - for (count = 0; - count < (u32)(HASH_BLOCK_SIZE - *index); - count++) { - buffer[*index + count] = - *(data_buffer + count); - } - hash_processblock(device_data, - (const u32 *)buffer, - HASH_BLOCK_SIZE); - } - hash_incrementlength(req_ctx, HASH_BLOCK_SIZE); - data_buffer += (HASH_BLOCK_SIZE - *index); - - msg_length -= (HASH_BLOCK_SIZE - *index); - *index = 0; - - ret = hash_save_state(device_data, - &device_data->state); + break; + } - memmove(device_data->state.buffer, - req_ctx->state.buffer, + if (req_ctx->updated) { + ret = hash_resume_state(device_data, + &device_data->state); + memmove(req_ctx->state.buffer, + device_data->state.buffer, HASH_BLOCK_SIZE); if (ret) { - dev_err(device_data->dev, "%s: hash_save_state() failed!\n", + dev_err(device_data->dev, + "%s: hash_resume_state() failed!\n", __func__); goto out; } + } else { + ret = init_hash_hw(device_data, ctx); + if (ret) { + dev_err(device_data->dev, + "%s: init_hash_hw() failed!\n", + __func__); + goto out; + } + req_ctx->updated = 1; + } + /* + * If 'data_buffer' is four byte aligned and + * local buffer does not have any data, we can + * write data directly from 'data_buffer' to + * HW peripheral, otherwise we first copy data + * to a local buffer + */ + if (IS_ALIGNED((unsigned long)data_buffer, 4) && + (*index == 0)) + hash_processblock(device_data, + (const u32 *)data_buffer, + HASH_BLOCK_SIZE); + else { + for (count = 0; + count < (u32)(HASH_BLOCK_SIZE - *index); + count++) { + buffer[*index + count] = + *(data_buffer + count); + } + hash_processblock(device_data, + (const u32 *)buffer, + HASH_BLOCK_SIZE); + } + hash_incrementlength(req_ctx, HASH_BLOCK_SIZE); + data_buffer += (HASH_BLOCK_SIZE - *index); + + msg_length -= (HASH_BLOCK_SIZE - *index); + *index = 0; + + ret = hash_save_state(device_data, + &device_data->state); + + memmove(device_data->state.buffer, + req_ctx->state.buffer, + HASH_BLOCK_SIZE); + if (ret) { + dev_err(device_data->dev, "%s: hash_save_state() failed!\n", + __func__); + goto out; } } while (msg_length != 0); out: From patchwork Thu Jul 21 13:40:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 592905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B3E1C433EF for ; Thu, 21 Jul 2022 13:45:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229978AbiGUNpH (ORCPT ); Thu, 21 Jul 2022 09:45:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230078AbiGUNnp (ORCPT ); Thu, 21 Jul 2022 09:43:45 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C611484EF6 for ; Thu, 21 Jul 2022 06:43:07 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id d17so702425lfa.12 for ; Thu, 21 Jul 2022 06:43:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HhpllRtGPyfYOFcVtALeo5Lim/8BCK7aMQ+o6IB1CCg=; b=SZiw2hljtgz/Tefp0Hm6SFpl31k3xFjh7vFkzR+iXOshIvlv2qWr0YysSjp8+Qb3zE juX6pgNSbVi+Gb+VObjbT69nq25tMCn6xDqn3yay42QpTezLdiEqSEvp/HBE+VeMgoFn u97mcz5XAJWnFQdXgJw8vi/m/phCJi3j0OszgqGGskBc0Z44cw7YW6JaLXk4hVuyEPm6 Pqz8W/VSG3GCGoaZWvNGIBiMLeOcbaKJ7/w2rVmRPi5XTWWgovR6s8kHczlAfntzMSnm 4V6NcKx5ZG3p3OXjqriiqBqFkqquf7itTRhqbAdffUSds01qHvOUnvHw7DA+wGIslDCn eU4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HhpllRtGPyfYOFcVtALeo5Lim/8BCK7aMQ+o6IB1CCg=; b=PcNrV/JiJazx/thpSt1764nVuT+hWFWBnR1EhZke4MlU9wL1+oreAixwDH9P/kBFEX JIvZlFxWZBdVGHvhzGo95mB0NfJBUb+g3OSD8kzAjKiBa6U7MJ/YPGW0n2iuqg0HY9e9 /mX/w53L/jc+cZvCdgO0oNGWFvDnss71cHNNkWJZuJ0NEpo7iJ5kv5hHh8R15Jq6aOnw EbEUcyvtgNniUy01rvYLYDEBe9vEZTeuXO9uSUvlyxqUz6oB5v0v1WuIPcTzmawAWfjd kvDW3TZnvzHM+P7WypoCNNefEAacC1oEGKWIxRXxZKdsUO+AZdHzOnki5pZSfRNssdvG a02g== X-Gm-Message-State: AJIora8oHkbPoWlU5hrJuWD8yOfHH83ZQXV9ffINN7v6UE/CDQzpecMs TVzqkU0QDBpQpPfzpLVWytT9LJnHXKDnOg== X-Google-Smtp-Source: AGRyM1vOjAxbnnjt1DpADEEVLl/xffxBjAPEqZVI++jUzSnHEYGPdIiryt/uyfD6GQ1rw8k2Fsp7sw== X-Received: by 2002:a05:6512:220d:b0:489:f036:7c8c with SMTP id h13-20020a056512220d00b00489f0367c8cmr21522487lfu.15.1658410985708; Thu, 21 Jul 2022 06:43:05 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.43.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:43:05 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 07/15] crypto: ux500/hash: Rename and switch type of member Date: Thu, 21 Jul 2022 15:40:42 +0200 Message-Id: <20220721134050.1047866-8-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The "updated" member of the context is very confusing, it actually means "hw_intialized" so rename it to this and switch it to a bool so it is clear how this is used. Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_alg.h | 4 ++-- drivers/crypto/ux500/hash/hash_core.c | 14 +++++++------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h index 00730c0090ae..d124fd17519f 100644 --- a/drivers/crypto/ux500/hash/hash_alg.h +++ b/drivers/crypto/ux500/hash/hash_alg.h @@ -336,12 +336,12 @@ struct hash_ctx { * @state: The state of the current calculations. * @dma_mode: Used in special cases (workaround), e.g. need to change to * cpu mode, if not supported/working in dma mode. - * @updated: Indicates if hardware is initialized for new operations. + * @hw_initialized: Indicates if hardware is initialized for new operations. */ struct hash_req_ctx { struct hash_state state; bool dma_mode; - u8 updated; + bool hw_initialized; }; /** diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index c9ceaa0b1778..b3649e00184f 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -449,7 +449,7 @@ static int ux500_hash_init(struct ahash_request *req) ctx->keylen = 0; memset(&req_ctx->state, 0, sizeof(struct hash_state)); - req_ctx->updated = 0; + req_ctx->hw_initialized = false; if (hash_mode == HASH_MODE_DMA) { if (req->nbytes < HASH_DMA_ALIGN_SIZE) { req_ctx->dma_mode = false; /* Don't use DMA */ @@ -674,7 +674,7 @@ static int hash_process_data(struct hash_device_data *device_data, break; } - if (req_ctx->updated) { + if (req_ctx->hw_initialized) { ret = hash_resume_state(device_data, &device_data->state); memmove(req_ctx->state.buffer, @@ -694,7 +694,7 @@ static int hash_process_data(struct hash_device_data *device_data, __func__); goto out; } - req_ctx->updated = 1; + req_ctx->hw_initialized = true; } /* * If 'data_buffer' is four byte aligned and @@ -759,7 +759,7 @@ static int hash_dma_final(struct ahash_request *req) dev_dbg(device_data->dev, "%s: (ctx=0x%lx)!\n", __func__, (unsigned long)ctx); - if (req_ctx->updated) { + if (req_ctx->hw_initialized) { ret = hash_resume_state(device_data, &device_data->state); if (ret) { @@ -794,7 +794,7 @@ static int hash_dma_final(struct ahash_request *req) /* Number of bits in last word = (nbytes * 8) % 32 */ HASH_SET_NBLW((req->nbytes * 8) % 32); - req_ctx->updated = 1; + req_ctx->hw_initialized = true; } /* Store the nents in the dma struct. */ @@ -857,7 +857,7 @@ static int hash_hw_final(struct ahash_request *req) dev_dbg(device_data->dev, "%s: (ctx=0x%lx)!\n", __func__, (unsigned long)ctx); - if (req_ctx->updated) { + if (req_ctx->hw_initialized) { ret = hash_resume_state(device_data, &device_data->state); if (ret) { @@ -899,7 +899,7 @@ static int hash_hw_final(struct ahash_request *req) goto out; } - if (!req_ctx->updated) { + if (!req_ctx->hw_initialized) { ret = init_hash_hw(device_data, ctx); if (ret) { dev_err(device_data->dev, From patchwork Thu Jul 21 13:40:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 592194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC19FC433EF for ; Thu, 21 Jul 2022 13:45:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230083AbiGUNpP (ORCPT ); Thu, 21 Jul 2022 09:45:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230106AbiGUNnp (ORCPT ); Thu, 21 Jul 2022 09:43:45 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C66D85D42 for ; Thu, 21 Jul 2022 06:43:09 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id z22so2851003lfu.7 for ; Thu, 21 Jul 2022 06:43:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kbCVp68pTylnpll/X9Y58r8MWp+XSo2mGEuR4kEk9k0=; b=KZysEJGF9UH4uakT8svVH4JJtlutY+f2qmieEzLmzim0oG18NBeW3X4oPJ5WYBZpX0 JhsXXACAudGyqwnd8ntMv30odZBC6TWR7RqJ8BYacgzaw0TFYLU6baicjvBYE76NDBtq JRiYgzrhQDIdX3df2PX8VuzFfEeJqQ2b7FQMYlj82vsaDyUiRdIFBuTa1stMj4HCOqzw thxgH0impl+8tz9g8LM+jtQqwC0rOqDw5rWk/zFHyf+ETntxssf19+USjCH1UWqrG3/A jaKCRrpRbVSYWjlHstWplEcr21gtBmWJgWB3AKlgtMBoBXVkjrQFEPj5+125cs8PuCy9 yLbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kbCVp68pTylnpll/X9Y58r8MWp+XSo2mGEuR4kEk9k0=; b=4f+arQNcfRraxcHEX/TWgJpr3+wcF3xZZUIK4RfGVWttUlDBd+uXDoKQ/DeSxGY3En Ro+jgqb1Ujx/o1N/AuS7Yj7XqKkEsbReYb3JIKDZtIrAnewPz8HtMy2EVkwvAX3vUC1P Pl/xZraKSiPKzx4vZn/nPOo2+HKreGIsTOQgvTeJSTTf7q/yIuTABQr0qwgByNuHTRp9 3mIPFh4R2GGdBK8/8OcejSR2JZOt+ANcC9MD0k3Oeerw36eGAEa7KAfyap0pKfJ7Tqfo U+z4QoPJiGC2XuUkmQxJS4vIwjTX+ZSED+TSYEGBPy+ZMU85mMoqZvjmn5prv8gu6Kd8 BTXg== X-Gm-Message-State: AJIora8a1Wxu5Etdn7oWIb9EnjZsnRJlHzsCLhEpRBQ66GucZimRqy3S iUQPwWfIVVoJrQmhYInCPl9fGegvXoc8ng== X-Google-Smtp-Source: AGRyM1sP8uN2UmbDxPkZ6BT+FFysbLQRDWXGFIwwmPllDY9kofBC0g8g8EM4kuYI2E5x4MaSKerYNQ== X-Received: by 2002:a05:6512:ba4:b0:489:d071:c085 with SMTP id b36-20020a0565120ba400b00489d071c085mr21837242lfv.652.1658410986951; Thu, 21 Jul 2022 06:43:06 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.43.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:43:06 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 08/15] crypto: ux500/hash: Stop saving/restoring compulsively Date: Thu, 21 Jul 2022 15:40:43 +0200 Message-Id: <20220721134050.1047866-9-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The driver is saving/restoring state very intensively, because of assumptions that suspend/resume can be called at any time. (Android behaviours.) We removed the state save/restore from the PM hooks and will use runtime PM for this instead so get rid of this. Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_alg.h | 1 - drivers/crypto/ux500/hash/hash_core.c | 44 +++------------------------ 2 files changed, 4 insertions(+), 41 deletions(-) diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h index d124fd17519f..d9d59dba6e6e 100644 --- a/drivers/crypto/ux500/hash/hash_alg.h +++ b/drivers/crypto/ux500/hash/hash_alg.h @@ -369,7 +369,6 @@ struct hash_device_data { spinlock_t power_state_lock; struct regulator *regulator; struct clk *clk; - struct hash_state state; /* Used for saving and resuming state */ struct hash_dma dma; }; diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index b3649e00184f..c2e8bd977f57 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -674,19 +674,7 @@ static int hash_process_data(struct hash_device_data *device_data, break; } - if (req_ctx->hw_initialized) { - ret = hash_resume_state(device_data, - &device_data->state); - memmove(req_ctx->state.buffer, - device_data->state.buffer, - HASH_BLOCK_SIZE); - if (ret) { - dev_err(device_data->dev, - "%s: hash_resume_state() failed!\n", - __func__); - goto out; - } - } else { + if (!req_ctx->hw_initialized) { ret = init_hash_hw(device_data, ctx); if (ret) { dev_err(device_data->dev, @@ -725,17 +713,6 @@ static int hash_process_data(struct hash_device_data *device_data, msg_length -= (HASH_BLOCK_SIZE - *index); *index = 0; - ret = hash_save_state(device_data, - &device_data->state); - - memmove(device_data->state.buffer, - req_ctx->state.buffer, - HASH_BLOCK_SIZE); - if (ret) { - dev_err(device_data->dev, "%s: hash_save_state() failed!\n", - __func__); - goto out; - } } while (msg_length != 0); out: @@ -759,15 +736,7 @@ static int hash_dma_final(struct ahash_request *req) dev_dbg(device_data->dev, "%s: (ctx=0x%lx)!\n", __func__, (unsigned long)ctx); - if (req_ctx->hw_initialized) { - ret = hash_resume_state(device_data, &device_data->state); - - if (ret) { - dev_err(device_data->dev, "%s: hash_resume_state() failed!\n", - __func__); - goto out; - } - } else { + if (!req_ctx->hw_initialized) { ret = hash_setconfiguration(device_data, ctx); if (ret) { dev_err(device_data->dev, @@ -858,13 +827,8 @@ static int hash_hw_final(struct ahash_request *req) (unsigned long)ctx); if (req_ctx->hw_initialized) { - ret = hash_resume_state(device_data, &device_data->state); - - if (ret) { - dev_err(device_data->dev, - "%s: hash_resume_state() failed!\n", __func__); - goto out; - } + /* That's fine, result is in HW */ + dev_dbg(device_data->dev, "%s hw initialized\n", __func__); } else if (req->nbytes == 0 && ctx->keylen == 0) { u8 zero_hash[SHA256_DIGEST_SIZE]; u32 zero_hash_size = 0; From patchwork Thu Jul 21 13:40:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 592903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52C90CCA479 for ; Thu, 21 Jul 2022 13:45:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230219AbiGUNpd (ORCPT ); Thu, 21 Jul 2022 09:45:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229988AbiGUNoV (ORCPT ); Thu, 21 Jul 2022 09:44:21 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B35385D7A for ; Thu, 21 Jul 2022 06:43:13 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id u19so2927532lfs.0 for ; Thu, 21 Jul 2022 06:43:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e5peYR0Efclqvks8gE1Xez5fN1UPbYUQQo+StiCfVL8=; b=Kedld5xfzBpCYIgbscjcyRNZ3LZV0mdUzdd6OPSW7bzd6LuE6vDnuwuCg3LsbsSbJf DXN1aFoKH0/H12BYIvjgSRqjCIw4HS5iAkLf4rKSkzC97aVVwmDt+qY9oakRzmaj1AEp u8AQzzAWfq+YIYe3HAZCVhKz6lDLwtHpa+XLzrn87KywTGLoFqmx0ig+KyxsQAE24hwo c3xSHcegT+h7bkjc0iNXJKnFFxWkWsBpYyGsWr1lPoZVfstm3CJjp7LzsvnzoK70R4ri WDSfx8iJALv2mOEvtvjt9CLFl2tgaHNlg1tRM1Ml3uEfzIZjiw2/PkOYYeH0tSQ4J8lP wjQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e5peYR0Efclqvks8gE1Xez5fN1UPbYUQQo+StiCfVL8=; b=2Y3G+8O4ajDA+X8oL7VX9tK2tricB7EThc9uaVh0b+XfrZCFfMYjP57VU30LzaClW9 3j2KFUWIEZxGER7/e7uxvFK2+GINeCkxKgt42saR41GEcF/wy3wYOqHcgphb90LxLxxb Ku2aylVoGkEnhliLRBw0lxDCEqBliCN/55Iz4NtiewjLLzyviQgl1p2049cZ5UG9YaVP e9qiz/JQGVp4POg7Ndvo1FaX9QF4REPbrAvC7h1zFq2x0i5Q98bOxQtWZWec9egFgdEx HRQNL4LOHKGITS6lYhtMv8nJ8yeabB/3ANUOv301ZYbXnuSAOyU24NC9juX3B2bHaA8K 2s2Q== X-Gm-Message-State: AJIora9hmq2RCQHGT5cGMQpLlAbyHsn7ymn/uzrGRuBMomB8seOV1KE2 0ixxGzoG4vH8NNtMEOL3DchcOgRY5sLNlw== X-Google-Smtp-Source: AGRyM1uBbJ1+R25sHXBzgNaAD8lR6mxDELXe22s0Ubvae8UDFz1KKJ/fxOZezmd7xEkEzob6fmfjoQ== X-Received: by 2002:a05:6512:32c9:b0:48a:2a34:1f53 with SMTP id f9-20020a05651232c900b0048a2a341f53mr14142009lfg.335.1658410988152; Thu, 21 Jul 2022 06:43:08 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.43.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:43:07 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 09/15] crypto: ux500/hash: Get rid of state from request context Date: Thu, 21 Jul 2022 15:40:44 +0200 Message-Id: <20220721134050.1047866-10-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The request context is exactly for that: context state related to the request. The code was (ab)using the state used to store the hardware state for this. Move out the three variables from the hardware state to the request context and clean up the mess left behind. Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_alg.h | 21 +++++++-------- drivers/crypto/ux500/hash/hash_core.c | 38 +++++++++++---------------- 2 files changed, 26 insertions(+), 33 deletions(-) diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h index d9d59dba6e6e..5aa86c4855f5 100644 --- a/drivers/crypto/ux500/hash/hash_alg.h +++ b/drivers/crypto/ux500/hash/hash_alg.h @@ -214,17 +214,10 @@ struct hash_register { * @csr[52]: HASH Context Swap Registers 0-39. * @csfull: HASH Context Swap Registers 40 ie Status flags. * @csdatain: HASH Context Swap Registers 41 ie Input data. - * @buffer: Working buffer for messages going to the hardware. - * @length: Length of the part of message hashed so far (floor(N/64) * 64). - * @index: Valid number of bytes in buffer (N % 64). * * This structure is used between context switches, i.e. when ongoing jobs are * interupted with new jobs. When this happens we need to store intermediate * results in software. - * - * WARNING: "index" is the member of the structure, to be sure that "buffer" - * is aligned on a 4-bytes boundary. This is highly implementation dependent - * and MUST be checked whenever this code is ported on new platforms. */ struct hash_state { u32 temp_cr; @@ -233,9 +226,6 @@ struct hash_state { u32 csr[52]; u32 csfull; u32 csdatain; - u32 buffer[HASH_BLOCK_SIZE / sizeof(u32)]; - struct uint64 length; - u8 index; }; /** @@ -333,13 +323,22 @@ struct hash_ctx { /** * struct hash_ctx - The request context used for hash calculations. + * @buffer: Working buffer for messages going to the hardware. + * @length: Length of the part of message hashed so far (floor(N/64) * 64). + * @index: Valid number of bytes in buffer (N % 64). * @state: The state of the current calculations. * @dma_mode: Used in special cases (workaround), e.g. need to change to * cpu mode, if not supported/working in dma mode. * @hw_initialized: Indicates if hardware is initialized for new operations. + * + * WARNING: "index" is the member of the structure, to be sure that "buffer" + * is aligned on a 4-bytes boundary. This is highly implementation dependent + * and MUST be checked whenever this code is ported on new platforms. */ struct hash_req_ctx { - struct hash_state state; + u32 buffer[HASH_BLOCK_SIZE / sizeof(u32)]; + struct uint64 length; + u8 index; bool dma_mode; bool hw_initialized; }; diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index c2e8bd977f57..46dad128b6fe 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -448,7 +448,9 @@ static int ux500_hash_init(struct ahash_request *req) if (!ctx->key) ctx->keylen = 0; - memset(&req_ctx->state, 0, sizeof(struct hash_state)); + req_ctx->index = 0; + req_ctx->length.low_word = 0; + req_ctx->length.high_word = 0; req_ctx->hw_initialized = false; if (hash_mode == HASH_MODE_DMA) { if (req->nbytes < HASH_DMA_ALIGN_SIZE) { @@ -553,11 +555,11 @@ static void hash_messagepad(struct hash_device_data *device_data, */ static void hash_incrementlength(struct hash_req_ctx *ctx, u32 incr) { - ctx->state.length.low_word += incr; + ctx->length.low_word += incr; /* Check for wrap-around */ - if (ctx->state.length.low_word < incr) - ctx->state.length.high_word++; + if (ctx->length.low_word < incr) + ctx->length.high_word++; } /** @@ -872,9 +874,9 @@ static int hash_hw_final(struct ahash_request *req) } } - if (req_ctx->state.index) { - hash_messagepad(device_data, req_ctx->state.buffer, - req_ctx->state.index); + if (req_ctx->index) { + hash_messagepad(device_data, req_ctx->buffer, + req_ctx->index); } else { HASH_SET_DCAL; while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) @@ -922,8 +924,8 @@ int hash_hw_update(struct ahash_request *req) struct crypto_hash_walk walk; int msg_length; - index = req_ctx->state.index; - buffer = (u8 *)req_ctx->state.buffer; + index = req_ctx->index; + buffer = (u8 *)req_ctx->buffer; msg_length = crypto_hash_walk_first(req, &walk); @@ -931,10 +933,10 @@ int hash_hw_update(struct ahash_request *req) if (msg_length == 0) return 0; - /* Check if ctx->state.length + msg_length + /* Check if ctx->length + msg_length overflows */ - if (msg_length > (req_ctx->state.length.low_word + msg_length) && - HASH_HIGH_WORD_MAX_VAL == req_ctx->state.length.high_word) { + if (msg_length > (req_ctx->length.low_word + msg_length) && + req_ctx->length.high_word == HASH_HIGH_WORD_VAL_MAX) { pr_err("%s: HASH_MSG_LENGTH_OVERFLOW!\n", __func__); return crypto_hash_walk_done(&walk, -EPERM); } @@ -955,9 +957,9 @@ int hash_hw_update(struct ahash_request *req) msg_length = crypto_hash_walk_done(&walk, 0); } - req_ctx->state.index = index; + req_ctx->index = index; dev_dbg(device_data->dev, "%s: indata length=%d\n", - __func__, req_ctx->state.index); + __func__, req_ctx->index); return 0; } @@ -980,14 +982,6 @@ int hash_resume_state(struct hash_device_data *device_data, return -EPERM; } - /* Check correctness of index and length members */ - if (device_state->index > HASH_BLOCK_SIZE || - (device_state->length.low_word % HASH_BLOCK_SIZE) != 0) { - dev_err(device_data->dev, "%s: HASH_INVALID_PARAMETER!\n", - __func__); - return -EPERM; - } - /* * INIT bit. Set this bit to 0b1 to reset the HASH processor core and * prepare the initialize the HASH accelerator to compute the message From patchwork Thu Jul 21 13:40:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 592192 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B6C7C43334 for ; Thu, 21 Jul 2022 13:45:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230223AbiGUNpe (ORCPT ); Thu, 21 Jul 2022 09:45:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229996AbiGUNod (ORCPT ); Thu, 21 Jul 2022 09:44:33 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4113D85F87 for ; Thu, 21 Jul 2022 06:43:14 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id d17so702870lfa.12 for ; Thu, 21 Jul 2022 06:43:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R2YP8hf62sewspiSTE/eVIUQ9Dbl6R6ObJkLzBoFtJw=; b=d2gWzCAwqoczmPdzT3yJczOOKuoBXetcOvh7Jbb0ZKoBMTytwjEl3W320OXRMa36RP 5LkkNAzlz4NNt+q+7cvRYY/Hiu9kp+6Fl9fykb6/762c6LaVSL2pzzqfWV9yjN0j2dXr eQo+ux1r43EV02T3hn+YFucpoxIzM4BkTf/rcyopEYlEms5naVrD8JLwDTm6ZxVsa4m/ uPwZWyfw0ASEthhvqCQ2LVwW4kDKYCY71p2ubb5LFDiwAG8bpZ9I5xsneE3m572WUZAm uK7/ZJu74F7lC+Jq5iYaOqjrTYNTkId0oDJC6yPI6/acsEF5V63TzG3BTyGy8V9P8RHY WVmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R2YP8hf62sewspiSTE/eVIUQ9Dbl6R6ObJkLzBoFtJw=; b=Oojx+bnGCY6kXFbHkoRRnn9i0O6pjDisO61E/Yvma/App8b0orlbilSaDgH3FI7+sb JLurNqUSmL7E84WknxF/MzjDjKvrhPEJ1KCMWoW4Gf25Pv27ZJIBqnuQV28YbqPbuGLx OZ5U6Q+C7LFUnTJyYIXgvhzjyyOUnM/H5M3n60SvHx5RpjZleMb2Uh5C9lUjN/gPbPno 4Psz8/yusxqcywyLaA1s6qwWVOX9RDK7vdCCaeNaqK02+cAw0PO6V+KDjsmQBcSA/Jnf S2w4VRfpiwU8TwQSz+h5oZNrAfiQWWSt+KR45TFsTKE57sUacC5ndsZRfShsgH6Hj/t4 cOVA== X-Gm-Message-State: AJIora+msTh+fEy4JTIaWCgRf6qDRuvWKN0Ww0m+fg59CDeAHCo2sac9 wJzYFyJCAFwQ+gK3iEojChru4j+GNwiG0A== X-Google-Smtp-Source: AGRyM1vFEVR8Jscvw9xY6XT+usU1QTVOWc+HyjuzSuSrj/9WThkW8h/IBKvgZ+CcK2lZwQjmbyldAA== X-Received: by 2002:a05:6512:31c9:b0:489:e037:31b9 with SMTP id j9-20020a05651231c900b00489e03731b9mr22178941lfe.178.1658410989440; Thu, 21 Jul 2022 06:43:09 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.43.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:43:09 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 10/15] crypto: ux500/hash: Implement .export and .import Date: Thu, 21 Jul 2022 15:40:45 +0200 Message-Id: <20220721134050.1047866-11-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The .export and .import callbacks are just implemented as stubs which makes the tests fail: alg: ahash: hmac-sha256-ux500 export() failed with err -38 on test vector 0, cfg="import/export" ------------[ cut here ]------------ WARNING: CPU: 1 PID: 92 at crypto/testmgr.c:5777 alg_test.part.0+0x160/0x3ec alg: self-tests for hmac-sha256-ux500 (hmac(sha256)) failed (rc=-38) The driver already has code for saving and restoring the hardware state, which is now unused. Pass the tests by simply implementing the callbacks properly, extending the state with the length, index and buffer from the ongoing request context. Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_alg.h | 5 + drivers/crypto/ux500/hash/hash_core.c | 227 +++++++++++++------------- 2 files changed, 114 insertions(+), 118 deletions(-) diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h index 5aa86c4855f5..05f0b0221a13 100644 --- a/drivers/crypto/ux500/hash/hash_alg.h +++ b/drivers/crypto/ux500/hash/hash_alg.h @@ -226,6 +226,11 @@ struct hash_state { u32 csr[52]; u32 csfull; u32 csdatain; + u32 buffer[HASH_BLOCK_SIZE / sizeof(u32)]; + struct uint64 length; + u8 index; + bool dma_mode; + bool hw_initialized; }; /** diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index 46dad128b6fe..1edb11812c7d 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -964,108 +964,6 @@ int hash_hw_update(struct ahash_request *req) return 0; } -/** - * hash_resume_state - Function that resumes the state of an calculation. - * @device_data: Pointer to the device structure. - * @device_state: The state to be restored in the hash hardware - */ -int hash_resume_state(struct hash_device_data *device_data, - const struct hash_state *device_state) -{ - u32 temp_cr; - s32 count; - int hash_mode = HASH_OPER_MODE_HASH; - - if (NULL == device_state) { - dev_err(device_data->dev, "%s: HASH_INVALID_PARAMETER!\n", - __func__); - return -EPERM; - } - - /* - * INIT bit. Set this bit to 0b1 to reset the HASH processor core and - * prepare the initialize the HASH accelerator to compute the message - * digest of a new message. - */ - HASH_INITIALIZE; - - temp_cr = device_state->temp_cr; - writel_relaxed(temp_cr & HASH_CR_RESUME_MASK, &device_data->base->cr); - - if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK) - hash_mode = HASH_OPER_MODE_HMAC; - else - hash_mode = HASH_OPER_MODE_HASH; - - for (count = 0; count < HASH_CSR_COUNT; count++) { - if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH)) - break; - - writel_relaxed(device_state->csr[count], - &device_data->base->csrx[count]); - } - - writel_relaxed(device_state->csfull, &device_data->base->csfull); - writel_relaxed(device_state->csdatain, &device_data->base->csdatain); - - writel_relaxed(device_state->str_reg, &device_data->base->str); - writel_relaxed(temp_cr, &device_data->base->cr); - - return 0; -} - -/** - * hash_save_state - Function that saves the state of hardware. - * @device_data: Pointer to the device structure. - * @device_state: The strucure where the hardware state should be saved. - */ -int hash_save_state(struct hash_device_data *device_data, - struct hash_state *device_state) -{ - u32 temp_cr; - u32 count; - int hash_mode = HASH_OPER_MODE_HASH; - - if (NULL == device_state) { - dev_err(device_data->dev, "%s: HASH_INVALID_PARAMETER!\n", - __func__); - return -ENOTSUPP; - } - - /* Write dummy value to force digest intermediate calculation. This - * actually makes sure that there isn't any ongoing calculation in the - * hardware. - */ - while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) - cpu_relax(); - - temp_cr = readl_relaxed(&device_data->base->cr); - - device_state->str_reg = readl_relaxed(&device_data->base->str); - - device_state->din_reg = readl_relaxed(&device_data->base->din); - - if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK) - hash_mode = HASH_OPER_MODE_HMAC; - else - hash_mode = HASH_OPER_MODE_HASH; - - for (count = 0; count < HASH_CSR_COUNT; count++) { - if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH)) - break; - - device_state->csr[count] = - readl_relaxed(&device_data->base->csrx[count]); - } - - device_state->csfull = readl_relaxed(&device_data->base->csfull); - device_state->csdatain = readl_relaxed(&device_data->base->csdatain); - - device_state->temp_cr = temp_cr; - - return 0; -} - /** * hash_check_hw - This routine checks for peripheral Ids and PCell Ids. * @device_data: @@ -1244,14 +1142,107 @@ static int ahash_sha256_digest(struct ahash_request *req) return ret1 ? ret1 : ret2; } -static int ahash_noimport(struct ahash_request *req, const void *in) +static int ahash_import(struct ahash_request *req, const void *in) { - return -ENOSYS; + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); + struct hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct hash_device_data *device_data = ctx->device; + struct hash_req_ctx *req_ctx = ahash_request_ctx(req); + const struct hash_state *hstate = in; + int hash_mode = HASH_OPER_MODE_HASH; + u32 cr; + s32 count; + + /* Restore software state */ + req_ctx->length = hstate->length; + req_ctx->index = hstate->index; + req_ctx->dma_mode = hstate->dma_mode; + req_ctx->hw_initialized = hstate->hw_initialized; + memcpy(req_ctx->buffer, hstate->buffer, HASH_BLOCK_SIZE); + + /* + * Restore hardware state + * INIT bit. Set this bit to 0b1 to reset the HASH processor core and + * prepare the initialize the HASH accelerator to compute the message + * digest of a new message. + */ + HASH_INITIALIZE; + + cr = hstate->temp_cr; + writel_relaxed(cr & HASH_CR_RESUME_MASK, &device_data->base->cr); + + if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK) + hash_mode = HASH_OPER_MODE_HMAC; + else + hash_mode = HASH_OPER_MODE_HASH; + + for (count = 0; count < HASH_CSR_COUNT; count++) { + if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH)) + break; + writel_relaxed(hstate->csr[count], + &device_data->base->csrx[count]); + } + + writel_relaxed(hstate->csfull, &device_data->base->csfull); + writel_relaxed(hstate->csdatain, &device_data->base->csdatain); + writel_relaxed(hstate->str_reg, &device_data->base->str); + writel_relaxed(cr, &device_data->base->cr); + + return 0; } -static int ahash_noexport(struct ahash_request *req, void *out) +static int ahash_export(struct ahash_request *req, void *out) { - return -ENOSYS; + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); + struct hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct hash_device_data *device_data = ctx->device; + struct hash_req_ctx *req_ctx = ahash_request_ctx(req); + struct hash_state *hstate = out; + int hash_mode = HASH_OPER_MODE_HASH; + u32 cr; + u32 count; + + /* + * Save hardware state: + * Write dummy value to force digest intermediate calculation. This + * actually makes sure that there isn't any ongoing calculation in the + * hardware. + */ + while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) + cpu_relax(); + + cr = readl_relaxed(&device_data->base->cr); + + hstate->str_reg = readl_relaxed(&device_data->base->str); + + hstate->din_reg = readl_relaxed(&device_data->base->din); + + if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK) + hash_mode = HASH_OPER_MODE_HMAC; + else + hash_mode = HASH_OPER_MODE_HASH; + + for (count = 0; count < HASH_CSR_COUNT; count++) { + if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH)) + break; + + hstate->csr[count] = + readl_relaxed(&device_data->base->csrx[count]); + } + + hstate->csfull = readl_relaxed(&device_data->base->csfull); + hstate->csdatain = readl_relaxed(&device_data->base->csdatain); + + hstate->temp_cr = cr; + + /* Save software state */ + hstate->length = req_ctx->length; + hstate->index = req_ctx->index; + hstate->dma_mode = req_ctx->dma_mode; + hstate->hw_initialized = req_ctx->hw_initialized; + memcpy(hstate->buffer, req_ctx->buffer, HASH_BLOCK_SIZE); + + return 0; } static int hmac_sha1_init(struct ahash_request *req) @@ -1361,10 +1352,10 @@ static struct hash_algo_template hash_algs[] = { .update = ahash_update, .final = ahash_final, .digest = ahash_sha1_digest, - .export = ahash_noexport, - .import = ahash_noimport, + .export = ahash_export, + .import = ahash_import, .halg.digestsize = SHA1_DIGEST_SIZE, - .halg.statesize = sizeof(struct hash_ctx), + .halg.statesize = sizeof(struct hash_state), .halg.base = { .cra_name = "sha1", .cra_driver_name = "sha1-ux500", @@ -1384,10 +1375,10 @@ static struct hash_algo_template hash_algs[] = { .update = ahash_update, .final = ahash_final, .digest = ahash_sha256_digest, - .export = ahash_noexport, - .import = ahash_noimport, + .export = ahash_export, + .import = ahash_import, .halg.digestsize = SHA256_DIGEST_SIZE, - .halg.statesize = sizeof(struct hash_ctx), + .halg.statesize = sizeof(struct hash_state), .halg.base = { .cra_name = "sha256", .cra_driver_name = "sha256-ux500", @@ -1408,10 +1399,10 @@ static struct hash_algo_template hash_algs[] = { .final = ahash_final, .digest = hmac_sha1_digest, .setkey = hmac_sha1_setkey, - .export = ahash_noexport, - .import = ahash_noimport, + .export = ahash_export, + .import = ahash_import, .halg.digestsize = SHA1_DIGEST_SIZE, - .halg.statesize = sizeof(struct hash_ctx), + .halg.statesize = sizeof(struct hash_state), .halg.base = { .cra_name = "hmac(sha1)", .cra_driver_name = "hmac-sha1-ux500", @@ -1432,10 +1423,10 @@ static struct hash_algo_template hash_algs[] = { .final = ahash_final, .digest = hmac_sha256_digest, .setkey = hmac_sha256_setkey, - .export = ahash_noexport, - .import = ahash_noimport, + .export = ahash_export, + .import = ahash_import, .halg.digestsize = SHA256_DIGEST_SIZE, - .halg.statesize = sizeof(struct hash_ctx), + .halg.statesize = sizeof(struct hash_state), .halg.base = { .cra_name = "hmac(sha256)", .cra_driver_name = "hmac-sha256-ux500", From patchwork Thu Jul 21 13:40:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 592904 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AE2FC433EF for ; Thu, 21 Jul 2022 13:45:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229897AbiGUNpW (ORCPT ); Thu, 21 Jul 2022 09:45:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230170AbiGUNns (ORCPT ); Thu, 21 Jul 2022 09:43:48 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 891D684EDE for ; Thu, 21 Jul 2022 06:43:11 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id y11so2858446lfs.6 for ; Thu, 21 Jul 2022 06:43:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wnw+J8g0tiBhDzUiau+rb2PQi3V9NPBPTs3vvmSimvA=; b=C/30z5ieecqUehs+DRtzuPB5/G+kSizttIIaABkDKMpSlvs4oOY1lTItvwUZitY155 JVT3fUHSfI/Sp4/5r8SP3STvPr3jM0AF6srfDc4GDa0ajcjgBlWvN90meerLs2EReuMp jJr/c+jdMTCvFfzhRe03l6Ez8a0wKMmKzHu2N/PBChSQsSYva4SfJrwCEOPA6PrKVYTg C2o/qoIacYS6dC/N3mfIgR3vi9J43lNccyIhOEUMGbJDlbXn3nksw0/HFrFB9ITYBILe ReqRy9ETf9hZVxKkLG0dCX8DiDtzNJ6gb2TGygeeVIH7dApKtFFiBeL71vH5WoqKiyxf HaDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wnw+J8g0tiBhDzUiau+rb2PQi3V9NPBPTs3vvmSimvA=; b=1hK7OazHykZOI870quKK7EKSJJng9WadTqnOolrwNSu/9WI3z5hZ9vR+hoazVZf3G6 oLzYTSTiu4EGf0MFFrtO/YsZLxY59a/w8sEskKJiWVsJf0c7H57JI1rtnMmX0pOyedT7 ECsV50RYou9waMfRC0FkTCGvjopAJjJ/2JiSfYOxjTtJYH62vUM81SA+N4+FwYhJ8XfQ end4ZPAqFNrK/bU6at3VhBxUdorTVh6mwaXvELK1ZDolBL6qVnssDXkRUF/O9gwWskFK GLQhX/itHj2wiZP8ybspQ4VGwb8q7B1uS/86T4DDclbEPtwtbJ6AnncXF/0q/Hj0HWCs V+Wg== X-Gm-Message-State: AJIora+qWTTrD1JHY3OoIf0ISVKJrJRfsUdscF/pUqoJEZxVW28zK+jN u+05eXqeGbwVesc5crlRYMIqY4UZlAWCGg== X-Google-Smtp-Source: AGRyM1up3uDJL+F6wFXlokobzv+BfbbhHSmmnKFXtK5/UNG931oQbQMPOjvf5vm/UJcpy9mbBjZG+A== X-Received: by 2002:a05:6512:3b27:b0:489:e87e:c1ef with SMTP id f39-20020a0565123b2700b00489e87ec1efmr22562535lfv.490.1658410990833; Thu, 21 Jul 2022 06:43:10 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.43.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:43:10 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 11/15] crypto: ux500/hash: Drop custom uint64 type Date: Thu, 21 Jul 2022 15:40:46 +0200 Message-Id: <20220721134050.1047866-12-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Drop the homebrewn uint64 support, the kernel has a u64 type that works just fine so we use that instead. Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_alg.h | 19 ++---------------- drivers/crypto/ux500/hash/hash_core.c | 28 ++++----------------------- 2 files changed, 6 insertions(+), 41 deletions(-) diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h index 05f0b0221a13..6a610c83e63d 100644 --- a/drivers/crypto/ux500/hash/hash_alg.h +++ b/drivers/crypto/ux500/hash/hash_alg.h @@ -16,9 +16,6 @@ #define HASH_DMA_PERFORMANCE_MIN_SIZE 1024 #define HASH_BYTES_PER_WORD 4 -/* Maximum value of the length's high word */ -#define HASH_HIGH_WORD_MAX_VAL 0xFFFFFFFFUL - /* Power on Reset values HASH registers */ #define HASH_RESET_CR_VALUE 0x0 #define HASH_RESET_STR_VALUE 0x0 @@ -135,18 +132,6 @@ enum hash_mode { HASH_MODE_DMA }; -/** - * struct uint64 - Structure to handle 64 bits integers. - * @high_word: Most significant bits. - * @low_word: Least significant bits. - * - * Used to handle 64 bits integers. - */ -struct uint64 { - u32 high_word; - u32 low_word; -}; - /** * struct hash_register - Contains all registers in ux500 hash hardware. * @cr: HASH control register (0x000). @@ -227,7 +212,7 @@ struct hash_state { u32 csfull; u32 csdatain; u32 buffer[HASH_BLOCK_SIZE / sizeof(u32)]; - struct uint64 length; + u64 length; u8 index; bool dma_mode; bool hw_initialized; @@ -342,7 +327,7 @@ struct hash_ctx { */ struct hash_req_ctx { u32 buffer[HASH_BLOCK_SIZE / sizeof(u32)]; - struct uint64 length; + u64 length; u8 index; bool dma_mode; bool hw_initialized; diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index 1edb11812c7d..390e50b2b1d2 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -449,8 +449,7 @@ static int ux500_hash_init(struct ahash_request *req) ctx->keylen = 0; req_ctx->index = 0; - req_ctx->length.low_word = 0; - req_ctx->length.high_word = 0; + req_ctx->length = 0; req_ctx->hw_initialized = false; if (hash_mode == HASH_MODE_DMA) { if (req->nbytes < HASH_DMA_ALIGN_SIZE) { @@ -545,23 +544,6 @@ static void hash_messagepad(struct hash_device_data *device_data, cpu_relax(); } -/** - * hash_incrementlength - Increments the length of the current message. - * @ctx: Hash context - * @incr: Length of message processed already - * - * Overflow cannot occur, because conditions for overflow are checked in - * hash_hw_update. - */ -static void hash_incrementlength(struct hash_req_ctx *ctx, u32 incr) -{ - ctx->length.low_word += incr; - - /* Check for wrap-around */ - if (ctx->length.low_word < incr) - ctx->length.high_word++; -} - /** * hash_setconfiguration - Sets the required configuration for the hash * hardware. @@ -709,7 +691,7 @@ static int hash_process_data(struct hash_device_data *device_data, (const u32 *)buffer, HASH_BLOCK_SIZE); } - hash_incrementlength(req_ctx, HASH_BLOCK_SIZE); + req_ctx->length += HASH_BLOCK_SIZE; data_buffer += (HASH_BLOCK_SIZE - *index); msg_length -= (HASH_BLOCK_SIZE - *index); @@ -933,10 +915,8 @@ int hash_hw_update(struct ahash_request *req) if (msg_length == 0) return 0; - /* Check if ctx->length + msg_length - overflows */ - if (msg_length > (req_ctx->length.low_word + msg_length) && - req_ctx->length.high_word == HASH_HIGH_WORD_VAL_MAX) { + /* Check if ctx->length + msg_length overflows */ + if ((req_ctx->length + msg_length) < msg_length) { pr_err("%s: HASH_MSG_LENGTH_OVERFLOW!\n", __func__); return crypto_hash_walk_done(&walk, -EPERM); } From patchwork Thu Jul 21 13:40:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 592191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B07EFC43334 for ; Thu, 21 Jul 2022 13:45:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230244AbiGUNpk (ORCPT ); Thu, 21 Jul 2022 09:45:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230029AbiGUNov (ORCPT ); Thu, 21 Jul 2022 09:44:51 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B70E85F97 for ; Thu, 21 Jul 2022 06:43:17 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id a13so1694401ljr.11 for ; Thu, 21 Jul 2022 06:43:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FG0jPdxq5eW4S8mi1x58YdL/tr+OhPTSCWiSDPmXccI=; b=opOBX+nqeRv3LFnIyskD2u2DWdz3/nzzFEqtOcW/p9sP76sLjCZq662hgSn0bQHR1Y VOERnXo5+bo3IJAlckB9hqijWhPiVIIFk/bnvfrieVnP+Y8CuAdQJr13o91VBFGlNWKV rkhZramDPVTKXSJYkJnje+/Wr79JQL8MKnqfUCkiqB/XUXLGn8QI3nebCgZYrP/CAJ2p kcHQBqTnQsFsO+u0ncx3I0bvNs3CVLB82Ow7UqO/bxyDEAmFS6jqw5uBsdTZm/IgbaLe nC1OLWfXSjfmGkv0WALmm9xja9kal0Lf+ANXp43U/C0SBmMpZm8vFlzgIBa7PMZR2RYK CWTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FG0jPdxq5eW4S8mi1x58YdL/tr+OhPTSCWiSDPmXccI=; b=2C2v9FvhRo5bRty1gJ5r3YoprC+lWCDUa38bLLdXQUDZrAiSJw9n3KmUFyfpFxqUCN tA+9Im/0KyMZuUX3Q/wi6CG8NHJ0rFlC+y1f37Atp71Nn5p9QHtiFpRg2Cp96NgMPfQ9 IN+xoC6fZy0ifXvjWK3ILgKITDE/+3di4KzuTvFGuq5/yjhvJU2QywwqB8YFSNYFSR9A ncpOWjP0XR1BuAJqDTvLcstbJHD0XJMdkY9m5PvZj67hyjJXI0QmC+JIsp2pJmVUFgOR SPAVK8xp9Y2lMSTIyAY18JshloR9hwRVANKiPRhUe5xCYLQWid+cJAN9IFZHOc+mAenS jC7A== X-Gm-Message-State: AJIora8Fu38XhBy/Fsq67dVy6FIA31dtZZTcanKTh5Ww0qjts4SqeMtV yATrEMwps/AYjsso8oNtJeQaLQkGyzCIsg== X-Google-Smtp-Source: AGRyM1u/jnmR7U/PtbYw3j2ilw4u4s8lNNfEV16X9C0NpovjEOc6HPqQ/JPGsQqqxngONJrGdm6jSg== X-Received: by 2002:a2e:9f51:0:b0:25d:e9da:829c with SMTP id v17-20020a2e9f51000000b0025de9da829cmr623091ljk.297.1658410992145; Thu, 21 Jul 2022 06:43:12 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.43.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:43:11 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 12/15] crypto: ux500/hash: Convert to regmap MMIO Date: Thu, 21 Jul 2022 15:40:47 +0200 Message-Id: <20220721134050.1047866-13-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The driver goes to extents to map a struct over all the registers and access the registers and macros to access certain fields and bits in a way equivalent but inferior to the existing Linux regmap. The driver predates the introduction of regmap MMIO, so this is understandable. Convert the driver to use regmap MMIO instead. Checkpatch complains about -ENOTSUPP so use -ENODEV instead. Signed-off-by: Linus Walleij --- drivers/crypto/ux500/Kconfig | 1 + drivers/crypto/ux500/hash/hash_alg.h | 200 +++----------- drivers/crypto/ux500/hash/hash_core.c | 360 +++++++++++++++----------- 3 files changed, 246 insertions(+), 315 deletions(-) diff --git a/drivers/crypto/ux500/Kconfig b/drivers/crypto/ux500/Kconfig index f56d65c56ccf..5d70f5965d06 100644 --- a/drivers/crypto/ux500/Kconfig +++ b/drivers/crypto/ux500/Kconfig @@ -20,6 +20,7 @@ config CRYPTO_DEV_UX500_HASH select CRYPTO_HASH select CRYPTO_SHA1 select CRYPTO_SHA256 + select REGMAP_MMIO help This selects the hash driver for the UX500_HASH hardware. Depends on UX500/STM DMA if running in DMA mode. diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h index 6a610c83e63d..cc44d3cb21ac 100644 --- a/drivers/crypto/ux500/hash/hash_alg.h +++ b/drivers/crypto/ux500/hash/hash_alg.h @@ -8,6 +8,7 @@ #ifndef _HASH_ALG_H #define _HASH_ALG_H +#include #include #define HASH_BLOCK_SIZE 64 @@ -16,70 +17,50 @@ #define HASH_DMA_PERFORMANCE_MIN_SIZE 1024 #define HASH_BYTES_PER_WORD 4 -/* Power on Reset values HASH registers */ -#define HASH_RESET_CR_VALUE 0x0 -#define HASH_RESET_STR_VALUE 0x0 - /* Number of context swap registers */ #define HASH_CSR_COUNT 52 -#define HASH_RESET_CSRX_REG_VALUE 0x0 -#define HASH_RESET_CSFULL_REG_VALUE 0x0 -#define HASH_RESET_CSDATAIN_REG_VALUE 0x0 - -#define HASH_RESET_INDEX_VAL 0x0 -#define HASH_RESET_BIT_INDEX_VAL 0x0 -#define HASH_RESET_BUFFER_VAL 0x0 -#define HASH_RESET_LEN_HIGH_VAL 0x0 -#define HASH_RESET_LEN_LOW_VAL 0x0 +#define UX500_HASH_CR 0x00 +#define UX500_HASH_DIN 0x04 +#define UX500_HASH_STR 0x08 +#define UX500_HASH_H(x) (0x0C + ((x) * 0x04)) +#define UX500_HASH_ITCR 0x80 +#define UX500_HASH_ITIP 0x84 +#define UX500_HASH_ITOP 0x88 +#define UX500_HASH_CSFULL 0xF8 +#define UX500_HASH_CSDATAIN 0xFC +#define UX500_HASH_CSR(x) (0x100 + ((x) * 0x04)) +#define UX500_HASH_PERIPHID0 0xFE0 +#define UX500_HASH_PERIPHID1 0xFE4 +#define UX500_HASH_PERIPHID2 0xFE8 +#define UX500_HASH_PERIPHID3 0xFEC +#define UX500_HASH_CELLID0 0xFF0 +#define UX500_HASH_CELLID1 0xFF4 +#define UX500_HASH_CELLID2 0xFF8 +#define UX500_HASH_CELLID3 0xFFC /* Control register bitfields */ #define HASH_CR_RESUME_MASK 0x11FCF - -#define HASH_CR_SWITCHON_POS 31 -#define HASH_CR_SWITCHON_MASK BIT(31) - -#define HASH_CR_EMPTYMSG_POS 20 -#define HASH_CR_EMPTYMSG_MASK BIT(20) - -#define HASH_CR_DINF_POS 12 -#define HASH_CR_DINF_MASK BIT(12) - -#define HASH_CR_NBW_POS 8 +#define HASH_CR_SWITCHON BIT(31) +#define HASH_CR_EMPTYMSG BIT(20) +#define HASH_CR_DINF BIT(12) #define HASH_CR_NBW_MASK 0x00000F00UL - -#define HASH_CR_LKEY_POS 16 -#define HASH_CR_LKEY_MASK BIT(16) - -#define HASH_CR_ALGO_POS 7 -#define HASH_CR_ALGO_MASK BIT(7) - -#define HASH_CR_MODE_POS 6 -#define HASH_CR_MODE_MASK BIT(6) - -#define HASH_CR_DATAFORM_POS 4 +#define HASH_CR_LKEY BIT(16) +#define HASH_CR_ALGO BIT(7) +#define HASH_CR_MODE BIT(6) #define HASH_CR_DATAFORM_MASK (BIT(4) | BIT(5)) - -#define HASH_CR_DMAE_POS 3 -#define HASH_CR_DMAE_MASK BIT(3) - -#define HASH_CR_INIT_POS 2 -#define HASH_CR_INIT_MASK BIT(2) - -#define HASH_CR_PRIVN_POS 1 -#define HASH_CR_PRIVN_MASK BIT(1) - -#define HASH_CR_SECN_POS 0 -#define HASH_CR_SECN_MASK BIT(0) +#define HASH_CR_DATAFORM_32BIT 0 +#define HASH_CR_DATAFORM_16BIT BIT(4) +#define HASH_CR_DATAFORM_8BIT BIT(5) +#define HASH_CR_DATAFORM_1BIT (BIT(4) | BIT(5)) +#define HASH_CR_DMAE BIT(3) +#define HASH_CR_INIT BIT(2) +#define HASH_CR_PRIVN BIT(1) +#define HASH_CR_SECN BIT(0) /* Start register bitfields */ -#define HASH_STR_DCAL_POS 8 -#define HASH_STR_DCAL_MASK BIT(8) -#define HASH_STR_DEFAULT 0x0 - -#define HASH_STR_NBLW_POS 0 +#define HASH_STR_DCAL BIT(8) #define HASH_STR_NBLW_MASK 0x0000001FUL - #define HASH_NBLW_MAX_VAL 0x1F /* PrimeCell IDs */ @@ -92,105 +73,12 @@ #define HASH_CELL_ID2 0x05 #define HASH_CELL_ID3 0xB1 -#define HASH_SET_BITS(reg_name, mask) \ - writel_relaxed((readl_relaxed(reg_name) | mask), reg_name) - -#define HASH_CLEAR_BITS(reg_name, mask) \ - writel_relaxed((readl_relaxed(reg_name) & ~mask), reg_name) - -#define HASH_PUT_BITS(reg, val, shift, mask) \ - writel_relaxed(((readl(reg) & ~(mask)) | \ - (((u32)val << shift) & (mask))), reg) - -#define HASH_SET_DIN(val, len) writesl(&device_data->base->din, (val), (len)) - -#define HASH_INITIALIZE \ - HASH_PUT_BITS( \ - &device_data->base->cr, \ - 0x01, HASH_CR_INIT_POS, \ - HASH_CR_INIT_MASK) - -#define HASH_SET_DATA_FORMAT(data_format) \ - HASH_PUT_BITS( \ - &device_data->base->cr, \ - (u32) (data_format), HASH_CR_DATAFORM_POS, \ - HASH_CR_DATAFORM_MASK) -#define HASH_SET_NBLW(val) \ - HASH_PUT_BITS( \ - &device_data->base->str, \ - (u32) (val), HASH_STR_NBLW_POS, \ - HASH_STR_NBLW_MASK) -#define HASH_SET_DCAL \ - HASH_PUT_BITS( \ - &device_data->base->str, \ - 0x01, HASH_STR_DCAL_POS, \ - HASH_STR_DCAL_MASK) - /* Hardware access method */ enum hash_mode { HASH_MODE_CPU, HASH_MODE_DMA }; -/** - * struct hash_register - Contains all registers in ux500 hash hardware. - * @cr: HASH control register (0x000). - * @din: HASH data input register (0x004). - * @str: HASH start register (0x008). - * @hx: HASH digest register 0..7 (0x00c-0x01C). - * @padding0: Reserved (0x02C). - * @itcr: Integration test control register (0x080). - * @itip: Integration test input register (0x084). - * @itop: Integration test output register (0x088). - * @padding1: Reserved (0x08C). - * @csfull: HASH context full register (0x0F8). - * @csdatain: HASH context swap data input register (0x0FC). - * @csrx: HASH context swap register 0..51 (0x100-0x1CC). - * @padding2: Reserved (0x1D0). - * @periphid0: HASH peripheral identification register 0 (0xFE0). - * @periphid1: HASH peripheral identification register 1 (0xFE4). - * @periphid2: HASH peripheral identification register 2 (0xFE8). - * @periphid3: HASH peripheral identification register 3 (0xFEC). - * @cellid0: HASH PCell identification register 0 (0xFF0). - * @cellid1: HASH PCell identification register 1 (0xFF4). - * @cellid2: HASH PCell identification register 2 (0xFF8). - * @cellid3: HASH PCell identification register 3 (0xFFC). - * - * The device communicates to the HASH via 32-bit-wide control registers - * accessible via the 32-bit width AMBA rev. 2.0 AHB Bus. Below is a structure - * with the registers used. - */ -struct hash_register { - u32 cr; - u32 din; - u32 str; - u32 hx[8]; - - u32 padding0[(0x080 - 0x02C) / sizeof(u32)]; - - u32 itcr; - u32 itip; - u32 itop; - - u32 padding1[(0x0F8 - 0x08C) / sizeof(u32)]; - - u32 csfull; - u32 csdatain; - u32 csrx[HASH_CSR_COUNT]; - - u32 padding2[(0xFE0 - 0x1D0) / sizeof(u32)]; - - u32 periphid0; - u32 periphid1; - u32 periphid2; - u32 periphid3; - - u32 cellid0; - u32 cellid1; - u32 cellid2; - u32 cellid3; -}; - /** * struct hash_state - Hash context state. * @temp_cr: Temporary HASH Control Register. @@ -228,20 +116,6 @@ enum hash_device_id { HASH_DEVICE_ID_1 = 1 }; -/** - * enum hash_data_format - HASH data format. - * @HASH_DATA_32_BITS: 32 bits data format - * @HASH_DATA_16_BITS: 16 bits data format - * @HASH_DATA_8_BITS: 8 bits data format. - * @HASH_DATA_1_BITS: 1 bit data format. - */ -enum hash_data_format { - HASH_DATA_32_BITS = 0x0, - HASH_DATA_16_BITS = 0x1, - HASH_DATA_8_BITS = 0x2, - HASH_DATA_1_BIT = 0x3 -}; - /** * enum hash_algo - Enumeration for selecting between SHA1 or SHA2 algorithm. * @HASH_ALGO_SHA1: Indicates that SHA1 is used. @@ -269,7 +143,7 @@ enum hash_op { * @oper_mode: Operating mode selection bit. */ struct hash_config { - int data_format; + unsigned int data_format; int algorithm; int oper_mode; }; @@ -335,7 +209,7 @@ struct hash_req_ctx { /** * struct hash_device_data - structure for a hash device. - * @base: Pointer to virtual base address of the hash device. + * @map: Regmap for the MMIO for the device * @phybase: Pointer to physical memory location of the hash device. * @list_node: For inclusion in klist. * @dev: Pointer to the device dev structure. @@ -348,7 +222,7 @@ struct hash_req_ctx { * @dma: Structure used for dma. */ struct hash_device_data { - struct hash_register __iomem *base; + struct regmap *map; phys_addr_t phybase; struct klist_node list_node; struct device *dev; diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index 390e50b2b1d2..83833cbe595f 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -305,6 +306,17 @@ static int hash_enable_power(struct hash_device_data *device_data) return ret; } +static void hash_wait_for_dcal(struct hash_device_data *device_data) +{ + unsigned int val; + + regmap_read(device_data->map, UX500_HASH_STR, &val); + while (val & HASH_STR_DCAL) { + cpu_relax(); + regmap_read(device_data->map, UX500_HASH_STR, &val); + } +} + /** * hash_hw_write_key - Writes the key to the hardware registries. * @@ -319,37 +331,18 @@ static int hash_enable_power(struct hash_device_data *device_data) static void hash_hw_write_key(struct hash_device_data *device_data, const u8 *key, unsigned int keylen) { - u32 word = 0; - int nwords = 1; - - HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK); + regmap_update_bits(device_data->map, UX500_HASH_STR, + HASH_STR_NBLW_MASK, 0); - while (keylen >= 4) { - u32 *key_word = (u32 *)key; + regmap_noinc_write(device_data->map, UX500_HASH_DIN, + key, keylen); - HASH_SET_DIN(key_word, nwords); - keylen -= 4; - key += 4; - } + hash_wait_for_dcal(device_data); - /* Take care of the remaining bytes in the last word */ - if (keylen) { - word = 0; - while (keylen) { - word |= (key[keylen - 1] << (8 * (keylen - 1))); - keylen--; - } + regmap_update_bits(device_data->map, UX500_HASH_STR, + HASH_STR_DCAL, HASH_STR_DCAL); - HASH_SET_DIN(&word, nwords); - } - - while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) - cpu_relax(); - - HASH_SET_DCAL; - - while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) - cpu_relax(); + hash_wait_for_dcal(device_data); } /** @@ -484,16 +477,17 @@ static int ux500_hash_init(struct ahash_request *req) static void hash_processblock(struct hash_device_data *device_data, const u32 *message, int length) { - int len = length / HASH_BYTES_PER_WORD; /* * NBLW bits. Reset the number of bits in last word (NBLW). */ - HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK); + regmap_update_bits(device_data->map, UX500_HASH_STR, + HASH_STR_NBLW_MASK, 0); /* * Write message data to the HASH_DIN register. */ - HASH_SET_DIN(message, len); + regmap_noinc_write(device_data->map, UX500_HASH_DIN, + message, length); } /** @@ -509,39 +503,25 @@ static void hash_processblock(struct hash_device_data *device_data, static void hash_messagepad(struct hash_device_data *device_data, const u32 *message, u8 index_bytes) { - int nwords = 1; - /* * Clear hash str register, only clear NBLW * since DCAL will be reset by hardware. */ - HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK); - - /* Main loop */ - while (index_bytes >= 4) { - HASH_SET_DIN(message, nwords); - index_bytes -= 4; - message++; - } + regmap_update_bits(device_data->map, UX500_HASH_STR, + HASH_STR_NBLW_MASK, 0); - if (index_bytes) - HASH_SET_DIN(message, nwords); + regmap_noinc_write(device_data->map, UX500_HASH_DIN, + message, index_bytes); - while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) - cpu_relax(); + hash_wait_for_dcal(device_data); /* num_of_bytes == 0 => NBLW <- 0 (32 bits valid in DATAIN) */ - HASH_SET_NBLW(index_bytes * 8); - dev_dbg(device_data->dev, "%s: DIN=0x%08x NBLW=%lu\n", - __func__, readl_relaxed(&device_data->base->din), - readl_relaxed(&device_data->base->str) & HASH_STR_NBLW_MASK); - HASH_SET_DCAL; - dev_dbg(device_data->dev, "%s: after dcal -> DIN=0x%08x NBLW=%lu\n", - __func__, readl_relaxed(&device_data->base->din), - readl_relaxed(&device_data->base->str) & HASH_STR_NBLW_MASK); - - while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) - cpu_relax(); + regmap_update_bits(device_data->map, UX500_HASH_STR, + HASH_STR_NBLW_MASK, index_bytes * 8); + regmap_update_bits(device_data->map, UX500_HASH_STR, + HASH_STR_DCAL, HASH_STR_DCAL); + + hash_wait_for_dcal(device_data); } /** @@ -564,18 +544,21 @@ int hash_setconfiguration(struct hash_device_data *device_data, * DATAFORM bits. Set the DATAFORM bits to 0b11, which means the data * to be written to HASH_DIN is considered as 32 bits. */ - HASH_SET_DATA_FORMAT(config->data_format); + regmap_update_bits(device_data->map, UX500_HASH_CR, + HASH_CR_DATAFORM_MASK, config->data_format); /* * ALGO bit. Set to 0b1 for SHA-1 and 0b0 for SHA-256 */ switch (config->algorithm) { case HASH_ALGO_SHA1: - HASH_SET_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK); + regmap_update_bits(device_data->map, UX500_HASH_CR, + HASH_CR_ALGO, HASH_CR_ALGO); break; case HASH_ALGO_SHA256: - HASH_CLEAR_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK); + regmap_update_bits(device_data->map, UX500_HASH_CR, + HASH_CR_ALGO, 0); break; default: @@ -589,20 +572,21 @@ int hash_setconfiguration(struct hash_device_data *device_data, * selected algorithm. 0b0 = HASH and 0b1 = HMAC. */ if (config->oper_mode == HASH_OPER_MODE_HASH) { - HASH_CLEAR_BITS(&device_data->base->cr, - HASH_CR_MODE_MASK); + regmap_update_bits(device_data->map, UX500_HASH_CR, + HASH_CR_MODE, 0); } else if (config->oper_mode == HASH_OPER_MODE_HMAC) { - HASH_SET_BITS(&device_data->base->cr, HASH_CR_MODE_MASK); + regmap_update_bits(device_data->map, UX500_HASH_CR, + HASH_CR_MODE, HASH_CR_MODE); if (ctx->keylen > HASH_BLOCK_SIZE) { /* Truncate key to blocksize */ dev_dbg(device_data->dev, "%s: LKEY set\n", __func__); - HASH_SET_BITS(&device_data->base->cr, - HASH_CR_LKEY_MASK); + regmap_update_bits(device_data->map, UX500_HASH_CR, + HASH_CR_LKEY, HASH_CR_LKEY); } else { dev_dbg(device_data->dev, "%s: LKEY cleared\n", __func__); - HASH_CLEAR_BITS(&device_data->base->cr, - HASH_CR_LKEY_MASK); + regmap_update_bits(device_data->map, UX500_HASH_CR, + HASH_CR_LKEY, 0); } } else { /* Wrong hash mode */ ret = -EPERM; @@ -623,20 +607,21 @@ void hash_begin(struct hash_device_data *device_data, struct hash_ctx *ctx) /* HW and SW initializations */ /* Note: there is no need to initialize buffer and digest members */ - while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) - cpu_relax(); + hash_wait_for_dcal(device_data); /* * INIT bit. Set this bit to 0b1 to reset the HASH processor core and * prepare the initialize the HASH accelerator to compute the message * digest of a new message. */ - HASH_INITIALIZE; + regmap_update_bits(device_data->map, UX500_HASH_CR, + HASH_CR_INIT, HASH_CR_INIT); /* * NBLW bits. Reset the number of bits in last word (NBLW). */ - HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK); + regmap_update_bits(device_data->map, UX500_HASH_STR, + HASH_STR_NBLW_MASK, 0); } static int hash_process_data(struct hash_device_data *device_data, @@ -731,22 +716,24 @@ static int hash_dma_final(struct ahash_request *req) /* Enable DMA input */ if (hash_mode != HASH_MODE_DMA || !req_ctx->dma_mode) { - HASH_CLEAR_BITS(&device_data->base->cr, - HASH_CR_DMAE_MASK); + regmap_update_bits(device_data->map, UX500_HASH_CR, + HASH_CR_DMAE, 0); } else { - HASH_SET_BITS(&device_data->base->cr, - HASH_CR_DMAE_MASK); - HASH_SET_BITS(&device_data->base->cr, - HASH_CR_PRIVN_MASK); + regmap_update_bits(device_data->map, UX500_HASH_CR, + HASH_CR_DMAE | HASH_CR_PRIVN, + HASH_CR_DMAE | HASH_CR_PRIVN); } - HASH_INITIALIZE; + regmap_update_bits(device_data->map, UX500_HASH_CR, + HASH_CR_INIT, HASH_CR_INIT); if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC) hash_hw_write_key(device_data, ctx->key, ctx->keylen); /* Number of bits in last word = (nbytes * 8) % 32 */ - HASH_SET_NBLW((req->nbytes * 8) % 32); + regmap_update_bits(device_data->map, UX500_HASH_STR, + HASH_STR_NBLW_MASK, (req->nbytes * 8) % 32); + req_ctx->hw_initialized = true; } @@ -770,8 +757,7 @@ static int hash_dma_final(struct ahash_request *req) wait_for_completion(&ctx->device->dma.complete); hash_dma_done(ctx); - while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) - cpu_relax(); + hash_wait_for_dcal(device_data); if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) { unsigned int keylen = ctx->keylen; @@ -860,9 +846,9 @@ static int hash_hw_final(struct ahash_request *req) hash_messagepad(device_data, req_ctx->buffer, req_ctx->index); } else { - HASH_SET_DCAL; - while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) - cpu_relax(); + regmap_update_bits(device_data->map, UX500_HASH_STR, + HASH_STR_DCAL, HASH_STR_DCAL); + hash_wait_for_dcal(device_data); } if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) { @@ -951,20 +937,24 @@ int hash_hw_update(struct ahash_request *req) */ int hash_check_hw(struct hash_device_data *device_data) { - /* Checking Peripheral Ids */ - if (HASH_P_ID0 == readl_relaxed(&device_data->base->periphid0) && - HASH_P_ID1 == readl_relaxed(&device_data->base->periphid1) && - HASH_P_ID2 == readl_relaxed(&device_data->base->periphid2) && - HASH_P_ID3 == readl_relaxed(&device_data->base->periphid3) && - HASH_CELL_ID0 == readl_relaxed(&device_data->base->cellid0) && - HASH_CELL_ID1 == readl_relaxed(&device_data->base->cellid1) && - HASH_CELL_ID2 == readl_relaxed(&device_data->base->cellid2) && - HASH_CELL_ID3 == readl_relaxed(&device_data->base->cellid3)) { - return 0; + unsigned int regs[] = { UX500_HASH_PERIPHID0, UX500_HASH_PERIPHID1, + UX500_HASH_PERIPHID2, UX500_HASH_PERIPHID3, UX500_HASH_CELLID0, + UX500_HASH_CELLID1, UX500_HASH_CELLID2, UX500_HASH_CELLID3 }; + unsigned int expected[] = { HASH_P_ID0, HASH_P_ID1, HASH_P_ID2, HASH_P_ID3, + HASH_CELL_ID0, HASH_CELL_ID1, HASH_CELL_ID2, HASH_CELL_ID3 }; + unsigned int val; + int i; + + for (i = 0; i < ARRAY_SIZE(regs); i++) { + regmap_read(device_data->map, regs[i], &val); + if (val != expected[i]) { + dev_err(device_data->dev, "ID word %d was %08x expected %08x\n", + i, val, expected[i]); + return -ENODEV; + } } - dev_err(device_data->dev, "%s: HASH_UNSUPPORTED_HW!\n", __func__); - return -ENOTSUPP; + return 0; } /** @@ -976,7 +966,6 @@ int hash_check_hw(struct hash_device_data *device_data) void hash_get_digest(struct hash_device_data *device_data, u8 *digest, int algorithm) { - u32 temp_hx_val, count; int loop_ctr; if (algorithm != HASH_ALGO_SHA1 && algorithm != HASH_ALGO_SHA256) { @@ -993,14 +982,8 @@ void hash_get_digest(struct hash_device_data *device_data, dev_dbg(device_data->dev, "%s: digest array:(0x%lx)\n", __func__, (unsigned long)digest); - /* Copy result into digest array */ - for (count = 0; count < loop_ctr; count++) { - temp_hx_val = readl_relaxed(&device_data->base->hx[count]); - digest[count * 4] = (u8) ((temp_hx_val >> 24) & 0xFF); - digest[count * 4 + 1] = (u8) ((temp_hx_val >> 16) & 0xFF); - digest[count * 4 + 2] = (u8) ((temp_hx_val >> 8) & 0xFF); - digest[count * 4 + 3] = (u8) ((temp_hx_val >> 0) & 0xFF); - } + regmap_bulk_read(device_data->map, UX500_HASH_H(0), + digest, loop_ctr); } /** @@ -1071,7 +1054,7 @@ static int ahash_sha1_init(struct ahash_request *req) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct hash_ctx *ctx = crypto_ahash_ctx(tfm); - ctx->config.data_format = HASH_DATA_8_BITS; + ctx->config.data_format = HASH_CR_DATAFORM_8BIT; ctx->config.algorithm = HASH_ALGO_SHA1; ctx->config.oper_mode = HASH_OPER_MODE_HASH; ctx->digestsize = SHA1_DIGEST_SIZE; @@ -1084,7 +1067,7 @@ static int ahash_sha256_init(struct ahash_request *req) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct hash_ctx *ctx = crypto_ahash_ctx(tfm); - ctx->config.data_format = HASH_DATA_8_BITS; + ctx->config.data_format = HASH_CR_DATAFORM_8BIT; ctx->config.algorithm = HASH_ALGO_SHA256; ctx->config.oper_mode = HASH_OPER_MODE_HASH; ctx->digestsize = SHA256_DIGEST_SIZE; @@ -1129,9 +1112,8 @@ static int ahash_import(struct ahash_request *req, const void *in) struct hash_device_data *device_data = ctx->device; struct hash_req_ctx *req_ctx = ahash_request_ctx(req); const struct hash_state *hstate = in; - int hash_mode = HASH_OPER_MODE_HASH; + unsigned int val; u32 cr; - s32 count; /* Restore software state */ req_ctx->length = hstate->length; @@ -1146,27 +1128,24 @@ static int ahash_import(struct ahash_request *req, const void *in) * prepare the initialize the HASH accelerator to compute the message * digest of a new message. */ - HASH_INITIALIZE; + regmap_update_bits(device_data->map, UX500_HASH_CR, + HASH_CR_INIT, HASH_CR_INIT); cr = hstate->temp_cr; - writel_relaxed(cr & HASH_CR_RESUME_MASK, &device_data->base->cr); + regmap_write(device_data->map, UX500_HASH_CR, cr & HASH_CR_RESUME_MASK); - if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK) - hash_mode = HASH_OPER_MODE_HMAC; + regmap_read(device_data->map, UX500_HASH_CR, &val); + if (val & HASH_CR_MODE) + regmap_bulk_write(device_data->map, UX500_HASH_CSR(0), + hstate->csr, HASH_CSR_COUNT); else - hash_mode = HASH_OPER_MODE_HASH; - - for (count = 0; count < HASH_CSR_COUNT; count++) { - if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH)) - break; - writel_relaxed(hstate->csr[count], - &device_data->base->csrx[count]); - } + regmap_bulk_write(device_data->map, UX500_HASH_CSR(0), + hstate->csr, 36); - writel_relaxed(hstate->csfull, &device_data->base->csfull); - writel_relaxed(hstate->csdatain, &device_data->base->csdatain); - writel_relaxed(hstate->str_reg, &device_data->base->str); - writel_relaxed(cr, &device_data->base->cr); + regmap_write(device_data->map, UX500_HASH_CSFULL, hstate->csfull); + regmap_write(device_data->map, UX500_HASH_CSDATAIN, hstate->csdatain); + regmap_write(device_data->map, UX500_HASH_STR, hstate->str_reg); + regmap_write(device_data->map, UX500_HASH_CR, cr); return 0; } @@ -1178,9 +1157,7 @@ static int ahash_export(struct ahash_request *req, void *out) struct hash_device_data *device_data = ctx->device; struct hash_req_ctx *req_ctx = ahash_request_ctx(req); struct hash_state *hstate = out; - int hash_mode = HASH_OPER_MODE_HASH; u32 cr; - u32 count; /* * Save hardware state: @@ -1188,31 +1165,21 @@ static int ahash_export(struct ahash_request *req, void *out) * actually makes sure that there isn't any ongoing calculation in the * hardware. */ - while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK) - cpu_relax(); - - cr = readl_relaxed(&device_data->base->cr); + hash_wait_for_dcal(device_data); - hstate->str_reg = readl_relaxed(&device_data->base->str); + regmap_read(device_data->map, UX500_HASH_CR, &cr); + regmap_read(device_data->map, UX500_HASH_STR, &hstate->str_reg); + regmap_read(device_data->map, UX500_HASH_DIN, &hstate->din_reg); - hstate->din_reg = readl_relaxed(&device_data->base->din); - - if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK) - hash_mode = HASH_OPER_MODE_HMAC; + if (cr & HASH_CR_MODE) + regmap_bulk_read(device_data->map, UX500_HASH_CSR(0), + hstate->csr, HASH_CSR_COUNT); else - hash_mode = HASH_OPER_MODE_HASH; - - for (count = 0; count < HASH_CSR_COUNT; count++) { - if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH)) - break; - - hstate->csr[count] = - readl_relaxed(&device_data->base->csrx[count]); - } - - hstate->csfull = readl_relaxed(&device_data->base->csfull); - hstate->csdatain = readl_relaxed(&device_data->base->csdatain); + regmap_bulk_read(device_data->map, UX500_HASH_CSR(0), + hstate->csr, 36); + regmap_read(device_data->map, UX500_HASH_CSFULL, &hstate->csfull); + regmap_read(device_data->map, UX500_HASH_CSDATAIN, &hstate->csdatain); hstate->temp_cr = cr; /* Save software state */ @@ -1230,7 +1197,7 @@ static int hmac_sha1_init(struct ahash_request *req) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct hash_ctx *ctx = crypto_ahash_ctx(tfm); - ctx->config.data_format = HASH_DATA_8_BITS; + ctx->config.data_format = HASH_CR_DATAFORM_8BIT; ctx->config.algorithm = HASH_ALGO_SHA1; ctx->config.oper_mode = HASH_OPER_MODE_HMAC; ctx->digestsize = SHA1_DIGEST_SIZE; @@ -1243,7 +1210,7 @@ static int hmac_sha256_init(struct ahash_request *req) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct hash_ctx *ctx = crypto_ahash_ctx(tfm); - ctx->config.data_format = HASH_DATA_8_BITS; + ctx->config.data_format = HASH_CR_DATAFORM_8BIT; ctx->config.algorithm = HASH_ALGO_SHA256; ctx->config.oper_mode = HASH_OPER_MODE_HMAC; ctx->digestsize = SHA256_DIGEST_SIZE; @@ -1314,7 +1281,7 @@ static int hash_cra_init(struct crypto_tfm *tfm) crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), sizeof(struct hash_req_ctx)); - ctx->config.data_format = HASH_DATA_8_BITS; + ctx->config.data_format = HASH_CR_DATAFORM_8BIT; ctx->config.algorithm = hash_alg->conf.algorithm; ctx->config.oper_mode = hash_alg->conf.oper_mode; @@ -1451,6 +1418,88 @@ static void ahash_algs_unregister_all(struct hash_device_data *device_data) crypto_unregister_ahash(&hash_algs[i].hash); } +static bool ux500_hash_reg_readable(struct device *dev, unsigned int reg) +{ + switch (reg) { + case UX500_HASH_CR: + case UX500_HASH_DIN: + case UX500_HASH_STR: + case UX500_HASH_ITCR: + case UX500_HASH_ITIP: + case UX500_HASH_ITOP: + case UX500_HASH_CSFULL: + case UX500_HASH_CSDATAIN: + case UX500_HASH_CSR(0) ... UX500_HASH_CSR(51): + case UX500_HASH_PERIPHID0: + case UX500_HASH_PERIPHID1: + case UX500_HASH_PERIPHID2: + case UX500_HASH_PERIPHID3: + case UX500_HASH_CELLID0: + case UX500_HASH_CELLID1: + case UX500_HASH_CELLID2: + case UX500_HASH_CELLID3: + return true; + default: + return false; + } +} + +static bool ux500_hash_reg_writeable(struct device *dev, unsigned int reg) +{ + switch (reg) { + case UX500_HASH_CR: + case UX500_HASH_DIN: + case UX500_HASH_STR: + case UX500_HASH_ITCR: + case UX500_HASH_ITIP: + case UX500_HASH_ITOP: + case UX500_HASH_CSFULL: + case UX500_HASH_CSDATAIN: + case UX500_HASH_CSR(0) ... UX500_HASH_CSR(51): + return true; + default: + return false; + } +} + +static bool ux500_hash_reg_writeable_noinc(struct device *dev, unsigned int reg) +{ + if (reg == UX500_HASH_DIN) + return true; + return false; +} + +static bool ux500_hash_reg_volatile(struct device *dev, unsigned int reg) +{ + switch (reg) { + case UX500_HASH_CR: + case UX500_HASH_STR: + case UX500_HASH_ITCR: + case UX500_HASH_ITIP: + case UX500_HASH_ITOP: + case UX500_HASH_CSFULL: + case UX500_HASH_CSDATAIN: + case UX500_HASH_CSR(0) ... UX500_HASH_CSR(51): + return true; + default: + return false; + } +} + +static const struct regmap_config ux500_hash_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .cache_type = REGCACHE_FLAT, + .max_raw_write = 4, /* Pretty evident in 32bit MMIO */ + .max_register = 0xFFC, + .use_relaxed_mmio = true, + .readable_reg = ux500_hash_reg_readable, + .writeable_reg = ux500_hash_reg_writeable, + .volatile_reg = ux500_hash_reg_volatile, + .writeable_noinc_reg = ux500_hash_reg_writeable_noinc, +}; + /** * ux500_hash_probe - Function that probes the hash hardware. * @pdev: The platform device. @@ -1461,6 +1510,7 @@ static int ux500_hash_probe(struct platform_device *pdev) struct resource *res = NULL; struct hash_device_data *device_data; struct device *dev = &pdev->dev; + void __iomem *base; device_data = devm_kzalloc(dev, sizeof(*device_data), GFP_KERNEL); if (!device_data) { @@ -1479,9 +1529,15 @@ static int ux500_hash_probe(struct platform_device *pdev) } device_data->phybase = res->start; - device_data->base = devm_ioremap_resource(dev, res); - if (IS_ERR(device_data->base)) { - ret = PTR_ERR(device_data->base); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) { + ret = PTR_ERR(base); + goto out; + } + device_data->map = devm_regmap_init_mmio(dev, base, + &ux500_hash_regmap_config); + if (IS_ERR(device_data->map)) { + ret = PTR_ERR(device_data->map); goto out; } spin_lock_init(&device_data->ctx_lock); From patchwork Thu Jul 21 13:40:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 592193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61074C43334 for ; Thu, 21 Jul 2022 13:45:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230204AbiGUNpc (ORCPT ); Thu, 21 Jul 2022 09:45:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229790AbiGUNoM (ORCPT ); Thu, 21 Jul 2022 09:44:12 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E73A185D69 for ; Thu, 21 Jul 2022 06:43:14 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id z22so2851553lfu.7 for ; Thu, 21 Jul 2022 06:43:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zYS++DqZZJZ4dvIqRTXxDhDnXHSI1cMkpUczRGNZhnA=; b=wATY/y0gsIvlvzvPsDq1n4/lpqroSymoajpW4vR+wn2co0/W8I1suw9tXibwdimcuo ca5z1C1DcPlusxluSCmtikMk/tSjPTICw+mJStRSqtZiszLq2jEbpD9ha/m5Q10VOrXi 2+8IVHI0u2Ns6Iynmev1bBXBEmGha22C9CA/seWpUuV1hy4p7kbCP32FSf0OMPmMH0ku oVa4KdVmjzNdS4cRrIz5sfdWdXE1w9kL1XUKzbx+JeMUeIkNdJ1gXi2AtTSzPYQd+T4w X0Y1j6WZZNuBQP2eyEqpc4mcScpa765ys8V6msDwNy6Ut8LOUoNwYFX49jR/W0jRGVyH Va5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zYS++DqZZJZ4dvIqRTXxDhDnXHSI1cMkpUczRGNZhnA=; b=RjLDcsGt2Pp5d5CjZzfBPay/iu80BWnAsqKeNg0b+f99f5+Gmgy19swCmPNB4SaZlV 3HVku1MjVChZmw6P9SSP9zHWlQTDkY5Ycfefx5RdqL59IRR32lmUlBJ7MrDvobftlNpG K+LZezhbtbatriJcN3kCIBMOVdLiX0caaSPioHcoWzknUiCUStu4ky9PnBmUgYtTwGMQ I+H6ht7UfE6a/lKPJN8ocwdrdvRyriq2vaEMWfw+JJ7uv24zlgiYMAYIWpfHIpngD6yf wSXptQ+xgBwPf1iokTNlQ9T3MDGTqMagZleR2nhg4Yftv/cPdhYWKRR0mD5zBt+TNuu5 xezw== X-Gm-Message-State: AJIora/6KWNINJ13pbcn58xCtW2kxBXi5vRCFJxBGw73W9cGEzmEXIMJ QIH5zgGUPEd5/Vewde5srwOluRy5en/Bdg== X-Google-Smtp-Source: AGRyM1ut2DRnSzjd5OOJ/DKEf9PjPiI2zOgsiVkU+gNjEy+OfjyoBRa+Y634aqVFaQcmUrojQWDOog== X-Received: by 2002:ac2:435a:0:b0:48a:73bf:7371 with SMTP id o26-20020ac2435a000000b0048a73bf7371mr424493lfl.96.1658410993483; Thu, 21 Jul 2022 06:43:13 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:43:13 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 13/15] crypto: ux500/hash: Use AMBA core primecell IDs Date: Thu, 21 Jul 2022 15:40:48 +0200 Message-Id: <20220721134050.1047866-14-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Use the AMBA (PrimeCell) bus core define and read 32bit CID and PID from the peripheral, then check those. Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_alg.h | 11 ++--------- drivers/crypto/ux500/hash/hash_core.c | 27 +++++++++++++++++++-------- 2 files changed, 21 insertions(+), 17 deletions(-) diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h index cc44d3cb21ac..96c614444fa2 100644 --- a/drivers/crypto/ux500/hash/hash_alg.h +++ b/drivers/crypto/ux500/hash/hash_alg.h @@ -63,15 +63,8 @@ #define HASH_STR_NBLW_MASK 0x0000001FUL #define HASH_NBLW_MAX_VAL 0x1F -/* PrimeCell IDs */ -#define HASH_P_ID0 0xE0 -#define HASH_P_ID1 0x05 -#define HASH_P_ID2 0x38 -#define HASH_P_ID3 0x00 -#define HASH_CELL_ID0 0x0D -#define HASH_CELL_ID1 0xF0 -#define HASH_CELL_ID2 0x05 -#define HASH_CELL_ID3 0xB1 +/* PrimeCell ID */ +#define UX500_HASH_PID 0x003805E0U /* Hardware access method */ enum hash_mode { diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index 83833cbe595f..a64edfb1cd96 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -13,6 +13,7 @@ #define pr_fmt(fmt) "hashX hashX: " fmt +#include #include #include #include @@ -940,18 +941,28 @@ int hash_check_hw(struct hash_device_data *device_data) unsigned int regs[] = { UX500_HASH_PERIPHID0, UX500_HASH_PERIPHID1, UX500_HASH_PERIPHID2, UX500_HASH_PERIPHID3, UX500_HASH_CELLID0, UX500_HASH_CELLID1, UX500_HASH_CELLID2, UX500_HASH_CELLID3 }; - unsigned int expected[] = { HASH_P_ID0, HASH_P_ID1, HASH_P_ID2, HASH_P_ID3, - HASH_CELL_ID0, HASH_CELL_ID1, HASH_CELL_ID2, HASH_CELL_ID3 }; unsigned int val; + u32 pid; + u32 cid; int i; - for (i = 0; i < ARRAY_SIZE(regs); i++) { + for (pid = 0, i = 0; i < 8; i++) { regmap_read(device_data->map, regs[i], &val); - if (val != expected[i]) { - dev_err(device_data->dev, "ID word %d was %08x expected %08x\n", - i, val, expected[i]); - return -ENODEV; - } + if (i < 4) + pid |= (val & 255) << (i * 8); + else + cid |= (val & 255) << ((i - 4) * 8); + } + + if (cid != AMBA_CID) { + dev_err(device_data->dev, "AMBA CID was %08x expected %08x\n", + cid, AMBA_CID); + return -ENODEV; + } + if (pid != UX500_HASH_PID) { + dev_err(device_data->dev, "PID was %08x expected %08x\n", + pid, UX500_HASH_PID); + return -ENODEV; } return 0; From patchwork Thu Jul 21 13:40:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 592902 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33CB4CCA48B for ; Thu, 21 Jul 2022 13:45:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230024AbiGUNpg (ORCPT ); Thu, 21 Jul 2022 09:45:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229854AbiGUNou (ORCPT ); Thu, 21 Jul 2022 09:44:50 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D2FE85FB1 for ; Thu, 21 Jul 2022 06:43:18 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id r14so1879752ljp.2 for ; Thu, 21 Jul 2022 06:43:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sSiRCl2FNVjumNTyEm6j/Y4BLdUSiRyHccgJSZvX0p8=; b=xvYxWLfVPUki9oW3YSagPynzuhJ7u47byExdN/63UgQm1JRrj31prOliILDFlcFmXH VMUitC202IBMB1aR4QW4jQ40+Pul/3nBqTW61GkLbY9PRJqKufUfpkkf34+LFvomIHvu MqBK1sFZAC/6dX2voqV0S8c7Ebh0Yp3CxUbBHQrBqlO09VBb7q2hzH/YuHU9K+OPmjZN PBfzXGekbwCkgNRnJC2u3GtIDiocVQaH8AbzdBvN85Nn6oYhRuXNGo3nNTm8tfaLPOYu 3nmUgTJjT+bm532g0737pc50VScQ13xDpBuyArdSDf7M5RxlSHw+TeaEgZNPjdlOnurt K/0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sSiRCl2FNVjumNTyEm6j/Y4BLdUSiRyHccgJSZvX0p8=; b=L9NipS30ooOcmokFZdF9oK/R1PcNGhWeceAEfu1qlWHi/Z1cOBNyw4qEPBwR5PnSo9 hj+3LjufR8LK6biwRufsShFSKRPpKuIfT4QGyHrcx2NEwKwSRwrfHUO9eFczmt9qqgKO /+p4S1UWHTwf2On6jjxFUBKO3GHccpd8FBsrLHy0sbQeQRNG6xn/tNLMHC+owr1v+RvN t1bkJg9o0eFDCd6tf3eK33cUaJeAWpSk6Q4E0boizjtY9tb4JS/YqzrNl5kAQRLcUXYQ IIaJOPaaiJylzbMidjQeJrST7o9Jn2v4w/NbVH1FFlIjQI0ReWyFjmggLMGtVw61cxDF KZSg== X-Gm-Message-State: AJIora+Whp13f6PsKCrGWlYou+c9HAMgVn0Ycg/3m9hVZNfCscYDy29b uWoPExLdssfkFd0JLKpsCDx6hR3lDHq0MA== X-Google-Smtp-Source: AGRyM1tjA7s4ANm+gAQnbAcC5qyPURyYcaU0iD3nUCP985Rmqk9Q6D0zIvuqbCX0BEQwJDpxUDaSUA== X-Received: by 2002:a05:651c:2111:b0:25d:6b28:3c96 with SMTP id a17-20020a05651c211100b0025d6b283c96mr20078491ljq.39.1658410994695; Thu, 21 Jul 2022 06:43:14 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.43.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:43:14 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 14/15] crypto: ux500/hash: Implement runtime PM Date: Thu, 21 Jul 2022 15:40:49 +0200 Message-Id: <20220721134050.1047866-15-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org This implements runtime PM to gate the clock and regulator when the hash block is unused. Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_alg.h | 1 + drivers/crypto/ux500/hash/hash_core.c | 60 +++++++++++++++++++++++---- 2 files changed, 52 insertions(+), 9 deletions(-) diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h index 96c614444fa2..57e4c7df4ac4 100644 --- a/drivers/crypto/ux500/hash/hash_alg.h +++ b/drivers/crypto/ux500/hash/hash_alg.h @@ -16,6 +16,7 @@ #define HASH_DMA_ALIGN_SIZE 4 #define HASH_DMA_PERFORMANCE_MIN_SIZE 1024 #define HASH_BYTES_PER_WORD 4 +#define UX500_HASH_AUTOSUSPEND_DELAY_MS 50 /* Number of context swap registers */ #define HASH_CSR_COUNT 52 diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index a64edfb1cd96..55d27af8c9de 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -438,6 +439,10 @@ static int ux500_hash_init(struct ahash_request *req) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct hash_ctx *ctx = crypto_ahash_ctx(tfm); struct hash_req_ctx *req_ctx = ahash_request_ctx(req); + struct hash_device_data *device_data = ctx->device; + + /* Power up on init() power down on final() */ + pm_runtime_get_sync(device_data->dev); if (!ctx->key) ctx->keylen = 0; @@ -463,6 +468,7 @@ static int ux500_hash_init(struct ahash_request *req) } } } + return 0; } @@ -773,6 +779,8 @@ static int hash_dma_final(struct ahash_request *req) memcpy(req->result, digest, ctx->digestsize); out: + pm_runtime_mark_last_busy(device_data->dev); + pm_runtime_put_autosuspend(device_data->dev); /** * Allocated in setkey, and only used in HMAC. */ @@ -1023,8 +1031,11 @@ static int ahash_update(struct ahash_request *req) */ static int ahash_final(struct ahash_request *req) { - int ret = 0; + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); + struct hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct hash_device_data *device_data = ctx->device; struct hash_req_ctx *req_ctx = ahash_request_ctx(req); + int ret = 0; pr_debug("%s: data size: %d\n", __func__, req->nbytes); @@ -1033,6 +1044,9 @@ static int ahash_final(struct ahash_request *req) else ret = hash_hw_final(req); + pm_runtime_mark_last_busy(device_data->dev); + pm_runtime_put_autosuspend(device_data->dev); + if (ret) { pr_err("%s: hash_hw/dma_final() failed\n", __func__); } @@ -1133,6 +1147,9 @@ static int ahash_import(struct ahash_request *req, const void *in) req_ctx->hw_initialized = hstate->hw_initialized; memcpy(req_ctx->buffer, hstate->buffer, HASH_BLOCK_SIZE); + /* Power up as we may have lost power being exported */ + pm_runtime_get_sync(device_data->dev); + /* * Restore hardware state * INIT bit. Set this bit to 0b1 to reset the HASH processor core and @@ -1200,6 +1217,10 @@ static int ahash_export(struct ahash_request *req, void *out) hstate->hw_initialized = req_ctx->hw_initialized; memcpy(hstate->buffer, req_ctx->buffer, HASH_BLOCK_SIZE); + /* We can power down while exported */ + pm_runtime_mark_last_busy(device_data->dev); + pm_runtime_put_autosuspend(device_data->dev); + return 0; } @@ -1554,7 +1575,6 @@ static int ux500_hash_probe(struct platform_device *pdev) spin_lock_init(&device_data->ctx_lock); spin_lock_init(&device_data->power_state_lock); - /* Enable power for HASH1 hardware block */ device_data->regulator = regulator_get(dev, "v-ape"); if (IS_ERR(device_data->regulator)) { dev_err(dev, "%s: regulator_get() failed!\n", __func__); @@ -1563,7 +1583,6 @@ static int ux500_hash_probe(struct platform_device *pdev) goto out; } - /* Enable the clock for HASH1 hardware block */ device_data->clk = devm_clk_get(dev, NULL); if (IS_ERR(device_data->clk)) { dev_err(dev, "%s: clk_get() failed!\n", __func__); @@ -1590,6 +1609,12 @@ static int ux500_hash_probe(struct platform_device *pdev) goto out_power; } + pm_runtime_set_autosuspend_delay(dev, UX500_HASH_AUTOSUSPEND_DELAY_MS); + pm_runtime_use_autosuspend(dev); + pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + if (hash_mode == HASH_MODE_DMA) hash_dma_setup_channel(device_data, dev); @@ -1602,6 +1627,7 @@ static int ux500_hash_probe(struct platform_device *pdev) goto out_power; } + pm_runtime_put_sync(dev); dev_info(dev, "successfully registered\n"); return 0; @@ -1647,6 +1673,10 @@ static int ux500_hash_remove(struct platform_device *pdev) ahash_algs_unregister_all(device_data); + pm_runtime_get_sync(device_data->dev); + pm_runtime_put_noidle(device_data->dev); + pm_runtime_disable(device_data->dev); + if (hash_disable_power(device_data)) dev_err(dev, "%s: hash_disable_power() failed\n", __func__); @@ -1687,6 +1717,10 @@ static void ux500_hash_shutdown(struct platform_device *pdev) ahash_algs_unregister_all(device_data); + pm_runtime_get_sync(device_data->dev); + pm_runtime_put_noidle(device_data->dev); + pm_runtime_disable(device_data->dev); + if (hash_disable_power(device_data)) dev_err(&pdev->dev, "%s: hash_disable_power() failed\n", __func__); @@ -1694,10 +1728,10 @@ static void ux500_hash_shutdown(struct platform_device *pdev) #ifdef CONFIG_PM_SLEEP /** - * ux500_hash_suspend - Function that suspends the hash device. + * ux500_hash_runtime_suspend - Function that suspends the hash device. * @dev: Device to suspend. */ -static int ux500_hash_suspend(struct device *dev) +static int ux500_hash_runtime_suspend(struct device *dev) { int ret; struct hash_device_data *device_data; @@ -1712,14 +1746,15 @@ static int ux500_hash_suspend(struct device *dev) if (ret) dev_err(dev, "%s: hash_disable_power()\n", __func__); + dev_info(dev, "runtime suspended\n"); return ret; } /** - * ux500_hash_resume - Function that resume the hash device. + * ux500_hash_runtime_resume - Function that resume the hash device. * @dev: Device to resume. */ -static int ux500_hash_resume(struct device *dev) +static int ux500_hash_runtime_resume(struct device *dev) { int ret = 0; struct hash_device_data *device_data; @@ -1734,11 +1769,18 @@ static int ux500_hash_resume(struct device *dev) if (ret) dev_err(dev, "%s: hash_enable_power() failed!\n", __func__); + dev_info(dev, "runtime resumed\n"); + return ret; } #endif -static SIMPLE_DEV_PM_OPS(ux500_hash_pm, ux500_hash_suspend, ux500_hash_resume); +static const struct dev_pm_ops ux500_hash_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(ux500_hash_runtime_suspend, + ux500_hash_runtime_resume, NULL) +}; static const struct of_device_id ux500_hash_match[] = { { .compatible = "stericsson,ux500-hash" }, @@ -1753,7 +1795,7 @@ static struct platform_driver ux500_hash_driver = { .driver = { .name = "hash1", .of_match_table = ux500_hash_match, - .pm = &ux500_hash_pm, + .pm = &ux500_hash_pm_ops, } }; module_platform_driver(ux500_hash_driver); From patchwork Thu Jul 21 13:40:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 592901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FB90CCA479 for ; Thu, 21 Jul 2022 13:45:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230029AbiGUNpl (ORCPT ); Thu, 21 Jul 2022 09:45:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229591AbiGUNow (ORCPT ); Thu, 21 Jul 2022 09:44:52 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CD74863CE for ; Thu, 21 Jul 2022 06:43:19 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id u19so2928030lfs.0 for ; Thu, 21 Jul 2022 06:43:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jqVIpScoCCWkDYabFnlwaaN9YoNnkMmK49AqBQlpN38=; b=pwObx/GcQLid5/AwpUISVuaVTzteHWScJQUuM1WEjLsOkMMiz5TsxXhF85mQdwOvaX nr7CMIWIZKl2bC1SuFVblpMBnCom3gKIMCVfHlQ3re2Hj18Tis/QKuXG+hce3EP9sx4n 9y8RNtaZgJZvAa9QKl16XEMt8XXTQ5DzYiG15FsO0c89UQK8gEuLzy0nhCkYhj9vpScZ g9Ypm9Ao4X7LLNbUK8n0f8oQKcmMpgH6rDSGG3bWXDFcjVhLFDF5jmWCoaFPBFOQTrk8 5PvXeelLKuNOQWezzvFe9YMsq0WBtiCKOsz7E1RfVWaJcprSOEK4rZqqlf6GkhWLRWC5 fwjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jqVIpScoCCWkDYabFnlwaaN9YoNnkMmK49AqBQlpN38=; b=Gz91WicJbxJNSvPxKnXG0d9dJXigYsdcMzZvB6NbSoSl3ELBB2mMx1Jnj8hA+FE2Vd 8PT/YR/+ABOYVrRRR9Ab5anQ6CUcsEN+eNthtU4UVvfUY8cUQj5i8KMg4TDVC5BM/5NJ 8uiBYl3WaRM7YyT6mONc7PZCrLJ/BFJ7VdVI2S4Oycxysuig9qxM9QkthxfolzgEQ518 L/0zGNBe1Jq7Vr/mhr1V85FzxPNl2D3ptcABoORHYW14usBXICBpED5plTW1oI6+uPl6 TplHPJsLErZ4KwWK5NuSMiGtvK9dqHggAdvWsmNZXVLL8ezVaraQdB+Kl+YHf1qsJcnM j03g== X-Gm-Message-State: AJIora9K1px962FKqRA+tCjgDHgCnzjN378zY84udmRzJRJGDb2BLpoQ ouf9uT5pxNb6AsSgmlcsk6nMTkpEBX3XLQ== X-Google-Smtp-Source: AGRyM1vgzjJ0BItV7slTtOxAPzurr5dvcxKAOsX1nCxr/sj7eczTLe7+VgthdYOaNjtRyAVTn8MZng== X-Received: by 2002:a05:6512:3fa2:b0:48a:16df:266f with SMTP id x34-20020a0565123fa200b0048a16df266fmr18593242lfa.414.1658410995946; Thu, 21 Jul 2022 06:43:15 -0700 (PDT) Received: from localhost.localdomain (c-fdcc225c.014-348-6c756e10.bbcust.telenor.se. [92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.43.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:43:15 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 15/15] crypto: ux500/hash: Drop regulator handling Date: Thu, 21 Jul 2022 15:40:50 +0200 Message-Id: <20220721134050.1047866-16-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org This "APE" voltage is not handled by a regulator but by the power domain, drop it. Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_core.c | 35 +++------------------------ 1 file changed, 4 insertions(+), 31 deletions(-) diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index 55d27af8c9de..35bda646f49c 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -27,8 +27,6 @@ #include #include #include - -#include #include #include @@ -247,8 +245,7 @@ static int get_empty_message_digest( * hash_disable_power - Request to disable power and clock. * @device_data: Structure for the hash device. * - * This function request for disabling power (regulator) and clock, - * and could also save current hw state. + * This function request for disabling the clock. */ static int hash_disable_power(struct hash_device_data *device_data) { @@ -260,9 +257,6 @@ static int hash_disable_power(struct hash_device_data *device_data) goto out; clk_disable(device_data->clk); - ret = regulator_disable(device_data->regulator); - if (ret) - dev_err(dev, "%s: regulator_disable() failed!\n", __func__); device_data->power_state = false; @@ -276,8 +270,7 @@ static int hash_disable_power(struct hash_device_data *device_data) * hash_enable_power - Request to enable power and clock. * @device_data: Structure for the hash device. * - * This function request for enabling power (regulator) and clock, - * and could also restore a previously saved hw state. + * This function request for enabling the clock. */ static int hash_enable_power(struct hash_device_data *device_data) { @@ -286,17 +279,9 @@ static int hash_enable_power(struct hash_device_data *device_data) spin_lock(&device_data->power_state_lock); if (!device_data->power_state) { - ret = regulator_enable(device_data->regulator); - if (ret) { - dev_err(dev, "%s: regulator_enable() failed!\n", - __func__); - goto out; - } ret = clk_enable(device_data->clk); if (ret) { dev_err(dev, "%s: clk_enable() failed!\n", __func__); - ret = regulator_disable( - device_data->regulator); goto out; } device_data->power_state = true; @@ -1575,25 +1560,17 @@ static int ux500_hash_probe(struct platform_device *pdev) spin_lock_init(&device_data->ctx_lock); spin_lock_init(&device_data->power_state_lock); - device_data->regulator = regulator_get(dev, "v-ape"); - if (IS_ERR(device_data->regulator)) { - dev_err(dev, "%s: regulator_get() failed!\n", __func__); - ret = PTR_ERR(device_data->regulator); - device_data->regulator = NULL; - goto out; - } - device_data->clk = devm_clk_get(dev, NULL); if (IS_ERR(device_data->clk)) { dev_err(dev, "%s: clk_get() failed!\n", __func__); ret = PTR_ERR(device_data->clk); - goto out_regulator; + goto out; } ret = clk_prepare(device_data->clk); if (ret) { dev_err(dev, "%s: clk_prepare() failed!\n", __func__); - goto out_regulator; + goto out; } /* Enable device power (and clock) */ @@ -1637,9 +1614,6 @@ static int ux500_hash_probe(struct platform_device *pdev) out_clk_unprepare: clk_unprepare(device_data->clk); -out_regulator: - regulator_put(device_data->regulator); - out: return ret; } @@ -1682,7 +1656,6 @@ static int ux500_hash_remove(struct platform_device *pdev) __func__); clk_unprepare(device_data->clk); - regulator_put(device_data->regulator); return 0; }