From patchwork Wed Jul 20 13:06:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 591934 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E15BC43334 for ; Wed, 20 Jul 2022 13:06:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238398AbiGTNGQ (ORCPT ); Wed, 20 Jul 2022 09:06:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235179AbiGTNGP (ORCPT ); Wed, 20 Jul 2022 09:06:15 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C1265288A; Wed, 20 Jul 2022 06:06:13 -0700 (PDT) X-UUID: 55a089cfd7f5432780d34ea347874e36-20220720 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8, REQID:778fec47-90c9-46d5-b7d3-a5188c2d933f, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:90 X-CID-INFO: VERSION:1.1.8, REQID:778fec47-90c9-46d5-b7d3-a5188c2d933f, OB:0, LOB: 0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:90 X-CID-META: VersionHash:0f94e32, CLOUDID:8e9000d8-5d6d-4eaf-a635-828a3ee48b7c, C OID:6d3e904289c2,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 55a089cfd7f5432780d34ea347874e36-20220720 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 925497398; Wed, 20 Jul 2022 21:06:07 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 20 Jul 2022 21:06:06 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 20 Jul 2022 21:06:06 +0800 From: Allen-KH Cheng To: Rob Herring , Matthias Brugger , Krzysztof Kozlowski , CK Hu , Jitao shi CC: , , , , , , , , Allen-KH Cheng Subject: [PATCH v2 1/1] dt-bindings: display: mediatek: dpi: add power-domains property Date: Wed, 20 Jul 2022 21:06:04 +0800 Message-ID: <20220720130604.14113-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220720130604.14113-1-allen-kh.cheng@mediatek.com> References: <20220720130604.14113-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org DPI is part of the display / multimedia block in MediaTek SoCs and is managed using power controller in some platforms. We add the power-domains property to the binding documentation. Fixes:9273cf7d3942("dt-bindings: display: mediatek: convert the dpi bindings to yaml") Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring --- .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 5bb23e97cf33..9f012afdf19b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -58,6 +58,9 @@ properties: Output port node. This port should be connected to the input port of an attached HDMI, LVDS or DisplayPort encoder chip. + power-domains: + maxItems: 1 + required: - compatible - reg @@ -72,11 +75,13 @@ examples: - | #include #include + #include dpi0: dpi@1401d000 { compatible = "mediatek,mt8173-dpi"; reg = <0x1401d000 0x1000>; interrupts = ; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DPI_PIXEL>, <&mmsys CLK_MM_DPI_ENGINE>, <&apmixedsys CLK_APMIXED_TVDPLL>;