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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id y9sm32950302pfi.74.2019.01.25.15.45.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Jan 2019 15:45:36 -0800 (PST) From: Bjorn Andersson To: Michael Turquette , Stephen Boyd Cc: Andy Gross , Bjorn Helgaas , David Brown , Khasim Syed Mohammed , Kishon Vijay Abraham I , Lorenzo Pieralisi , Mark Rutland , Niklas Cassel , Rob Herring , Stanimir Varbanov , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 1/7] clk: gcc-qcs404: Add PCIe resets Date: Fri, 25 Jan 2019 15:45:03 -0800 Message-Id: <20190125234509.26419-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190125234509.26419-1-bjorn.andersson@linaro.org> References: <20190125234509.26419-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enabling PCIe requires several of the PCIe related resets from GCC, so add them all. Signed-off-by: Bjorn Andersson --- Stephen, I suggest that we merge this patch through Andy's devicetree branch, together with the DT patch in the end of this series. drivers/clk/qcom/gcc-qcs404.c | 7 +++++++ include/dt-bindings/clock/qcom,gcc-qcs404.h | 7 +++++++ 2 files changed, 14 insertions(+) -- 2.18.0 diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 64da032bb9ed..cfb8789ff706 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -2675,6 +2675,13 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = { [GCC_PCIE_0_PHY_BCR] = { 0x3e004 }, [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 }, [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c }, + [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = {0x3e040, 6}, + [GCC_PCIE_0_AHB_ARES] = {0x3e040, 5}, + [GCC_PCIE_0_AXI_SLAVE_ARES] = {0x3e040, 4}, + [GCC_PCIE_0_AXI_MASTER_ARES] = {0x3e040, 3}, + [GCC_PCIE_0_CORE_STICKY_ARES] = {0x3e040, 2}, + [GCC_PCIE_0_SLEEP_ARES] = {0x3e040, 1}, + [GCC_PCIE_0_PIPE_ARES] = {0x3e040, 0}, [GCC_EMAC_BCR] = { 0x4e000 }, }; diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h index 6ceb55ed72c6..00ab0d77b38a 100644 --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h @@ -161,5 +161,12 @@ #define GCC_PCIE_0_LINK_DOWN_BCR 11 #define GCC_PCIEPHY_0_PHY_BCR 12 #define GCC_EMAC_BCR 13 +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14 +#define GCC_PCIE_0_AHB_ARES 15 +#define GCC_PCIE_0_AXI_SLAVE_ARES 16 +#define GCC_PCIE_0_AXI_MASTER_ARES 17 +#define GCC_PCIE_0_CORE_STICKY_ARES 18 +#define GCC_PCIE_0_SLEEP_ARES 19 +#define GCC_PCIE_0_PIPE_ARES 20 #endif From patchwork Fri Jan 25 23:45:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 156656 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp938095jaa; Fri, 25 Jan 2019 15:45:42 -0800 (PST) X-Google-Smtp-Source: ALg8bN4OEaAajrS1EffRijWoOBpVMpduEnXz1Z1e4E9tFNFP6j3hFeK54el464iKOxcZ5l2tUjNy X-Received: by 2002:a63:d40a:: with SMTP id a10mr11631023pgh.394.1548459942195; Fri, 25 Jan 2019 15:45:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548459942; cv=none; d=google.com; s=arc-20160816; b=naNbTCT2Dlsw9dDQ+5dF15TQa4vVS1gV7joGgLHij/FDZV3oNydUbVvgIi907DkgL0 2OhCU59cKbtZ6iPuGZhUFa51uxbFzlDazQKn3HETeSfzcAlFBFzm2op/zGaN+Reg0IL4 xIx6DTezLl7F6vn2k6s31zhryXWtlGr0aj3zz2GwchDAJPqJbDEGRgnPepYT5akw1CtM Wwy44DV7fphg/zrDjiM1SrqF4PO4wx31GUpZXdmaNS8WaLo5IPm8Dnj0AMjqcBnyI/lp 1HQePB4V4TqZ2tXSketp3Y02vcddDlJKCteNdrAtLb3kgioSMy5mmyBswTGUaOe4m4fm mwvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=uK46UagMeCc0KFc0YPlTS4qrXQgdBZIe1DAGlyy2xmU=; b=I29wNg27rYyQD2LwWmkqp+SBLoLzUvIgtfIE8UfdBkXMSgjYmDmIvutMb4ntQnNBUF TXOiHOlUJdrsngwq9y4QMaJwORI+i32G8VrZV6tUQkmeuB3j4M4Ic4mAkBnm6O6b3zR7 P7G2fwG4HzMq9PMiNMdznf4Kns3l85R2ZhJU14TSdEEv4wyh+fhlNXsBn6MpWGzyjVKo cThqDH0FpLmWHercInx0qCV5Mxr9KO6/FZ/mcVDOZxfFTBu989Efk3EpDyP1/EKuB7rO bKRzgDZQtQWh4SKZg8hL7artCaxjcL7PC4UWxsDSgMZRdiJFkejWOnfPWlfpwo44DhwU qLSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PVTbFBab; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id y9sm32950302pfi.74.2019.01.25.15.45.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Jan 2019 15:45:37 -0800 (PST) From: Bjorn Andersson To: Kishon Vijay Abraham I , Mark Rutland , Rob Herring Cc: Andy Gross , Bjorn Helgaas , David Brown , Khasim Syed Mohammed , Lorenzo Pieralisi , Michael Turquette , Niklas Cassel , Stanimir Varbanov , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 2/7] dt-bindings: phy: Add binding for Qualcomm PCIe2 PHY Date: Fri, 25 Jan 2019 15:45:04 -0800 Message-Id: <20190125234509.26419-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190125234509.26419-1-bjorn.andersson@linaro.org> References: <20190125234509.26419-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Qualcomm PCIe2 PHY is a Synopsys based PCIe PHY found in a number of Qualcomm platforms, add a binding to describe this. Signed-off-by: Bjorn Andersson --- .../bindings/phy/qcom-pcie2-phy.txt | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt -- 2.18.0 diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt new file mode 100644 index 000000000000..7da02f9d78c7 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt @@ -0,0 +1,40 @@ +Qualcomm PCIe2 PHY controller +============================= + +The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm +platforms. + +Required properties: + - compatible: compatible list, should be: + "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy" + + - reg: offset and length of the PHY register set. + - #phy-cells: must be 0. + + - clocks: a clock-specifier pair for the "pipe" clock + + - vdda-vp-supply: phandle to low voltage regulator + - vdda-vph-supply: phandle to high voltage regulator + + - resets: reset-specifier pairs for the "phy" and "pipe" resets + - reset-names: list of resets, should contain: + "phy" and "pipe" + + - clock-output-names: name of the outgoing clock signal from the PHY PLL + +Example: + phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc GCC_PCIE_0_PIPE_ARES>; + reset-names = "phy", "pipe"; + + vdda-vp-supply = <&vreg_l3_1p05>; + vdda-vph-supply = <&vreg_l5_1p8>; + + clock-output-names = "pcie_0_pipe_clk"; + #phy-cells = <0>; + }; From patchwork Fri Jan 25 23:45:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 156658 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp938164jaa; Fri, 25 Jan 2019 15:45:46 -0800 (PST) X-Google-Smtp-Source: ALg8bN4yJVFLTgwfEYwFOwiAd4G9gBOeo14P2qYKFA84+LyMYAtM0vrf6pnS3RcXt4ioeGvzmnIq X-Received: by 2002:a62:26c7:: with SMTP id m190mr13168765pfm.79.1548459946893; Fri, 25 Jan 2019 15:45:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548459946; cv=none; d=google.com; s=arc-20160816; b=FGjrsyHfYtI68EOLbOJg0I6KgMpR0oizZd1qhsemvWvSKEWtPa3100ncaNgY+5pcgm UMcWRjcewquobCu9HqYTyhVinrCHoev0Y6XPhMxEqp51en/iLnwFrWAQldx2ZZMYo82L zq3G9DT4vTJi44EiGRfU0MyLSXDeKItBC5jf3muIsOtb8X7uVQBo05wSfoEATZk2uCMT v3R5ANKMK+Iw11SQDykg0E79xYg34KhbLr3pE4rvHsyvmM/fId2BD4INUqWptHuTgrEI 8yfuUVk1QhV/KF00duRICCdTFR9P5WTyJyQCXeMX5fuRgSpOXVM27U3TMxuwpdsmh0KF n1mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=YIBGhshphmqGmFPFNQUnKC9COYnakAlugF3+NXMGOm8=; b=PNYVxEm2ZH+kerpTTCwpqag29GiEXxd3tepJZ8e/TBrcSNcLfN6oOjXhpXKdAn4glj MORoiSaFdbyu2O9BSK4WJVMZtVgv+UziXCiCfuI2En30ubtCabTC05EtarKh89NsG7rp KY188+Hx0aUg8tiUnmrq2ERHq8Mfk/K7qGnqGZS65ZQ6uJd8EVs09o204m1Bx0z66iAv VubAiyrrzbxLK60+Bcc3sim9l4ehkNuxBzlupGNAyzDKquizZ8GrAMkLFp40QU3gWlem O7N/K1RcJ2HXlVezi4GPEKg0GeKuCt0blJsV5/VfLZLb1qvI4XS4GkwxyGKzt5elKXfx HgLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QAuLQIak; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id y9sm32950302pfi.74.2019.01.25.15.45.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Jan 2019 15:45:39 -0800 (PST) From: Bjorn Andersson To: Kishon Vijay Abraham I Cc: Andy Gross , Bjorn Helgaas , David Brown , Khasim Syed Mohammed , Lorenzo Pieralisi , Mark Rutland , Michael Turquette , Niklas Cassel , Rob Herring , Stanimir Varbanov , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 3/7] phy: qcom: Add Qualcomm PCIe2 PHY driver Date: Fri, 25 Jan 2019 15:45:05 -0800 Message-Id: <20190125234509.26419-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190125234509.26419-1-bjorn.andersson@linaro.org> References: <20190125234509.26419-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Qualcomm PCIe2 PHY is based on design from Synopsys and found in several different platforms where the QMP PHY isn't used. Signed-off-by: Bjorn Andersson --- drivers/phy/qualcomm/Kconfig | 8 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-pcie2.c | 331 ++++++++++++++++++++++++++ 3 files changed, 340 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-pcie2.c -- 2.18.0 diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 32f7d34eb784..0edb5316972f 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -24,6 +24,14 @@ config PHY_QCOM_IPQ806X_SATA depends on OF select GENERIC_PHY +config PHY_QCOM_PCIE2 + tristate "Qualcomm PCIe PHY Driver" + depends on OF && COMMON_CLK && (ARCH_QCOM || COMPILE_TEST) + select GENERIC_PHY + help + Enable this to support the Qualcomm PCIe PHY, used with the Synopsys + based PCIe controller. + config PHY_QCOM_QMP tristate "Qualcomm QMP PHY Driver" depends on OF && COMMON_CLK && (ARCH_QCOM || COMPILE_TEST) diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index c56efd3af205..283251d6a5d9 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o +obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o diff --git a/drivers/phy/qualcomm/phy-qcom-pcie2.c b/drivers/phy/qualcomm/phy-qcom-pcie2.c new file mode 100644 index 000000000000..2fa891c18b6f --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-pcie2.c @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. + * Copyright (c) 2019, Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define PCIE20_PARF_PHY_STTS 0x3c +#define PCIE2_PHY_RESET_CTRL 0x44 +#define PCIE20_PARF_PHY_REFCLK_CTRL2 0xa0 +#define PCIE20_PARF_PHY_REFCLK_CTRL3 0xa4 +#define PCIE20_PARF_PCS_SWING_CTRL1 0x88 +#define PCIE20_PARF_PCS_SWING_CTRL2 0x8c +#define PCIE20_PARF_PCS_DEEMPH1 0x74 +#define PCIE20_PARF_PCS_DEEMPH2 0x78 +#define PCIE20_PARF_PCS_DEEMPH3 0x7c +#define PCIE20_PARF_CONFIGBITS 0x84 +#define PCIE20_PARF_PHY_CTRL3 0x94 +#define PCIE20_PARF_PCS_CTRL 0x80 + +#define TX_AMP_VAL 120 +#define PHY_RX0_EQ_GEN1_VAL 0 +#define PHY_RX0_EQ_GEN2_VAL 4 +#define TX_DEEMPH_GEN1_VAL 24 +#define TX_DEEMPH_GEN2_3_5DB_VAL 26 +#define TX_DEEMPH_GEN2_6DB_VAL 36 +#define PHY_TX0_TERM_OFFST_VAL 0 + +struct qcom_phy { + struct device *dev; + void __iomem *base; + + struct regulator_bulk_data vregs[2]; + + struct reset_control *phy_reset; + struct reset_control *pipe_reset; + struct clk *pipe_clk; +}; + +static int qcom_pcie2_phy_init(struct phy *phy) +{ + struct qcom_phy *qphy = phy_get_drvdata(phy); + int ret; + + ret = reset_control_deassert(qphy->phy_reset); + if (ret) { + dev_err(qphy->dev, "cannot deassert pipe reset\n"); + return ret; + } + + ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); + if (ret) + reset_control_assert(qphy->phy_reset); + + return ret; +} + +static int qcom_pcie2_phy_power_on(struct phy *phy) +{ + struct qcom_phy *qphy = phy_get_drvdata(phy); + int ret; + u32 val; + + /* Program REF_CLK source */ + val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); + val &= ~BIT(1); + writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); + + usleep_range(1000, 2000); + + /* Don't use PAD for refclock */ + val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); + val &= ~BIT(0); + writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2); + + /* Program SSP ENABLE */ + val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3); + val |= BIT(0); + writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3); + + usleep_range(1000, 2000); + + /* Assert Phy SW Reset */ + val = readl(qphy->base + PCIE2_PHY_RESET_CTRL); + val |= BIT(0); + writel(val, qphy->base + PCIE2_PHY_RESET_CTRL); + + /* Program Tx Amplitude */ + val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL1); + val &= ~0x7f; + val |= TX_AMP_VAL; + writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL1); + + val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL2); + val &= ~0x7f; + val |= TX_AMP_VAL; + writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL2); + + /* Program De-Emphasis */ + val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH1); + val &= ~0x3f; + val |= TX_DEEMPH_GEN2_6DB_VAL; + writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH1); + + val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH2); + val &= ~0x3f; + val |= TX_DEEMPH_GEN2_3_5DB_VAL; + writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH2); + + val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH3); + val &= ~0x3f; + val |= TX_DEEMPH_GEN1_VAL; + writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH3); + + /* Program Rx_Eq */ + val = readl(qphy->base + PCIE20_PARF_CONFIGBITS); + val &= ~0x7; + val |= PHY_RX0_EQ_GEN2_VAL; + writel(val, qphy->base + PCIE20_PARF_CONFIGBITS); + + /* Program Tx0_term_offset */ + val = readl(qphy->base + PCIE20_PARF_PHY_CTRL3); + val &= ~0x1f; + val |= PHY_TX0_TERM_OFFST_VAL; + writel(val, qphy->base + PCIE20_PARF_PHY_CTRL3); + + /* disable Tx2Rx Loopback */ + val = readl(qphy->base + PCIE20_PARF_PCS_CTRL); + val &= ~BIT(1); + writel(val, qphy->base + PCIE20_PARF_PCS_CTRL); + + /* De-assert Phy SW Reset */ + val = readl(qphy->base + PCIE2_PHY_RESET_CTRL); + val &= ~BIT(0); + writel(val, qphy->base + PCIE2_PHY_RESET_CTRL); + + usleep_range(1000, 2000); + + ret = reset_control_deassert(qphy->pipe_reset); + if (ret) { + dev_err(qphy->dev, "cannot deassert pipe reset\n"); + goto out; + } + + clk_set_rate(qphy->pipe_clk, 250000000); + + ret = clk_prepare_enable(qphy->pipe_clk); + if (ret) { + dev_err(qphy->dev, "failed to enable pipe clock\n"); + goto out; + } + + ret = readl_poll_timeout(qphy->base + PCIE20_PARF_PHY_STTS, val, + !(val & BIT(0)), 1000, 10); + if (ret) + dev_err(qphy->dev, "phy initialization failed\n"); + +out: + return ret; +} + +static int qcom_pcie2_phy_power_off(struct phy *phy) +{ + struct qcom_phy *qphy = phy_get_drvdata(phy); + u32 val; + + val = readl(qphy->base + PCIE2_PHY_RESET_CTRL); + val |= BIT(0); + writel(val, qphy->base + PCIE2_PHY_RESET_CTRL); + + clk_disable_unprepare(qphy->pipe_clk); + reset_control_assert(qphy->pipe_reset); + + return 0; +} + +static int qcom_pcie2_phy_exit(struct phy *phy) +{ + struct qcom_phy *qphy = phy_get_drvdata(phy); + + regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); + reset_control_assert(qphy->phy_reset); + + return 0; +} + +static const struct phy_ops qcom_pcie2_ops = { + .init = qcom_pcie2_phy_init, + .power_on = qcom_pcie2_phy_power_on, + .power_off = qcom_pcie2_phy_power_off, + .exit = qcom_pcie2_phy_exit, + .owner = THIS_MODULE, +}; + +/* + * Register a fixed rate pipe clock. + * + * The _pipe_clksrc generated by PHY goes to the GCC that gate + * controls it. The _pipe_clk coming out of the GCC is requested + * by the PHY driver for its operations. + * We register the _pipe_clksrc here. The gcc driver takes care + * of assigning this _pipe_clksrc as parent to _pipe_clk. + * Below picture shows this relationship. + * + * +---------------+ + * | PHY block |<<---------------------------------------+ + * | | | + * | +-------+ | +-----+ | + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ + * clk | +-------+ | +-----+ + * +---------------+ + */ +static int phy_pipe_clk_register(struct qcom_phy *qphy) +{ + struct device_node *np = qphy->dev->of_node; + struct clk_fixed_rate *fixed; + struct clk_init_data init = { }; + int ret; + + ret = of_property_read_string(np, "clock-output-names", &init.name); + if (ret) { + dev_err(qphy->dev, "%s: No clock-output-names\n", np->name); + return ret; + } + + fixed = devm_kzalloc(qphy->dev, sizeof(*fixed), GFP_KERNEL); + if (!fixed) + return -ENOMEM; + + init.ops = &clk_fixed_rate_ops; + + /* controllers using QMP phys use 250MHz pipe clock interface */ + fixed->fixed_rate = 250000000; + fixed->hw.init = &init; + + return devm_clk_hw_register(qphy->dev, &fixed->hw); +} + +static int qcom_pcie2_phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct qcom_phy *qphy; + struct resource *res; + struct device *dev = &pdev->dev; + struct phy *phy; + int ret; + + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); + if (!qphy) + return -ENOMEM; + + qphy->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + qphy->base = devm_ioremap_resource(dev, res); + if (IS_ERR(qphy->base)) + return PTR_ERR(qphy->base); + + ret = phy_pipe_clk_register(qphy); + if (ret) { + dev_err(dev, "failed to register pipe_clk\n"); + return ret; + } + + qphy->vregs[0].supply = "vdda-vp"; + qphy->vregs[1].supply = "vdda-vph"; + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(qphy->vregs), qphy->vregs); + if (ret < 0) + return ret; + + qphy->pipe_clk = devm_clk_get(dev, NULL); + if (IS_ERR(qphy->pipe_clk)) { + dev_err(dev, "failed to acquire pipe clock\n"); + return PTR_ERR(qphy->pipe_clk); + } + + qphy->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); + if (IS_ERR(qphy->phy_reset)) { + dev_err(dev, "failed to acquire phy reset\n"); + return PTR_ERR(qphy->phy_reset); + } + + qphy->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe"); + if (IS_ERR(qphy->pipe_reset)) { + dev_err(dev, "failed to acquire pipe reset\n"); + return PTR_ERR(qphy->pipe_reset); + } + + phy = devm_phy_create(dev, dev->of_node, &qcom_pcie2_ops); + if (IS_ERR(phy)) { + dev_err(dev, "failed to create phy\n"); + return PTR_ERR(phy); + } + + phy_set_drvdata(phy, qphy); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(phy_provider)) + dev_err(dev, "failed to register phy provider\n"); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id qcom_pcie2_phy_match_table[] = { + { .compatible = "qcom,pcie2-phy" }, + {} +}; +MODULE_DEVICE_TABLE(of, qcom_pcie2_phy_match_table); + +static struct platform_driver qcom_pcie2_phy_driver = { + .probe = qcom_pcie2_phy_probe, + .driver = { + .name = "qcom-pcie2-phy", + .of_match_table = qcom_pcie2_phy_match_table, + }, +}; + +module_platform_driver(qcom_pcie2_phy_driver); + +MODULE_DESCRIPTION("Qualcomm PCIe PHY driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Jan 25 23:45:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 156659 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp938268jaa; Fri, 25 Jan 2019 15:45:53 -0800 (PST) X-Google-Smtp-Source: ALg8bN6xhqExF/+MThq4sYVQbdQyHpNQ8szxVSIjSqlrld163RTEYYofhKIUylf3F2lBKQuOhwDY X-Received: by 2002:a17:902:6b87:: with SMTP id p7mr13250153plk.282.1548459953264; Fri, 25 Jan 2019 15:45:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548459953; cv=none; d=google.com; s=arc-20160816; b=Mkf8oUTlzi6VmxTdeID2OSlhU9fLGIy/aET4mNEGE9pZX8PH96D0Glp8J8t8Z4SncK ZwBhUjetHZ3HfZoc2v875l4ti32zNe/wvndVPVB+tzTPAQVPPkKGdyaiVPJ+AThtbI6F YUe/4glUyKphSh8r3NHRcgXw7EhZBcWCBPhuS6qI8oq6k8lEVHOZptjjN1mBlO3Q6hb/ 7zuX3SlUs65yUZAgMXvtpke3J/NmqxRzo+OyYikyqqcenIw6TJ/0jH8OT6QTNcrjPjOk xrCzNaAS+L3vLWOHyBH+TPkx5qdh1P13XYlqzc8gUQocAT7a4S82sb3wssjYNUvIDq7y DF9g== ARC-Message-Signature: i=1; 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id y9sm32950302pfi.74.2019.01.25.15.45.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Jan 2019 15:45:46 -0800 (PST) From: Bjorn Andersson To: Andy Gross Cc: Bjorn Helgaas , David Brown , Khasim Syed Mohammed , Kishon Vijay Abraham I , Lorenzo Pieralisi , Mark Rutland , Michael Turquette , Niklas Cassel , Rob Herring , Stanimir Varbanov , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: qcom: qcs404: Add PCIe related nodes Date: Fri, 25 Jan 2019 15:45:09 -0800 Message-Id: <20190125234509.26419-8-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190125234509.26419-1-bjorn.andersson@linaro.org> References: <20190125234509.26419-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, add these to the platform dtsi and enable them for the EVB with the perst gpio and analog supplies defined. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 25 +++++++++ arch/arm64/boot/dts/qcom/qcs404.dtsi | 67 ++++++++++++++++++++++++ 2 files changed, 92 insertions(+) -- 2.18.0 diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 50b3589c7f15..579ddaf4f5fa 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -21,6 +21,22 @@ }; }; +&pcie { + status = "ok"; + + perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&perst_state>; +}; + +&pcie_phy { + status = "ok"; + + vdda-vp-supply = <&vreg_l3_1p05>; + vdda-vph-supply = <&vreg_l5_1p8>; +}; + &remoteproc_adsp { status = "ok"; }; @@ -137,6 +153,15 @@ }; &tlmm { + perst_state: perst { + pins = "gpio43"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + output-low; + }; + sdc1_on: sdc1-on { clk { pins = "sdc1_clk"; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 76699435c8bd..7b219865ba7e 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -3,6 +3,7 @@ #include #include +#include / { interrupt-parent = <&intc>; @@ -377,6 +378,7 @@ compatible = "qcom,gcc-qcs404"; reg = <0x01800000 0x80000>; #clock-cells = <1>; + #reset-cells = <1>; assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; @@ -405,6 +407,21 @@ #interrupt-cells = <4>; }; + pcie_phy: phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc GCC_PCIE_0_PIPE_ARES>; + reset-names = "phy", "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #phy-cells = <0>; + + status = "disabled"; + }; + sdcc1: sdcc@7804000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x7805000 0x1000>; @@ -771,6 +788,56 @@ status = "disabled"; }; }; + + pcie: pci@10000000 { + compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; + reg = <0x10000000 0xf1d + 0x10000f20 0xa8 + 0x07780000 0x2000 + 0x10001000 0x2000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x81000000 0 0 0x10003000 0 0x00010000 /* I/O */ + 0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>; + clock-names = "iface", "aux", "master_bus", "slave_bus"; + + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_AHB_ARES>; + reset-names = "axi_m", + "axi_s", + "axi_m_sticky", + "pipe_sticky", + "pwr", + "ahb"; + + phys = <&pcie_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; }; timer {