From patchwork Thu Jul 14 10:03:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 590435 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F25BCCA482 for ; Thu, 14 Jul 2022 10:03:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237452AbiGNKD6 (ORCPT ); Thu, 14 Jul 2022 06:03:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237636AbiGNKD4 (ORCPT ); Thu, 14 Jul 2022 06:03:56 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5483E2DD9 for ; Thu, 14 Jul 2022 03:03:55 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id r9so1944283lfp.10 for ; Thu, 14 Jul 2022 03:03:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WtGXMZeQ1/E9YVNo9kt0RDpVQ/UMPDWOUEtZUMYvREM=; b=ur1fHf53L/VK6/p1uxz8CdbnajFUATp9dy1USmYBHhlezIMaXowPBJYM6E14tIPCcG uSOJMN7FGQdw8TlZMAMPpbiJg8FRhIJG+QOF3Q+6clhjAJgvx6Y+sl5uKMnJ8Gjdko/1 bds0rSADuDMu0WaMGvETRvSJ953KXusi4HB5H5DWlpGD1nvylDJm++EHPQXzjtRNAVfg TLQ1C/q9vLH626GNiyXnvNfVftpOdkI3FVsdrMAxCuTHWJdFN5UpYl+pvg44niyc9B6Q ZlOfMNcIAHOXl960c94zVv5rCcTDa8gNJYnqQyVpPqiGBliAVRwoeUVZEH9rMRRMcoDA wceQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WtGXMZeQ1/E9YVNo9kt0RDpVQ/UMPDWOUEtZUMYvREM=; b=Gq0BY1o7fyTlFYOGMlDEO0wUJOCo/V9jdMAgO3dBpNW3lWsP5Lh7h5H0h7qErCVdH0 EIX56CRVWuDDIxkpeFaygZjALvX4KaPJobt91QqQvufX3AGEkTZRw4/q/cGcQUgLfQ3m DnJbJ80f9wYIaQVcgyuacuWUo4OoD7ebLUoqOPyOc2cQwu0BRz0fveIxKmnfWMfaQJYc EKWK1gQdMMsccAPsMgtZQ2wRVoRp/ejslnUNtjTBhyUivri2NPTcQDE1cEfMnonnN+85 o73ZuofoOK53qWcrGp95MucGSmfeo+JqIdplEDUCzJLSPDmQL9F4aUGNLtwSFXmdZXD3 N7gg== X-Gm-Message-State: AJIora8OYFhZ3itbBTf0NEOJ7/bsiivRukbqPqUxEVFyCobskVIpzT0x 5HU0MtAP2extzq5hETAYZlK8ImkVmzu6NQ== X-Google-Smtp-Source: AGRyM1tQsov6jq1AQpedk7p9vnY/OmyxCp39xokGY0eLArLiBx4ZW1Hr2b4L5JCoCW+y149By92eqg== X-Received: by 2002:a05:6512:e83:b0:489:c6fe:e121 with SMTP id bi3-20020a0565120e8300b00489c6fee121mr4647150lfb.100.1657793033674; Thu, 14 Jul 2022 03:03:53 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id c9-20020a056512074900b00489c92779f8sm273355lfs.184.2022.07.14.03.03.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 03:03:53 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Yassine Oudjana , Yassine Oudjana Subject: [PATCH 1/6] clk: qcom: msm8996-cpu: Use parent_data/_hws for all clocks Date: Thu, 14 Jul 2022 13:03:46 +0300 Message-Id: <20220714100351.1834711-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220714100351.1834711-1-dmitry.baryshkov@linaro.org> References: <20220714100351.1834711-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Yassine Oudjana Replace parent_names in PLLs, secondary muxes and primary muxes with parent_data. For primary muxes there were never any *cl_pll_acd clocks, so instead of adding them, put the primary PLLs in both PLL_INDEX and ACD_INDEX, then make sure ACD_INDEX is always picked over PLL_INDEX when setting parent since we always want ACD when using the primary PLLs. Signed-off-by: Yassine Oudjana [DB: switch to parent_hws for pmux clocks] Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-cpu-8996.c | 79 ++++++++++++++++++++------------- 1 file changed, 47 insertions(+), 32 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index b3ad9245874d..708a8ad0c933 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -112,14 +112,18 @@ static const struct alpha_pll_config hfpll_config = { .early_output_mask = BIT(3), }; +static const struct clk_parent_data pll_parent[] = { + { .fw_name = "xo" }, +}; + static struct clk_alpha_pll pwrcl_pll = { .offset = PWRCL_REG_OFFSET, .regs = prim_pll_regs, .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "pwrcl_pll", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, + .parent_data = pll_parent, + .num_parents = ARRAY_SIZE(pll_parent), .ops = &clk_alpha_pll_huayra_ops, }, }; @@ -130,8 +134,8 @@ static struct clk_alpha_pll perfcl_pll = { .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "perfcl_pll", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, + .parent_data = pll_parent, + .num_parents = ARRAY_SIZE(pll_parent), .ops = &clk_alpha_pll_huayra_ops, }, }; @@ -190,8 +194,8 @@ static struct clk_alpha_pll pwrcl_alt_pll = { .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_alt_pll", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, + .parent_data = pll_parent, + .num_parents = ARRAY_SIZE(pll_parent), .ops = &clk_alpha_pll_hwfsm_ops, }, }; @@ -204,8 +208,8 @@ static struct clk_alpha_pll perfcl_alt_pll = { .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_alt_pll", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, + .parent_data = pll_parent, + .num_parents = ARRAY_SIZE(pll_parent), .ops = &clk_alpha_pll_hwfsm_ops, }, }; @@ -252,6 +256,9 @@ static int clk_cpu_8996_pmux_set_parent(struct clk_hw *hw, u8 index) u32 val; val = index; + /* We always want ACD when using the primary PLL */ + if (val == PLL_INDEX) + val = ACD_INDEX; val <<= cpuclk->shift; return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val); @@ -282,17 +289,24 @@ static const struct clk_ops clk_cpu_8996_pmux_ops = { .determine_rate = clk_cpu_8996_pmux_determine_rate, }; +static const struct clk_parent_data pwrcl_smux_parents[] = { + { .fw_name = "xo" }, + { .hw = &pwrcl_pll_postdiv.hw }, +}; + +static const struct clk_parent_data perfcl_smux_parents[] = { + { .fw_name = "xo" }, + { .hw = &perfcl_pll_postdiv.hw }, +}; + static struct clk_regmap_mux pwrcl_smux = { .reg = PWRCL_REG_OFFSET + MUX_OFFSET, .shift = 2, .width = 2, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_smux", - .parent_names = (const char *[]){ - "xo", - "pwrcl_pll_postdiv", - }, - .num_parents = 2, + .parent_data = pwrcl_smux_parents, + .num_parents = ARRAY_SIZE(pwrcl_smux_parents), .ops = &clk_regmap_mux_closest_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -304,16 +318,27 @@ static struct clk_regmap_mux perfcl_smux = { .width = 2, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_smux", - .parent_names = (const char *[]){ - "xo", - "perfcl_pll_postdiv", - }, - .num_parents = 2, + .parent_data = perfcl_smux_parents, + .num_parents = ARRAY_SIZE(perfcl_smux_parents), .ops = &clk_regmap_mux_closest_ops, .flags = CLK_SET_RATE_PARENT, }, }; +static const struct clk_hw *pwrcl_pmux_parents[] = { + [SMUX_INDEX] = &pwrcl_smux.clkr.hw, + [PLL_INDEX] = &pwrcl_pll.clkr.hw, + [ACD_INDEX] = &pwrcl_pll.clkr.hw, + [ALT_INDEX] = &pwrcl_alt_pll.clkr.hw, +}; + +static const struct clk_hw *perfcl_pmux_parents[] = { + [SMUX_INDEX] = &perfcl_smux.clkr.hw, + [PLL_INDEX] = &perfcl_pll.clkr.hw, + [ACD_INDEX] = &perfcl_pll.clkr.hw, + [ALT_INDEX] = &perfcl_alt_pll.clkr.hw, +}; + static struct clk_cpu_8996_pmux pwrcl_pmux = { .reg = PWRCL_REG_OFFSET + MUX_OFFSET, .shift = 0, @@ -323,13 +348,8 @@ static struct clk_cpu_8996_pmux pwrcl_pmux = { .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_pmux", - .parent_names = (const char *[]){ - "pwrcl_smux", - "pwrcl_pll", - "pwrcl_pll_acd", - "pwrcl_alt_pll", - }, - .num_parents = 4, + .parent_hws = pwrcl_pmux_parents, + .num_parents = ARRAY_SIZE(pwrcl_pmux_parents), .ops = &clk_cpu_8996_pmux_ops, /* CPU clock is critical and should never be gated */ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, @@ -345,13 +365,8 @@ static struct clk_cpu_8996_pmux perfcl_pmux = { .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_pmux", - .parent_names = (const char *[]){ - "perfcl_smux", - "perfcl_pll", - "perfcl_pll_acd", - "perfcl_alt_pll", - }, - .num_parents = 4, + .parent_hws = perfcl_pmux_parents, + .num_parents = ARRAY_SIZE(perfcl_pmux_parents), .ops = &clk_cpu_8996_pmux_ops, /* CPU clock is critical and should never be gated */ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, From patchwork Thu Jul 14 10:03:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 590964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8561FCCA480 for ; Thu, 14 Jul 2022 10:04:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237840AbiGNKEA (ORCPT ); Thu, 14 Jul 2022 06:04:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237725AbiGNKD5 (ORCPT ); Thu, 14 Jul 2022 06:03:57 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5595E6259 for ; Thu, 14 Jul 2022 03:03:56 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id u13so1971790lfn.5 for ; Thu, 14 Jul 2022 03:03:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JTKBL6Aor4zd0gi9+YpsM0tS+Wh8c3Pxgu/O7VusGAc=; b=XSP18C8zz0oix63kSQznFfQcyuoXYYWwuSlLN7U2taqc6gNNJA2Akk295PvVJrUFLI PvF5aU+Ardnwb0jXkCd26K062PKDvC/MhXCWuGfr3HQ3dZY0Ny9oe/2jHvNxZ3xRY/ry nfhn+eSKy77dIO+TrXCvq8Fj6txV4LIJMkSeIvv9H54vWSPHvoPXd084ISjTn555DS6k w/74DnRfX7RSicmZiadRQ5bDq1c+5prRL3rt+tGzA8egyHB5UNvAd44Fud1N0TfkhDSf K0ID+CAXsRNZ6Zsx/8TuuNSyP6rk6JGEwVnk+M0UFPwRMJA8tx5wwAnUqOD5aS2c0YLp P7eQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JTKBL6Aor4zd0gi9+YpsM0tS+Wh8c3Pxgu/O7VusGAc=; b=cwFEZHh1z86x7QZqQ7hjSxF52BMqnWjuVHvF5DJQCfrP1/GyrovmtvNWGmNtwUFZOT MaPq2qx5yGD8cvVidB6/ZWEaN4p20JY7Y4pd4xMv9eW7DqwDUPWSHMsTIPI1McrJ0HEu 5j70iPyJBYUC+GSEcyUqTyBpdqu3z2lihoVChvDGfHdNd5FUWfoHVA+/XKII6tKcnrV7 gL/vbTSCEGI2B7iwdtWNns+EgY8IuHEIz6so3aFpW0p4jILFeDiRlNCH2pEbTyCuMNnl MZuvvCQcFS1hBNN0ReOVH6jbVvI07NI+vOuWuBdBjnN0/jzSVJ7fA5c8WssJmWWf5YO2 q+rA== X-Gm-Message-State: AJIora8W3FXNHz1n3PPvZM06sHUS8Sn08DXMk7uO9pyvAQdqA5D09YwD 4J+55AYp/L0tKjWMhhAxd9/VlQ== X-Google-Smtp-Source: AGRyM1uxX9d1GQ16nOwzfxzni70OBrd8AJiy3hVmto0DyaAUNXDchl1mlionWd+uV2qy9epbN9i60g== X-Received: by 2002:a05:6512:2610:b0:47f:74dc:3205 with SMTP id bt16-20020a056512261000b0047f74dc3205mr4497506lfb.429.1657793034742; Thu, 14 Jul 2022 03:03:54 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id c9-20020a056512074900b00489c92779f8sm273355lfs.184.2022.07.14.03.03.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 03:03:54 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Yassine Oudjana Subject: [PATCH 2/6] clk: qcom: cpu-8996: switch to devm_clk_notifier_register Date: Thu, 14 Jul 2022 13:03:47 +0300 Message-Id: <20220714100351.1834711-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220714100351.1834711-1-dmitry.baryshkov@linaro.org> References: <20220714100351.1834711-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Switch to using devres-managed version of clk_notifier_register(). This allows us to drop driver's remove() callback. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-cpu-8996.c | 25 ++----------------------- 1 file changed, 2 insertions(+), 23 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 708a8ad0c933..ff90cd5b4fba 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -425,27 +425,12 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk); clk_prepare_enable(perfcl_alt_pll.clkr.hw.clk); - clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb); - clk_notifier_register(perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb); + devm_clk_notifier_register(dev, pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb); + devm_clk_notifier_register(dev, perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb); return ret; } -static int qcom_cpu_clk_msm8996_unregister_clks(void) -{ - int ret = 0; - - ret = clk_notifier_unregister(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb); - if (ret) - return ret; - - ret = clk_notifier_unregister(perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb); - if (ret) - return ret; - - return 0; -} - #define CPU_AFINITY_MASK 0xFFF #define PWRCL_CPU_REG_MASK 0x3 #define PERFCL_CPU_REG_MASK 0x103 @@ -544,11 +529,6 @@ static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev) return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data); } -static int qcom_cpu_clk_msm8996_driver_remove(struct platform_device *pdev) -{ - return qcom_cpu_clk_msm8996_unregister_clks(); -} - static const struct of_device_id qcom_cpu_clk_msm8996_match_table[] = { { .compatible = "qcom,msm8996-apcc" }, {} @@ -557,7 +537,6 @@ MODULE_DEVICE_TABLE(of, qcom_cpu_clk_msm8996_match_table); static struct platform_driver qcom_cpu_clk_msm8996_driver = { .probe = qcom_cpu_clk_msm8996_driver_probe, - .remove = qcom_cpu_clk_msm8996_driver_remove, .driver = { .name = "qcom-msm8996-apcc", .of_match_table = qcom_cpu_clk_msm8996_match_table, From patchwork Thu Jul 14 10:03:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 590434 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE2D9C43334 for ; Thu, 14 Jul 2022 10:04:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237903AbiGNKEC (ORCPT ); Thu, 14 Jul 2022 06:04:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237612AbiGNKD7 (ORCPT ); Thu, 14 Jul 2022 06:03:59 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E5B1BC8B for ; Thu, 14 Jul 2022 03:03:57 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id x10so1102004ljj.11 for ; Thu, 14 Jul 2022 03:03:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4+ZXhanq0yeTnNAKNTjduoC20FlvSPFcgOLSol78gzo=; b=IN6kbsCNGAOFbD1Rtu5j0AY/OxDKSFTPYEFKSxnHgREsFXjjcUVec8ewD0KfnY4TOG +hJeGFMRnbCerIHwMQ60ysHvWEsPFVQwikzlGWk116cthricZGpynfR+YnMemQeibAE2 msWvEC0PR56jSxpvbcj/UxozKiUaRVD8oKV31MN0bkFbnc9vM10FM3D/HUBX/oZdm61v +tXvVIuGPYKXrb9hmdqIjsPkVtjZUnOffdI15qcDiaWk0/AhGhp1sSYOpGodOisSVJl+ g+PJEERAHBwV56CocR1g5JXhXDNdheebOxh4gAHyigO5pNLzrCMrDicvE+UhK2Wirv6F j4Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4+ZXhanq0yeTnNAKNTjduoC20FlvSPFcgOLSol78gzo=; b=lz7C4kHTHE110u1Mt5WW++dB93FpJc7sa/VppCZ3v1YdnE4jIyFd3NOp4PeBFGkDiB umDXsK5XCiDKASKyUxq+2THoRP3QQrMjzV6CrNlrjebMeC1IRwlPTrf7Ko50Ft/mR/p1 phO5wvutg3KzIfBlIMFnfcc2LhWF+rC6k6WNsoYdsP0QwAHsAsn8kuJyiovWp8IeIHTe pBle68BqxBfd/3QING0nLoDLi/OciV4TWxyiU+s0QAAtnBGKI2to2/ffE+tTc1OWNIHE 8E3ZF4dHqFmuA+3wSZE+HSJfQ8do98b6LGnc2kNQ4wqTJiEoJvSmz4qyjPwUY/LXEkkm R3Ew== X-Gm-Message-State: AJIora8AVwTP1Cf/dbYsiNwb7VqtAJ/QJ8adxLsQiHTzrdDqjfx4UaEI PuXTgeFINLowKNLl1qDaQQru3w== X-Google-Smtp-Source: AGRyM1uIitr7ZeSJL1fQkE+RMwrBHC2Lspr+3bc8UHiopY1PbSKeRcs/Woz7En+4X/w4LCyqksSyrw== X-Received: by 2002:a2e:2a41:0:b0:25d:832d:2af9 with SMTP id q62-20020a2e2a41000000b0025d832d2af9mr3983587ljq.429.1657793035621; Thu, 14 Jul 2022 03:03:55 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id c9-20020a056512074900b00489c92779f8sm273355lfs.184.2022.07.14.03.03.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 03:03:55 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Yassine Oudjana Subject: [PATCH 3/6] clk: qcom: cpu-8996: declare ACD clocks Date: Thu, 14 Jul 2022 13:03:48 +0300 Message-Id: <20220714100351.1834711-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220714100351.1834711-1-dmitry.baryshkov@linaro.org> References: <20220714100351.1834711-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org To simplify the code, define 1:1 fixed factor clocks to represent the ACD pmux parent. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-cpu-8996.c | 53 +++++++++++++++++++++++++-------- 1 file changed, 41 insertions(+), 12 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index ff90cd5b4fba..3dd6efdef82d 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -168,6 +168,34 @@ static struct clk_fixed_factor perfcl_pll_postdiv = { }, }; +static struct clk_fixed_factor perfcl_pll_acd = { + .mult = 1, + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "perfcl_pll_acd", + .parent_data = &(const struct clk_parent_data){ + .hw = &perfcl_pll.clkr.hw + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor pwrcl_pll_acd = { + .mult = 1, + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "pwrcl_pll_acd", + .parent_data = &(const struct clk_parent_data){ + .hw = &pwrcl_pll.clkr.hw + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + static const struct pll_vco alt_pll_vco_modes[] = { VCO(3, 250000000, 500000000), VCO(2, 500000000, 750000000), @@ -328,14 +356,14 @@ static struct clk_regmap_mux perfcl_smux = { static const struct clk_hw *pwrcl_pmux_parents[] = { [SMUX_INDEX] = &pwrcl_smux.clkr.hw, [PLL_INDEX] = &pwrcl_pll.clkr.hw, - [ACD_INDEX] = &pwrcl_pll.clkr.hw, + [ACD_INDEX] = &pwrcl_pll_acd.hw, [ALT_INDEX] = &pwrcl_alt_pll.clkr.hw, }; static const struct clk_hw *perfcl_pmux_parents[] = { [SMUX_INDEX] = &perfcl_smux.clkr.hw, [PLL_INDEX] = &perfcl_pll.clkr.hw, - [ACD_INDEX] = &perfcl_pll.clkr.hw, + [ACD_INDEX] = &perfcl_pll_acd.hw, [ALT_INDEX] = &perfcl_alt_pll.clkr.hw, }; @@ -382,6 +410,13 @@ static const struct regmap_config cpu_msm8996_regmap_config = { .val_format_endian = REGMAP_ENDIAN_LITTLE, }; +static struct clk_hw *cpu_msm8996_hw_clks[] = { + &pwrcl_pll_postdiv.hw, + &perfcl_pll_postdiv.hw, + &pwrcl_pll_acd.hw, + &perfcl_pll_acd.hw, +}; + static struct clk_regmap *cpu_msm8996_clks[] = { &pwrcl_pll.clkr, &perfcl_pll.clkr, @@ -398,16 +433,10 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, { int i, ret; - ret = devm_clk_hw_register(dev, &pwrcl_pll_postdiv.hw); - if (ret) { - dev_err(dev, "Failed to register pwrcl_pll_postdiv: %d", ret); - return ret; - } - - ret = devm_clk_hw_register(dev, &perfcl_pll_postdiv.hw); - if (ret) { - dev_err(dev, "Failed to register perfcl_pll_postdiv: %d", ret); - return ret; + for (i = 0; i < ARRAY_SIZE(cpu_msm8996_hw_clks); i++) { + ret = devm_clk_hw_register(dev, cpu_msm8996_hw_clks[i]); + if (ret) + return ret; } for (i = 0; i < ARRAY_SIZE(cpu_msm8996_clks); i++) { From patchwork Thu Jul 14 10:03:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 590962 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60660C43334 for ; Thu, 14 Jul 2022 10:04:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237858AbiGNKER (ORCPT ); Thu, 14 Jul 2022 06:04:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237673AbiGNKD7 (ORCPT ); Thu, 14 Jul 2022 06:03:59 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03A48DF9B for ; Thu, 14 Jul 2022 03:03:58 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id bp17so1978061lfb.3 for ; Thu, 14 Jul 2022 03:03:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YqQw+hyZrOSvmDZjue9kde/HY6butVNaHprEEy1Lvvs=; b=yEXH5JSEEmuCje6GpBhQX95NQ+K/ECEoI/mIj7PJDK0z6LI/cNmhK2cv8IbwV/B1Hb 0kY7bQXObD1eo3eFGp8IlQP0PLkM+RBCy/CZF9Y/ZH/rUMzDJiWo+ydlel4xP4DeP8bE E31+weZEyXSuvDwYJuceOH9SdZ2CexRnL2yHf75zvq7o+tw5vtRkLTTcIu+/IV6tfpcp D+lhxMJJHuHT7qX5xMf+Z28+rinkd9iutST+nMoFP3+L9NTIMTpBsk6FesojRzHL6oEK UZ1wT226gGVO0E5dq6F4w15HTzCd5IxlRNGDA1q+VhXa6+TmUy4IaEj4+ldkTZp7sx9q NdnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YqQw+hyZrOSvmDZjue9kde/HY6butVNaHprEEy1Lvvs=; b=aB+7exHC92ubjjnkYIt6o7SfYqOmb6enf5gAVS0EGAjTX7Ysw40GVjRXJS78sWJ+wD sDtfbg67nk4URMmoErb1dTXVv1X2nCXG83jMxDUz8mxz8FBJzxaiezhZExJqHibVVBTb KDRrTR5QCLyMYRRtVyxrFbRhyTNQfwX17Qv2Ev982Y1+JWYOCzRyHxcbbNJu2F8bz9N9 Wzt++aRXyl+dDmCv6EnaQwSH4jJFXGCCyKix9/470Hb4hUFupeGrPU8PSx6kvPv5zO4d UYaRVmvgYeK94nH7Uzxytavcs3pEKSltwJwngGlK+W1djuk/dezqZ81Ca86OjJ2zthhV ch/g== X-Gm-Message-State: AJIora/QpgoUt4wZ63uOEHkEgy8129mFqMmHxFSJ4+ycrdTObnhMTv99 xoWeWZrYyXaTj1Kn8/+ww30zGQ== X-Google-Smtp-Source: AGRyM1u3UowzkELPYriWql+Kw5rsqUcTow48EopecVCSSsFRtxVaO8JJtQpLsVro0WsrsPKJ1os02w== X-Received: by 2002:ac2:5389:0:b0:48a:1070:775d with SMTP id g9-20020ac25389000000b0048a1070775dmr3179089lfh.266.1657793036327; Thu, 14 Jul 2022 03:03:56 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id c9-20020a056512074900b00489c92779f8sm273355lfs.184.2022.07.14.03.03.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 03:03:55 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Yassine Oudjana Subject: [PATCH 4/6] clk: qcom: cpu-8996: move ACD logic to clk_cpu_8996_pmux_determine_rate Date: Thu, 14 Jul 2022 13:03:49 +0300 Message-Id: <20220714100351.1834711-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220714100351.1834711-1-dmitry.baryshkov@linaro.org> References: <20220714100351.1834711-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rather than telling everybody that we are using PLL as a parent (and using ACD clock instead) properly select ACD as a pmux parent clock. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-cpu-8996.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 3dd6efdef82d..5c5adcb533ce 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -284,9 +284,6 @@ static int clk_cpu_8996_pmux_set_parent(struct clk_hw *hw, u8 index) u32 val; val = index; - /* We always want ACD when using the primary PLL */ - if (val == PLL_INDEX) - val = ACD_INDEX; val <<= cpuclk->shift; return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val); @@ -371,7 +368,7 @@ static struct clk_cpu_8996_pmux pwrcl_pmux = { .reg = PWRCL_REG_OFFSET + MUX_OFFSET, .shift = 0, .width = 2, - .pll = &pwrcl_pll.clkr.hw, + .pll = &pwrcl_pll_acd.clkr.hw, .pll_div_2 = &pwrcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { @@ -388,7 +385,7 @@ static struct clk_cpu_8996_pmux perfcl_pmux = { .reg = PERFCL_REG_OFFSET + MUX_OFFSET, .shift = 0, .width = 2, - .pll = &perfcl_pll.clkr.hw, + .pll = &perfcl_pll_acd.clkr.hw, .pll_div_2 = &perfcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { From patchwork Thu Jul 14 10:03:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 590963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 986B2CCA483 for ; Thu, 14 Jul 2022 10:04:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237030AbiGNKEP (ORCPT ); Thu, 14 Jul 2022 06:04:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237856AbiGNKEA (ORCPT ); Thu, 14 Jul 2022 06:04:00 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A92FDB49C for ; Thu, 14 Jul 2022 03:03:58 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id w17so1566703ljh.6 for ; Thu, 14 Jul 2022 03:03:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6sI+cun9sqvSMZVYqB1PbbtuHQ6v+tt2HHn2LrmcZhI=; b=BagQF/DTiIOVdYDZI5Z/Jk+XUpDAtmhS+vV3ZZQdULIk9UvwM6vvhyrWpmS3Jbbwfw WxWlp/bWu6i8I0JKaQGosdxYr++oGMIkkhuWup1JEQ4p95rbEzNW0gULFmuvyo/rUeh+ rNaQJ6j7GvuuvaTLxjWMtKlP0/QQIGVF8cckDxNBZTeNUSpHPtNXQeYFqKNzDmQdx94M gSirvluErr8LUYAiBDNdfXRNKm4FZ52BEvmGrJ+KfaDwNldTpCGt2ckrzTKhC7EcpL0q 4/pN12w9Gx0tWt94x41AxL5VlT7/IV6XyQsoj//nW0zFdDwvD0IQVuqjiv6Ih9e/Yie9 +CBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6sI+cun9sqvSMZVYqB1PbbtuHQ6v+tt2HHn2LrmcZhI=; b=lOgmbHBGHM8SzfBntqY34YNBl9LLKcN9xdOYMYX36EuTzuUcSqkQbkfpJ4brpm/PoN PaJSf17wgEYryvZ2W6sIDZPd0CmZR7uyOqkbieB36crn/blxUCABQX18sZ9vuj0NzdoJ VGKn1jU4O+aP9NmnXm6W+IbSbGplvwtE3nEWndgbd8OTB1GfIc5tLxTOudmxHVjpOFz0 9u9fb9l5hzRYoiwYfiGYE+ZjPzbFWT4qUJmsbUeDwfDHMAu2RPvYKPedEoemNPw00au/ zkKb862/WZksyLIti5pnCalCME9LTQjQe2O7fykzBx1pn+INjV01buFK5aTifrzXPhp/ /Yxw== X-Gm-Message-State: AJIora/wyrNMD+WUUWtR2HqFcM2ruRtp8FMbZUH8Saa8QDU6/XmocS9T ld7ZDFayVbQGAkR1GjOP38HuupROzu9GWw== X-Google-Smtp-Source: AGRyM1uv4wkJ0EJPbrqRDeIOSoEQVjhxZTEn5xWzjWdOG/EatAuIuJz3tpKbbCGvVF59RzBWrkftwQ== X-Received: by 2002:a05:651c:b13:b0:25d:8342:e11 with SMTP id b19-20020a05651c0b1300b0025d83420e11mr3928646ljr.266.1657793037064; Thu, 14 Jul 2022 03:03:57 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id c9-20020a056512074900b00489c92779f8sm273355lfs.184.2022.07.14.03.03.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 03:03:56 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Yassine Oudjana Subject: [PATCH 5/6] clk: qcom: cpu-8996: don't store parents in clk_cpu_8996_pmux Date: Thu, 14 Jul 2022 13:03:50 +0300 Message-Id: <20220714100351.1834711-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220714100351.1834711-1-dmitry.baryshkov@linaro.org> References: <20220714100351.1834711-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Don't store pointers to parents in struct clk_cpu_8996_pmux. Instead use clk_hw_get_parent_by_index to fetch them. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-cpu-8996.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 5c5adcb533ce..0a336adb02b5 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -247,8 +247,6 @@ struct clk_cpu_8996_pmux { u8 shift; u8 width; struct notifier_block nb; - struct clk_hw *pll; - struct clk_hw *pll_div_2; struct clk_regmap clkr; }; @@ -292,15 +290,17 @@ static int clk_cpu_8996_pmux_set_parent(struct clk_hw *hw, u8 index) static int clk_cpu_8996_pmux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); - struct clk_hw *parent = cpuclk->pll; + struct clk_hw *parent; - if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) { - if (req->rate < (DIV_2_THRESHOLD / 2)) - return -EINVAL; + if (req->rate < (DIV_2_THRESHOLD / 2)) + return -EINVAL; - parent = cpuclk->pll_div_2; - } + if (req->rate < DIV_2_THRESHOLD) + parent = clk_hw_get_parent_by_index(hw, SMUX_INDEX); + else + parent = clk_hw_get_parent_by_index(hw, ACD_INDEX); + if (!parent) + return -EINVAL; req->best_parent_rate = clk_hw_round_rate(parent, req->rate); req->best_parent_hw = parent; @@ -368,8 +368,6 @@ static struct clk_cpu_8996_pmux pwrcl_pmux = { .reg = PWRCL_REG_OFFSET + MUX_OFFSET, .shift = 0, .width = 2, - .pll = &pwrcl_pll_acd.clkr.hw, - .pll_div_2 = &pwrcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_pmux", @@ -385,8 +383,6 @@ static struct clk_cpu_8996_pmux perfcl_pmux = { .reg = PERFCL_REG_OFFSET + MUX_OFFSET, .shift = 0, .width = 2, - .pll = &perfcl_pll_acd.clkr.hw, - .pll_div_2 = &perfcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_pmux", From patchwork Thu Jul 14 10:03:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 590433 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71751CCA47B for ; Thu, 14 Jul 2022 10:04:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237641AbiGNKEQ (ORCPT ); Thu, 14 Jul 2022 06:04:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237878AbiGNKEC (ORCPT ); Thu, 14 Jul 2022 06:04:02 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BD39E0A1 for ; Thu, 14 Jul 2022 03:03:59 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id o7so1945655lfq.9 for ; Thu, 14 Jul 2022 03:03:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iSjDY003YCEJCAL+QFpIk6XgpVGUGc1D7V9hV3sdds8=; b=oaKJTR9qMGTUFrv93sM3Up09q7/CKcNxyofNpoGaPGkSmp4EtVTp5IVfdwZaMIQT38 XPzYHZyPvazmKC/t7fzVwj+BG5o3nA7LJRYC2m5VhtBNwYdzTiPepjkrZf1LlLsgCJmU 68AdPk4IU8WEYaFntkDYx/Fm6tqG6//xUXA+JXRkfQHVQEKnDBiGdPVVSfMLkJ7DnEF4 oi8lVTx8sdM4115m4mYPLmbbygLex75c/S3mJT73A+XFuf5fZSAdkb1RCsahZhvAqnlB KGFalhqEWWaXPuv7KJR18upfMshC2GYAg4Gr6cnDTin3gDwkkHLAPkRrPkya6XDuu3WE iEAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iSjDY003YCEJCAL+QFpIk6XgpVGUGc1D7V9hV3sdds8=; b=bkAKdsqUZBbkOiZjxBWaoiEz5kM7fBPVxy4GzW5mdR543egYAW86iYDj6SNZnLbWDQ 43x2LZ+BqJOrzryiEuYv6CI3kz1dr9K3WFgVFoUr0vjGlI7+KuPkqyVPFA87Q0aKygnU Ac14sjIZVUc4zxaog/SKV7LaqXnYua+qmjaLKkUj/DCng0r7LefxWXFxcl/vr45afsbb CuDJElc6OdGarBUnj3nbQqW+0FEUi3eJu+mJYlc757+v/vG3/ucxHSBwz2GVNN2ftuRJ YnC4AeC7CurHVfGZmDI8BUwfSju1ZE3k7d3ylRVisMKmqycBqVO9k9h6OlbGpoc5OFCa zEaA== X-Gm-Message-State: AJIora8nRYkSKFx3KSy0twPGBDfu5w9OrncbVVJ9WBQ4v/vkomt5P9Br ZyMs9hbRXtnDK4tHIpZsS1fk9w== X-Google-Smtp-Source: AGRyM1vns3Jat5Zluvzc1MJY1pz1ufsAxWFrQ6prhmCJo119bmbWhsaH88i+Ow0IrOG2G1oh12Xupw== X-Received: by 2002:a05:6512:ba3:b0:489:ed8b:a172 with SMTP id b35-20020a0565120ba300b00489ed8ba172mr4621121lfv.584.1657793037760; Thu, 14 Jul 2022 03:03:57 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id c9-20020a056512074900b00489c92779f8sm273355lfs.184.2022.07.14.03.03.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 03:03:57 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Yassine Oudjana Subject: [PATCH 6/6] clk: qcom: cpu-8996: use constant mask for pmux Date: Thu, 14 Jul 2022 13:03:51 +0300 Message-Id: <20220714100351.1834711-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220714100351.1834711-1-dmitry.baryshkov@linaro.org> References: <20220714100351.1834711-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Both pmux instances share the same width and shift. Specify the mask at compile time to simplify functions. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-cpu-8996.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 0a336adb02b5..ee76ef958d31 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -49,6 +49,7 @@ * detect voltage droops. */ +#include #include #include #include @@ -76,6 +77,8 @@ enum _pmux_input { #define ALT_PLL_OFFSET 0x100 #define SSSCTL_OFFSET 0x160 +#define PMUX_MASK 0x3 + static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = { [PLL_OFF_L_VAL] = 0x04, [PLL_OFF_ALPHA_VAL] = 0x08, @@ -244,8 +247,6 @@ static struct clk_alpha_pll perfcl_alt_pll = { struct clk_cpu_8996_pmux { u32 reg; - u8 shift; - u8 width; struct notifier_block nb; struct clk_regmap clkr; }; @@ -265,26 +266,22 @@ static u8 clk_cpu_8996_pmux_get_parent(struct clk_hw *hw) { struct clk_regmap *clkr = to_clk_regmap(hw); struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); - u32 mask = GENMASK(cpuclk->width - 1, 0); u32 val; regmap_read(clkr->regmap, cpuclk->reg, &val); - val >>= cpuclk->shift; - return val & mask; + return FIELD_GET(PMUX_MASK, val); } static int clk_cpu_8996_pmux_set_parent(struct clk_hw *hw, u8 index) { struct clk_regmap *clkr = to_clk_regmap(hw); struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); - u32 mask = GENMASK(cpuclk->width + cpuclk->shift - 1, cpuclk->shift); u32 val; - val = index; - val <<= cpuclk->shift; + val = FIELD_PREP(PMUX_MASK, index); - return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val); + return regmap_update_bits(clkr->regmap, cpuclk->reg, PMUX_MASK, val); } static int clk_cpu_8996_pmux_determine_rate(struct clk_hw *hw, @@ -366,8 +363,6 @@ static const struct clk_hw *perfcl_pmux_parents[] = { static struct clk_cpu_8996_pmux pwrcl_pmux = { .reg = PWRCL_REG_OFFSET + MUX_OFFSET, - .shift = 0, - .width = 2, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_pmux", @@ -381,8 +376,6 @@ static struct clk_cpu_8996_pmux pwrcl_pmux = { static struct clk_cpu_8996_pmux perfcl_pmux = { .reg = PERFCL_REG_OFFSET + MUX_OFFSET, - .shift = 0, - .width = 2, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_pmux",