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spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pj1-x102e.google.com with SMTP id g16-20020a17090a7d1000b001ea9f820449so10550697pjl.5 for ; Tue, 12 Jul 2022 00:12:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SKWZ5cG2J3xwUvRRn6Veqj5+m3lltWnRiukCAl4Sf4o=; b=uZbnKsuxZA+i6thIYpl+Cw2uXyJUy0GH/OQsas6F/NB6Flusp4ydcDYkUWS0iV/SyY 5bKs42mO7Mm0w+V9xkjjOP387rz3v/QWWL4HGS64jRFU6viMUFen/hhgmkimxD38+r/Q ktQE9CaN8zNGCqZxc/xpGMeRu/MBJCekKUqwtOtztK/hK3+sQZJvMSvXinpufAwlFiqD vJP566XuUmMiHGw3q9zY7ZMBEBn9n6Ag2no8X8xStALwxQWtadgqQtT9yo/SRjrWZ9iS HCz8tkMjnb4VHq0ptb3hNgEm942piSyLrC71lY6gTuNE1nuXWZNTJd8GmrUZNPS0NVoe RKDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SKWZ5cG2J3xwUvRRn6Veqj5+m3lltWnRiukCAl4Sf4o=; b=JE1ILA93kr8HUt+J7uO3ejawI4pglyARut6BFixsqDwz+nF5Q/mTXTprd5OEU/FBIK SJabSmUln7V6H7pSEaZXFUpfwnBOIsWC3HbMA9IZdWAwAUdc64wo6GujRRdmaaDIwtm5 o+3AwJHD6s9UHYatehfQJ/HzN2xdaCDE1CKoskOLBW8TzNp8woryR/0ZAJarbaakNxj6 rgEOxKJywXUgQFecdhHtrAWhZpBPGq9KoP5OsST0QoHUas86qjsP6psyh7GMYqJoSLpj C3I/m+0lLrnVOfq+AdlMxhYNkAulpV10TdLJo9dP4vhfkooCjhcfvALbu4+MTp/fOzP3 H1Kg== X-Gm-Message-State: AJIora/IcrQbQ6vU4sm55QiDetYsNXSGAJ6rXvhscfwLLosUP5g7iZLF 1HqPjP5GOaDdKRQpsD7Bw+yGrY0S+rvrag== X-Received: by 2002:a17:90b:3b90:b0:1ef:eb4a:fbd with SMTP id pc16-20020a17090b3b9000b001efeb4a0fbdmr2720833pjb.2.1657609949921; Tue, 12 Jul 2022 00:12:29 -0700 (PDT) Received: from localhost.localdomain ([27.56.177.217]) by smtp.gmail.com with ESMTPSA id x10-20020a170902a38a00b001678ce9080dsm5928843pla.258.2022.07.12.00.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 00:12:29 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, peng.fan@nxp.com, jh80.chung@samsung.com, sjg@chromium.org, trini@konsulko.com, dsankouski@gmail.com, stephan@gerhold.net, vinod.koul@linaro.org, nicolas.dechesne@linaro.org, mworsfold@impinj.com, daniel.thompson@linaro.org, pbrobinson@gmail.com, Sumit Garg Subject: [PATCH v3 1/9] board: starqltechn: Align DT node overrides with sdm845.dtsi Date: Tue, 12 Jul 2022 12:42:04 +0530 Message-Id: <20220712071212.2188390-2-sumit.garg@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220712071212.2188390-1-sumit.garg@linaro.org> References: <20220712071212.2188390-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Currently there is a mismatch among DT node overrides in starqltechn board DTS file and the actual DT nodes in the sdm845.dtsi. So fix that to align with DT nodes in sdm845.dtsi. Signed-off-by: Sumit Garg Reviewed-by: Ramon Fried --- arch/arm/dts/starqltechn-uboot.dtsi | 18 ++++++++---------- arch/arm/dts/starqltechn.dts | 2 +- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/arch/arm/dts/starqltechn-uboot.dtsi b/arch/arm/dts/starqltechn-uboot.dtsi index b55cccfe14..8d5d09c3a5 100644 --- a/arch/arm/dts/starqltechn-uboot.dtsi +++ b/arch/arm/dts/starqltechn-uboot.dtsi @@ -16,16 +16,14 @@ serial@a84000 { u-boot,dm-pre-reloc; }; - gcc { - clock-controller@100000 { - u-boot,dm-pre-reloc; - }; - gpio_north@3900000 { - u-boot,dm-pre-reloc; - }; - pinctrl@3900000 { - u-boot,dm-pre-reloc; - }; + clock-controller@100000 { + u-boot,dm-pre-reloc; + }; + gpio_north@3900000 { + u-boot,dm-pre-reloc; + }; + pinctrl_north@3900000 { + u-boot,dm-pre-reloc; }; }; }; diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts index 0261388319..34a4f59cbd 100644 --- a/arch/arm/dts/starqltechn.dts +++ b/arch/arm/dts/starqltechn.dts @@ -48,7 +48,7 @@ status = "okay"; }; - pinctrl@3900000 { + pinctrl_north@3900000 { muic_i2c: muic_i2c { pins = "GPIO_33", "GPIO_34"; drive-strength = <0x2>; From patchwork Tue Jul 12 07:12:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 589787 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp8681max; Tue, 12 Jul 2022 00:12:57 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vwAb2r2o+6nnrlichb1zNL+HS4afhX29nZohHzsn58+VgXfOjs3yCMVXw5pKUyO/A9AE2c X-Received: by 2002:a05:6512:234f:b0:47f:792c:7ce8 with SMTP id p15-20020a056512234f00b0047f792c7ce8mr14035205lfu.548.1657609977027; Tue, 12 Jul 2022 00:12:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657609977; cv=none; d=google.com; s=arc-20160816; b=L5VLjlIbQtvID5QtPwgE5kEvmNf+ZeinA/mTz5hQbAASEeM1oZCU/56ocNNBqh1BcI Nre86pPH6NVIxKNFMenpg+aTbAyHMjuhvDemTBZraemp3k5bjX2YIpzdjs0kSfVOk7m3 Pb+EPalgKcJbwreb2+Spz9cJU1O07RT3c2PwuM9apmZ6Qs64h9oXN79kxW0cEEOj54A7 kpDm2EUZX7J1l7jHHxLLqqXgwqukeOXSlEfD2Rh4MeWxirNz7usj9xKzNUxmlGMhJNkg zJUBeeKnagEuIzTlgzuzJNq59BMZ8nb2RZ1eUVKleSkdHWmJXrualf3ZA9rzq38Fqrq/ jscA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ulaWzm/C1DROOaw1foRAtYVKRminRETc8Ip10mZfuMI=; b=rRfZFgBTqc699TSIdNkahPJVoBWRI8ZL2TqE4fj/pLN8FadlvlFDbPrZ5OWg+ik9AJ M56gQr5MZJpey4jPoaIHjr7y6vnVJyztXZ1xG4IRtrctUpXXSgH6egUMslqQgszIOJcS qwZfzxOlu15bZn01QaVBqZ86pH88X7AI4ZZ+iI7bDtyXfcAa68Vga9NkCxoicJfRzNHc Fzqc7o0ukhge/Y2nyUv6Wh5skgRegogQpJtY3/H3z2KTdH3RjF3EdPu7/vW8U3/wrtQ1 2m8/8CDFvvRnkP4J3+sXX1f5cE6LByMYNFpmwTXR28QBON/vLbaR8VYMRfho6LPnve/9 CuOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hSG6kaHj; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Also for starqltechn board (which is the only current consumer of sdm845.dtsi), the properties are already included in starqltechn-uboot.dtsi, so remove corresponding redundant properties. Signed-off-by: Sumit Garg Reviewed-by: Ramon Fried --- arch/arm/dts/sdm845.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi index 6f2fb20d68..88030156d9 100644 --- a/arch/arm/dts/sdm845.dtsi +++ b/arch/arm/dts/sdm845.dtsi @@ -18,7 +18,6 @@ compatible = "simple-bus"; gcc: clock-controller@100000 { - u-boot,dm-pre-reloc; compatible = "qcom,gcc-sdm845"; reg = <0x100000 0x1f0000>; #clock-cells = <1>; @@ -27,7 +26,6 @@ }; gpio_north: gpio_north@3900000 { - u-boot,dm-pre-reloc; #gpio-cells = <2>; compatible = "qcom,sdm845-pinctrl"; reg = <0x3900000 0x400000>; @@ -38,7 +36,6 @@ }; tlmm_north: pinctrl_north@3900000 { - u-boot,dm-pre-reloc; compatible = "qcom,tlmm-sdm845"; reg = <0x3900000 0x400000>; gpio-count = <150>; From patchwork Tue Jul 12 07:12:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 589789 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp8925max; Tue, 12 Jul 2022 00:13:21 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tL128S4u+1TZOHoioZ6QJS8rX4gcO9GtoKvkwUKGaBQWO4X4MamLkphg93vcNoNvEBHL+h X-Received: by 2002:a2e:bea7:0:b0:25d:5eb6:7390 with SMTP id a39-20020a2ebea7000000b0025d5eb67390mr9104741ljr.269.1657610000955; Tue, 12 Jul 2022 00:13:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657610000; cv=none; d=google.com; s=arc-20160816; b=VxZOXAUeh4+H3v4PW+8AX6yYFaOaYKGPzxGLWOR1ezysXg3bigkRpeEfEBwgdcyhI7 QOu09u6wUMk28IVY+yx3qwqPKr6VMHb0EUz6n0Y4dJNtc8xD8wl0iEV6XgLG0Z38G/uu hxQhkd4wrQp6HaT1GEX49MyGc2OeL0bM5+9nLcC6revDGAtpqq4kZzVrMXZt8FKRHWwQ B5h68eS5nEgpToBaDIdlVuHDTBxNSYf4Dw6rXZK6WtLVyESWJaL2TAWT3w2Tu0ffXMKt yGCbPYNtOMJvQEom1Lg6vnbNsDpEzwthRd/3VFJOSIvIUCi4a0OpicNPMCZIxsWL6S2u 1Cdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+kXLxf0HGEGZ56Ymn4be8NS3fxhslbGhwDADwKCHSwY=; b=A0up3j8CeGIH4BOgJeS0vRQDi38VZZ+tAv9ranQIAYySfmI6vZFgKrAg4hxl31J60B TNHEYjBn0tGXYK6Ek5UJ304jbBTG9z61LQIQOIEiu8ZIHWWOJSzTJFEcES4EAAku/9Ao 6Wm6ku7IGr0meFUx4/xBxroAw7dbvvdY4lJIoYTBodO8UrZ2QY+q9eUNyyS820mVACCl VVprRyFpfh7T78LoAFhNo5gx1oTbnNyZap/mbhpPOzc+Gi4cTr6awtRcnCJa+jfk7sMR jiSW5L1nJa8EkGhuH9FffN+7K2X+PRP3nnZo74UsxEej3riuiE8zMqFGRAz99RTDstM0 mCww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Dzi/J9lh"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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So start using corresponding clk-id macro for debug UART. Signed-off-by: Sumit Garg Reviewed-by: Ramon Fried --- arch/arm/dts/sdm845.dtsi | 3 +- arch/arm/mach-snapdragon/clock-sdm845.c | 3 +- include/dt-bindings/clock/qcom,gcc-sdm845.h | 246 ++++++++++++++++++++ 3 files changed, 250 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm845.h diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi index 88030156d9..b9506f1297 100644 --- a/arch/arm/dts/sdm845.dtsi +++ b/arch/arm/dts/sdm845.dtsi @@ -8,6 +8,7 @@ /dts-v1/; +#include #include "skeleton64.dtsi" / { @@ -55,7 +56,7 @@ reg = <0xa84000 0x4000>; reg-names = "se_phys"; clock-names = "se-clk"; - clocks = <&gcc 0x58>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart9>; qcom,wrapper-core = <0x8a>; diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c b/arch/arm/mach-snapdragon/clock-sdm845.c index 9572639238..f69be80898 100644 --- a/arch/arm/mach-snapdragon/clock-sdm845.c +++ b/arch/arm/mach-snapdragon/clock-sdm845.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "clock-snapdragon.h" #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } @@ -84,7 +85,7 @@ ulong msm_set_rate(struct clk *clk, ulong rate) struct msm_clk_priv *priv = dev_get_priv(clk->dev); switch (clk->id) { - case 0x58: /*UART2*/ + case GCC_QUPV3_WRAP1_S1_CLK: /*UART2*/ return clk_init_uart(priv, rate); default: return 0; diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h new file mode 100644 index 0000000000..968fa65b9c --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sdm845.h @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H + +/* GCC clock registers */ +#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 +#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 2 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 4 +#define GCC_BOOT_ROM_AHB_CLK 5 +#define GCC_CAMERA_AHB_CLK 6 +#define GCC_CAMERA_AXI_CLK 7 +#define GCC_CAMERA_XO_CLK 8 +#define GCC_CE1_AHB_CLK 9 +#define GCC_CE1_AXI_CLK 10 +#define GCC_CE1_CLK 11 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 +#define GCC_CPUSS_AHB_CLK 14 +#define GCC_CPUSS_AHB_CLK_SRC 15 +#define GCC_CPUSS_RBCPR_CLK 16 +#define GCC_CPUSS_RBCPR_CLK_SRC 17 +#define GCC_DDRSS_GPU_AXI_CLK 18 +#define GCC_DISP_AHB_CLK 19 +#define GCC_DISP_AXI_CLK 20 +#define GCC_DISP_GPLL0_CLK_SRC 21 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 22 +#define GCC_DISP_XO_CLK 23 +#define GCC_GP1_CLK 24 +#define GCC_GP1_CLK_SRC 25 +#define GCC_GP2_CLK 26 +#define GCC_GP2_CLK_SRC 27 +#define GCC_GP3_CLK 28 +#define GCC_GP3_CLK_SRC 29 +#define GCC_GPU_CFG_AHB_CLK 30 +#define GCC_GPU_GPLL0_CLK_SRC 31 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 32 +#define GCC_GPU_MEMNOC_GFX_CLK 33 +#define GCC_GPU_SNOC_DVM_GFX_CLK 34 +#define GCC_MSS_AXIS2_CLK 35 +#define GCC_MSS_CFG_AHB_CLK 36 +#define GCC_MSS_GPLL0_DIV_CLK_SRC 37 +#define GCC_MSS_MFAB_AXIS_CLK 38 +#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39 +#define GCC_MSS_SNOC_AXI_CLK 40 +#define GCC_PCIE_0_AUX_CLK 41 +#define GCC_PCIE_0_AUX_CLK_SRC 42 +#define GCC_PCIE_0_CFG_AHB_CLK 43 +#define GCC_PCIE_0_CLKREF_CLK 44 +#define GCC_PCIE_0_MSTR_AXI_CLK 45 +#define GCC_PCIE_0_PIPE_CLK 46 +#define GCC_PCIE_0_SLV_AXI_CLK 47 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 +#define GCC_PCIE_1_AUX_CLK 49 +#define GCC_PCIE_1_AUX_CLK_SRC 50 +#define GCC_PCIE_1_CFG_AHB_CLK 51 +#define GCC_PCIE_1_CLKREF_CLK 52 +#define GCC_PCIE_1_MSTR_AXI_CLK 53 +#define GCC_PCIE_1_PIPE_CLK 54 +#define GCC_PCIE_1_SLV_AXI_CLK 55 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56 +#define GCC_PCIE_PHY_AUX_CLK 57 +#define GCC_PCIE_PHY_REFGEN_CLK 58 +#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59 +#define GCC_PDM2_CLK 60 +#define GCC_PDM2_CLK_SRC 61 +#define GCC_PDM_AHB_CLK 62 +#define GCC_PDM_XO4_CLK 63 +#define GCC_PRNG_AHB_CLK 64 +#define GCC_QMIP_CAMERA_AHB_CLK 65 +#define GCC_QMIP_DISP_AHB_CLK 66 +#define GCC_QMIP_VIDEO_AHB_CLK 67 +#define GCC_QUPV3_WRAP0_S0_CLK 68 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69 +#define GCC_QUPV3_WRAP0_S1_CLK 70 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71 +#define GCC_QUPV3_WRAP0_S2_CLK 72 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73 +#define GCC_QUPV3_WRAP0_S3_CLK 74 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75 +#define GCC_QUPV3_WRAP0_S4_CLK 76 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77 +#define GCC_QUPV3_WRAP0_S5_CLK 78 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79 +#define GCC_QUPV3_WRAP0_S6_CLK 80 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81 +#define GCC_QUPV3_WRAP0_S7_CLK 82 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83 +#define GCC_QUPV3_WRAP1_S0_CLK 84 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85 +#define GCC_QUPV3_WRAP1_S1_CLK 86 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87 +#define GCC_QUPV3_WRAP1_S2_CLK 88 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89 +#define GCC_QUPV3_WRAP1_S3_CLK 90 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91 +#define GCC_QUPV3_WRAP1_S4_CLK 92 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93 +#define GCC_QUPV3_WRAP1_S5_CLK 94 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95 +#define GCC_QUPV3_WRAP1_S6_CLK 96 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97 +#define GCC_QUPV3_WRAP1_S7_CLK 98 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103 +#define GCC_SDCC2_AHB_CLK 104 +#define GCC_SDCC2_APPS_CLK 105 +#define GCC_SDCC2_APPS_CLK_SRC 106 +#define GCC_SDCC4_AHB_CLK 107 +#define GCC_SDCC4_APPS_CLK 108 +#define GCC_SDCC4_APPS_CLK_SRC 109 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 110 +#define GCC_TSIF_AHB_CLK 111 +#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112 +#define GCC_TSIF_REF_CLK 113 +#define GCC_TSIF_REF_CLK_SRC 114 +#define GCC_UFS_CARD_AHB_CLK 115 +#define GCC_UFS_CARD_AXI_CLK 116 +#define GCC_UFS_CARD_AXI_CLK_SRC 117 +#define GCC_UFS_CARD_CLKREF_CLK 118 +#define GCC_UFS_CARD_ICE_CORE_CLK 119 +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120 +#define GCC_UFS_CARD_PHY_AUX_CLK 121 +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127 +#define GCC_UFS_MEM_CLKREF_CLK 128 +#define GCC_UFS_PHY_AHB_CLK 129 +#define GCC_UFS_PHY_AXI_CLK 130 +#define GCC_UFS_PHY_AXI_CLK_SRC 131 +#define GCC_UFS_PHY_ICE_CORE_CLK 132 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133 +#define GCC_UFS_PHY_PHY_AUX_CLK 134 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140 +#define GCC_USB30_PRIM_MASTER_CLK 141 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 142 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144 +#define GCC_USB30_PRIM_SLEEP_CLK 145 +#define GCC_USB30_SEC_MASTER_CLK 146 +#define GCC_USB30_SEC_MASTER_CLK_SRC 147 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 148 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149 +#define GCC_USB30_SEC_SLEEP_CLK 150 +#define GCC_USB3_PRIM_CLKREF_CLK 151 +#define GCC_USB3_PRIM_PHY_AUX_CLK 152 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 155 +#define GCC_USB3_SEC_CLKREF_CLK 156 +#define GCC_USB3_SEC_PHY_AUX_CLK 157 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158 +#define GCC_USB3_SEC_PHY_PIPE_CLK 159 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161 +#define GCC_VIDEO_AHB_CLK 162 +#define GCC_VIDEO_AXI_CLK 163 +#define GCC_VIDEO_XO_CLK 164 +#define GPLL0 165 +#define GPLL0_OUT_EVEN 166 +#define GPLL0_OUT_MAIN 167 +#define GCC_GPU_IREF_CLK 168 +#define GCC_SDCC1_AHB_CLK 169 +#define GCC_SDCC1_APPS_CLK 170 +#define GCC_SDCC1_ICE_CORE_CLK 171 +#define GCC_SDCC1_APPS_CLK_SRC 172 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 173 +#define GCC_APC_VS_CLK 174 +#define GCC_GPU_VS_CLK 175 +#define GCC_MSS_VS_CLK 176 +#define GCC_VDDA_VS_CLK 177 +#define GCC_VDDCX_VS_CLK 178 +#define GCC_VDDMX_VS_CLK 179 +#define GCC_VS_CTRL_AHB_CLK 180 +#define GCC_VS_CTRL_CLK 181 +#define GCC_VS_CTRL_CLK_SRC 182 +#define GCC_VSENSOR_CLK_SRC 183 +#define GPLL4 184 +#define GCC_CPUSS_DVM_BUS_CLK 185 +#define GCC_CPUSS_GNOC_CLK 186 +#define GCC_QSPI_CORE_CLK_SRC 187 +#define GCC_QSPI_CORE_CLK 188 +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 +#define GCC_LPASS_Q6_AXI_CLK 190 +#define GCC_LPASS_SWAY_CLK 191 + +/* GCC Resets */ +#define GCC_MMSS_BCR 0 +#define GCC_PCIE_0_BCR 1 +#define GCC_PCIE_1_BCR 2 +#define GCC_PCIE_PHY_BCR 3 +#define GCC_PDM_BCR 4 +#define GCC_PRNG_BCR 5 +#define GCC_QUPV3_WRAPPER_0_BCR 6 +#define GCC_QUPV3_WRAPPER_1_BCR 7 +#define GCC_QUSB2PHY_PRIM_BCR 8 +#define GCC_QUSB2PHY_SEC_BCR 9 +#define GCC_SDCC2_BCR 10 +#define GCC_SDCC4_BCR 11 +#define GCC_TSIF_BCR 12 +#define GCC_UFS_CARD_BCR 13 +#define GCC_UFS_PHY_BCR 14 +#define GCC_USB30_PRIM_BCR 15 +#define GCC_USB30_SEC_BCR 16 +#define GCC_USB3_PHY_PRIM_BCR 17 +#define GCC_USB3PHY_PHY_PRIM_BCR 18 +#define GCC_USB3_DP_PHY_PRIM_BCR 19 +#define GCC_USB3_PHY_SEC_BCR 20 +#define GCC_USB3PHY_PHY_SEC_BCR 21 +#define GCC_USB3_DP_PHY_SEC_BCR 22 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 +#define GCC_PCIE_0_PHY_BCR 24 +#define GCC_PCIE_1_PHY_BCR 25 + +/* GCC GDSCRs */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 +#define UFS_CARD_GDSC 2 +#define UFS_PHY_GDSC 3 +#define USB30_PRIM_GDSC 4 +#define USB30_SEC_GDSC 5 +#define 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Tue, 12 Jul 2022 00:12:43 -0700 (PDT) Received: from localhost.localdomain ([27.56.177.217]) by smtp.gmail.com with ESMTPSA id x10-20020a170902a38a00b001678ce9080dsm5928843pla.258.2022.07.12.00.12.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 00:12:43 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, peng.fan@nxp.com, jh80.chung@samsung.com, sjg@chromium.org, trini@konsulko.com, dsankouski@gmail.com, stephan@gerhold.net, vinod.koul@linaro.org, nicolas.dechesne@linaro.org, mworsfold@impinj.com, daniel.thompson@linaro.org, pbrobinson@gmail.com, Sumit Garg Subject: [PATCH v3 4/9] uart: sdm845: Fix debug UART pinmux Date: Tue, 12 Jul 2022 12:42:07 +0530 Message-Id: <20220712071212.2188390-5-sumit.garg@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220712071212.2188390-1-sumit.garg@linaro.org> References: <20220712071212.2188390-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Configure debug UART pins as function: "qup9" rather than being regular gpios. It fixes a hang seen during pinmux setting. Signed-off-by: Sumit Garg Reviewed-by: Ramon Fried --- arch/arm/dts/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi index b9506f1297..df5b6dfcfc 100644 --- a/arch/arm/dts/sdm845.dtsi +++ b/arch/arm/dts/sdm845.dtsi @@ -47,7 +47,7 @@ /* DEBUG UART */ qup_uart9: qup-uart9-default { pins = "GPIO_4", "GPIO_5"; - function = "gpio"; + function = "qup9"; }; }; From patchwork Tue Jul 12 07:12:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 589790 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp9053max; Tue, 12 Jul 2022 00:13:35 -0700 (PDT) X-Google-Smtp-Source: AGRyM1siEgbPhOzj7S8w5KcCEyyd1UJp1GGfHimYhONaoOadlZ4nl+U4emsOLU4cOKWpBEMaxerU X-Received: by 2002:a2e:5c1:0:b0:25d:46f3:ba5 with SMTP id 184-20020a2e05c1000000b0025d46f30ba5mr12586115ljf.156.1657610015739; Tue, 12 Jul 2022 00:13:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657610015; cv=none; d=google.com; s=arc-20160816; b=b+x2SWnn9VShvk3Iqv6eHeiakXIa/tPzz53xdw0Fp52rUwnDRyPIYgNEYqbwrQk0at G9sEfhbMcvWBiGSVupqH4qBhCGcTMYoHOZOzj836JojQDpgkIXDmUlFRv3ykzidfwXi6 8GbkR+ldOCNHor74POSRHdtR0SRz1rSZIM09lPSobbbctNSoFMvXR4vck07oEOjeIvuw wdkJFlDIb8AzAC3zOQPblCokjQ6gPugDzl90tt1+TbriWYQ1pjTGTwNaF29i9AMJwJzs ewEH2FxrwzcP2R93dUm51eqbpx98pAoZrIWsC75W6+UXnLqqYD9+VeCQWW0ugu2wiHno OluQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=E/TXvBCsPWhKaGGX7nMlwF3B8p3Id3ErUi/QXuDh4DI=; b=vxLKhSuzeLWcSxl7k7mwGBsWV57QGiF+0UAxC/DydLHQ2iDsCJFdsfsecUsE6N+4Nl V3lfcriEb5qMm6TZpXGKp8uMmpfEBCpGcav96Cqwg8BJnDKwfm4F/8jRnmJO4IEx/gns u5TGbcldI3KhQmkvV+kMNaZgOSVY0OWszcqK3DT1W6r5c0tOZGkxQRxOc52sEAT1AauQ 8hWHWdW43wLNq8Er8LfPHov5sBgr3FN2pPd1QxF8SZb8iddgzS3aXsWM0Ox/VhYFJ4ec 2KIkWaSHfB5pxK4KVAlBoastiyt/2tHkSGGpxj+9fA8V/QqeC67GG4L9hJUS8Lr08KBh V0xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I5+4i9ee; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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This board complies with 96Boards Open Platform Specifications. Features: - Qualcomm Snapdragon SDA845 SoC - 4GiB RAM - 64GiB UFS drive U-boot is chain loaded by ABL in 64-bit mode as part of boot.img. For detailed build and boot instructions, refer to doc/board/qualcomm/sdm845.rst, board: dragonboard845c. Signed-off-by: Sumit Garg Reviewed-by: Ramon Fried --- arch/arm/dts/dragonboard845c-uboot.dtsi | 37 +++++++ arch/arm/dts/dragonboard845c.dts | 44 ++++++++ arch/arm/mach-snapdragon/Kconfig | 14 +++ board/qualcomm/dragonboard845c/Kconfig | 12 +++ board/qualcomm/dragonboard845c/MAINTAINERS | 6 ++ board/qualcomm/dragonboard845c/Makefile | 9 ++ board/qualcomm/dragonboard845c/db845c.its | 63 +++++++++++ .../dragonboard845c/dragonboard845c.c | 9 ++ configs/dragonboard845c_defconfig | 28 +++++ doc/board/qualcomm/sdm845.rst | 100 +++++++++++++++--- include/configs/dragonboard845c.h | 28 +++++ 11 files changed, 337 insertions(+), 13 deletions(-) create mode 100644 arch/arm/dts/dragonboard845c-uboot.dtsi create mode 100644 arch/arm/dts/dragonboard845c.dts create mode 100644 board/qualcomm/dragonboard845c/Kconfig create mode 100644 board/qualcomm/dragonboard845c/MAINTAINERS create mode 100644 board/qualcomm/dragonboard845c/Makefile create mode 100644 board/qualcomm/dragonboard845c/db845c.its create mode 100644 board/qualcomm/dragonboard845c/dragonboard845c.c create mode 100644 configs/dragonboard845c_defconfig create mode 100644 include/configs/dragonboard845c.h diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi b/arch/arm/dts/dragonboard845c-uboot.dtsi new file mode 100644 index 0000000000..8b5a7ee573 --- /dev/null +++ b/arch/arm/dts/dragonboard845c-uboot.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot addition to handle Qualcomm Robotics RB3 Development Platform + * (dragonboard845c) pins + * + * (C) Copyright 2022 Sumit Garg + */ + +/ +{ + soc { + u-boot,dm-pre-reloc; + + serial@a84000 { + u-boot,dm-pre-reloc; + }; + + clock-controller@100000 { + u-boot,dm-pre-reloc; + }; + + pinctrl_north@3900000 { + u-boot,dm-pre-reloc; + }; + }; +}; + +&pm8998_pon { + key_vol_down { + gpios = <&pm8998_pon 1 0>; + label = "key_vol_down"; + }; + key_power { + gpios = <&pm8998_pon 0 0>; + label = "key_power"; + }; +}; diff --git a/arch/arm/dts/dragonboard845c.dts b/arch/arm/dts/dragonboard845c.dts new file mode 100644 index 0000000000..1722dce33f --- /dev/null +++ b/arch/arm/dts/dragonboard845c.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm Robotics RB3 Development (dragonboard845c) board device + * tree source + * + * (C) Copyright 2022 Sumit Garg + */ + +/dts-v1/; + +#include "sdm845.dtsi" + +/ { + model = "Thundercomm Dragonboard 845c"; + compatible = "thundercomm,db845c", "qcom,sdm845"; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &debug_uart; + }; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0xfdfa0000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc { + serial@a84000 { + status = "okay"; + }; + }; +}; + +#include "dragonboard845c-uboot.dtsi" diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 12cf02a56a..cb53dc8901 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -44,6 +44,19 @@ config TARGET_DRAGONBOARD820C - 3GiB RAM - 32GiB UFS drive +config TARGET_DRAGONBOARD845C + bool "96Boards Dragonboard 845C" + help + Support for 96Boards Dragonboard 845C aka Robotics RB3 Development + Platform. This board complies with 96Boards Open Platform + Specifications. Features: + - Qualcomm Snapdragon SDA845 SoC + - 4GiB RAM + - 64GiB UFS drive + select MISC_INIT_R + select SDM845 + select DM_ETH if NET + config TARGET_STARQLTECHN bool "Samsung S9 SM-G9600(starqltechn)" help @@ -60,6 +73,7 @@ endchoice source "board/qualcomm/dragonboard410c/Kconfig" source "board/qualcomm/dragonboard820c/Kconfig" +source "board/qualcomm/dragonboard845c/Kconfig" source "board/samsung/starqltechn/Kconfig" endif diff --git a/board/qualcomm/dragonboard845c/Kconfig b/board/qualcomm/dragonboard845c/Kconfig new file mode 100644 index 0000000000..52fdff288d --- /dev/null +++ b/board/qualcomm/dragonboard845c/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DRAGONBOARD845C + +config SYS_BOARD + default "dragonboard845c" + +config SYS_CONFIG_NAME + default "dragonboard845c" + +config SYS_VENDOR + default "qualcomm" + +endif diff --git a/board/qualcomm/dragonboard845c/MAINTAINERS b/board/qualcomm/dragonboard845c/MAINTAINERS new file mode 100644 index 0000000000..e555953df6 --- /dev/null +++ b/board/qualcomm/dragonboard845c/MAINTAINERS @@ -0,0 +1,6 @@ +Qualcomm Robotics RB3 Development Platform (dragonboard845c) +M: Sumit Garg +S: Maintained +F: board/qualcomm/dragonboard845c/ +F: include/configs/dragonboard845c.h +F: configs/dragonboard845c_defconfig diff --git a/board/qualcomm/dragonboard845c/Makefile b/board/qualcomm/dragonboard845c/Makefile new file mode 100644 index 0000000000..0abefdaf36 --- /dev/null +++ b/board/qualcomm/dragonboard845c/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Sumit Garg +# +# This empty file prevents make error. +# Board logic defined in board/qualcomm/common/sdm845.c, no custom logic for dragonboard845c so far. +# + +obj-y += dragonboard845c.o diff --git a/board/qualcomm/dragonboard845c/db845c.its b/board/qualcomm/dragonboard845c/db845c.its new file mode 100644 index 0000000000..a2621340d1 --- /dev/null +++ b/board/qualcomm/dragonboard845c/db845c.its @@ -0,0 +1,63 @@ +/* + * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs + */ + +/dts-v1/; + +/ { + description = "Various kernels, ramdisks and FDT blobs"; + #address-cells = <1>; + + images { + kernel-1 { + description = "5.15.0-qcomlt-arm64"; + data = /incbin/("./db845c_imgs/Image.gz--5.15-r0-dragonboard-845c-20211218193034-511.bin"); + type = "kernel"; + arch = "arm64"; + os = "linux"; + compression = "gzip"; + load = <0x80000000>; + entry = <0x80000000>; + hash-1 { + algo = "sha1"; + }; + }; + + ramdisk-1 { + description = "initramfs-test-full-image-dragonboard-845c"; + data = /incbin/("./db845c_imgs/initramfs-test-full-image-dragonboard-845c-20211218193034-511.rootfs.cpio.gz"); + type = "ramdisk"; + arch = "arm64"; + os = "linux"; + compression = "gzip"; + load = <00000000>; + entry = <00000000>; + hash-1 { + algo = "sha1"; + }; + }; + + fdt-1 { + description = "sdm845-db845c-fdt"; + data = /incbin/("./db845c_imgs/sdm845-db845c--5.15-r0-dragonboard-845c-20211218193034.dtb"); + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + hash-1 { + algo = "sha1"; + }; + }; + + }; + + configurations { + default = "config-1"; + + config-1 { + description = "db845c kernel-5.15.0 configuration"; + kernel = "kernel-1"; + ramdisk = "ramdisk-1"; + fdt = "fdt-1"; + }; + }; +}; diff --git a/board/qualcomm/dragonboard845c/dragonboard845c.c b/board/qualcomm/dragonboard845c/dragonboard845c.c new file mode 100644 index 0000000000..c7685de306 --- /dev/null +++ b/board/qualcomm/dragonboard845c/dragonboard845c.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This empty file prevents make linking error. + * No custom logic for dragonboard845c so far. + * + * (C) Copyright 2022 Sumit Garg + */ + +void noop(void) {} diff --git a/configs/dragonboard845c_defconfig b/configs/dragonboard845c_defconfig new file mode 100644 index 0000000000..a19e46a74b --- /dev/null +++ b/configs/dragonboard845c_defconfig @@ -0,0 +1,28 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=19000000 +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_SNAPDRAGON=y +CONFIG_DEFAULT_DEVICE_TREE="dragonboard845c" +CONFIG_TARGET_DRAGONBOARD845C=y +CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 845C" +CONFIG_SYS_LOAD_ADDR=0x80000000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTDELAY=5 +CONFIG_SAVE_PREV_BL_FDT_ADDR=y +CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_BMP=y +# CONFIG_NET is not set +CONFIG_CLK=y +CONFIG_MSM_GPIO=y +CONFIG_PM8916_GPIO=y +CONFIG_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_PM8916=y +CONFIG_MSM_GENI_SERIAL=y +CONFIG_SPMI_MSM=y +CONFIG_LMB_MAX_REGIONS=64 diff --git a/doc/board/qualcomm/sdm845.rst b/doc/board/qualcomm/sdm845.rst index b6642c9579..8ef4749287 100644 --- a/doc/board/qualcomm/sdm845.rst +++ b/doc/board/qualcomm/sdm845.rst @@ -35,9 +35,25 @@ Pack android boot image ^^^^^^^^^^^^^^^^^^^^^^^ We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel, and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel -with appended dtb, so let's mimic linux to satisfy stock bootloader: +with appended dtb, so let's mimic linux to satisfy stock bootloader. -- create dump dtb:: +Boards +------------ +starqlte +^^^^^^^^^^^^ + +The starqltechn is a production board for Samsung S9 (SM-G9600) phone, +based on the Qualcomm SDM845 SoC. + +Steps: + +- Build u-boot:: + + $ export CROSS_COMPILE= + $ make starqltechn_defconfig + $ make + +- Create dump dtb:: workdir=/tmp/prepare_payload mkdir -p "$workdir" @@ -56,10 +72,15 @@ with appended dtb, so let's mimic linux to satisfy stock bootloader: }; EOF -- gzip u-boot ``gzip u-boot.bin`` -- append dtb to gzipped u-boot: ``cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb`` +- gzip u-boot:: + + gzip u-boot.bin -Now we've got everything to build android boot image::: +- Append dtb to gzipped u-boot:: + + cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb + +- Now we've got everything to build android boot image:: mkbootimg --base 0x0 --kernel_offset 0x00008000 \ --ramdisk_offset 0x02000000 --tags_offset 0x01e00000 \ @@ -68,16 +89,69 @@ Now we've got everything to build android boot image::: --kernel u-boot.bin.gz-dtb \ -o boot.img -Flash image with your phone's flashing method. +- Flash image with your phone's flashing method. -Boards ------------- -starqlte -^^^^^^^^^^^^ +More information can be found on the `Samsung S9 page`_. -The starqltechn is a production board for Samsung S9 (SM-G9600) phone, -based on the Qualcomm SDM845 SoC. +dragonboard845c +^^^^^^^^^^^^^^^ -More information can be found on the `Samsung S9 page`_. +The dragonboard845c is a Qualcomm Robotics RB3 Development Platform, based on +the Qualcomm SDM845 SoC. + +Steps: + +- Build u-boot:: + + $ export CROSS_COMPILE= + $ make dragonboard845c_defconfig + $ make + +- Create dummy dtb:: + + workdir=/tmp/prepare_payload + mkdir -p "$workdir" + mock_dtb="$workdir"/payload_mock.dtb + + dtc -I dts -O dtb -o "$mock_dtb" << EOF + /dts-v1/; + / { + #address-cells = <2>; + #size-cells = <2>; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + chosen { }; + }; + EOF + +- gzip u-boot:: + + gzip u-boot.bin + +- Append dtb to gzipped u-boot:: + + cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb + +- A ``db845c.its`` file can be found in ``board/qualcomm/dragonboard845c/`` + directory. It expects a folder as ``db845c_imgs/`` in the main directory + containing pre-built kernel, dts and ramdisk images. See ``db845c.its`` + for full path to images:: + + mkimage -f db845c.its db845c.itb + +- Now we've got everything to build android boot image:: + + mkbootimg --kernel u-boot.bin.gz-dtb --ramdisk db845c.itb \ + --output boot.img --pagesize 4096 --base 0x80000000 + +- Flash boot.img using db845c fastboot method. + +More information can be found on the `DragonBoard 845c page`_. .. _Samsung S9 page: https://en.wikipedia.org/wiki/Samsung_Galaxy_S9 +.. _DragonBoard 845c page: https://www.96boards.org/product/rb3-platform/ diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h new file mode 100644 index 0000000000..108dde199b --- /dev/null +++ b/include/configs/dragonboard845c.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for Dragonboard 845c, based on Qualcomm SDA845 chip + * + * (C) Copyright 2022 Sumit Garg + */ + +#ifndef __CONFIGS_SDM845_H +#define __CONFIGS_SDM845_H + +#include +#include + +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x5000000\0" \ + "bootm_low=0x80000000\0" \ + "bootcmd=bootm $prevbl_initrd_start_addr\0" + +/* Size of malloc() pool */ +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 64 + +#endif From patchwork Tue Jul 12 07:12:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 589792 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp9270max; Tue, 12 Jul 2022 00:14:08 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vkV1u0F7jOGY2rJrrqj8I59i/Fge+BZG4XKGREpRg1JKQx5LaZLKzUiPgQs5tzwrAQbms7 X-Received: by 2002:a05:651c:154a:b0:25d:7a5c:b854 with SMTP id y10-20020a05651c154a00b0025d7a5cb854mr854225ljp.193.1657610048144; Tue, 12 Jul 2022 00:14:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657610048; cv=none; d=google.com; s=arc-20160816; b=HYx0wgNIR2IQCnflXu8fVNTNji7Jgi1PV5YDA0Wtq50xbZZkX3q1EmQ9veTFet+JH8 w6BBGHFtdPFOoTmmmsQ7hHaLmZ2QTq0ed7MhVnfLHZHhwuSRY/7xnY09W+hEowqFWXOD nu0y/bbvKewmHclb9V/GJtY/yG+RJCGZ4/5gcipbMNJ7FIS9X3u656l2/7HrPrnldSyn otBQneY0qUwqHarYG3pJWztyTMZ31iGp9NXtgyt3RAaxlOq9TqRJ1x5X2/A3o1kT6L/N Bi7/Vnmy9B5MIJKvrUUmsZywkpmT2YaKBA6asy6cFGRMa88Pzl82vn3pWVv5lhw7hR4F wHYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Meq/9myZlZI/0FAOKLfCfPeH8NoYyvt4UlP0TUcyWxE=; b=JCHKXdmdjpBV3mELUDG0/rCpKIHwMNFQgkGgrup+sHBz37kL6wm/TiDfU3YqKaT508 7gepgnpfAxsWUSNZAfuX+J/QEYK07lT6RWtxtcWof0cgR6a9/armM9PrahtLTr7t5U1g KGsnavtuUJdGVHhdh2LK5EgyNYV0T19UrD6En0II+4NI6puJs6wUrySPOAJqbbiXH1UU M+25dxO9kK1gij7lRJrFHjeDeJmAOd/q8I9n9+EuUy2dl9CukQ4WMPwP7WsjjOiZGg2n jdzWPOUJ6dPfspw+1ebjuLAT/1RCG75eK6BHKRZPYlHjPycdkWHdSfVYlUVovmo8ruZc avaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yXjmGb2n; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Tue, 12 Jul 2022 00:12:52 -0700 (PDT) Received: from localhost.localdomain ([27.56.177.217]) by smtp.gmail.com with ESMTPSA id x10-20020a170902a38a00b001678ce9080dsm5928843pla.258.2022.07.12.00.12.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 00:12:52 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, peng.fan@nxp.com, jh80.chung@samsung.com, sjg@chromium.org, trini@konsulko.com, dsankouski@gmail.com, stephan@gerhold.net, vinod.koul@linaro.org, nicolas.dechesne@linaro.org, mworsfold@impinj.com, daniel.thompson@linaro.org, pbrobinson@gmail.com, Sumit Garg Subject: [PATCH v3 6/9] mmc: msm_sdhci: Add SDCC version 5.0.0 support Date: Tue, 12 Jul 2022 12:42:09 +0530 Message-Id: <20220712071212.2188390-7-sumit.garg@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220712071212.2188390-1-sumit.garg@linaro.org> References: <20220712071212.2188390-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean For SDCC version 5.0.0, MCI registers are removed from SDCC interface and some registers are moved to HC. So add support to use the new compatible string "qcom,sdhci-msm-v5". Based on this new msm variant, pick the relevant variant data and use it to detect MCI presence thereby configuring register read/write to msm specific registers. Signed-off-by: Sumit Garg Reviewed-by: Ramon Fried --- drivers/mmc/msm_sdhci.c | 96 +++++++++++++++++++++++++++-------------- 1 file changed, 64 insertions(+), 32 deletions(-) diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index d63d7b3a2c..604f9c3ff9 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -22,18 +22,17 @@ #define SDCC_MCI_POWER_SW_RST BIT(7) /* This is undocumented register */ -#define SDCC_MCI_VERSION 0x50 -#define SDCC_MCI_VERSION_MAJOR_SHIFT 28 -#define SDCC_MCI_VERSION_MAJOR_MASK (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT) -#define SDCC_MCI_VERSION_MINOR_MASK 0xff +#define SDCC_MCI_VERSION 0x50 +#define SDCC_V5_VERSION 0x318 + +#define SDCC_VERSION_MAJOR_SHIFT 28 +#define SDCC_VERSION_MAJOR_MASK (0xf << SDCC_VERSION_MAJOR_SHIFT) +#define SDCC_VERSION_MINOR_MASK 0xff #define SDCC_MCI_STATUS2 0x6C #define SDCC_MCI_STATUS2_MCI_ACT 0x1 #define SDCC_MCI_HC_MODE 0x78 -/* Offset to SDHCI registers */ -#define SDCC_SDHCI_OFFSET 0x900 - /* Non standard (?) SDHCI register */ #define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c @@ -47,6 +46,10 @@ struct msm_sdhc { void *base; }; +struct msm_sdhc_variant_info { + bool mci_removed; +}; + DECLARE_GLOBAL_DATA_PTR; static int msm_sdc_clk_init(struct udevice *dev) @@ -85,25 +88,8 @@ static int msm_sdc_clk_init(struct udevice *dev) return 0; } -static int msm_sdc_probe(struct udevice *dev) +static int msm_sdc_mci_init(struct msm_sdhc *prv) { - struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); - struct msm_sdhc_plat *plat = dev_get_plat(dev); - struct msm_sdhc *prv = dev_get_priv(dev); - struct sdhci_host *host = &prv->host; - u32 core_version, core_minor, core_major; - u32 caps; - int ret; - - host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; - - host->max_clk = 0; - - /* Init clocks */ - ret = msm_sdc_clk_init(dev); - if (ret) - return ret; - /* Reset the core and Enable SDHC mode */ writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST, prv->base + SDCC_MCI_POWER); @@ -126,12 +112,45 @@ static int msm_sdc_probe(struct udevice *dev) /* Enable host-controller mode */ writel(1, prv->base + SDCC_MCI_HC_MODE); - core_version = readl(prv->base + SDCC_MCI_VERSION); + return 0; +} - core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK); - core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT; +static int msm_sdc_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct msm_sdhc_plat *plat = dev_get_plat(dev); + struct msm_sdhc *prv = dev_get_priv(dev); + const struct msm_sdhc_variant_info *var_info; + struct sdhci_host *host = &prv->host; + u32 core_version, core_minor, core_major; + u32 caps; + int ret; - core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK; + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; + + host->max_clk = 0; + + /* Init clocks */ + ret = msm_sdc_clk_init(dev); + if (ret) + return ret; + + var_info = (void *)dev_get_driver_data(dev); + if (!var_info->mci_removed) { + ret = msm_sdc_mci_init(prv); + if (ret) + return ret; + } + + if (!var_info->mci_removed) + core_version = readl(prv->base + SDCC_MCI_VERSION); + else + core_version = readl(host->ioaddr + SDCC_V5_VERSION); + + core_major = (core_version & SDCC_VERSION_MAJOR_MASK); + core_major >>= SDCC_VERSION_MAJOR_SHIFT; + + core_minor = core_version & SDCC_VERSION_MINOR_MASK; /* * Support for some capabilities is not advertised by newer @@ -161,9 +180,13 @@ static int msm_sdc_probe(struct udevice *dev) static int msm_sdc_remove(struct udevice *dev) { struct msm_sdhc *priv = dev_get_priv(dev); + const struct msm_sdhc_variant_info *var_info; + + var_info = (void *)dev_get_driver_data(dev); - /* Disable host-controller mode */ - writel(0, priv->base + SDCC_MCI_HC_MODE); + /* Disable host-controller mode */ + if (!var_info->mci_removed) + writel(0, priv->base + SDCC_MCI_HC_MODE); return 0; } @@ -195,8 +218,17 @@ static int msm_sdc_bind(struct udevice *dev) return sdhci_bind(dev, &plat->mmc, &plat->cfg); } +static const struct msm_sdhc_variant_info msm_sdhc_mci_var = { + .mci_removed = false, +}; + +static const struct msm_sdhc_variant_info msm_sdhc_v5_var = { + .mci_removed = true, +}; + static const struct udevice_id msm_mmc_ids[] = { - { .compatible = "qcom,sdhci-msm-v4" }, + { .compatible = "qcom,sdhci-msm-v4", .data = (ulong)&msm_sdhc_mci_var }, + { .compatible = "qcom,sdhci-msm-v5", .data = (ulong)&msm_sdhc_v5_var }, { } }; From patchwork Tue Jul 12 07:12:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 589791 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5817:0:0:0:0 with SMTP id j23csp9153max; Tue, 12 Jul 2022 00:13:49 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sgjlrkrwtf2IqLF6HpaPf5VAgTmu69d1YNOaWao1vfizZPf8i5zMCEi0DwQ1c1XNYQn24k X-Received: by 2002:ac2:4c42:0:b0:482:cb18:25ac with SMTP id o2-20020ac24c42000000b00482cb1825acmr14555665lfk.643.1657610029371; Tue, 12 Jul 2022 00:13:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657610029; cv=none; d=google.com; s=arc-20160816; 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Signed-off-by: Sumit Garg Reviewed-by: Ramon Fried --- arch/arm/mach-snapdragon/Makefile | 1 + arch/arm/mach-snapdragon/pinctrl-qcs404.c | 55 +++++++++++++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 + arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 + 4 files changed, 58 insertions(+) create mode 100644 arch/arm/mach-snapdragon/pinctrl-qcs404.c diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 962855eb8c..cb8c1aa8d2 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -15,4 +15,5 @@ obj-y += dram.o obj-y += pinctrl-snapdragon.o obj-y += pinctrl-apq8016.o obj-y += pinctrl-apq8096.o +obj-y += pinctrl-qcs404.o obj-$(CONFIG_SDM845) += pinctrl-sdm845.o diff --git a/arch/arm/mach-snapdragon/pinctrl-qcs404.c b/arch/arm/mach-snapdragon/pinctrl-qcs404.c new file mode 100644 index 0000000000..889ead0f57 --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-qcs404.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm QCS404 pinctrl + * + * (C) Copyright 2022 Sumit Garg + */ + +#include "pinctrl-snapdragon.h" +#include + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); +static const char * const msm_pinctrl_pins[] = { + "SDC1_RCLK", + "SDC1_CLK", + "SDC1_CMD", + "SDC1_DATA", + "SDC2_CLK", + "SDC2_CMD", + "SDC2_DATA", +}; + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"blsp_uart2", 1}, +}; + +static const char *qcs404_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *qcs404_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + if (selector < 120) { + snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + return pin_name; + } else { + return msm_pinctrl_pins[selector - 120]; + } +} + +static unsigned int qcs404_get_function_mux(unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data qcs404_data = { + .pin_count = 126, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = qcs404_get_function_name, + .get_function_mux = qcs404_get_function_mux, + .get_pin_name = qcs404_get_pin_name, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index d1c560dd40..c2148a5d0a 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -119,6 +119,7 @@ static const struct udevice_id msm_pinctrl_ids[] = { #ifdef CONFIG_SDM845 { .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data }, #endif + { .compatible = "qcom,tlmm-qcs404", .data = (ulong)&qcs404_data }, { } }; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h index ea524312a0..178ee01a41 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h @@ -28,5 +28,6 @@ struct pinctrl_function { extern struct msm_pinctrl_data apq8016_data; extern struct msm_pinctrl_data apq8096_data; extern struct msm_pinctrl_data sdm845_data; +extern struct msm_pinctrl_data qcs404_data; #endif From patchwork Tue Jul 12 07:12:11 2022 Content-Type: text/plain; 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Along with this import "qcom,gcc-qcs404.h" header from Linux mainline to support DT bindings. Signed-off-by: Sumit Garg --- arch/arm/mach-snapdragon/clock-qcs404.c | 79 ++++++++ arch/arm/mach-snapdragon/clock-snapdragon.c | 1 + .../include/mach/sysmap-qcs404.h | 40 ++++ include/dt-bindings/clock/qcom,gcc-qcs404.h | 180 ++++++++++++++++++ 4 files changed, 300 insertions(+) create mode 100644 arch/arm/mach-snapdragon/clock-qcs404.c create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h create mode 100644 include/dt-bindings/clock/qcom,gcc-qcs404.h diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c b/arch/arm/mach-snapdragon/clock-qcs404.c new file mode 100644 index 0000000000..bb8a6fe067 --- /dev/null +++ b/arch/arm/mach-snapdragon/clock-qcs404.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm QCS404 + * + * (C) Copyright 2022 Sumit Garg + */ + +#include +#include +#include +#include +#include +#include +#include "clock-snapdragon.h" + +#include + +/* GPLL0 clock control registers */ +#define GPLL0_STATUS_ACTIVE BIT(31) + +static struct vote_clk gcc_blsp1_ahb_clk = { + .cbcr_reg = BLSP1_AHB_CBCR, + .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE, + .vote_bit = BIT(10) | BIT(5) | BIT(4), +}; + +static const struct bcr_regs uart2_regs = { + .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR, + .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR, + .M = BLSP1_UART2_APPS_M, + .N = BLSP1_UART2_APPS_N, + .D = BLSP1_UART2_APPS_D, +}; + +static const struct bcr_regs sdc_regs = { + .cfg_rcgr = SDCC_CFG_RCGR(1), + .cmd_rcgr = SDCC_CMD_RCGR(1), + .M = SDCC_M(1), + .N = SDCC_N(1), + .D = SDCC_D(1), +}; + +static struct pll_vote_clk gpll0_vote_clk = { + .status = GPLL0_STATUS, + .status_bit = GPLL0_STATUS_ACTIVE, + .ena_vote = APCS_GPLL_ENA_VOTE, + .vote_bit = BIT(0), +}; + +ulong msm_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case GCC_BLSP1_UART2_APPS_CLK: + /* UART: 115200 */ + clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125, + CFG_CLK_SRC_CXO); + clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); + break; + case GCC_BLSP1_AHB_CLK: + clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk); + break; + case GCC_SDCC1_APPS_CLK: + /* SDCC1: 200MHz */ + clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0, + CFG_CLK_SRC_GPLL0); + clk_enable_gpll0(priv->base, &gpll0_vote_clk); + clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); + break; + case GCC_SDCC1_AHB_CLK: + clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1)); + break; + default: + return 0; + } + + return 0; +} diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index 3deb08ac4a..5652d2fa36 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -136,6 +136,7 @@ static const struct udevice_id msm_clk_ids[] = { { .compatible = "qcom,gcc-msm8996" }, { .compatible = "qcom,gcc-apq8096" }, { .compatible = "qcom,gcc-sdm845" }, + { .compatible = "qcom,gcc-qcs404" }, { } }; diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h new file mode 100644 index 0000000000..4dc96b9fbc --- /dev/null +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Qualcomm QCS404 sysmap + * + * (C) Copyright 2022 Sumit Garg + */ +#ifndef _MACH_SYSMAP_QCS404_H +#define _MACH_SYSMAP_QCS404_H + +#define GICD_BASE (0x0b000000) +#define GICC_BASE (0x0b002000) + +/* Clocks: (from CLK_CTL_BASE) */ +#define GPLL0_STATUS (0x21000) +#define APCS_GPLL_ENA_VOTE (0x45000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) + +/* BLSP1 AHB clock (root clock for BLSP) */ +#define BLSP1_AHB_CBCR 0x1008 + +/* Uart clock control registers */ +#define BLSP1_UART2_BCR (0x3028) +#define BLSP1_UART2_APPS_CBCR (0x302C) +#define BLSP1_UART2_APPS_CMD_RCGR (0x3034) +#define BLSP1_UART2_APPS_CFG_RCGR (0x3038) +#define BLSP1_UART2_APPS_M (0x303C) +#define BLSP1_UART2_APPS_N (0x3040) +#define BLSP1_UART2_APPS_D (0x3044) + +/* SD controller clock control registers */ +#define SDCC_BCR(n) (((n) * 0x1000) + 0x41000) +#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004) +#define SDCC_CFG_RCGR(n) (((n) * 0x1000) + 0x41008) +#define SDCC_M(n) (((n) * 0x1000) + 0x4100C) +#define SDCC_N(n) (((n) * 0x1000) + 0x41010) +#define SDCC_D(n) (((n) * 0x1000) + 0x41014) +#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018) +#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C) + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h new file mode 100644 index 0000000000..bc30515433 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H +#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H + +#define GCC_APSS_AHB_CLK_SRC 0 +#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1 +#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10 +#define GCC_BLSP1_UART0_APPS_CLK_SRC 11 +#define GCC_BLSP1_UART1_APPS_CLK_SRC 12 +#define GCC_BLSP1_UART2_APPS_CLK_SRC 13 +#define GCC_BLSP1_UART3_APPS_CLK_SRC 14 +#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15 +#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16 +#define GCC_BLSP2_UART0_APPS_CLK_SRC 17 +#define GCC_BYTE0_CLK_SRC 18 +#define GCC_EMAC_CLK_SRC 19 +#define GCC_EMAC_PTP_CLK_SRC 20 +#define GCC_ESC0_CLK_SRC 21 +#define GCC_APSS_AHB_CLK 22 +#define GCC_APSS_AXI_CLK 23 +#define GCC_BIMC_APSS_AXI_CLK 24 +#define GCC_BIMC_GFX_CLK 25 +#define GCC_BIMC_MDSS_CLK 26 +#define GCC_BLSP1_AHB_CLK 27 +#define GCC_BLSP1_QUP0_I2C_APPS_CLK 28 +#define GCC_BLSP1_QUP0_SPI_APPS_CLK 29 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 30 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 31 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 32 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 33 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 34 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 35 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 36 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 37 +#define GCC_BLSP1_UART0_APPS_CLK 38 +#define GCC_BLSP1_UART1_APPS_CLK 39 +#define GCC_BLSP1_UART2_APPS_CLK 40 +#define GCC_BLSP1_UART3_APPS_CLK 41 +#define GCC_BLSP2_AHB_CLK 42 +#define GCC_BLSP2_QUP0_I2C_APPS_CLK 43 +#define GCC_BLSP2_QUP0_SPI_APPS_CLK 44 +#define GCC_BLSP2_UART0_APPS_CLK 45 +#define GCC_BOOT_ROM_AHB_CLK 46 +#define GCC_DCC_CLK 47 +#define GCC_GENI_IR_H_CLK 48 +#define GCC_ETH_AXI_CLK 49 +#define GCC_ETH_PTP_CLK 50 +#define GCC_ETH_RGMII_CLK 51 +#define GCC_ETH_SLAVE_AHB_CLK 52 +#define GCC_GENI_IR_S_CLK 53 +#define GCC_GP1_CLK 54 +#define GCC_GP2_CLK 55 +#define GCC_GP3_CLK 56 +#define GCC_MDSS_AHB_CLK 57 +#define GCC_MDSS_AXI_CLK 58 +#define GCC_MDSS_BYTE0_CLK 59 +#define GCC_MDSS_ESC0_CLK 60 +#define GCC_MDSS_HDMI_APP_CLK 61 +#define GCC_MDSS_HDMI_PCLK_CLK 62 +#define GCC_MDSS_MDP_CLK 63 +#define GCC_MDSS_PCLK0_CLK 64 +#define GCC_MDSS_VSYNC_CLK 65 +#define GCC_OXILI_AHB_CLK 66 +#define GCC_OXILI_GFX3D_CLK 67 +#define GCC_PCIE_0_AUX_CLK 68 +#define GCC_PCIE_0_CFG_AHB_CLK 69 +#define GCC_PCIE_0_MSTR_AXI_CLK 70 +#define GCC_PCIE_0_PIPE_CLK 71 +#define GCC_PCIE_0_SLV_AXI_CLK 72 +#define GCC_PCNOC_USB2_CLK 73 +#define GCC_PCNOC_USB3_CLK 74 +#define GCC_PDM2_CLK 75 +#define GCC_PDM_AHB_CLK 76 +#define GCC_VSYNC_CLK_SRC 77 +#define GCC_PRNG_AHB_CLK 78 +#define GCC_PWM0_XO512_CLK 79 +#define GCC_PWM1_XO512_CLK 80 +#define GCC_PWM2_XO512_CLK 81 +#define GCC_SDCC1_AHB_CLK 82 +#define GCC_SDCC1_APPS_CLK 83 +#define GCC_SDCC1_ICE_CORE_CLK 84 +#define GCC_SDCC2_AHB_CLK 85 +#define GCC_SDCC2_APPS_CLK 86 +#define GCC_SYS_NOC_USB3_CLK 87 +#define GCC_USB20_MOCK_UTMI_CLK 88 +#define GCC_USB2A_PHY_SLEEP_CLK 89 +#define GCC_USB30_MASTER_CLK 90 +#define GCC_USB30_MOCK_UTMI_CLK 91 +#define GCC_USB30_SLEEP_CLK 92 +#define GCC_USB3_PHY_AUX_CLK 93 +#define GCC_USB3_PHY_PIPE_CLK 94 +#define GCC_USB_HS_PHY_CFG_AHB_CLK 95 +#define GCC_USB_HS_SYSTEM_CLK 96 +#define GCC_GFX3D_CLK_SRC 97 +#define GCC_GP1_CLK_SRC 98 +#define GCC_GP2_CLK_SRC 99 +#define GCC_GP3_CLK_SRC 100 +#define GCC_GPLL0_OUT_MAIN 101 +#define GCC_GPLL1_OUT_MAIN 102 +#define GCC_GPLL3_OUT_MAIN 103 +#define GCC_GPLL4_OUT_MAIN 104 +#define GCC_HDMI_APP_CLK_SRC 105 +#define GCC_HDMI_PCLK_CLK_SRC 106 +#define GCC_MDP_CLK_SRC 107 +#define GCC_PCIE_0_AUX_CLK_SRC 108 +#define GCC_PCIE_0_PIPE_CLK_SRC 109 +#define GCC_PCLK0_CLK_SRC 110 +#define GCC_PDM2_CLK_SRC 111 +#define GCC_SDCC1_APPS_CLK_SRC 112 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 113 +#define GCC_SDCC2_APPS_CLK_SRC 114 +#define GCC_USB20_MOCK_UTMI_CLK_SRC 115 +#define GCC_USB30_MASTER_CLK_SRC 116 +#define GCC_USB30_MOCK_UTMI_CLK_SRC 117 +#define GCC_USB3_PHY_AUX_CLK_SRC 118 +#define GCC_USB_HS_SYSTEM_CLK_SRC 119 +#define GCC_GPLL0_AO_CLK_SRC 120 +#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122 +#define GCC_GPLL0_AO_OUT_MAIN 123 +#define GCC_GPLL0_SLEEP_CLK_SRC 124 +#define GCC_GPLL6 125 +#define GCC_GPLL6_OUT_AUX 126 +#define GCC_MDSS_MDP_VOTE_CLK 127 +#define GCC_MDSS_ROTATOR_VOTE_CLK 128 +#define GCC_BIMC_GPU_CLK 129 +#define GCC_GTCU_AHB_CLK 130 +#define GCC_GFX_TCU_CLK 131 +#define GCC_GFX_TBU_CLK 132 +#define GCC_SMMU_CFG_CLK 133 +#define GCC_APSS_TCU_CLK 134 +#define GCC_CRYPTO_AHB_CLK 135 +#define GCC_CRYPTO_AXI_CLK 136 +#define GCC_CRYPTO_CLK 137 +#define GCC_MDP_TBU_CLK 138 +#define GCC_QDSS_DAP_CLK 139 +#define GCC_DCC_XO_CLK 140 +#define GCC_WCSS_Q6_AHB_CLK 141 +#define GCC_WCSS_Q6_AXIM_CLK 142 +#define GCC_CDSP_CFG_AHB_CLK 143 +#define GCC_BIMC_CDSP_CLK 144 +#define GCC_CDSP_TBU_CLK 145 +#define GCC_CDSP_BIMC_CLK_SRC 146 + +#define GCC_GENI_IR_BCR 0 +#define GCC_USB_HS_BCR 1 +#define GCC_USB2_HS_PHY_ONLY_BCR 2 +#define GCC_QUSB2_PHY_BCR 3 +#define GCC_USB_HS_PHY_CFG_AHB_BCR 4 +#define GCC_USB2A_PHY_BCR 5 +#define GCC_USB3_PHY_BCR 6 +#define GCC_USB_30_BCR 7 +#define GCC_USB3PHY_PHY_BCR 8 +#define GCC_PCIE_0_BCR 9 +#define GCC_PCIE_0_PHY_BCR 10 +#define GCC_PCIE_0_LINK_DOWN_BCR 11 +#define GCC_PCIEPHY_0_PHY_BCR 12 +#define GCC_EMAC_BCR 13 +#define GCC_CDSP_RESTART 14 +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15 +#define GCC_PCIE_0_AHB_ARES 16 +#define GCC_PCIE_0_AXI_SLAVE_ARES 17 +#define GCC_PCIE_0_AXI_MASTER_ARES 18 +#define GCC_PCIE_0_CORE_STICKY_ARES 19 +#define GCC_PCIE_0_SLEEP_ARES 20 +#define GCC_PCIE_0_PIPE_ARES 21 +#define GCC_WDSP_RESTART 22 + +#endif From patchwork Tue Jul 12 07:12:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit 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Features: - Qualcomm Snapdragon QCS404 SoC - 1GiB RAM - 8GiB eMMC, uSD slot U-boot is chain loaded by ABL in 64-bit mode as part of boot.img. For detailed build and boot instructions, refer to doc/board/qualcomm/qcs404.rst. Signed-off-by: Sumit Garg --- arch/arm/dts/Makefile | 1 + arch/arm/dts/qcs404-evb-uboot.dtsi | 24 +++++++ arch/arm/dts/qcs404-evb.dts | 81 ++++++++++++++++++++++++ arch/arm/mach-snapdragon/Kconfig | 11 ++++ arch/arm/mach-snapdragon/Makefile | 2 + arch/arm/mach-snapdragon/sysmap-qcs404.c | 31 +++++++++ board/qualcomm/qcs404-evb/Kconfig | 15 +++++ board/qualcomm/qcs404-evb/MAINTAINERS | 6 ++ board/qualcomm/qcs404-evb/Makefile | 6 ++ board/qualcomm/qcs404-evb/qcs404-evb.c | 33 ++++++++++ board/qualcomm/qcs404-evb/qcs404-evb.its | 64 +++++++++++++++++++ configs/qcs404evb_defconfig | 39 ++++++++++++ doc/board/qualcomm/index.rst | 1 + doc/board/qualcomm/qcs404.rst | 79 +++++++++++++++++++++++ include/configs/qcs404-evb.h | 27 ++++++++ 15 files changed, 420 insertions(+) create mode 100644 arch/arm/dts/qcs404-evb-uboot.dtsi create mode 100644 arch/arm/dts/qcs404-evb.dts create mode 100644 arch/arm/mach-snapdragon/sysmap-qcs404.c create mode 100644 board/qualcomm/qcs404-evb/Kconfig create mode 100644 board/qualcomm/qcs404-evb/MAINTAINERS create mode 100644 board/qualcomm/qcs404-evb/Makefile create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.c create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.its create mode 100644 configs/qcs404evb_defconfig create mode 100644 doc/board/qualcomm/qcs404.rst create mode 100644 include/configs/qcs404-evb.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a7e0d9f6c0..a561b28cef 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -502,6 +502,7 @@ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb +dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb diff --git a/arch/arm/dts/qcs404-evb-uboot.dtsi b/arch/arm/dts/qcs404-evb-uboot.dtsi new file mode 100644 index 0000000000..c18080a483 --- /dev/null +++ b/arch/arm/dts/qcs404-evb-uboot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot addition to handle QCS404 EVB pre-relocation devices + * + * (C) Copyright 2022 Sumit Garg + */ + +/ { + soc { + u-boot,dm-pre-reloc; + + pinctrl_north@1300000 { + u-boot,dm-pre-reloc; + }; + + clock-controller@1800000 { + u-boot,dm-pre-reloc; + }; + + serial@78b1000 { + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts new file mode 100644 index 0000000000..4f0ae20bdb --- /dev/null +++ b/arch/arm/dts/qcs404-evb.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm QCS404 based evaluation board device tree source + * + * (C) Copyright 2022 Sumit Garg + */ + +/dts-v1/; + +#include "skeleton64.dtsi" +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. QCS404 EVB"; + compatible = "qcom,qcs404-evb", "qcom,qcs404"; + #address-cells = <0x2>; + #size-cells = <0x2>; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &debug_uart; + }; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + soc { + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0x0 0x0 0x0 0xffffffff>; + compatible = "simple-bus"; + + pinctrl_north@1300000 { + compatible = "qcom,tlmm-qcs404"; + reg = <0x1300000 0x200000>; + + blsp1_uart2: uart { + pins = "GPIO_17", "GPIO_18"; + function = "blsp_uart2"; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-qcs404"; + reg = <0x1800000 0x80000>; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + debug_uart: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4"; + reg = <0x78b1000 0x200>; + clock = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + bit-rate = <0xFF>; + pinctrl-names = "uart"; + pinctrl-0 = <&blsp1_uart2>; + }; + + sdhci@7804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x7804000 0x1000 0x7805000 0x1000>; + clock = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + bus-width = <0x8>; + index = <0x0>; + non-removable; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + }; + }; +}; + +#include "qcs404-evb-uboot.dtsi" diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index cb53dc8901..0927333306 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -69,11 +69,22 @@ config TARGET_STARQLTECHN select SDM845 select DM_ETH if NET +config TARGET_QCS404EVB + bool "Qualcomm Technologies, Inc. QCS404 EVB" + select LINUX_KERNEL_IMAGE_HEADER + help + Support for Qualcomm Technologies, Inc. QCS404 evaluation board. + Features: + - Qualcomm Snapdragon QCS404 SoC + - 1GiB RAM + - 8GiB eMMC, uSD slot + endchoice source "board/qualcomm/dragonboard410c/Kconfig" source "board/qualcomm/dragonboard820c/Kconfig" source "board/qualcomm/dragonboard845c/Kconfig" source "board/samsung/starqltechn/Kconfig" +source "board/qualcomm/qcs404-evb/Kconfig" endif diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index cb8c1aa8d2..0d31f10f68 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -17,3 +17,5 @@ obj-y += pinctrl-apq8016.o obj-y += pinctrl-apq8096.o obj-y += pinctrl-qcs404.o obj-$(CONFIG_SDM845) += pinctrl-sdm845.o +obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o +obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o diff --git a/arch/arm/mach-snapdragon/sysmap-qcs404.c b/arch/arm/mach-snapdragon/sysmap-qcs404.c new file mode 100644 index 0000000000..b7409031a0 --- /dev/null +++ b/arch/arm/mach-snapdragon/sysmap-qcs404.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm QCS404 memory map + * + * (C) Copyright 2022 Sumit Garg + */ + +#include +#include + +static struct mm_region qcs404_mem_map[] = { + { + .virt = 0x0UL, /* Peripheral block */ + .phys = 0x0UL, /* Peripheral block */ + .size = 0x8000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x80000000UL, /* DDR */ + .phys = 0x80000000UL, /* DDR */ + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = qcs404_mem_map; diff --git a/board/qualcomm/qcs404-evb/Kconfig b/board/qualcomm/qcs404-evb/Kconfig new file mode 100644 index 0000000000..32657c7d5e --- /dev/null +++ b/board/qualcomm/qcs404-evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_QCS404EVB + +config SYS_BOARD + default "qcs404-evb" + +config SYS_VENDOR + default "qualcomm" + +config SYS_SOC + default "qcs404" + +config SYS_CONFIG_NAME + default "qcs404-evb" + +endif diff --git a/board/qualcomm/qcs404-evb/MAINTAINERS b/board/qualcomm/qcs404-evb/MAINTAINERS new file mode 100644 index 0000000000..0a2e194ff6 --- /dev/null +++ b/board/qualcomm/qcs404-evb/MAINTAINERS @@ -0,0 +1,6 @@ +Qualcomm Technologies, Inc. QCS404 evaluation board +M: Sumit Garg +S: Maintained +F: board/qualcomm/qcs404-evb/ +F: include/configs/qcs404-evb.h +F: configs/qcs404evb_defconfig diff --git a/board/qualcomm/qcs404-evb/Makefile b/board/qualcomm/qcs404-evb/Makefile new file mode 100644 index 0000000000..4665827e08 --- /dev/null +++ b/board/qualcomm/qcs404-evb/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Sumit Garg +# + +obj-y += qcs404-evb.o diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.c b/board/qualcomm/qcs404-evb/qcs404-evb.c new file mode 100644 index 0000000000..f1e6e7f7eb --- /dev/null +++ b/board/qualcomm/qcs404-evb/qcs404-evb.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board init file for QCS404-EVB + * + * (C) Copyright 2022 Sumit Garg + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + psci_system_reset(); +} diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.its b/board/qualcomm/qcs404-evb/qcs404-evb.its new file mode 100644 index 0000000000..c9822827c9 --- /dev/null +++ b/board/qualcomm/qcs404-evb/qcs404-evb.its @@ -0,0 +1,64 @@ +/* + * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs + */ + +/dts-v1/; + +/ { + description = "Various kernels, ramdisks and FDT blobs"; + #address-cells = <1>; + + images { + kernel-1 { + description = "5.18.0-rc1"; + data = /incbin/("./qcs404_imgs/Image.gz"); + type = "kernel"; + arch = "arm64"; + os = "linux"; + compression = "gzip"; + load = <0x80000000>; + entry = <0x80000000>; + hash-1 { + algo = "sha1"; + }; + }; + + ramdisk-1 { + description = "Initial ramdisk"; + data = /incbin/("./qcs404_imgs/initramfs-tiny-image-qemuarm64-20220618074058-1169.rootfs.cpio.gz"); + type = "ramdisk"; + arch = "arm64"; + os = "linux"; + compression = "gzip"; + load = <00000000>; + entry = <00000000>; + hash-1 { + algo = "sha1"; + }; + }; + + fdt-1 { + description = "qcs404-evb-fdt"; + data = /incbin/("./qcs404_imgs/qcs404-evb-4000.dtb"); + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + load = <0x83000000>; + hash-1 { + algo = "sha1"; + }; + }; + + }; + + configurations { + default = "config-1"; + + config-1 { + description = "qcs404-evb kernel-5.18.0-rc1 configuration"; + kernel = "kernel-1"; + ramdisk = "ramdisk-1"; + fdt = "fdt-1"; + }; + }; +}; diff --git a/configs/qcs404evb_defconfig b/configs/qcs404evb_defconfig new file mode 100644 index 0000000000..7c76e8353e --- /dev/null +++ b/configs/qcs404evb_defconfig @@ -0,0 +1,39 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=19000000 +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_SNAPDRAGON=y +CONFIG_DEFAULT_DEVICE_TREE="qcs404-evb" +CONFIG_TARGET_QCS404EVB=y +CONFIG_IDENT_STRING="\nQualcomm QCS404-EVB" +CONFIG_SYS_TEXT_BASE=0x0 +CONFIG_SYS_LOAD_ADDR=0x80000000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTDELAY=5 +CONFIG_SAVE_PREV_BL_FDT_ADDR=y +CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BMP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_GPT=y +CONFIG_CMD_PART=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_NET is not set +CONFIG_CLK=y +CONFIG_PINCTRL=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MSM_SERIAL=y +CONFIG_LMB_MAX_REGIONS=64 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon ignore_loglevel root= clk_ignore_unused" diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst index 10b98214e9..0f9c429956 100644 --- a/doc/board/qualcomm/index.rst +++ b/doc/board/qualcomm/index.rst @@ -8,3 +8,4 @@ Qualcomm dragonboard410c sdm845 + qcs404 diff --git a/doc/board/qualcomm/qcs404.rst b/doc/board/qualcomm/qcs404.rst new file mode 100644 index 0000000000..bbb40b043b --- /dev/null +++ b/doc/board/qualcomm/qcs404.rst @@ -0,0 +1,79 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Sumit Garg + +QCS404 EVB +========== + +About this +---------- +This document describes the information about Qualcomm QCS404 evaluation board +and it's usage steps. + +U-Boot can be used as a replacement for Qualcomm's original ABL (UEFI) bootloader. +It is loaded as an Android boot image through ABL + +Installation +------------ +Build +^^^^^ +Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board:: + + $ export CROSS_COMPILE= + $ make qcs404evb_defconfig + $ make + +This will build ``u-boot.bin`` in the configured output directory. + +Generate FIT image +^^^^^^^^^^^^^^^^^^ +A ``qcs404.its`` file can be found in ``board/qualcomm/qcs404-evb/`` directory. +It expects a folder as ``qcs404_imgs/`` in the main directory containing +pre-built kernel, dts and ramdisk images. See ``qcs404.its`` for full path to +images. + +- Build FIT image:: + + mkimage -f qcs404-evb.its qcs404-evb.itb + +Pack android boot image +^^^^^^^^^^^^^^^^^^^^^^^ +We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel, +and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel +with appended dtb, so let's mimic linux to satisfy stock bootloader: + +- create dump dtb:: + + workdir=/tmp/prepare_payload + mkdir -p "$workdir" + cd "$workdir" + mock_dtb="$workdir"/payload_mock.dtb + + dtc -I dts -O dtb -o "$mock_dtb" << EOF + /dts-v1/; + / { + model = "Qualcomm Technologies, Inc. QCS404 EVB 4000"; + compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb", "qcom,qcs404"; + + #address-cells = <2>; + #size-cells = <2>; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + chosen { }; + }; + EOF + +- gzip u-boot ``gzip u-boot.bin`` +- append dtb to gzipped u-boot: ``cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb`` + +Now we've got everything to build android boot image::: + + mkbootimg --kernel u-boot.bin.gz-dtb \ + --ramdisk qcs404-evb.itb --pagesize 4096 \ + --base 0x80000000 --output boot.img + +Flash image on qcs404-evb using fastboot method. diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h new file mode 100644 index 0000000000..a7f645b613 --- /dev/null +++ b/include/configs/qcs404-evb.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for QCS404 evaluation board + * + * (C) Copyright 2022 Sumit Garg + */ + +#ifndef __CONFIGS_QCS404EVB_H +#define __CONFIGS_QCS404EVB_H + +#include +#include + +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x5000000\0" \ + "bootm_low=0x80000000\0" \ + "bootcmd=bootm $prevbl_initrd_start_addr\0" + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 64 + +#endif