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[88.92.171.55]) by smtp.gmail.com with ESMTPSA id u2-20020a05651206c200b00488ab8914b5sm1401504lff.213.2022.07.11.01.29.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 01:29:50 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Douglas Anderson , Krzysztof Kozlowski Subject: [PATCH v2 2/5] dt-bindings: mmc: sdhci-msm: constrain reg-names perp variants Date: Mon, 11 Jul 2022 10:29:37 +0200 Message-Id: <20220711082940.39539-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220711082940.39539-1-krzysztof.kozlowski@linaro.org> References: <20220711082940.39539-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The entries in arrays must have fixed order, so the bindings and Linux driver expecting various combinations of 'reg' addresses was never actually conforming to guidelines. The 'core' reg entry is valid only for SDCC v4 and lower, so disallow it in SDCC v5. SDCC v4 supports CQE and ICE, so allow them, even though the qcom,sdhci-msm-v4 compatible is used also for earlier SoCs with SDCC v2 or v3, so it is not entirely accurate. Signed-off-by: Krzysztof Kozlowski --- Changes since v1: 1. Rework the patch based on Doug's feedback. --- .../devicetree/bindings/mmc/sdhci-msm.yaml | 61 ++++++++++++------- 1 file changed, 38 insertions(+), 23 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index fc6e5221985a..2f0fdd65e908 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -49,33 +49,11 @@ properties: reg: minItems: 1 - items: - - description: Host controller register map - - description: SD Core register map - - description: CQE register map - - description: Inline Crypto Engine register map + maxItems: 4 reg-names: minItems: 1 maxItems: 4 - oneOf: - - items: - - const: hc - - items: - - const: hc - - const: core - - items: - - const: hc - - const: cqhci - - items: - - const: hc - - const: cqhci - - const: ice - - items: - - const: hc - - const: core - - const: cqhci - - const: ice clocks: minItems: 3 @@ -177,6 +155,43 @@ required: allOf: - $ref: mmc-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sdhci-msm-v4 + then: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + - const: ice + else: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + - const: ice + unevaluatedProperties: false examples: From patchwork Mon Jul 11 08:29:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 589555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2A1ACCA480 for ; Mon, 11 Jul 2022 08:30:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230097AbiGKIaN (ORCPT ); Mon, 11 Jul 2022 04:30:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230083AbiGKIaK (ORCPT ); Mon, 11 Jul 2022 04:30:10 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCC451F2CC for ; Mon, 11 Jul 2022 01:29:57 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id q7so5309842lji.12 for ; Mon, 11 Jul 2022 01:29:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dC6LNIuV4u3SkoGFdSK182o/o6Da8Zz3GIIdjx4l8L0=; b=lzSyO4Ox0rVozeD1AtRgwVLBVTRwfCmvF0gjrNi5W87whAJGsO7EM7+7hp6EsDVlWb RuIO3TGkcXGuTpIL06BY8G70JF/Vzz55tQ96qTO4I54X2dkfOFNmUw1UBQ60Xe6jb79q rCySCVMos7qeBVmV8OI68pf1kNT0i2eSLxKMTqmIrDVjmX+X9fDd4ZTzCbA1vX6UjRin GqE7Z+xQNaRDoVYIl2FrWz1SsbHLISwnxOCCQTBb2sb7U7W7NKtTX96cfOmzpRcMuieR 9L3Hady7EBgRXs9q9X5+JiVoz2GSmtE/0exEq0mkIdpMH5CptiA5nwDeRO+sl+1nVaVX bFOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dC6LNIuV4u3SkoGFdSK182o/o6Da8Zz3GIIdjx4l8L0=; b=mEYDuuJBvCdd8dngrahN4jgU7CVeDYcuhCczTf5zmNcjikdYdlVLtjBa4AfmMK2vy5 wNQgwaXH1boyIvm0R2vzG6h2z5JJDy1n7oMPoaevy2ivn2fePHf6CmoCfPGSe5WuOJT3 hi580gNlozrhs7n43XAE337Y8lnpNf3/jSSND6IRCJPiEr2VT4WRvSgK2wsvJ6AHkP0K 2PwrvSv2OdeqqC2cLV0Z4IeZSSm90HWVRFC0IhsvYG4xmQvkUJ4T4go+IWnfuEGmo39Y D1R64GJaCU2cTOSLwFHZl6kVUTN270sIxbOpXGfBxu8Y+Ic5YA6gg+1CIW1JAiwWXCWf Y+OA== X-Gm-Message-State: AJIora/00SRst20Uqj2/xEslyRZccuSDzkff5BsZMhkT2iuDt3wg7P4i F/Vmd7EXlMfNqIiNqeX1hcxzEA== X-Google-Smtp-Source: AGRyM1tdY2eyygsG2BT5OsoToJC2/vIqxkxEPyuz1dOZfZ8VA+OfdC49cPRm3S4cylCSw9AAlByAVQ== X-Received: by 2002:a2e:908e:0:b0:25d:53c2:5395 with SMTP id l14-20020a2e908e000000b0025d53c25395mr9280286ljg.120.1657528196136; Mon, 11 Jul 2022 01:29:56 -0700 (PDT) Received: from krzk-bin.. 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[88.92.171.55]) by smtp.gmail.com with ESMTPSA id u2-20020a05651206c200b00488ab8914b5sm1401504lff.213.2022.07.11.01.29.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 01:29:55 -0700 (PDT) From: Krzysztof Kozlowski To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Douglas Anderson , Krzysztof Kozlowski Subject: [PATCH v2 4/5] ARM: dts: qcom: align SDHCI reg-names with DT schema Date: Mon, 11 Jul 2022 10:29:39 +0200 Message-Id: <20220711082940.39539-5-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220711082940.39539-1-krzysztof.kozlowski@linaro.org> References: <20220711082940.39539-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org DT schema requires SDHCI reg names to be hc/core without "_mem" suffix, just like TXT bindings were expecting before the conversion. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson --- arch/arm/boot/dts/qcom-apq8084.dtsi | 4 ++-- arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 + arch/arm/boot/dts/qcom-msm8226.dtsi | 6 +++--- arch/arm/boot/dts/qcom-msm8974.dtsi | 6 +++--- arch/arm/boot/dts/qcom-sdx65.dtsi | 2 +- 5 files changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 3e8bded2b5c8..45f3cbcf6238 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -422,7 +422,7 @@ blsp2_uart2: serial@f995e000 { mmc@f9824900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, @@ -435,7 +435,7 @@ mmc@f9824900 { mmc@f98a4900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_APPS_CLK>, diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index a2632349cec4..1b98764bab7a 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -224,6 +224,7 @@ vqmmc: regulator@1948000 { sdhci: mmc@7824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0x7824900 0x11c>, <0x7824000 0x800>; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; bus-width = <8>; diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 0b5effdb269a..f711463d22dc 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -137,7 +137,7 @@ apcs: syscon@f9011000 { sdhc_1: mmc@f9824900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; @@ -153,7 +153,7 @@ sdhc_1: mmc@f9824900 { sdhc_2: mmc@f98a4900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; @@ -169,7 +169,7 @@ sdhc_2: mmc@f98a4900 { sdhc_3: mmc@f9864900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 11b4206036e6..971eceaef3d1 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -439,7 +439,7 @@ acc3: clock-controller@f90b8000 { sdhc_1: mmc@f9824900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; @@ -456,7 +456,7 @@ sdhc_1: mmc@f9824900 { sdhc_3: mmc@f9864900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; @@ -475,7 +475,7 @@ sdhc_3: mmc@f9864900 { sdhc_2: mmc@f98a4900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; + reg-names = "hc", "core"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 7a193678b4f5..4f3389cb6300 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -334,7 +334,7 @@ glink-edge { sdhc_1: mmc@8804000 { compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; - reg-names = "hc_mem"; + reg-names = "hc"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq";