From patchwork Sun Jul 10 09:00:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 589248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16FB2C433EF for ; Sun, 10 Jul 2022 09:00:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229679AbiGJJAs (ORCPT ); Sun, 10 Jul 2022 05:00:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229668AbiGJJAp (ORCPT ); Sun, 10 Jul 2022 05:00:45 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F81C11A3F for ; Sun, 10 Jul 2022 02:00:44 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id e28so678231lfj.4 for ; Sun, 10 Jul 2022 02:00:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VZs4kXHK9xbLHkrqMGuJyZ5VoLx/pQiEUX4aKEkcY5A=; b=NE0ahQ1LMEzRiDmam57ajPEX+MCfHm20NEAFqzHi/YYk76pgWNaUlBynt1fjo/qMqo A5T7sD6O3yrfZ+QlLQMO8PtLQxQMwVmJafXTbs7ZuetGUdqlXQh5HTNaVbSAN2wVKGUc cMNEjYgeVeYSPiXtMLgVYI5kF7Bqlmycx42OBbb7lYvSGfrmKY5t+YOkZlpsRZIG4I7y B4e2VMR639gQv28cRqt+G/I0+5/d+5fFNL/Owvr2JlPJ/Bo+OZH6Thpd/pvl4DgEK5Q1 vetJToJjxA0y29kuoXjHpUQO9ixHE8maBjjvBA1B52WYok3uv8CkCQY3Z8HTAEaMAp0R CO1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VZs4kXHK9xbLHkrqMGuJyZ5VoLx/pQiEUX4aKEkcY5A=; b=7EXq3efPhXMvvbbtCUxDujOpylWxxp4w0SYSgdSfCB2ORKc9Ji7DaOict5yKTjcP0x q0TbiFqC4adHssh8h8o5J0uLNo7Y9rdXBz3u2q3Wr4Agz1c+QmpSlCx0SdAQVMoA8Bhd dKJu/wywUDSwqvoZwK1Liq1wPeUwLR9KmhkjFaQ4KNOKPTGGm05L8EubgNwhkpKPVbFH V9Jjf08TLi20QFR/Ao0np7IAoM5CXsCPMb0Igua3CQ5fUQnmw0qsTmiQ7TK05Qr1ma/m +jXzdxWxvBnUHQQH9dzlxj6eXwRy7jUP3SLR3xOVMGf0AwhD2zH00phUcKc/2OKfr/Fa CpVA== X-Gm-Message-State: AJIora+LjOX3SCkDOzCmjaShswyFpqO+n0Ykke+CyXsvc6toCfYCVhnT gmbnvcJ9/imowyyhMfco2zZoPQ== X-Google-Smtp-Source: AGRyM1vJ2bvlLB+NlRwTwtW/ZZXgTuVBInd2vfmXy7JJPK9tbJTYw/ZGF0qL4Nv+Gv+WtrPPjOt2CA== X-Received: by 2002:ac2:4e08:0:b0:47f:7b73:c9b9 with SMTP id e8-20020ac24e08000000b0047f7b73c9b9mr8006082lfr.5.1657443642786; Sun, 10 Jul 2022 02:00:42 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id u16-20020a056512095000b004896b58f2fasm822881lft.270.2022.07.10.02.00.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jul 2022 02:00:42 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 02/11] arm64: dts: qcom: sc7180: rename DPU device node Date: Sun, 10 Jul 2022 12:00:31 +0300 Message-Id: <20220710090040.35193-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220710090040.35193-1-dmitry.baryshkov@linaro.org> References: <20220710090040.35193-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rename DPU device node to display-controller@ae01000 to follow the DPU schema. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 72994f599825..e63b4515453f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2911,7 +2911,7 @@ mdss: mdss@ae00000 { status = "disabled"; - mdp: mdp@ae01000 { + mdp: display-controller@ae01000 { compatible = "qcom,sc7180-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x2008>; From patchwork Sun Jul 10 09:00:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 589245 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 824BDCCA487 for ; Sun, 10 Jul 2022 09:00:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229558AbiGJJAx (ORCPT ); Sun, 10 Jul 2022 05:00:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229682AbiGJJAu (ORCPT ); Sun, 10 Jul 2022 05:00:50 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D49611C00 for ; Sun, 10 Jul 2022 02:00:46 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id bn33so3016810ljb.13 for ; Sun, 10 Jul 2022 02:00:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IxYOYEArwHfC1EBEGrasikYW6pj0UuIU8vXNFVNnVMM=; b=VA+Ew8NFOYAPVzxbQ7T7bB6jiXXyevij1M/DS3zsxWNnvntUeUmoJq6aydmYxKWtsR fyFYn6D2D1+xrukR8wIY0d8iG3Iz7PO6Kpl1dIE3U0KY/IO6bT60nIUSr4eLNfBbO5dY Ta3ExK0k5B14QkCua0E8gVXlk/xgzY/yZFVkV5nr8QhvuCGNwb2p7vKjRMC42topR5Xz ag1rpc/0n+acj1oEM9+wVPgFNnuyLh10w8OXaZifShu2CgyBk4B/SPFAjUm6Tjc6gHms SHE6b658GPbgpwF8GUW3kQhheHMSak4xVkQtNbmNeUnNdUL8orEBKYPeAUi+j4lo7371 JffA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IxYOYEArwHfC1EBEGrasikYW6pj0UuIU8vXNFVNnVMM=; b=VGRoVxm73owRuafXcakEnvxvHto0qzFYtus/DN3C3yfPhcA8iaL+Q+qDcNZ2sturSg UgV6IC7yBol6G64fQoNkI1jf8lRNIYFM8Y+eZgOePdAe8kFljkbouRdeQYOAw/ZasLW1 AT9T0mG5k5frOV0fESAm181gCmpcCfHmhhdo5mgP4sr7BmemFvJwEOvdBBEssT/K8hG6 xDiSdZ3SM85HEmA+KVI0LvUcQemkykzKjqqbq27ujMOl9iT5KIUV5FZFlglDLHGUorvh finubZEt+PKTyrWO/twcEyu/8rXWLiagUibTWiaZCRCUxPxzXh2GLqHmkxSI4C6rypQU mNDg== X-Gm-Message-State: AJIora8UqPPTeTr4TXvQ/Aei6ezae1iz///sGJi26HQ0d2jslYQ+hpAb c+c3QPXUqUc5RRd4XtjZTGmsCQ== X-Google-Smtp-Source: AGRyM1t/mPCH+3KpPAwyzSrxnOmsiAFwLrShnV1B0VGJHnnxi1cL4OM8P4nzwzwVvRTNcpqeGnS+Pg== X-Received: by 2002:a2e:a78b:0:b0:25d:6898:d0d1 with SMTP id c11-20020a2ea78b000000b0025d6898d0d1mr913245ljf.218.1657443644479; Sun, 10 Jul 2022 02:00:44 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id u16-20020a056512095000b004896b58f2fasm822881lft.270.2022.07.10.02.00.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jul 2022 02:00:44 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 04/11] dt-bindings: display/msm: split qcom, mdss bindings Date: Sun, 10 Jul 2022 12:00:33 +0300 Message-Id: <20220710090040.35193-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220710090040.35193-1-dmitry.baryshkov@linaro.org> References: <20220710090040.35193-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Split Mobile Display SubSystem (MDSS) root node bindings to the separate yaml file. Changes to the existing (txt) schema: - Added optional "vbif_nrt_phys" region used by msm8996 - Made "bus" and "vsync" clocks optional (they are not used by some platforms) - Added (optional) "core" clock added recently to the mdss driver - Added optional resets property referencing MDSS reset - Defined child nodes pointing to corresponding reference schema. - Dropped the "lut" clock. It was added to the schema by mistake (it is a part of mdp4 schema, not the mdss). Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/mdp5.txt | 30 +--- .../devicetree/bindings/display/msm/mdss.yaml | 161 ++++++++++++++++++ 2 files changed, 162 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/mdp5.txt b/Documentation/devicetree/bindings/display/msm/mdp5.txt index 43d11279c925..65d03c58dee6 100644 --- a/Documentation/devicetree/bindings/display/msm/mdp5.txt +++ b/Documentation/devicetree/bindings/display/msm/mdp5.txt @@ -2,37 +2,9 @@ Qualcomm adreno/snapdragon MDP5 display controller Description: -This is the bindings documentation for the Mobile Display Subsytem(MDSS) that -encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display +This is the bindings documentation for the MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996. -MDSS: -Required properties: -- compatible: - * "qcom,mdss" - MDSS -- reg: Physical base address and length of the controller's registers. -- reg-names: The names of register regions. The following regions are required: - * "mdss_phys" - * "vbif_phys" -- interrupts: The interrupt signal from MDSS. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt -- clocks: device clocks. See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required. - * "iface" - * "bus" - * "vsync" -- #address-cells: number of address cells for the MDSS children. Should be 1. -- #size-cells: Should be 1. -- ranges: parent bus address space is the same as the child bus address space. - -Optional properties: -- clock-names: the following clocks are optional: - * "lut" - MDP5: Required properties: - compatible: diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml new file mode 100644 index 000000000000..ba674a261b18 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Mobile Display SubSystem (MDSS) + +maintainers: + - Dmitry Baryshkov + - Rob Clark + +description: + This is the bindings documentation for the Mobile Display Subsytem(MDSS) that + encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc. + +properties: + compatible: + enum: + - qcom,mdss + + reg: + minItems: 2 + maxItems: 3 + + reg-names: + minItems: 2 + items: + - const: mdss_phys + - const: vbif_phys + - const: vbif_nrt_phys + + interrupts: + maxItems: 1 + + interrupt-controller: + true + + "#interrupt-cells": + const: 1 + + power-domains: + maxItems: 1 + description: | + The MDSS power domain provided by GCC + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: + true + + resets: + items: + - description: MDSS_CORE reset + +oneOf: + - properties: + clocks: + minItems: 3 + maxItems: 4 + + clock-names: + minItems: 3 + items: + - const: iface + - const: bus + - const: vsync + - const: core + - properties: + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: iface + - const: core + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-controller + - "#interrupt-cells" + - power-domains + - clocks + - clock-names + - "#address-cells" + - "#size-cells" + - ranges + +patternProperties: + "^mdp@(0|[1-9a-f][0-9a-f]*)$": + type: object + # TODO: add reference once the mdp5 is converted + + "^dsi@(0|[1-9a-f][0-9a-f]*)$": + $ref: dsi-controller-main.yaml# + + "^dsi-phy@(0|[1-9a-f][0-9a-f]*)$": + oneOf: + - $ref: dsi-phy-28nm.yaml# + - $ref: dsi-phy-20nm.yaml# + - $ref: dsi-phy-14nm.yaml# + - $ref: dsi-phy-10nm.yaml# + - $ref: dsi-phy-7nm.yaml# + + "^hdmi-phy@(0|[1-9a-f][0-9a-f]*)$": + oneOf: + - $ref: /schemas/phy/qcom,hdmi-phy-qmp.yaml# + - $ref: /schemas/phy/qcom,hdmi-phy-other.yaml# + + "^hdmi-tx@(0|[1-9a-f][0-9a-f]*)$": + $ref: hdmi.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + mdss@1a00000 { + compatible = "qcom,mdss"; + reg = <0x1a00000 0x1000>, + <0x1ac8000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync"; + + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + }; +... From patchwork Sun Jul 10 09:00:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 589247 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49394C43334 for ; Sun, 10 Jul 2022 09:00:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229579AbiGJJAu (ORCPT ); Sun, 10 Jul 2022 05:00:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229552AbiGJJAs (ORCPT ); Sun, 10 Jul 2022 05:00:48 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E61B919006 for ; Sun, 10 Jul 2022 02:00:46 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id t25so4274154lfg.7 for ; Sun, 10 Jul 2022 02:00:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LZmw/9n0J4sxjxv7YAo4yzPry54U6TAPdmwFIYw1fWI=; b=EIH7k5vVqdVKYpxlaQzHyYnEgHz7p1gff6K2AC/cMhoUQgzah7HipjO04bFdczBIW0 /oeiNBqqzaMuXqc0qjNpih0nHH4+sX2DJeWjcS6Rr9IwhEv99gWIDZUBW3xj4MtWlXj6 DJHOcm60bHgFXHHhztk6gGbl4qQf11NAq7w86j0noHkv+aEROgFRgNEcm/q23+0uvj6w El8GjTbXI772es+8yOz4kI6ULWwzkkVB2J8OFIqg3i+z5dM8mNS8kEXAjubw7THFzFp/ ojibgkuxvDc8Njpx8wxSTkU8IiTpIMmIGrd5uBqevpqqh9JuaTPGzVF/vMZ/ANpGp/sH f1cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LZmw/9n0J4sxjxv7YAo4yzPry54U6TAPdmwFIYw1fWI=; b=7nvYXj4EblhQ/2yA+m0hY/mjLXyEn+jdByGv9tpKaUHeaTo6zqsU5hrPIzR1mSRlNo M3TpoYQS5Z0kkkKmke5RWqd9XCidh4ad9vuQSKSmi4dMlug1uPGqRTsH0tLJNIETbVdp t4e+QCI14pNIFUuUfBIgdmT5fZ5Ibc7Cdn/KOPKx7Fj6ZaJ9jt6Zh11plMRcA1TlZJdE DAlsmLvqkE7nEU5meTEzq2AxWgYgXzblnaspXbtjG7N2SkUCZVnzw6vdpxGypciUs9Ja 94sRf4QbdZjmfc6i8CikswE/Yo3y+HP0kRpTdKrLvhMWN5qY553tSpQ8lGausgvUo2zw KujQ== X-Gm-Message-State: AJIora/LIW6tg2Ja0hxCHiRKJbLjqq/NEnAa4AFX3GM/t+O507e9wQlh KvId5aUUqHU+UjBO28foVooJSw== X-Google-Smtp-Source: AGRyM1vID3BbBxGW6+jsKggDcSujbkNN8erm+mJpghfomNtLqro6d+fKaIBq3gwGe5hV01+/Gv2l4g== X-Received: by 2002:ac2:4d93:0:b0:489:c69d:59c0 with SMTP id g19-20020ac24d93000000b00489c69d59c0mr6551482lfe.329.1657443645261; Sun, 10 Jul 2022 02:00:45 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id u16-20020a056512095000b004896b58f2fasm822881lft.270.2022.07.10.02.00.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jul 2022 02:00:44 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 05/11] dt-bindings: display/msm: move qcom,sdm845-mdss schema to mdss.yaml Date: Sun, 10 Jul 2022 12:00:34 +0300 Message-Id: <20220710090040.35193-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220710090040.35193-1-dmitry.baryshkov@linaro.org> References: <20220710090040.35193-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Move schema for qcom,sdm845-mdss from dpu-sdm845.yaml to mdss.yaml so that the dpu file describes only the DPU schema. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-sdm845.yaml | 135 ++++----------- .../devicetree/bindings/display/msm/mdss.yaml | 156 ++++++++++++++---- 2 files changed, 160 insertions(+), 131 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml index 2bb8896beffc..2074e954372f 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml @@ -10,139 +10,74 @@ maintainers: - Krishna Manikandan description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for SDM845 target. + Device tree bindings for the DPU display controller for SDM845 target. properties: compatible: items: - - const: qcom,sdm845-mdss + - const: qcom,sdm845-dpu reg: - maxItems: 1 + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set reg-names: - const: mdss - - power-domains: - maxItems: 1 + items: + - const: mdp + - const: vbif clocks: items: - - description: Display AHB clock from gcc + - description: Display ahb clock + - description: Display axi clock - description: Display core clock + - description: Display vsync clock clock-names: items: - const: iface + - const: bus - const: core + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 - - ranges: true - - resets: - items: - - description: MDSS_CORE reset + power-domains: + maxItems: 1 -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. + operating-points-v2: true + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: - items: - - const: qcom,sdm845-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display ahb clock - - description: Display axi clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: iface - - const: bus - - const: core - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF2 (DSI2) - - required: - - port@0 - - port@1 + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI1) + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF2 (DSI2) required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports + - port@0 + - port@1 required: - compatible - reg - reg-names - - power-domains - clocks - interrupts - - interrupt-controller - - iommus - - ranges + - power-domains + - operating-points-v2 + - ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml index ba674a261b18..7d4ab3d71d2d 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -17,18 +17,16 @@ description: properties: compatible: enum: + - qcom,sdm845-mdss - qcom,mdss reg: - minItems: 2 + minItems: 1 maxItems: 3 reg-names: - minItems: 2 - items: - - const: mdss_phys - - const: vbif_phys - - const: vbif_nrt_phys + minItems: 1 + maxItems: 3 interrupts: maxItems: 1 @@ -53,10 +51,10 @@ properties: maxItems: 4 "#address-cells": - const: 1 + enum: [1, 2] "#size-cells": - const: 1 + enum: [1, 2] ranges: true @@ -65,29 +63,99 @@ properties: items: - description: MDSS_CORE reset -oneOf: - - properties: - clocks: - minItems: 3 - maxItems: 4 - - clock-names: - minItems: 3 - items: - - const: iface - - const: bus - - const: vsync - - const: core - - properties: - clocks: - minItems: 1 - maxItems: 2 - - clock-names: - minItems: 1 - items: - - const: iface - - const: core + interconnects: + minItems: 2 + items: + - description: MDP port 0 + - description: MDP port 1 + - description: Rotator + + interconnect-names: + minItems: 2 + items: + - const: mdp0-mem + - const: mdp1-mem + - const: rotator-mem + + iommus: + items: + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,mdss + then: + properties: + reg-names: + minItems: 2 + items: + - const: mdss_phys + - const: vbif_phys + - const: vbif_nrt_phys + oneOf: + - properties: + clocks: + minItems: 3 + maxItems: 4 + + clock-names: + minItems: 3 + items: + - const: iface + - const: bus + - const: vsync + - const: core + - properties: + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: iface + - const: core + else: + properties: + regs: + maxItems: 1 + + reg-names: + items: + - const: mdss + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + + required: + - iommus + + - if: + properties: + compatible: + contains: + const: qcom,sdm845-mdss + then: + properties: + clocks: + items: + - description: Display AHB clock from gcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: core + + iommus: + minItems: 2 required: - compatible @@ -108,6 +176,9 @@ patternProperties: type: object # TODO: add reference once the mdp5 is converted + "^display-controller@(0|[1-9a-f][0-9a-f]*)$": + $ref: dpu-sdm845.yaml + "^dsi@(0|[1-9a-f][0-9a-f]*)$": $ref: dsi-controller-main.yaml# @@ -158,4 +229,27 @@ examples: ranges; }; + - | + #include + #include + display-subsystem@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sdm845-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc 19>, + <&dispcc 12>; + clock-names = "iface", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x880 0x8>, + <&apps_smmu 0xc80 0x8>; + ranges; + }; ... From patchwork Sun Jul 10 09:00:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 589244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64516C43334 for ; Sun, 10 Jul 2022 09:00:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229557AbiGJJAz (ORCPT ); Sun, 10 Jul 2022 05:00:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229678AbiGJJAv (ORCPT ); Sun, 10 Jul 2022 05:00:51 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E42719006 for ; Sun, 10 Jul 2022 02:00:50 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id w17so1495857ljh.6 for ; Sun, 10 Jul 2022 02:00:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zohW/RPNsF1wTu6pVEHKvimYKxrdBoHOypxhIFAavrk=; b=nrVbi9g/8ofxcgWSgKwJqpWbDDT5e20o9uHMQfCXBI/1wTpekutTw7gORclfjdWos0 1SvBPnbgxZdoAnyg4De496heD1xbdJtCxnb+3fYY4P8LisXMwgpuzE0wBi2tC6dboTzE f8ZxJoyjyFNUIZ0aZv52tBEBW3XgbNIAyoH4uS8Yu5cewcLXTrwo+uYJstPw9wrrPyTO nmDlDfO23ItphZMl6Tj/6fNgBOEcjop1QeqeJcy5WlGK0kDMs1gmMmC1kfGpgmDzRUCd E4c39gfn4icAFS8+V6a9cy2nvaj3t7guhf17UDpn1seWATqWkGrhAsQ+BZRw18/VSw3X NTmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zohW/RPNsF1wTu6pVEHKvimYKxrdBoHOypxhIFAavrk=; b=5uLbJb32DxjTetZts7abQx7MoqoCUyA6mn5rvDGXeVZyfooCXAjKPQKq2Mqm7f2TvQ V51k+UKCyNVypTKmN/VbPPghYWTNS1w9cH3ri0LN6d9j2S/TAZcgFDDWk8S44jQPa6c9 5gXE57oq07fGZaQ2OFkA6kK7Zesqw+5fQrmWaZxTtu6NodTvBwGl0F5spySwmSc58OqU wVlta39EgZYTF+/IajFra8HwO+HioLeKTsyNcaXYsDeVnbwmrazYPRJ+SJg5hm8OObYg mnItb8QjgyZeonhOl+lrkf6QF8wXHdnd4jAFNjdHEl0FxHEp6zsDg5nqDG749UFZ4rRh w38A== X-Gm-Message-State: AJIora8X+m43uenXQPlUWvu1u5Un5U0oB6QVaCnqU9DbEID725sp2gjl aW4BWRXxgF62crdMUBMU+LmExWZ/GCUlRw== X-Google-Smtp-Source: AGRyM1tLWkCXOxx0GDuoGW26o7FMlsMD6EZkmixXby2y0zc+1Ln4akUi3GqD9en/9p+g6NnybFXX1Q== X-Received: by 2002:a2e:9f16:0:b0:25d:48a9:4f2a with SMTP id u22-20020a2e9f16000000b0025d48a94f2amr6985476ljk.454.1657443648520; Sun, 10 Jul 2022 02:00:48 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id u16-20020a056512095000b004896b58f2fasm822881lft.270.2022.07.10.02.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jul 2022 02:00:48 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 09/11] dt-bindings: display/msm: move qcom,msm8998-mdss schema to mdss.yaml Date: Sun, 10 Jul 2022 12:00:38 +0300 Message-Id: <20220710090040.35193-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220710090040.35193-1-dmitry.baryshkov@linaro.org> References: <20220710090040.35193-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Move schema for qcom,msm8998-mdss from dpu-msm8998.yaml to mdss.yaml so that the dpu file describes only the DPU schema. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-msm8998.yaml | 142 +++++------------- .../devicetree/bindings/display/msm/mdss.yaml | 24 +++ 2 files changed, 64 insertions(+), 102 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml index 2df64afb76e6..5caf46a1dd88 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml @@ -10,142 +10,80 @@ maintainers: - AngeloGioacchino Del Regno description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for MSM8998 target. + Device tree bindings for the DPU display controller for MSM8998 target. properties: compatible: items: - - const: qcom,msm8998-mdss + - const: qcom,msm8998-dpu reg: - maxItems: 1 + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for regdma register set + - description: Address offset and size for vbif register set + - description: Address offset and size for non-realtime vbif register set reg-names: - const: mdss - - power-domains: - maxItems: 1 + items: + - const: mdp + - const: regdma + - const: vbif + - const: vbif_nrt clocks: items: - - description: Display AHB clock - - description: Display AXI clock + - description: Display ahb clock + - description: Display axi clock + - description: Display mem-noc clock - description: Display core clock + - description: Display vsync clock clock-names: items: - const: iface - const: bus + - const: mnoc - const: core + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": - const: 1 - - iommus: - items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true + power-domains: + maxItems: 1 -patternProperties: - "^display-controller@[0-9a-f]+$": - type: object - description: Node containing the properties of DPU. + operating-points-v2: true + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: - items: - - const: qcom,msm8998-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for regdma register set - - description: Address offset and size for vbif register set - - description: Address offset and size for non-realtime vbif register set - - reg-names: - items: - - const: mdp - - const: regdma - - const: vbif - - const: vbif_nrt - - clocks: - items: - - description: Display ahb clock - - description: Display axi clock - - description: Display mem-noc clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: iface - - const: bus - - const: mnoc - - const: core - - const: vsync - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - operating-points-v2: true - ports: - $ref: /schemas/graph.yaml#/properties/ports - description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - - properties: - port@0: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF1 (DSI1) - - port@1: - $ref: /schemas/graph.yaml#/properties/port - description: DPU_INTF2 (DSI2) - - required: - - port@0 - - port@1 + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI1) + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF2 (DSI2) required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports + - port@0 + - port@1 required: - compatible - reg - reg-names - - power-domains - clocks - interrupts - - interrupt-controller - - iommus - - ranges + - power-domains + - operating-points-v2 + - ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml index 7359b233f3eb..87c7f9d8f49c 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -17,6 +17,7 @@ description: properties: compatible: enum: + - qcom,msm8998-mdss - qcom,qcm2290-mdss - qcom,sc7180-mdss - qcom,sc7280-mdss @@ -143,6 +144,28 @@ allOf: required: - iommus + - if: + properties: + compatible: + contains: + const: qcom,msm8998-mdss + then: + properties: + clocks: + items: + - description: Display AHB clock + - description: Display AXI clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 1 + - if: properties: compatible: @@ -230,6 +253,7 @@ patternProperties: "^display-controller@(0|[1-9a-f][0-9a-f]*)$": oneOf: + - $ref: dpu-msm8998.yaml - $ref: dpu-qcm2290.yaml - $ref: dpu-sc7180.yaml - $ref: dpu-sc7280.yaml From patchwork Sun Jul 10 09:00:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 589246 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 236ACCCA483 for ; Sun, 10 Jul 2022 09:00:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229514AbiGJJAx (ORCPT ); Sun, 10 Jul 2022 05:00:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229557AbiGJJAu (ORCPT ); Sun, 10 Jul 2022 05:00:50 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCB7815720 for ; Sun, 10 Jul 2022 02:00:49 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id bx13so3063225ljb.1 for ; Sun, 10 Jul 2022 02:00:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r8uP7epyJQsP5rWLMlZPU+2WIXogmdHgKsCg4a6KbsQ=; b=kKvMJpP/ZP5JytTzFf0NPpp8SzSAfBXi7jIqa8Hk+QV/PNSoE+sayfQtZTrEoBYI7g zh1795kR7Ag0oYToA8bVBDV63ZDa25O2kr9/slwZOiuq3YVXmZnE/XueoDzXzCK25KC8 Ja9SHBSKnWtTnKsOHT4hLR5PRhPv1Wili1yg9pfLS0xpOjl2Dy+E7PKoRY6X15LptQAw xj9XJmWz98sTcxxSvIAzoSpOutu1J1Usqjf4PzUq9yKQokTadq+1+S/qQPk2/Ru9c6+T bKflirilmwVHMJuW/U5LaoJce+IUl9y+PkbmTIIogjjRUJ3NO/aS0mjooKx7edaIv1I7 9ipQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r8uP7epyJQsP5rWLMlZPU+2WIXogmdHgKsCg4a6KbsQ=; b=1+RwkZcvJVuiJlSzXMgOdyLcad6Zrfp13Of8ETovs1QKTVNvIizktgK8eqOz+H3bAC izN7xIfW1aHOpGAR5gCNf8avsyy3s1zuvJq1/13l60f29Y2NRzo0GQHExINLsO9k7Ykv xqy79PLNBJRuVUoLC8viACqWxkDLihNseKE1Dof4PXBCvey4+axTONNruiJVpdLRc1NT 7y6wyn+i3RU7Y49eB61TaewHB+6fBHBZhlRMgVTPL87cDXSSe2AuPNljPXqHPjK5lA/y uxF/BVEz8i0kkNeNqwiIQIDHKG94WMIdGxoZChzos135Rb7sb+3u4n6XGsnN1dXR03Uj FiQA== X-Gm-Message-State: AJIora9KI0F54Szo7y5pcToAuEk/eog0ZzoLcuSux+4mPH6sBtAcKw/R plWGn/8mmP6HQqLC+gM195MgVw== X-Google-Smtp-Source: AGRyM1tRRC56ermrH8sFgyeA0GHovNm/nUTSJV/sXXfkIPvFNvOYIpxVOLE4kCIzUkymapoQz2jyjg== X-Received: by 2002:a2e:82cf:0:b0:25d:490f:4035 with SMTP id n15-20020a2e82cf000000b0025d490f4035mr7391229ljh.290.1657443649443; Sun, 10 Jul 2022 02:00:49 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id u16-20020a056512095000b004896b58f2fasm822881lft.270.2022.07.10.02.00.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Jul 2022 02:00:48 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 10/11] dt-bindings: display/mdm: add gcc-bus clock to dpu-smd845 Date: Sun, 10 Jul 2022 12:00:39 +0300 Message-Id: <20220710090040.35193-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220710090040.35193-1-dmitry.baryshkov@linaro.org> References: <20220710090040.35193-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add gcc-bus clock required for the SDM845 DPU device tree node. This change was made in the commit 111c52854102 ("arm64: dts: qcom: sdm845: move bus clock to mdp node for sdm845 target"), but was not reflected in the schema. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/dpu-sdm845.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml index 2074e954372f..42ff85e80f45 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml @@ -29,6 +29,7 @@ properties: clocks: items: + - description: Display GCC bus clock - description: Display ahb clock - description: Display axi clock - description: Display core clock @@ -36,6 +37,7 @@ properties: clock-names: items: + - const: gcc-bus - const: iface - const: bus - const: core @@ -114,11 +116,12 @@ examples: <0x0aeb0000 0x2008>; reg-names = "mdp", "vbif"; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; + clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; interrupt-parent = <&mdss>; interrupts = <0>;