From patchwork Fri Jul 8 14:29:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 588662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69DE3CCA483 for ; Fri, 8 Jul 2022 14:30:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238106AbiGHOaK (ORCPT ); Fri, 8 Jul 2022 10:30:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238088AbiGHOaK (ORCPT ); Fri, 8 Jul 2022 10:30:10 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20886B7DC; Fri, 8 Jul 2022 07:30:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657290609; x=1688826609; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yF1NojDTOGwCGkFGTDOFrruBHppEMQq5PgQMjxraLpE=; b=ha5JYFACH956PPxidTUoFxQV33IEtKmqbHPiDYqjB9MT+gGJo1tUmvOg WU4st+tMecMdEj0TQchzNIYpQX76tHECoVRxb6QGdFqGwhiNN10L5esDN H4Pdjnium4wF5i66DLaj7BSgM8rF+hTmFMoQFF/9jI5z3Ikepw2seqdBI B6On/jNmzij+G0+wUurmTN1gBnUSnk1XDHVbIiXR5DVmosg/Xgj8TBl8w /xntC+Dtys8ibsprsEPGxHPcXr6dZIaYqNJ4cUJKrQU15F0CdTWHXPVtm Bn7/4q2uwOpgsD7d+SszI+0YIBsSNGEe4KYlxuu9Nii5k3KTJ7r2HtmtS A==; X-IronPort-AV: E=Sophos;i="5.92,255,1650956400"; d="scan'208";a="103658958" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Jul 2022 07:30:08 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Jul 2022 07:30:08 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Jul 2022 07:30:06 -0700 From: Conor Dooley To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , "Lee Jones" , Rob Herring , "Krzysztof Kozlowski" CC: Daire McNamara , , , , , Conor Dooley Subject: [PATCH v4 2/4] riscv: dts: fix the icicle's #pwm-cells Date: Fri, 8 Jul 2022 15:29:36 +0100 Message-ID: <20220708142937.1120121-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220708142937.1120121-1-conor.dooley@microchip.com> References: <20220708142937.1120121-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org \#pwm-cells for the Icicle kit's fabric PWM was incorrectly set to 2 & blindly overridden by the (out of tree) driver anyway. The core can support inverted operation, so update the entry to correctly report its capabilities. Fixes: 72560c6559b8 ("riscv: dts: microchip: add fpga fabric section to icicle kit") Signed-off-by: Conor Dooley --- .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +- .../dts/microchip/mpfs-tysom-m-fabric.dtsi | 18 ++ .../riscv/boot/dts/microchip/mpfs-tysom-m.dts | 185 ++++++++++++++++++ 3 files changed, 204 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 0d28858b83f2..e09a13aef268 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -8,7 +8,7 @@ core_pwm0: pwm@41000000 { compatible = "microchip,corepwm-rtl-v4"; reg = <0x0 0x41000000 0x0 0xF0>; microchip,sync-update-mask = /bits/ 32 <0>; - #pwm-cells = <2>; + #pwm-cells = <3>; clocks = <&fabric_clk3>; status = "disabled"; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi new file mode 100644 index 000000000000..98f642e83ad4 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +// #include "dt-bindings/mailbox/miv-ihc.h" + +/ { + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts new file mode 100644 index 000000000000..0b664c591255 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2020-2022 - Aldec + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley + */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-tysom-m-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model = "Aldec TySOM-M-MPFS250T"; + compatible = "aldec,tysom-m-mpfs250t", "microchip,mpfs"; + + aliases { + ethernet0 = &mac0; + ethernet1 = &mac1; + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; + gpio0 = &gpio0; + gpio1 = &gpio2; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x2e000000>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x00000000 0x0 0x40000000>; + status = "okay"; + }; + + soc { + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + led0 { + gpios = <&gpio1 23 1>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + ina219: ina219@45 { + status = "okay"; + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <0x7d0>; + }; +}; + +&gpio1 { + interrupts = <27 28 29 30 31 32 33 47 35 36 37 38 39 40 41 42 43 44 45 46 34 48 49 50>; + status = "okay"; +}; + +&mac0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + +}; + +&mac1 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@1 { + reg = <1>; + ti,fifo-depth = <0x01>; + }; + phy0: ethernet-phy@0 { + reg = <0>; + ti,fifo-depth = <0x01>; + }; +}; + +&mbox { + status = "okay"; +}; + +&mmc { + max-frequency = <200000000>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-1-8-v; + disable-wp; + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +&mmuart2 { + status = "okay"; +}; + +&mmuart3 { + status = "okay"; +}; + +&mmuart4 { + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + pseFlash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a11", "jedec,spi-nor"; + status = "okay"; + reg = <0x0>; + spi-max-frequency = <10000000>; + + partition@test-0 { /* test purposes */ + label = "qspi-test-0"; + reg = <0x00000000 0x00800000>; + }; + partition@test-1 { /* test purposes */ + label = "qspi-test-1"; + reg = <0x00800000 0x00800000>; + }; + partition@test-2 { /* test purposes */ + label = "qspi-test-2"; + reg = <0x01000000 0x00800000>; + }; + partition@test-3 { /* test purposes */ + label = "qspi-test-3"; + reg = <0x01800000 0x00800000>; + }; + }; +}; + +&syscontroller { + status = "okay"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +}; From patchwork Fri Jul 8 14:29:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 588661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A432C433EF for ; Fri, 8 Jul 2022 14:30:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238088AbiGHOaS (ORCPT ); Fri, 8 Jul 2022 10:30:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238148AbiGHOaR (ORCPT ); Fri, 8 Jul 2022 10:30:17 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F2F2326E6; Fri, 8 Jul 2022 07:30:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657290616; x=1688826616; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fnl5CGvXmbwoIcy91psfgiwxnD3o6LZLHepJqwb/OE0=; b=ZKxTDAwRjdI7OnXWJtlxXl5RWPXvZ0c3gjf668vGlO8gZwLwIgtnoy67 MzubyA3vWZH4rXD/UmDG5ZlmOWjAV6bZXE4ytTFSiI/j1KqLw78AHm+wa 32ffLnjXo9viwfMAQvHxkaXGN9BBYZs/nwNK0pjhXipSWzcKgMAg7avRp loSQj+gJT6HoVYGMbIpGnn45aS6GvvltjeJ5kIv5KKS/CxpYZFbMi+rzC fKSqF39dLnoJ6YnNs+2l1HJ35ie6Qwj/yxb3yi7oIlDUeH3diWcUf4edn Fz0cIdQyYCZp+Afw90WpOSI0yfAAfWltwKpBOeoiHFd+c2wDo3cdiKqsJ A==; X-IronPort-AV: E=Sophos;i="5.92,255,1650956400"; d="scan'208";a="171340873" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Jul 2022 07:30:16 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Jul 2022 07:30:13 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Jul 2022 07:30:11 -0700 From: Conor Dooley To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , "Lee Jones" , Rob Herring , "Krzysztof Kozlowski" CC: Daire McNamara , , , , , Conor Dooley Subject: [PATCH v4 4/4] MAINTAINERS: add pwm to PolarFire SoC entry Date: Fri, 8 Jul 2022 15:29:38 +0100 Message-ID: <20220708142937.1120121-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220708142937.1120121-1-conor.dooley@microchip.com> References: <20220708142937.1120121-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the newly introduced pwm driver to the existing PolarFire SoC entry. Signed-off-by: Conor Dooley --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index d64d79eb36a2..f023ae8442ab 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17429,6 +17429,7 @@ L: linux-riscv@lists.infradead.org S: Supported F: arch/riscv/boot/dts/microchip/ F: drivers/mailbox/mailbox-mpfs.c +F: drivers/pwm/pwm-microchip-core.c F: drivers/rtc/rtc-mpfs.c F: drivers/soc/microchip/ F: drivers/spi/spi-microchip-core.c