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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.15.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:15:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 01/45] target/arm: Handle SME in aarch64_cpu_dump_state Date: Fri, 8 Jul 2022 20:44:56 +0530 Message-Id: <20220708151540.18136-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Dump SVCR, plus use the correct access check for Streaming Mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ae6dca2f01..9c58be8b14 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -878,6 +878,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) int i; int el = arm_current_el(env); const char *ns_status; + bool sve; qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); for (i = 0; i < 32; i++) { @@ -904,6 +905,12 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) el, psr & PSTATE_SP ? 'h' : 't'); + if (cpu_isar_feature(aa64_sme, cpu)) { + qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", + env->svcr, + (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), + (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); + } if (cpu_isar_feature(aa64_bti, cpu)) { qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); } @@ -918,7 +925,15 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", vfp_get_fpcr(env), vfp_get_fpsr(env)); - if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { + if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { + sve = sme_exception_el(env, el) == 0; + } else if (cpu_isar_feature(aa64_sve, cpu)) { + sve = sve_exception_el(env, el) == 0; + } else { + sve = false; + } + + if (sve) { int j, zcr_len = sve_vqm1_for_el(env, el); for (i = 0; i <= FFR_PRED_NUM; i++) { From patchwork Fri Jul 8 15:14:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588512 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp753097mab; Fri, 8 Jul 2022 08:18:00 -0700 (PDT) X-Google-Smtp-Source: AGRyM1v8s+25W5rZ38IYulpUXVl0WCOJXGpgOE3ZxJi7bOzIr+rfYsjklkU1APpxL5aGS6W0/CKW X-Received: by 2002:a05:620a:4449:b0:6b2:83d3:2e13 with SMTP id w9-20020a05620a444900b006b283d32e13mr2850456qkp.658.1657293480299; Fri, 08 Jul 2022 08:18:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657293480; cv=none; d=google.com; s=arc-20160816; b=lxwbMXzss/PjGB2GmVsaWG5rqO9v8R7nCRauh2IPZCmnvFpo4XiLJvsv65czAY4UrU F2oklWaZ/bVHsy2AuSVqn8BVsW2/KDxwP1TaSxthY6CDh7aZdj+SVckc9ERVj06GjAkX V/Ru3RX8d7pddXn0h+h/LrX8EfR/k1GRRdefuEc1wrHvOSdfcHNt7uiBCp4h2F82ou+Y LyjQrPuICirRHRo9h58mxaMEfvHDBhYzLiDHGXIfPfdFT2ZP+SssVPehhFn3Fvzisu6t DhLJGx5OVSJsx6MMGYnCtgGGZgRBvxNPeyVv9q+0F5I5PwVE8ky8dvOzW6wfGxBPLzAL nJSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Zt0iFWR3qz21z3bSyJ1iuT1OyELXtc2hbyVwv56j1M4=; b=dUiEkUELdNnIlB1eTKhpxTORRQZPPfUslTlX4SH8vSAJyi225jiwHAGPj+Soubnl58 bgJnyXQ50SHTCLlQPsBIs28aote6nxhv4IN6HPSgp1xA1Ov3FGLYu7X4qyLn2q/JPL2Q Vy+VVuCpQSNRi3uHKeN1i8O89vq5xWbWnHRU3Gl21OwkgufUU4GitEUnBtzOV8U/b2zn N5bm8m6+8BgxauLOXFmFzILgM/JCPYYN+b7uLw4b6adruRMzJ0fOB7qAbYpA1L8Ryz9N ik+CIxz969ix4k1XPaoh+X2m/escuvOra4+1fx7sQJt7FECWJlYr2kYGyPyIYtW7sOo3 Dpyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r1il2+o3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.15.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:15:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 02/45] target/arm: Add infrastructure for disas_sme Date: Fri, 8 Jul 2022 20:44:57 +0530 Message-Id: <20220708151540.18136-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This includes the build rules for the decoder, and the new file for translation, but excludes any instructions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 1 + target/arm/sme.decode | 20 ++++++++++++++++++++ target/arm/translate-a64.c | 7 ++++++- target/arm/translate-sme.c | 35 +++++++++++++++++++++++++++++++++++ target/arm/meson.build | 2 ++ 5 files changed, 64 insertions(+), 1 deletion(-) create mode 100644 target/arm/sme.decode create mode 100644 target/arm/translate-sme.c diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index f0970c6b8c..789b6e8e78 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -146,6 +146,7 @@ static inline int pred_gvec_reg_size(DisasContext *s) } bool disas_sve(DisasContext *, uint32_t); +bool disas_sme(DisasContext *, uint32_t); void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); diff --git a/target/arm/sme.decode b/target/arm/sme.decode new file mode 100644 index 0000000000..c25c031a71 --- /dev/null +++ b/target/arm/sme.decode @@ -0,0 +1,20 @@ +# AArch64 SME instruction descriptions +# +# Copyright (c) 2022 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c86b97b1d4..a5f8a6c771 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14806,7 +14806,12 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } switch (extract32(insn, 25, 4)) { - case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ + case 0x0: + if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) { + unallocated_encoding(s); + } + break; + case 0x1: case 0x3: /* UNALLOCATED */ unallocated_encoding(s); break; case 0x2: diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c new file mode 100644 index 0000000000..786c93fb2d --- /dev/null +++ b/target/arm/translate-sme.c @@ -0,0 +1,35 @@ +/* + * AArch64 SME translation + * + * Copyright (c) 2022 Linaro, Ltd + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" +#include "tcg/tcg-gvec-desc.h" +#include "translate.h" +#include "exec/helper-gen.h" +#include "translate-a64.h" +#include "fpu/softfloat.h" + + +/* + * Include the generated decoder. + */ + +#include "decode-sme.c.inc" diff --git a/target/arm/meson.build b/target/arm/meson.build index 43dc600547..6dd7e93643 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,5 +1,6 @@ gen = [ decodetree.process('sve.decode', extra_args: '--decode=disas_sve'), + decodetree.process('sme.decode', extra_args: '--decode=disas_sme'), decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'), decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'), decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'), @@ -50,6 +51,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'sme_helper.c', 'translate-a64.c', 'translate-sve.c', + 'translate-sme.c', )) arm_softmmu_ss = ss.source_set() From patchwork Fri Jul 8 15:14:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588514 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp753148mab; Fri, 8 Jul 2022 08:18:03 -0700 (PDT) X-Google-Smtp-Source: AGRyM1siPb+lGcD/NzIkrMfhl0zP6HIsyjvGFZrtdJPtEw0+LuZzGTmnIRoeF+Prz5intJ5XeY6v X-Received: by 2002:a05:620a:460f:b0:6b1:533e:7f1c with SMTP id br15-20020a05620a460f00b006b1533e7f1cmr2608158qkb.217.1657293483729; Fri, 08 Jul 2022 08:18:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657293483; cv=none; d=google.com; s=arc-20160816; b=gJMmEuqNz8oOaPiH8VuLsiMeNX/0UPlFDcpj3B4cWgSWexl/6YGrs5hLjiQzObds8z WdVtsmKQ+0HgHSlmRnGEoJAi79DGEn1WmjfbrWBAFVrlyUgfnBO0GgIy8RCOZBiP4jfi B7orOdVLyPmBRj8FEBNIAS9Ak3lzsE7IuTVzaFmrxhlS6lXX0TF0cMJEAfM5AKshOoB2 D/z9/Am0/5ubzffEIGjH6W/1BctZ0d7F76Vh+OF7c1wntmvA45Alh9fM62+ujm1GlPsm VpRdOHzwmpUIiK0nbavhILMTofna9FIf0awZ/A/7QEehVFuK6M6ydCz4PooeiExFa763 AITA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TCGRYaM9CMo/9aFeB3/W5WDfDKYHUGdwXwE5N2wq+aM=; b=BvCHxur+sVMw9yHD5DuCveQCtoMkeBMIGIBKlDlLnj4PxAYIB4fbR7Ghl4KpMtSWvj iflfoarS/lNiok2P6JuG+SXnl7ANhe9PhCk7XTH4eKrONoSlfZH+u2PVRgGvt/V/ZFbl jP3IodguQ0cEWgks/55ydGbpvexd8eIpH6BQdmUcu7qO4SiHmnMzHNTRnpkfGA7zQRIX GAUmMtdq8CrolbLVUtQl2cX/GAMJivL0wGXFe8/NmxCiF+eOsDNnVd+SWUFZc66mEnT9 eZ57+HuYCIounrwjHujNXCX9WoApBpjhlQsXQLqAgUy8cCNkxvUDWMAfRJs8xt3ncMIY TRqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xhrrwgLb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.15.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:15:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active Date: Fri, 8 Jul 2022 20:44:58 +0530 Message-Id: <20220708151540.18136-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This new behaviour is in the ARM pseudocode function AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32 via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which the trap would be delivered is in AArch64 mode. Given that ARMv9 drops support for AArch32 outside EL0, the trap EL detection ought to be trivially true, but the pseudocode still contains a number of conditions, and QEMU has not yet committed to dropping A32 support for EL[12] when v9 features are present. Since the computation of SME_TRAP_NONSTREAMING is necessarily different for the two modes, we might as well preserve bits within TBFLAG_ANY and allocate separate bits within TBFLAG_A32 and TBFLAG_A64 instead. Note that DDI0616A.a has typos for bits [22:21] of LD1RO in the table of instructions illegal in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 7 +++ target/arm/translate.h | 4 ++ target/arm/sme-fa64.decode | 90 ++++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 41 +++++++++++++++++ target/arm/translate-a64.c | 40 ++++++++++++++++- target/arm/translate-vfp.c | 12 +++++ target/arm/translate.c | 2 + target/arm/meson.build | 1 + 8 files changed, 195 insertions(+), 2 deletions(-) create mode 100644 target/arm/sme-fa64.decode diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1f4f3e0485..1e36a839ee 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3158,6 +3158,11 @@ FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 10, 1) +/* + * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. + * This requires an SME trap from AArch32 mode when using NEON. + */ +FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) /* * Bit usage when in AArch32 state, for M-profile only. @@ -3195,6 +3200,8 @@ FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) FIELD(TBFLAG_A64, SVL, 24, 4) +/* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ +FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) /* * Helpers for using the above. diff --git a/target/arm/translate.h b/target/arm/translate.h index 22fd882368..cbc907c751 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -102,6 +102,10 @@ typedef struct DisasContext { bool pstate_sm; /* True if PSTATE.ZA is set. */ bool pstate_za; + /* True if non-streaming insns should raise an SME Streaming exception. */ + bool sme_trap_nonstreaming; + /* True if the current instruction is non-streaming. */ + bool is_nonstreaming; /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ bool mve_no_pred; /* diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode new file mode 100644 index 0000000000..3d90837fc7 --- /dev/null +++ b/target/arm/sme-fa64.decode @@ -0,0 +1,90 @@ +# AArch64 SME allowed instruction decoding +# +# Copyright (c) 2022 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# + +# These patterns are taken from Appendix E1.1 of DDI0616 A.a, +# Arm Architecture Reference Manual Supplement, +# The Scalable Matrix Extension (SME), for Armv9-A + +{ + [ + OK 0-00 1110 0000 0001 0010 11-- ---- ---- # SMOV W|Xd,Vn.B[0] + OK 0-00 1110 0000 0010 0010 11-- ---- ---- # SMOV W|Xd,Vn.H[0] + OK 0100 1110 0000 0100 0010 11-- ---- ---- # SMOV Xd,Vn.S[0] + OK 0000 1110 0000 0001 0011 11-- ---- ---- # UMOV Wd,Vn.B[0] + OK 0000 1110 0000 0010 0011 11-- ---- ---- # UMOV Wd,Vn.H[0] + OK 0000 1110 0000 0100 0011 11-- ---- ---- # UMOV Wd,Vn.S[0] + OK 0100 1110 0000 1000 0011 11-- ---- ---- # UMOV Xd,Vn.D[0] + ] + FAIL 0--0 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD vector operations +} + +{ + [ + OK 0101 1110 --1- ---- 11-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar) + OK 0101 1110 -10- ---- 00-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar, FP16) + OK 01-1 1110 1-10 0001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar) + OK 01-1 1110 1111 1001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar, FP16) + ] + FAIL 01-1 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD single-element operations +} + +FAIL 0-00 110- ---- ---- ---- ---- ---- ---- # Advanced SIMD structure load/store +FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography extensions +FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS + +# These are the "avoidance of doubt" final table of Illegal Advanced SIMD instructions +# We don't actually need to include these, as the default is OK. +# -001 111- ---- ---- ---- ---- ---- ---- # Scalar floating-point operations +# --10 110- ---- ---- ---- ---- ---- ---- # Load/store pair of FP registers +# --01 1100 ---- ---- ---- ---- ---- ---- # Load FP register (PC-relative literal) +# --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm) +# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) +# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) + +FAIL 0000 0100 --1- ---- 1010 ---- ---- ---- # ADR +FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA +FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT +FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS +FAIL 0010 0101 --10 1--- 1001 ---- ---- ---- # WRFFR, SETFFR +FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP +FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result) +FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA +FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL +FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD +FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA +FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA +FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions +FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar) +FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm) +FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather prefetch (scalar+vector) +FAIL 1000 010- -01- ---- 1--- ---- ---- ---- # SVE 32-bit gather load (vector+imm) +FAIL 1000 0100 0-0- ---- 0--- ---- ---- ---- # SVE 32-bit gather load byte (scalar+vector) +FAIL 1000 0100 1--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load half (scalar+vector) +FAIL 1000 0101 0--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load word (scalar+vector) +FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load (scalar+scalar) +FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load (scalar+imm) +FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar) +FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm) +FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load/prefetch +FAIL 1110 010- -00- ---- 001- ---- ---- ---- # SVE2 64-bit scatter NT store (vector+scalar) +FAIL 1110 010- -10- ---- 001- ---- ---- ---- # SVE2 32-bit scatter NT store (vector+scalar) +FAIL 1110 010- ---- ---- 1-0- ---- ---- ---- # SVE scatter store (scalar+32-bit vector) +FAIL 1110 010- ---- ---- 101- ---- ---- ---- # SVE scatter store (misc) diff --git a/target/arm/helper.c b/target/arm/helper.c index e6f37e160f..73a5b2b86d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6098,6 +6098,32 @@ int sme_exception_el(CPUARMState *env, int el) return 0; } +/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ +static bool sme_fa64(CPUARMState *env, int el) +{ + if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { + return false; + } + + if (el <= 1 && !el_is_in_host(env, el)) { + if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) { + return false; + } + } + if (el <= 2 && arm_is_el2_enabled(env)) { + if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) { + return false; + } + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) { + return false; + } + } + + return true; +} + /* * Given that SVE is enabled, return the vector length for EL. */ @@ -10801,6 +10827,20 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, DP_TBFLAG_ANY(flags, PSTATE__IL, 1); } + /* + * The SME exception we are testing for is raised via + * AArch64.CheckFPAdvSIMDEnabled(), as called from + * AArch32.CheckAdvSIMDOrFPEnabled(). + */ + if (el == 0 + && FIELD_EX64(env->svcr, SVCR, SM) + && (!arm_is_el2_enabled(env) + || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) + && arm_el_is_aa64(env, 1) + && !sme_fa64(env, el)) { + DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); + } + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } @@ -10850,6 +10890,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } if (FIELD_EX64(env->svcr, SVCR, SM)) { DP_TBFLAG_A64(flags, PSTATE_SM, 1); + DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)); } DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a5f8a6c771..7fab7f64f8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1155,7 +1155,7 @@ static void do_vec_ld(DisasContext *s, int destidx, int element, * unallocated-encoding checks (otherwise the syndrome information * for the resulting exception will be incorrect). */ -static bool fp_access_check(DisasContext *s) +static bool fp_access_check_only(DisasContext *s) { if (s->fp_excp_el) { assert(!s->fp_access_checked); @@ -1170,6 +1170,19 @@ static bool fp_access_check(DisasContext *s) return true; } +static bool fp_access_check(DisasContext *s) +{ + if (!fp_access_check_only(s)) { + return false; + } + if (s->sme_trap_nonstreaming && s->is_nonstreaming) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_Streaming, false)); + return false; + } + return true; +} + /* Check that SVE access is enabled. If it is, return true. * If not, emit code to generate an appropriate exception and return false. */ @@ -1994,7 +2007,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, default: g_assert_not_reached(); } - if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { + if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) { return; } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { return; @@ -14530,6 +14543,23 @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) } } +/* + * Include the generated SME FA64 decoder. + */ + +#include "decode-sme-fa64.c.inc" + +static bool trans_OK(DisasContext *s, arg_OK *a) +{ + return true; +} + +static bool trans_FAIL(DisasContext *s, arg_OK *a) +{ + s->is_nonstreaming = true; + return true; +} + /** * is_guarded_page: * @env: The cpu environment @@ -14657,6 +14687,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE); dc->pstate_sm = EX_TBFLAG_A64(tb_flags, PSTATE_SM); dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA); + dc->sme_trap_nonstreaming = EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTREAMING); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; @@ -14805,6 +14836,11 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } } + s->is_nonstreaming = false; + if (s->sme_trap_nonstreaming) { + disas_sme_fa64(s, insn); + } + switch (extract32(insn, 25, 4)) { case 0x0: if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) { diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 82fdbcae53..bd5ae27d09 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -234,6 +234,18 @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) return false; } + /* + * Note that rebuild_hflags_a32 has already accounted for being in EL0 + * and the higher EL in A64 mode, etc. Unlike A64 mode, there do not + * appear to be any insns which touch VFP which are allowed. + */ + if (s->sme_trap_nonstreaming) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_Streaming, + s->base.pc_next - s->pc_curr == 2)); + return false; + } + if (!s->vfp_enabled && !ignore_vfp_enabled) { assert(!arm_dc_feature(s, ARM_FEATURE_M)); unallocated_encoding(s); diff --git a/target/arm/translate.c b/target/arm/translate.c index 6617de775f..4ffb095c73 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9378,6 +9378,8 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->vec_len = EX_TBFLAG_A32(tb_flags, VECLEN); dc->vec_stride = EX_TBFLAG_A32(tb_flags, VECSTRIDE); } + dc->sme_trap_nonstreaming = + EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING); } dc->cp_regs = cpu->cp_regs; dc->features = env->features; diff --git a/target/arm/meson.build b/target/arm/meson.build index 6dd7e93643..87e911b27f 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,6 +1,7 @@ gen = [ decodetree.process('sve.decode', extra_args: '--decode=disas_sve'), decodetree.process('sme.decode', extra_args: '--decode=disas_sme'), + decodetree.process('sme-fa64.decode', extra_args: '--static-decode=disas_sme_fa64'), decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'), decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'), decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'), From patchwork Fri Jul 8 15:14:59 2022 Content-Type: text/plain; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:15:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 04/45] target/arm: Mark ADR as non-streaming Date: Fri, 8 Jul 2022 20:44:59 +0530 Message-Id: <20220708151540.18136-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Mark ADR as a non-streaming instruction, which should trap if full a64 support is not enabled in streaming mode. Removing entries from sme-fa64.decode is an easy way to see what remains to be done. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.h | 7 +++++++ target/arm/sme-fa64.decode | 1 - target/arm/translate-sve.c | 8 ++++---- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index cbc907c751..e2e619dab2 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -566,4 +566,11 @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op); static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); } +#define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \ + static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ + { \ + s->is_nonstreaming = true; \ + return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \ + } + #endif /* TARGET_ARM_TRANSLATE_H */ diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 3d90837fc7..73c71abc46 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,7 +59,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) -FAIL 0000 0100 --1- ---- 1010 ---- ---- ---- # ADR FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 62b5f3040c..5d1db0d3ff 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1320,10 +1320,10 @@ static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn) return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm); } -TRANS_FEAT(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32) -TRANS_FEAT(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64) -TRANS_FEAT(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32) -TRANS_FEAT(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32) +TRANS_FEAT_NONSTREAMING(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32) +TRANS_FEAT_NONSTREAMING(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64) +TRANS_FEAT_NONSTREAMING(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32) +TRANS_FEAT_NONSTREAMING(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32) /* *** SVE Integer Misc - Unpredicated Group From patchwork Fri Jul 8 15:15:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588517 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp755794mab; Fri, 8 Jul 2022 08:20:51 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sBHmldqv74AwrqJGTuwOG566I1yMilSlMG7ds2XTPtVoBg7+DfmYM5T6iu/GwYTQUHQG1B X-Received: by 2002:a05:6214:2b09:b0:473:4543:b3e0 with SMTP id jx9-20020a0562142b0900b004734543b3e0mr1719962qvb.0.1657293651698; Fri, 08 Jul 2022 08:20:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657293651; cv=none; d=google.com; s=arc-20160816; b=XUa4l9JIjV3pFyNzI+9vVUGsJuaE6qrZbU+EQf78q1Kn+9daX3MiHN2JWW1lGUb2R7 IwDfQbgoDHhzkEWWQf1qkFCRRS3DW+HAazv0rJv6U0uwZNDmbugggjox69FsnsHD7Qq0 LWX4T/Xx0yr1LkHNs/qFTIYclRGnCwqwetJdEXuj/LsXunohVE6OT8p4Ni+r46dqh4Vs p9Di8fqnAPd7UkWsalvlYusWkXDfjKljfac3pjDJ7fbMNPxBAG6fNvBlbCTcYmJEKcvd UAOSy4lIqFAk3enuY+w6kex2PdjfsAi4nZL+mWR8OKWEeAwbtWyMcdqxRth3fpvrR3ji y0xg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pHHLspKH8W4B5YilQ8WrGPBQ+uTIDLVeEbSmBurKp7U=; b=J1HDaJkd2KxD8J+oU5xqofUqECq8CmAlgbWEBzlG28EGgC4gWm4Rxsv9EjCnR1uG9n 9tnymzGWO473LzLxn+HMnB/XnWVDUJKheuGRe0aDzjg/BMxahmF+1WiSwZD6TLOSifrd lhFEZgPpxneLNbhIv3Z3v8aFIe9E75i0sTNHXQcNP0Fnwxt/Pz+PX0iGG05Rc/60TnPi /38Mgf89x0JEIQZi8cYYJRoFS4L2Cn9gtLtyBjPIuyBvzGsyaZrDM/lHXa62QfkQTY12 xdlrRi1UtNo4D7TnI0mvlcHlNhEu7nHIyPpPWqqwb5t1gPVDBGvksK+Rpqg2Sc50RefY /hVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LymeUmer; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.15.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 05/45] target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming Date: Fri, 8 Jul 2022 20:45:00 +0530 Message-Id: <20220708151540.18136-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 9 ++++++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 73c71abc46..fa2b5cbf1a 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -61,8 +61,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT -FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS -FAIL 0010 0101 --10 1--- 1001 ---- ---- ---- # WRFFR, SETFFR FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result) FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 5d1db0d3ff..d6faec15fe 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1785,7 +1785,8 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag) TRANS_FEAT(PTRUE, aa64_sve, do_predset, a->esz, a->rd, a->pat, a->s) /* Note pat == 31 is #all, to set all elements. */ -TRANS_FEAT(SETFFR, aa64_sve, do_predset, 0, FFR_PRED_NUM, 31, false) +TRANS_FEAT_NONSTREAMING(SETFFR, aa64_sve, + do_predset, 0, FFR_PRED_NUM, 31, false) /* Note pat == 32 is #unimp, to set no elements. */ TRANS_FEAT(PFALSE, aa64_sve, do_predset, 0, a->rd, 32, false) @@ -1799,11 +1800,13 @@ static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a) .rd = a->rd, .pg = a->pg, .s = a->s, .rn = FFR_PRED_NUM, .rm = FFR_PRED_NUM, }; + + s->is_nonstreaming = true; return trans_AND_pppp(s, &alt_a); } -TRANS_FEAT(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM) -TRANS_FEAT(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn) +TRANS_FEAT_NONSTREAMING(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM) +TRANS_FEAT_NONSTREAMING(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn) static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a, void (*gen_fn)(TCGv_i32, TCGv_ptr, From patchwork Fri Jul 8 15:15:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588521 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp758129mab; Fri, 8 Jul 2022 08:23:35 -0700 (PDT) X-Google-Smtp-Source: AGRyM1swD+Q2Q6P+kDZi2En73giMShe+5PyE/+5i7l058pt/0xF8Qffm66h8BO4XVQYbTTI6+gfu X-Received: by 2002:a05:6214:5190:b0:473:1c6a:9836 with SMTP id kl16-20020a056214519000b004731c6a9836mr3126321qvb.53.1657293815540; Fri, 08 Jul 2022 08:23:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657293815; cv=none; d=google.com; s=arc-20160816; b=zAdpaNHveOWtRj5spu3fFe+LfSc1Oat9lDaZbzo2enbBt35K0kS9IA3NKza9ap5PkM B2dlR4NPaifoFuFc7gNIxgJ9k0D6WFzmficpby6B0gNM9IjEuOSNgqa83qAOBxGmZtoh saH3ZAagY5xK88K+uNYGa717hhQfHkBHhFHXiD6Pjrxiye4eHVvOYfl3UrDIGmHVYO34 TrRMfojwlimmi7bDkaWOIN9q6v+JLUpnoenGgaheGIrrwYXKRiylbVTVDt6e18wOi903 qJla3clJ9W06/GTyySFXEkDgFggPZYi0nXy2trHc44tKVi6dPp4/WsF2LeQPc2OyQsp3 62OA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hqPebj8e+A/slNwJFXKTlqvHw3rlOVkEOFZ7HeJe4nE=; b=pxwTDHk5GOcYsVZpJ98qVUPGsqSv+5IHDt3xIui6EZHeabHRs69rx4HP+GOMILYBvF wdhossH4QIc9hzrWHD7squEN4LAAG3i3yQJLAiHJC2HkJ+2FTs1m1mGOAICx8cY1Mlor V0Sc3EB2ZXJOq7mf3sP7JNo1Q/3qzsiwA4BjSnVj7zThVf0ThUbTELsHdjqIAMWUzqMF EuNkfOygEourGLD73qRdNy7evlwVCMoQiQ+ZBWHKpLGS9A/3+YtulLgjG+0xhVxIQhKs Z1w4ZDeiyEI/o4FJ7815kku0hoZJH4m26/r3QH8QqWW9lSBQGcNesVgULt0hUxqImHCK 9yiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kXgJ9Llj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming Date: Fri, 8 Jul 2022 20:45:01 +0530 Message-Id: <20220708151540.18136-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 22 ++++++++++++---------- 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index fa2b5cbf1a..4f515939d9 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,9 +59,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) -FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA -FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT -FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result) FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index d6faec15fe..ae48040aa4 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1333,14 +1333,15 @@ static gen_helper_gvec_2 * const fexpa_fns[4] = { NULL, gen_helper_sve_fexpa_h, gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d, }; -TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz, - fexpa_fns[a->esz], a->rd, a->rn, 0) +TRANS_FEAT_NONSTREAMING(FEXPA, aa64_sve, gen_gvec_ool_zz, + fexpa_fns[a->esz], a->rd, a->rn, 0) static gen_helper_gvec_3 * const ftssel_fns[4] = { NULL, gen_helper_sve_ftssel_h, gen_helper_sve_ftssel_s, gen_helper_sve_ftssel_d, }; -TRANS_FEAT(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, ftssel_fns[a->esz], a, 0) +TRANS_FEAT_NONSTREAMING(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, + ftssel_fns[a->esz], a, 0) /* *** SVE Predicate Logical Operations Group @@ -2536,7 +2537,8 @@ TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz, static gen_helper_gvec_3 * const compact_fns[4] = { NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d }; -TRANS_FEAT(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, compact_fns[a->esz], a, 0) +TRANS_FEAT_NONSTREAMING(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, + compact_fns[a->esz], a, 0) /* Call the helper that computes the ARM LastActiveElement pseudocode * function, scaled by the element size. This includes the not found @@ -6374,22 +6376,22 @@ static gen_helper_gvec_3 * const bext_fns[4] = { gen_helper_sve2_bext_b, gen_helper_sve2_bext_h, gen_helper_sve2_bext_s, gen_helper_sve2_bext_d, }; -TRANS_FEAT(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, - bext_fns[a->esz], a, 0) +TRANS_FEAT_NONSTREAMING(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, + bext_fns[a->esz], a, 0) static gen_helper_gvec_3 * const bdep_fns[4] = { gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h, gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d, }; -TRANS_FEAT(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, - bdep_fns[a->esz], a, 0) +TRANS_FEAT_NONSTREAMING(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, + bdep_fns[a->esz], a, 0) static gen_helper_gvec_3 * const bgrp_fns[4] = { gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h, gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d, }; -TRANS_FEAT(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, - bgrp_fns[a->esz], a, 0) +TRANS_FEAT_NONSTREAMING(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, + bgrp_fns[a->esz], a, 0) static gen_helper_gvec_3 * const cadd_fns[4] = { gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h, From patchwork Fri Jul 8 15:15:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588515 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp754562mab; Fri, 8 Jul 2022 08:19:34 -0700 (PDT) X-Google-Smtp-Source: AGRyM1s6oFXRGudv/UdAXeN7/AZ0NBGZbp+8LLKtswjZewPxQ9s/5L0CbGDFqHyOTezP5ztDTiKv X-Received: by 2002:ac8:5d49:0:b0:31e:9b43:9366 with SMTP id g9-20020ac85d49000000b0031e9b439366mr3501026qtx.69.1657293574353; Fri, 08 Jul 2022 08:19:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657293574; cv=none; d=google.com; s=arc-20160816; b=uTbJi0ZQJLaYKERdcJZT/WpIFngQ7l7gJBl2oSXC0NgoberrvX3t4Ytmu3BW7JozWm v02d+nFJ8Q0ZRSu/IyPiuQXIdnt0OK0FudeciEO+jE5yvrBlGNRoINdTlsko5miPocPm Mke0FTuKe81+2dyEJqHxlY5M3P9ZIrVKlVEFM0onRJiwqPmsgnoY3Z3XLc/o3RtGFbnd 43jDn6klnRrbK/g53SjDKzrgZKGqbfOhSrAWQYijP6nTCAftNb6TtKmCYSnMrBOKTEoE EZ3si+OCJQFlsV55ThM6ABOIDG5RhvRKkxjNNvMZA0pRRoTvirgJXFPPAaM8quxpIEx2 Zm+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1btQdC+wS4/yxekRBbxVZ7KHECPJ8mO9wBrq6XRLd5o=; b=AXZotaGcDyIao9eeekDTlfxeCvlJ97NMjBUUFV3avjYNNMa9tV7a4kBRuqff3J+wF/ x0Ycxl5g90zdGPc8xq8B/6mTUN9dlj89yJtR+2AXduEYj5QAzDfqDhDAnV2WiXLhoLoi 4IMmwc3Ori60R0leMasgAxKVuIx848/+l0yRn/Qu8ZF/7ZJlMy+GMEJ526fILxNtYk0n LD0QpYU+wM8K3UYBN+ymYql/4HweWvQpR7Y2fzlO5krhpUUR55tfSM000wUV69/GIShz SEBtuQv3iA0oWRXzzx/D4uKr/n7h31DD/+ZavBhv36BnGl0Ud53/w24ZUeowThZr7Hk7 idcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y2cqkqQp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 07/45] target/arm: Mark PMULL, FMMLA as non-streaming Date: Fri, 8 Jul 2022 20:45:02 +0530 Message-Id: <20220708151540.18136-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 24 +++++++++++++++--------- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 4f515939d9..4ff2df82e5 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,8 +59,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) -FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result) -FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index ae48040aa4..4ff2102fc8 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -6186,9 +6186,13 @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel) gen_helper_gvec_pmull_q, gen_helper_sve2_pmull_h, NULL, gen_helper_sve2_pmull_d, }; - if (a->esz == 0 - ? !dc_isar_feature(aa64_sve2_pmull128, s) - : !dc_isar_feature(aa64_sve, s)) { + + if (a->esz == 0) { + if (!dc_isar_feature(aa64_sve2_pmull128, s)) { + return false; + } + s->is_nonstreaming = true; + } else if (!dc_isar_feature(aa64_sve, s)) { return false; } return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel); @@ -7125,10 +7129,12 @@ DO_ZPZZ_FP(FMINP, aa64_sve2, sve2_fminp_zpzz) * SVE Integer Multiply-Add (unpredicated) */ -TRANS_FEAT(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_s, - a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR) -TRANS_FEAT(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_d, - a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR) +TRANS_FEAT_NONSTREAMING(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, + gen_helper_fmmla_s, a->rd, a->rn, a->rm, a->ra, + 0, FPST_FPCR) +TRANS_FEAT_NONSTREAMING(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, + gen_helper_fmmla_d, a->rd, a->rn, a->rm, a->ra, + 0, FPST_FPCR) static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = { NULL, gen_helper_sve2_sqdmlal_zzzw_h, @@ -7301,8 +7307,8 @@ TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz, gen_helper_gvec_bfdot_idx, a) -TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, - gen_helper_gvec_bfmmla, a, 0) +TRANS_FEAT_NONSTREAMING(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, + gen_helper_gvec_bfmmla, a, 0) static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) { From patchwork Fri Jul 8 15:15:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588524 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp760318mab; Fri, 8 Jul 2022 08:26:19 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tANHArCusuy8bs5mvBZIp/OKi8PuwUz4oMxrzr6Sawv8/hA8FgyHjwAv0JGtCrlhsBPDWF X-Received: by 2002:a05:622a:1897:b0:31d:3f9e:d6de with SMTP id v23-20020a05622a189700b0031d3f9ed6demr3522977qtc.396.1657293979045; Fri, 08 Jul 2022 08:26:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657293979; cv=none; d=google.com; s=arc-20160816; b=067frHoUZNI937zvhy2SQ+h+m5g3i3tDx1mW0TrYjTYF4fakxsSDtk0XipFx2U7D8d qVj0vu/vEdA1jvqG1biA3WjbnG7RKFfSs/akMfpP4/G0OJmze/w9M+Q/iHideCki19Z+ dJgNnpRFoQqQOHtxRWZLERc3b7ucOGEDft7fd/NFN68hfET6ZcD/mDFnWc2Ro9jAoM2T NB0Inci5KB91QKFHuG/fpd/K+LkkNaZLgp8vSZAmIaXsL+aRP50s0A00jHdl6Vb+JbmZ lludy/5Hvo/2Rre1AuW/Kg3lojThPQjAmillvJh7oIW78ACLXdSYDdC/puFsx9jwHfvk WqUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dcHardhOi3ouG3QD1ZaU/LIrZV5tMarYA0PaEYIlrzQ=; b=MYK5/ezcFqEJZs1C02KlMvQf5onEo6fWyEXK532n28UoXksK+5aHsGmfzZ86TOUpAo UtRV2OA8Z1ekcs1+8w6FM0U9ON6ITVIcdWWzhC1YMLT04D1sfu9RyqXP5zEbqxwCOnC2 IB52QvYyhaaWCn4O4693O3HZPE4OO/eHP4xf4RVynsS5vPnsV4Lbt5peXD2Kq3y9LU1A sbprN4e8AIsPSicmVAxWFnJphJiW8DevkhXduu2+3uKGGUkN6e/HHSsMG5CRYsUMABUJ phX+4DWOKLCNALT87jkh2zT7HATuNDRDLltKQnORAon8oRXetcTEL81LnJqmJR5Eb/xV RwtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Kwr26iqk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 08/45] target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming Date: Fri, 8 Jul 2022 20:45:03 +0530 Message-Id: <20220708151540.18136-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 15 +++++++++++---- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 4ff2df82e5..b5eaa2d0fa 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,9 +59,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) -FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL -FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD -FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 4ff2102fc8..d5aad53923 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3861,9 +3861,9 @@ static gen_helper_gvec_3_ptr * const ftmad_fns[4] = { NULL, gen_helper_sve_ftmad_h, gen_helper_sve_ftmad_s, gen_helper_sve_ftmad_d, }; -TRANS_FEAT(FTMAD, aa64_sve, gen_gvec_fpst_zzz, - ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm, - a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR) +TRANS_FEAT_NONSTREAMING(FTMAD, aa64_sve, gen_gvec_fpst_zzz, + ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm, + a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR) /* *** SVE Floating Point Accumulating Reduction Group @@ -3886,6 +3886,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a) if (a->esz == 0 || !dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming = true; if (!sve_access_check(s)) { return true; } @@ -3923,12 +3924,18 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a) DO_FP3(FADD_zzz, fadd) DO_FP3(FSUB_zzz, fsub) DO_FP3(FMUL_zzz, fmul) -DO_FP3(FTSMUL, ftsmul) DO_FP3(FRECPS, recps) DO_FP3(FRSQRTS, rsqrts) #undef DO_FP3 +static gen_helper_gvec_3_ptr * const ftsmul_fns[4] = { + NULL, gen_helper_gvec_ftsmul_h, + gen_helper_gvec_ftsmul_s, gen_helper_gvec_ftsmul_d +}; +TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_fpst_arg_zzz, + ftsmul_fns[a->esz], a, 0) + /* *** SVE Floating Point Arithmetic - Predicated Group */ From patchwork Fri Jul 8 15:15:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588523 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp760205mab; Fri, 8 Jul 2022 08:26:11 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tgJDe9z9kYQTGZ49H2BxI4coxrJiivUnZKwhWRAJZ27qqxy2sWPvJe54Hw0wOrP00aNutu X-Received: by 2002:a05:622a:294:b0:31d:2983:2883 with SMTP id z20-20020a05622a029400b0031d29832883mr3448134qtw.687.1657293971861; Fri, 08 Jul 2022 08:26:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657293971; cv=none; d=google.com; s=arc-20160816; b=sOfIAzXWBTihuMazh2F4K51Xsm3o0JZ+V83xvc5oX0ihxexixolFlXQ+yylB+3dj9M CqiS8OWgePtkHQQTPAWkJYGeMUen49vSFzxF7f94MOBvPRJ2jwEyna/EvEYyzDhSnJuZ B3WwWUTR5g6c3mF55Wrjw9FjJk/DwB8Jz0NvzhFZuT5Nnh7xnGUGXGEJIcaTSM+yFLOu lJ8B2T7G1t2M9saE3dD4/zKNNVZ2D+9HPC5g7bFRjRiHer2WQ/NMxfApR64/p2kRHxqs 1Pow5O/fink2rNipMQebMgU2THMWld6uO7i6v491w5TlX4kFzZ2RCcYE0hbsMa0Vp1xh MrZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5diXjDkZ8lDduwnyqU3jDTWthnVlvOOyK5gnN0aC3a8=; b=Xdnz6idughvAKbk8VLao5uFnUEhcDiJhwOkez9wba4lZiSHAY4fxQT6x/boswTh3Zs 8N67z5NSOUQGpphwFf5Q7CdcHVPvYx4YMDg/vIkLJonYOTqq4HMgRjAiatc0v50wVOhk P2Tzq8Oz84RcY4gMx0qnGVdd5/nhKLIJDkiE7Qr0m7xtLkVA1dJtPfUDnDDqboQYLEnP ScoAWlRxhzmtfEKXnmnD4H1L1fxoNCcbT3L8ijaW22ZL6qdEOiS9MNJs1m4pzxMZuf0D cMv5UXiO/mvIgJuch+w2BRxEQHVm25RPqwgp2p/G0ah89j8HXKIz6sQMLONMUa/MGG66 xSZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xs3H7pLU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming Date: Fri, 8 Jul 2022 20:45:04 +0530 Message-Id: <20220708151540.18136-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 1 - target/arm/translate-sve.c | 12 ++++++------ 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index b5eaa2d0fa..3260ea2d64 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,7 +59,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) -FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar) FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index d5aad53923..9bbf44f008 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7302,12 +7302,12 @@ TRANS_FEAT(FMLALT_zzxw, aa64_sve2, do_FMLAL_zzxw, a, false, true) TRANS_FEAT(FMLSLB_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, false) TRANS_FEAT(FMLSLT_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, true) -TRANS_FEAT(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, - gen_helper_gvec_smmla_b, a, 0) -TRANS_FEAT(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, - gen_helper_gvec_usmmla_b, a, 0) -TRANS_FEAT(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, - gen_helper_gvec_ummla_b, a, 0) +TRANS_FEAT_NONSTREAMING(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, + gen_helper_gvec_smmla_b, a, 0) +TRANS_FEAT_NONSTREAMING(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, + gen_helper_gvec_usmmla_b, a, 0) +TRANS_FEAT_NONSTREAMING(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, + gen_helper_gvec_ummla_b, a, 0) TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, gen_helper_gvec_bfdot, a, 0) From patchwork Fri Jul 8 15:15:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588518 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp756363mab; Fri, 8 Jul 2022 08:21:35 -0700 (PDT) X-Google-Smtp-Source: AGRyM1skw8rTrY05wqjVRMXx28eISZ8qTcS9rZGA2znIB9K+WSrkQJ+jEJQrnFj951cJx4A0rqVb X-Received: by 2002:a05:620a:1e3:b0:6af:504d:c1f2 with SMTP id x3-20020a05620a01e300b006af504dc1f2mr2825647qkn.34.1657293695059; Fri, 08 Jul 2022 08:21:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657293695; cv=none; d=google.com; s=arc-20160816; b=zeeoWYXV8/XJ2SiD7bUXTV+pZDwQq3pFBpexvLGC+zGrbDaspXV24sLwyeh42M/D78 QE+IzNCbdF1Dnz17RZgXvHKkVCP+SC/rrpyP7NSoaCKj8CLjD0OeEt7pVv2Wueoo1VCW tKJ6Dknhwttq3MDRgCHmHxTB4eR+A6X1+CYVHW/V4Vt1IqvtByiiRVuQGeF185/erxIW R0xLFQYsjifqM3KzINTCat/lECxLDAUof3NxWK2NfHIpMDrX/+OKeM0krqxnPjbvKuCZ FdVGyH9cSFWMldcPdwZv2dASFPA5nTSJo9n4qVsSE1PYi/aYwjfbUz4Q1YiHYxiq6+Sz A2KA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=eMDZljSMa7lgcdxc4v8wiBGe99d03Zr6CetA/Z+JkFo=; b=QXyR7p2bAG0lt+6aYBISvMWpRvuKN1Eoe6IjmLzGvra30oakb1WUUJNYoG53X0RYrr rZDquOy1ZM8VysXiIFYlHBJgFSXNesKRVf5N/DtTPPytl0/xye2ENbdvmACO999OJT9Y EM5/4ccqjCeooxoKJU2KY1cNLObDPMdx/9d0pXN0pNuMvs0cAH+GtpjyYbrrqE2H+Om/ CdJ8yUGgb4SaCLLCNGdQa/huO00/VeXSv/gpicSRiXzyBOAOt9xyedt1bKScdh9i+Frs XEkiycwTpy5LSOwjCJr564lXpK3TdCwSdBC1cWtVDR3Sgz9UbE7JT4TEO+aRSY8IDupb ntVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bBknTnws; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 10/45] target/arm: Mark string/histo/crypto as non-streaming Date: Fri, 8 Jul 2022 20:45:05 +0530 Message-Id: <20220708151540.18136-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Mark these as non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 1 - target/arm/translate-sve.c | 35 ++++++++++++++++++----------------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 3260ea2d64..fe462d2ccc 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,7 +59,6 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) -FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar) FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm) FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather prefetch (scalar+vector) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9bbf44f008..f8e0716474 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7110,21 +7110,21 @@ DO_SVE2_ZZZ_NARROW(RSUBHNT, rsubhnt) static gen_helper_gvec_flags_4 * const match_fns[4] = { gen_helper_sve2_match_ppzz_b, gen_helper_sve2_match_ppzz_h, NULL, NULL }; -TRANS_FEAT(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz]) +TRANS_FEAT_NONSTREAMING(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz]) static gen_helper_gvec_flags_4 * const nmatch_fns[4] = { gen_helper_sve2_nmatch_ppzz_b, gen_helper_sve2_nmatch_ppzz_h, NULL, NULL }; -TRANS_FEAT(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz]) +TRANS_FEAT_NONSTREAMING(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz]) static gen_helper_gvec_4 * const histcnt_fns[4] = { NULL, NULL, gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d }; -TRANS_FEAT(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz, - histcnt_fns[a->esz], a, 0) +TRANS_FEAT_NONSTREAMING(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz, + histcnt_fns[a->esz], a, 0) -TRANS_FEAT(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz, - a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0) +TRANS_FEAT_NONSTREAMING(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz, + a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0) DO_ZPZZ_FP(FADDP, aa64_sve2, sve2_faddp_zpzz) DO_ZPZZ_FP(FMAXNMP, aa64_sve2, sve2_fmaxnmp_zpzz) @@ -7238,20 +7238,21 @@ TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_zzzz, TRANS_FEAT(USDOT_zzzz, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, a->esz == 2 ? gen_helper_gvec_usdot_b : NULL, a, 0) -TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz, - gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt) +TRANS_FEAT_NONSTREAMING(AESMC, aa64_sve2_aes, gen_gvec_ool_zz, + gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt) -TRANS_FEAT(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz, - gen_helper_crypto_aese, a, false) -TRANS_FEAT(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz, - gen_helper_crypto_aese, a, true) +TRANS_FEAT_NONSTREAMING(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz, + gen_helper_crypto_aese, a, false) +TRANS_FEAT_NONSTREAMING(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz, + gen_helper_crypto_aese, a, true) -TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, - gen_helper_crypto_sm4e, a, 0) -TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, - gen_helper_crypto_sm4ekey, a, 0) +TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, + gen_helper_crypto_sm4e, a, 0) +TRANS_FEAT_NONSTREAMING(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, + gen_helper_crypto_sm4ekey, a, 0) -TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a) +TRANS_FEAT_NONSTREAMING(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, + gen_gvec_rax1, a) TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_sh, a, 0, FPST_FPCR) From patchwork Fri Jul 8 15:15:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588519 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp757554mab; Fri, 8 Jul 2022 08:22:58 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sgG6P3fJwQ8Z6MX9eH10ppfPzJ7nzI9DDPnm2HEGA/6kwyhErG36C6vMFKTRrlb6egWh0s X-Received: by 2002:a05:620a:1907:b0:6a6:2fac:462f with SMTP id bj7-20020a05620a190700b006a62fac462fmr2588525qkb.213.1657293778840; Fri, 08 Jul 2022 08:22:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657293778; cv=none; d=google.com; s=arc-20160816; b=PRAdwallpmUy35o3rOM8ShJYakQ6ENE1fTA2hM/FB+94YDdOYmeak6M1MlWmmy5NZB wm1n4mQMFfE0XJsU09fip4GS/gFyoX7pa4Nu/6Wb2QRggcpd7yaoAnIl3Mdp41WBTAWW QUxcLectEW1PIJOtm1jpvm9PBHlVZ7UYxAZWvVtAY9xL8HxzZgFxQcxWYGfp0MiFyqqC B5Z57xqzBTU5myQCmDPcFfIS7hPVO5k6KeLFsNLXbHfdomAv6u5uBqrMBykp4IWY4MVs dQb38y7wg1S67PiVooyLd0gFBxWn0Lc5L63/7QlzQMtrwr3IhZBJeF4ZsSfrrHwdsUpQ ghZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BY/R+8YJ5Dv/43YfnL4nTrVKxj1X4wUM5az+kdRyBN4=; b=SWv3fPyyKHG2ShinehqiEKVDGlnVxBKAvgYwBcR9d86UQs6SQL69HYrpdO0xYu4iHa ykw/NbMzcABSijcaw2CALHOH5cuPgcQ4GgSGFXyYpoRiSeAVW1xYY46iyqhVj7aEZSYJ VmpQSdHm5DwKMgq0C2mqb+B5zzTh/GN+4qSiVtkgWLQG7z/FjVAoxQINuDr/qYYsvXU9 Af/4D8ODNtWxv1HgSmiq17ynPjqoO/w7z/RP9M2Snu0iMMinPc1KNGpuG4jFVOPcT6gZ cDSXmNR8dJWZ/ao7gVHq3QQ0VkW28JyLYedm5UJ/PTSu1cRsmIkpe23Vb9QRu1H9oDAW 5LJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H3aB0a6K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 11/45] target/arm: Mark gather/scatter load/store as non-streaming Date: Fri, 8 Jul 2022 20:45:06 +0530 Message-Id: <20220708151540.18136-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 9 --------- target/arm/translate-sve.c | 6 ++++++ 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index fe462d2ccc..1acc3ae080 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,19 +59,10 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) -FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar) FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm) FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather prefetch (scalar+vector) -FAIL 1000 010- -01- ---- 1--- ---- ---- ---- # SVE 32-bit gather load (vector+imm) -FAIL 1000 0100 0-0- ---- 0--- ---- ---- ---- # SVE 32-bit gather load byte (scalar+vector) -FAIL 1000 0100 1--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load half (scalar+vector) -FAIL 1000 0101 0--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load word (scalar+vector) FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load (scalar+scalar) FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load (scalar+imm) FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar) FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm) FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load/prefetch -FAIL 1110 010- -00- ---- 001- ---- ---- ---- # SVE2 64-bit scatter NT store (vector+scalar) -FAIL 1110 010- -10- ---- 001- ---- ---- ---- # SVE2 32-bit scatter NT store (vector+scalar) -FAIL 1110 010- ---- ---- 1-0- ---- ---- ---- # SVE scatter store (scalar+32-bit vector) -FAIL 1110 010- ---- ---- 101- ---- ---- ---- # SVE scatter store (misc) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index f8e0716474..b23c6aa0bf 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5669,6 +5669,7 @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming = true; if (!sve_access_check(s)) { return true; } @@ -5700,6 +5701,7 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming = true; if (!sve_access_check(s)) { return true; } @@ -5734,6 +5736,7 @@ static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a) if (!dc_isar_feature(aa64_sve2, s)) { return false; } + s->is_nonstreaming = true; if (!sve_access_check(s)) { return true; } @@ -5857,6 +5860,7 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming = true; if (!sve_access_check(s)) { return true; } @@ -5887,6 +5891,7 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming = true; if (!sve_access_check(s)) { return true; } @@ -5921,6 +5926,7 @@ static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a) if (!dc_isar_feature(aa64_sve2, s)) { return false; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 12/45] target/arm: Mark gather prefetch as non-streaming Date: Fri, 8 Jul 2022 20:45:07 +0530 Message-Id: <20220708151540.18136-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. In this case, introduce PRF_ns (prefetch non-streaming) to handle the checks. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/sve.decode | 10 +++++----- target/arm/translate-sve.c | 11 +++++++++++ 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 1acc3ae080..7d4c33fb5b 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,10 +59,7 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) -FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm) -FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather prefetch (scalar+vector) FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load (scalar+scalar) FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load (scalar+imm) FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar) FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm) -FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load/prefetch diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a54feb2f61..908643d7d9 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1183,10 +1183,10 @@ LD1RO_zpri 1010010 .. 01 0.... 001 ... ..... ..... \ @rpri_load_msz nreg=0 # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) -PRF 1000010 00 -1 ----- 0-- --- ----- 0 ---- +PRF_ns 1000010 00 -1 ----- 0-- --- ----- 0 ---- # SVE 32-bit gather prefetch (vector plus immediate) -PRF 1000010 -- 00 ----- 111 --- ----- 0 ---- +PRF_ns 1000010 -- 00 ----- 111 --- ----- 0 ---- # SVE contiguous prefetch (scalar plus immediate) PRF 1000010 11 1- ----- 0-- --- ----- 0 ---- @@ -1223,13 +1223,13 @@ LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \ @rpri_g_load esz=3 # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets) -PRF 1100010 00 11 ----- 1-- --- ----- 0 ---- +PRF_ns 1100010 00 11 ----- 1-- --- ----- 0 ---- # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets) -PRF 1100010 00 -1 ----- 0-- --- ----- 0 ---- +PRF_ns 1100010 00 -1 ----- 0-- --- ----- 0 ---- # SVE 64-bit gather prefetch (vector plus immediate) -PRF 1100010 -- 00 ----- 111 --- ----- 0 ---- +PRF_ns 1100010 -- 00 ----- 111 --- ----- 0 ---- ### SVE Memory Store Group diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index b23c6aa0bf..bbf3bf2119 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5971,6 +5971,17 @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a) return true; } +static bool trans_PRF_ns(DisasContext *s, arg_PRF_ns *a) +{ + if (!dc_isar_feature(aa64_sve, s)) { + return false; + } + /* Prefetch is a nop within QEMU. */ + s->is_nonstreaming = true; + (void)sve_access_check(s); + return true; +} + /* * Move Prefix * From patchwork Fri Jul 8 15:15:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588527 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp762462mab; Fri, 8 Jul 2022 08:28:59 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tSHVUszL5LtdgfAAbDnT1393D1fqKekxBpYywqEFPrYEYp6GiYvDNPGaWs5cc/kvJnIg2t X-Received: by 2002:ac8:5f8e:0:b0:31e:79ec:2931 with SMTP id j14-20020ac85f8e000000b0031e79ec2931mr3428310qta.196.1657294139814; Fri, 08 Jul 2022 08:28:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657294139; cv=none; d=google.com; s=arc-20160816; b=0qTE/WeH/bvJlmZSPMaBGldL4X07QngBK3AOexaE6LG8BaGWtza2CZrkH6fqx4iZ1Z Urm2ywPwojjJX4Nng/6pJwfUJ7hnXW2YpGg3IIlFPesNJ7v2RilpGNczfjd+pyMevbnJ TJqKwlxdpev/GW1HkZXi288pD0lddObQVZz1Du7CSsO2l9nfRUyhSZasnEaSAu7u2Q71 SxPzk75ZUijFJCS5E6IgbxXlAWc8hHNKRlR3jccsSljA54B8xxJXCGdt4Tq/uqa9dIq3 j95cblpILGt125SPt6BBpIn+kMBpiCn+4oL+fXC/cVapYfK1GnUvfNgeaeHqQh1s1v/S LxTg== ARC-Message-Signature: i=1; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 13/45] target/arm: Mark LDFF1 and LDNF1 as non-streaming Date: Fri, 8 Jul 2022 20:45:08 +0530 Message-Id: <20220708151540.18136-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 7d4c33fb5b..2b5432bf85 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -59,7 +59,5 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) -FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load (scalar+scalar) -FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load (scalar+imm) FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar) FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index bbf3bf2119..5182ee4c06 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4805,6 +4805,7 @@ static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming = true; if (sve_access_check(s)) { TCGv_i64 addr = new_tmp_a64(s); tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); @@ -4906,6 +4907,7 @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming = true; if (sve_access_check(s)) { int vsz = vec_full_reg_size(s); int elements = vsz >> dtype_esz[a->dtype]; From patchwork Fri Jul 8 15:15:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588526 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp762120mab; Fri, 8 Jul 2022 08:28:32 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tVmFuHhXVzE58ybDTUSGn3Oc3tYJiQUtF1MIPSUMYYXRgAHmSRLz0RcODgxiX1XeVob7u2 X-Received: by 2002:ad4:4ea7:0:b0:473:444c:d522 with SMTP id ed7-20020ad44ea7000000b00473444cd522mr1837587qvb.44.1657294112173; Fri, 08 Jul 2022 08:28:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657294112; cv=none; d=google.com; s=arc-20160816; b=VqIrCfl2FPhTZYhBOFf/90UGysh3EsBB5E9Ewt6x4poKQF4dL27tOdz4QImOJCCr8P 0dOS2h3Np8UnOWh+ckOfK0KcSNATyY+Cv/xIIhNd1xnMQPNQd/uTNYO1lmU5sBJsY1CL 8DGHYEulCMyxQkVYTj33aV5vofnuiJbgqrswRsSaEQFHFVbUgmceCxToic+3WkZXsHqU gHd2Tr2ecng37onJGRyn+DMmyxrKQ7TAFHW2qFL6NljDqomDpupVtG2VY4G2owFGl0Us bFznRvFuvxgkspu6JJBt5nGi7CxckezXP12SZeEqv5s43DmokeQ4RWeAjdpJ+ZT5zSK3 X8iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Eedjnu3eOCixQFi7+Gzy6ksLbMXPKA3RAkF+Pv5QpfE=; b=oQns4mLoSMm3aKDuKouLdZo/kqqH6KJu0E/kzrqc2YwyWj1GAPYP+UPeZaHtlrfx8S NN0z7fINOOaqf5Wt5Qv/TlvjCxMHBnx8KkTUJOoWr+dDiizn6zYANlSj1uFE9GRfDu13 pjhQSB5f93opARB6oj3btkq+Ri2qkYlzHzlxMf12gHdAh0Er/Ra4w4f05tIzZFw+kYNF 37cqjc/vws50bBPdfS5qvTRZDnIA4LKUApRcCNu2hp8X+Nxz2s3yWoNUFjxhDEv7GD64 LBq96JXmLzJ2380RBvmrR72xf/3bEzw06qY9WeSLD87njhXt9AVk/LlmNgSvD+Y+/6ey bfDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RLRqYk0b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 14/45] target/arm: Mark LD1RO as non-streaming Date: Fri, 8 Jul 2022 20:45:09 +0530 Message-Id: <20220708151540.18136-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 2b5432bf85..47708ccc8d 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -58,6 +58,3 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS # --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm) # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) - -FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar) -FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 5182ee4c06..96e934c1ea 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5062,6 +5062,7 @@ static bool trans_LD1RO_zprr(DisasContext *s, arg_rprr_load *a) if (a->rm == 31) { return false; } + s->is_nonstreaming = true; if (sve_access_check(s)) { TCGv_i64 addr = new_tmp_a64(s); tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); @@ -5076,6 +5077,7 @@ static bool trans_LD1RO_zpri(DisasContext *s, arg_rpri_load *a) if (!dc_isar_feature(aa64_sve_f64mm, s)) { return false; } + s->is_nonstreaming = true; if (sve_access_check(s)) { TCGv_i64 addr = new_tmp_a64(s); tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32); From patchwork Fri Jul 8 15:15:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588531 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp765281mab; Fri, 8 Jul 2022 08:32:16 -0700 (PDT) X-Google-Smtp-Source: AGRyM1ujeg/PksXvkMXCUsNa/eakT8rfah5nesGzoG6tZsvsatC1n7X5s1XmXH9K8VUcU++EMoFE X-Received: by 2002:a05:620a:4843:b0:6ae:e906:ea49 with SMTP id ec3-20020a05620a484300b006aee906ea49mr2708086qkb.744.1657294336496; Fri, 08 Jul 2022 08:32:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657294336; cv=none; d=google.com; s=arc-20160816; b=r9saU3ZtkiwVfjdDfvxXgsVR5A3dMVi0QMKxztaYNNr/Pt/9gECskPrzNG4rF9euiA TJ5Ba1vVUnizJkKH0sB6VrEv/Vbl2Wj9hEx7oufvg/9avBgTcsdm7sunQgF956h9KG4D s80PYYdl3vMLoAibm5ako8H4iH4nY5swsk4kAIsZ+QDg0ZgFZ9ddjNFjno2xHPajgWal kYtteILvvKXAXMnbrPXjKbmFUYGVb9Ll66o+2Q1aqG8nRG0BdfiteKAc3hwzUeQwW8xT bZ3QPe4Oe57+M8ENnmUztyxlZkxVPexHSNr6qfFIf+h4WuB1zrcBKBE6FINjPIKuLkM1 CwcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PhJtFSrquOFUVO5QY9Q5zh4pNEWnYjCw2RgtobhuW2s=; b=Z5vEbE6eknTfgeXKwsORf3KkAO7cldOq5Tf6I9Dba/PRWDISD2F3Hh+g+P5ZWlJAkw drSEh/Y7VY6jDRnpN3zfUHMZK1YaTx9qJyD6K44grYqWkPjGwltnS5meoqo/2XyyM2JQ D0fVwYvsL4ZvhhdTJHIGu4AEkTJxrnZcphzVH1qNKmzNgB9EMHf9oVVo1Yq0VeBMSxYC aeU1a0VH4iLCbOSMd9knSDk2Iv8zI0Ps7MOjWwjNt8Buk7oJ5bixv3Qrir8uqSOcnoW/ cUEri1a9hCcMSR2ftZKJ5ykKvdqGadHAa5R1egK2W8OfIFSsmM52eN0Jd4YYlMQDACot A3Zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lWMF37XJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 15/45] target/arm: Add SME enablement checks Date: Fri, 8 Jul 2022 20:45:10 +0530 Message-Id: <20220708151540.18136-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These functions will be used to verify that the cpu is in the correct state for a given instruction. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 21 +++++++++++++++++++++ target/arm/translate-a64.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 789b6e8e78..02fb95e019 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -29,6 +29,27 @@ void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v); bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, unsigned int imms, unsigned int immr); bool sve_access_check(DisasContext *s); +bool sme_enabled_check(DisasContext *s); +bool sme_enabled_check_with_svcr(DisasContext *s, unsigned); + +/* This function corresponds to CheckStreamingSVEEnabled. */ +static inline bool sme_sm_enabled_check(DisasContext *s) +{ + return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK); +} + +/* This function corresponds to CheckSMEAndZAEnabled. */ +static inline bool sme_za_enabled_check(DisasContext *s) +{ + return sme_enabled_check_with_svcr(s, R_SVCR_ZA_MASK); +} + +/* Note that this function corresponds to CheckStreamingSVEAndZAEnabled. */ +static inline bool sme_smza_enabled_check(DisasContext *s) +{ + return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK | R_SVCR_ZA_MASK); +} + TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int log2_size); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7fab7f64f8..b16d81bf19 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1216,6 +1216,40 @@ static bool sme_access_check(DisasContext *s) return true; } +/* This function corresponds to CheckSMEEnabled. */ +bool sme_enabled_check(DisasContext *s) +{ + /* + * Note that unlike sve_excp_el, we have not constrained sme_excp_el + * to be zero when fp_excp_el has priority. This is because we need + * sme_excp_el by itself for cpregs access checks. + */ + if (!s->fp_excp_el || s->sme_excp_el < s->fp_excp_el) { + s->fp_access_checked = true; + return sme_access_check(s); + } + return fp_access_check_only(s); +} + +/* Common subroutine for CheckSMEAnd*Enabled. */ +bool sme_enabled_check_with_svcr(DisasContext *s, unsigned req) +{ + if (!sme_enabled_check(s)) { + return false; + } + if (FIELD_EX64(req, SVCR, SM) && !s->pstate_sm) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_NotStreaming, false)); + return false; + } + if (FIELD_EX64(req, SVCR, ZA) && !s->pstate_za) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_InactiveZA, false)); + return false; + } + return true; +} + /* * This utility function is for doing register extension with an * optional shift. You will likely want to pass a temporary for the From patchwork Fri Jul 8 15:15:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588530 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp764179mab; Fri, 8 Jul 2022 08:31:01 -0700 (PDT) X-Google-Smtp-Source: AGRyM1twuhCxz+FYBqAiQzNLZv7ujvgYfVmSeJ4/SafOYwEhrnuDXqsanswfBDhRR3rOYwwjsDYi X-Received: by 2002:a05:620a:284b:b0:6b4:8685:2aa6 with SMTP id h11-20020a05620a284b00b006b486852aa6mr2754427qkp.780.1657294261578; Fri, 08 Jul 2022 08:31:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657294261; cv=none; d=google.com; s=arc-20160816; b=D4DPH7Cnqout1yodNe28N6pzdhzm3oMp8VWBTE5qrlYp02c0o4v9d0AreaaAf40Hg/ oCAaEnGu6VGBUQ2YkiJ6g1fIKsn1uvFWGIuCavLFTc/MQzPQIwVLS8c/dfD7+IQ3slRM dxnKBsSCtK4gE/sscuB30gfpHnaSSptxr9KmH2cLPymNXPzGAYvReD80KCCyCbfBwiZ0 aRGV88rqVIvsYTpRZfptBuQkSA00WOtcCt4D0KjYqP49wTNG3duMao55JQ4oBM8PZ4sL ONp5OXoOw7s6kb9KhKYronHTvAVKeoizhyU9mDlAWdCUw+Ce176afqkqYXCCt1a75JkV ICHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0yTWCJ1DktZzYQTXntYaiEXNGmdccKtN6uvynpzt0IU=; b=Fh6rjlJifHJoxSohVUDtbxbflY7Xro7xGI0trQbHc0dLzTpLH0cmGoPfvpkZgSybfd s5O5ChjaEwLjK09VqVPX0WUVi7gS+i7820cB6NeN9yQyx3YHDHY3LcrZr+GybPyAe1au LZxsw7HyuxpH0s500iA473ovhrmhQLbpNJtEtmHjN0plBgzo7vOnG3KJTlOPQo7F25iZ BDQVeksfQkwSCcgMgQUtg0xPMEplPdF3/O4BvKQ9RYnfy+d0z/in6CjXu23nl4rZQP00 5U9ejt3QH+1kqEch6lq/OV+FBvFhACuUWdK21UtUOa647WY5iqjKxzwLRHxEzFln9pGJ oNVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ykcqy5iL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 16/45] target/arm: Handle SME in sve_access_check Date: Fri, 8 Jul 2022 20:45:11 +0530 Message-Id: <20220708151540.18136-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The pseudocode for CheckSVEEnabled gains a check for Streaming SVE mode, and for SME present but SVE absent. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b16d81bf19..b7b64f7358 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1183,21 +1183,31 @@ static bool fp_access_check(DisasContext *s) return true; } -/* Check that SVE access is enabled. If it is, return true. +/* + * Check that SVE access is enabled. If it is, return true. * If not, emit code to generate an appropriate exception and return false. + * This function corresponds to CheckSVEEnabled(). */ bool sve_access_check(DisasContext *s) { - if (s->sve_excp_el) { - assert(!s->sve_access_checked); - s->sve_access_checked = true; - + if (s->pstate_sm || !dc_isar_feature(aa64_sve, s)) { + assert(dc_isar_feature(aa64_sme, s)); + if (!sme_sm_enabled_check(s)) { + goto fail_exit; + } + } else if (s->sve_excp_el) { gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(), s->sve_excp_el); - return false; + goto fail_exit; } s->sve_access_checked = true; return fp_access_check(s); + + fail_exit: + /* Assert that we only raise one exception per instruction. */ + assert(!s->sve_access_checked); + s->sve_access_checked = true; + return false; } /* From patchwork Fri Jul 8 15:15:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588533 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp767668mab; Fri, 8 Jul 2022 08:34:58 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vGTTNoD0sJD7vBS8/+t3X0N4Ygf1bMb/4UpXcw1qy4WkcnVT3jw9yXfNDFHRV2fNaDIj5+ X-Received: by 2002:a05:620a:440e:b0:6b2:82cf:d7f9 with SMTP id v14-20020a05620a440e00b006b282cfd7f9mr2674743qkp.761.1657294498851; Fri, 08 Jul 2022 08:34:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657294498; cv=none; d=google.com; s=arc-20160816; b=eh97qnUCMxVIxhNmRASxzI6+ccVQQCQT/n8RgXAloBoFxFgqgT0u1x8gNrVzivVvlY BTgpvthLl4maUNYCN7XojsH1fjvBuFvwtMtuvF0jX2H0S6s8dMiS00dLiT04nGbqXwnN GzD7rP1TvBhsVGGudLoypMQu4ViOm6VD8EquUBiQxyGmKsLORa1zF6ZXrxqlwbsnrj5V Hj9+Jnani78czR1EsgMcdnpv6fIwqSzpCsHycWB7SisqSE4qjUXWqGJRGTJvZHc5kt8R LKHp1OjXBTU7YS38Kr7Vb3vP2UzYiZjci9+/ExHvajlXX8EL/GOtXEeExNAKe1Xk4rJ4 6U0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KwsMd3cs1kMRtBrVlO0pZElFPRsZqBMQRBB6JbUzQes=; b=cz0VFSPD/kOSIDghP1ZKYWk8c6kp10Z4jesXYe3t9NxhrGMF61xLN//ZnZnT9yDQaf Wr9B4vZx/6Azj6FxT4DpRUv1n3g+HKwZjut5YJxV1JuTSc0T2RyHIG1czr/heVkKEPOj zqOK17IdYEeJ1Y6I6qaYaLfQWcCUSF9oPHpbPf9wlQVLPSrYktLTT4hsF9oodZK8PpRV By7RERhkUfNqIZT3oG15hUXOZjaO6oblxUAiFZyhZRu3R7R1Vcs1rYjc045nBKdFO0aS N46eezbF2V760EreI4jsZrG9PvU9pbxq0sV16B6SRGqBdWpPDjjFXfPUahmMPnuALesO t6QQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cRKGy8VK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 17/45] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL Date: Fri, 8 Jul 2022 20:45:12 +0530 Message-Id: <20220708151540.18136-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These SME instructions are nominally within the SVE decode space, so we add them to sve.decode and translate-sve.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Add streaming_{vec,pred}_reg_size. --- target/arm/translate-a64.h | 12 ++++++++++++ target/arm/sve.decode | 5 ++++- target/arm/translate-sve.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 02fb95e019..099d3d11d6 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -128,6 +128,12 @@ static inline int vec_full_reg_size(DisasContext *s) return s->vl; } +/* Return the byte size of the vector register, SVL / 8. */ +static inline int streaming_vec_reg_size(DisasContext *s) +{ + return s->svl; +} + /* * Return the offset info CPUARMState of the predicate vector register Pn. * Note for this purpose, FFR is P16. @@ -143,6 +149,12 @@ static inline int pred_full_reg_size(DisasContext *s) return s->vl >> 3; } +/* Return the byte size of the predicate register, SVL / 64. */ +static inline int streaming_pred_reg_size(DisasContext *s) +{ + return s->svl >> 3; +} + /* * Round up the size of a register to a size allowed by * the tcg vector infrastructure. Any operation which uses this diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 908643d7d9..95af08c139 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -449,14 +449,17 @@ INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 # SVE index generation (register start, register increment) INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm -### SVE Stack Allocation Group +### SVE / Streaming SVE Stack Allocation Group # SVE stack frame adjustment ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 +ADDSVL 00000100 001 ..... 01011 ...... ..... @rd_rn_i6 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 +ADDSPL 00000100 011 ..... 01011 ...... ..... @rd_rn_i6 # SVE stack frame size RDVL 00000100 101 11111 01010 imm:s6 rd:5 +RDSVL 00000100 101 11111 01011 imm:s6 rd:5 ### SVE Bitwise Shift - Unpredicated Group diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 96e934c1ea..95016e49e9 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1286,6 +1286,19 @@ static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a) return true; } +static bool trans_ADDSVL(DisasContext *s, arg_ADDSVL *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_enabled_check(s)) { + TCGv_i64 rd = cpu_reg_sp(s, a->rd); + TCGv_i64 rn = cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * streaming_vec_reg_size(s)); + } + return true; +} + static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) { if (!dc_isar_feature(aa64_sve, s)) { @@ -1299,6 +1312,19 @@ static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) return true; } +static bool trans_ADDSPL(DisasContext *s, arg_ADDSPL *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_enabled_check(s)) { + TCGv_i64 rd = cpu_reg_sp(s, a->rd); + TCGv_i64 rn = cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * streaming_pred_reg_size(s)); + } + return true; +} + static bool trans_RDVL(DisasContext *s, arg_RDVL *a) { if (!dc_isar_feature(aa64_sve, s)) { @@ -1311,6 +1337,18 @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a) return true; } +static bool trans_RDSVL(DisasContext *s, arg_RDSVL *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_enabled_check(s)) { + TCGv_i64 reg = cpu_reg(s, a->rd); + tcg_gen_movi_i64(reg, a->imm * streaming_vec_reg_size(s)); + } + return true; +} + /* *** SVE Compute Vector Address Group */ From patchwork Fri Jul 8 15:15:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588537 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp770665mab; Fri, 8 Jul 2022 08:38:42 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uxOoakO31UoqdO7JzxDAa2Qyk28mWNgaM0eE1nvV8BQlZlCrte3rfgA0pz8x2deHj+UcpQ X-Received: by 2002:a05:622a:1453:b0:31d:4c06:4a04 with SMTP id v19-20020a05622a145300b0031d4c064a04mr3505141qtx.432.1657294722187; Fri, 08 Jul 2022 08:38:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657294722; cv=none; d=google.com; s=arc-20160816; b=VAOZEXKymrQMmLzca0xNen6J7cQnMcN/aSDmCSGwYAJAK7rYLZr7k7XKqfvFY3TJzd CvFPVDvZVxgg5+yNi87MGXsSWLWO0Xk+j9LEz+01fQUaRhj39iCKaXb1RlpZQxzg/eVU ywKtYnhdNUY9BwhdINkDhNRsV0b1F0eOjE+FIqm8W8bOrXcCMjP+sqIhZoLGgLVnGEQ7 +oBxCcOpM6LSI2ZJTLm5jnASBYafJVfd73rOKILt9aFCqZTqQbuugixb90lSCT6RHgA+ A2iP8ftMLgIVqNoi8kXE17gu2o/yc1/YFg4ZhpwTjpdYjasZh60qkbKpaVCzTBK7WPhh Ippg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8q6UgHZNxgLAwjYyD3emx4pnHnGEMm3xg5CqdRKZ5yA=; b=h8RlRlMkXnSYSZsPM14yuw58wGo/pla/WRFRdvXwtlfyYUo21HAoq3O/dzPJzs43q9 XaRjODwT427d5oTFp0fDyDJ5th3guyO7U+gFP6AXHOv+9WduiXzEPeD6w0sud00FYq7b gb3l38UVUjsZWbw7UUBl+OjgEatty20sMFz493PrLUlzXiUTmr/Ia3+VY6TGHCf1H/vr TEk0AJKeudyCM0WkuWq2uC5SfV2r8q2pere4BVstBwB1a42J5jVorvqd85FPgtxyINyB pgWDA5q1p9tivtBiQOnsH3GEN/JGaiNAx1i0OBI3GD9artoZMt6qHsemH1d+3Y5yN1XG eUyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rlh1uGi3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 18/45] target/arm: Implement SME ZERO Date: Fri, 8 Jul 2022 20:45:13 +0530 Message-Id: <20220708151540.18136-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Fix ZA[] comment in helper_sme_zero. --- target/arm/helper-sme.h | 2 ++ target/arm/sme.decode | 4 ++++ target/arm/sme_helper.c | 25 +++++++++++++++++++++++++ target/arm/translate-sme.c | 13 +++++++++++++ 4 files changed, 44 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 3bd48c235f..c4ee1f09e4 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -19,3 +19,5 @@ DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32) + +DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index c25c031a71..6e4483fdce 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -18,3 +18,7 @@ # # This file is processed by scripts/decodetree.py # + +### SME Misc + +ZERO 11000000 00 001 00000000000 imm:8 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index b215725594..eef2df73e1 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -59,3 +59,28 @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i) memset(env->zarray, 0, sizeof(env->zarray)); } } + +void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl) +{ + uint32_t i; + + /* + * Special case clearing the entire ZA space. + * This falls into the CONSTRAINED UNPREDICTABLE zeroing of any + * parts of the ZA storage outside of SVL. + */ + if (imm == 0xff) { + memset(env->zarray, 0, sizeof(env->zarray)); + return; + } + + /* + * Recall that ZAnH.D[m] is spread across ZA[n+8*m], + * so each row is discontiguous within ZA[]. + */ + for (i = 0; i < svl; i++) { + if (imm & (1 << (i % 8))) { + memset(&env->zarray[i], 0, svl); + } + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 786c93fb2d..971504559b 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -33,3 +33,16 @@ */ #include "decode-sme.c.inc" + + +static bool trans_ZERO(DisasContext *s, arg_ZERO *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_za_enabled_check(s)) { + gen_helper_sme_zero(cpu_env, tcg_constant_i32(a->imm), + tcg_constant_i32(streaming_vec_reg_size(s))); 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 19/45] target/arm: Implement SME MOVA Date: Fri, 8 Jul 2022 20:45:14 +0530 Message-Id: <20220708151540.18136-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can reuse the SVE functions for implementing moves to/from horizontal tile slices, but we need new ones for moves to/from vertical tile slices. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 12 +++ target/arm/helper-sve.h | 2 + target/arm/translate-a64.h | 8 ++ target/arm/translate.h | 5 ++ target/arm/sme.decode | 15 ++++ target/arm/sme_helper.c | 151 ++++++++++++++++++++++++++++++++++++- target/arm/sve_helper.c | 12 +++ target/arm/translate-sme.c | 127 +++++++++++++++++++++++++++++++ 8 files changed, 331 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index c4ee1f09e4..154bc73d2e 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -21,3 +21,15 @@ DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32) + +/* Move to/from vertical array slices, i.e. columns, so 'c'. */ +DEF_HELPER_FLAGS_4(sme_mova_cz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_zc_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_cz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_zc_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_cz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_zc_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_cz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_zc_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_cz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_zc_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index dc629f851a..ab0333400f 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -325,6 +325,8 @@ DEF_HELPER_FLAGS_5(sve_sel_zpzz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve_sel_zpzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_sel_zpzz_q, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve2_addp_zpzz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 099d3d11d6..2a7fe6e9e7 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -178,6 +178,14 @@ static inline int pred_gvec_reg_size(DisasContext *s) return size_for_gvec(pred_full_reg_size(s)); } +/* Return a newly allocated pointer to the predicate register. */ +static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno) +{ + TCGv_ptr ret = tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ret, cpu_env, pred_full_reg_offset(s, regno)); + return ret; +} + bool disas_sve(DisasContext *, uint32_t); bool disas_sme(DisasContext *, uint32_t); diff --git a/target/arm/translate.h b/target/arm/translate.h index e2e619dab2..af5d4a7086 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -156,6 +156,11 @@ static inline int plus_2(DisasContext *s, int x) return x + 2; } +static inline int plus_12(DisasContext *s, int x) +{ + return x + 12; +} + static inline int times_2(DisasContext *s, int x) { return x * 2; diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 6e4483fdce..241b4895b7 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -22,3 +22,18 @@ ### SME Misc ZERO 11000000 00 001 00000000000 imm:8 + +### SME Move into/from Array + +%mova_rs 13:2 !function=plus_12 +&mova esz rs pg zr za_imm v:bool to_vec:bool + +MOVA 11000000 esz:2 00000 0 v:1 .. pg:3 zr:5 0 za_imm:4 \ + &mova to_vec=0 rs=%mova_rs +MOVA 11000000 11 00000 1 v:1 .. pg:3 zr:5 0 za_imm:4 \ + &mova to_vec=0 rs=%mova_rs esz=4 + +MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5 \ + &mova to_vec=1 rs=%mova_rs +MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \ + &mova to_vec=1 rs=%mova_rs esz=4 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index eef2df73e1..e88244423d 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -19,8 +19,10 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "internals.h" +#include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" +#include "qemu/int128.h" +#include "vec_internal.h" /* ResetSVEState */ void arm_reset_sve_state(CPUARMState *env) @@ -84,3 +86,150 @@ void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl) } } } + + +/* + * When considering the ZA storage as an array of elements of + * type T, the index within that array of the Nth element of + * a vertical slice of a tile can be calculated like this, + * regardless of the size of type T. This is because the tiles + * are interleaved, so if type T is size N bytes then row 1 of + * the tile is N rows away from row 0. The division by N to + * convert a byte offset into an array index and the multiplication + * by N to convert from vslice-index-within-the-tile to + * the index within the ZA storage cancel out. + */ +#define tile_vslice_index(i) ((i) * sizeof(ARMVectorReg)) + +/* + * When doing byte arithmetic on the ZA storage, the element + * byteoff bytes away in a tile vertical slice is always this + * many bytes away in the ZA storage, regardless of the + * size of the tile element, assuming that byteoff is a multiple + * of the element size. Again this is because of the interleaving + * of the tiles. For instance if we have 1 byte per element then + * each row of the ZA storage has one byte of the vslice data, + * and (counting from 0) byte 8 goes in row 8 of the storage + * at offset (8 * row-size-in-bytes). + * If we have 8 bytes per element then each row of the ZA storage + * has 8 bytes of the data, but there are 8 interleaved tiles and + * so byte 8 of the data goes into row 1 of the tile, + * which is again row 8 of the storage, so the offset is still + * (8 * row-size-in-bytes). Similarly for other element sizes. + */ +#define tile_vslice_offset(byteoff) ((byteoff) * sizeof(ARMVectorReg)) + + +/* + * Move Zreg vector to ZArray column. + */ +#define DO_MOVA_C(NAME, TYPE, H) \ +void HELPER(NAME)(void *za, void *vn, void *vg, uint32_t desc) \ +{ \ + int i, oprsz = simd_oprsz(desc); \ + for (i = 0; i < oprsz; ) { \ + uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + *(TYPE *)(za + tile_vslice_offset(i)) = *(TYPE *)(vn + H(i)); \ + } \ + i += sizeof(TYPE); \ + pg >>= sizeof(TYPE); \ + } while (i & 15); \ + } \ +} + +DO_MOVA_C(sme_mova_cz_b, uint8_t, H1) +DO_MOVA_C(sme_mova_cz_h, uint16_t, H1_2) +DO_MOVA_C(sme_mova_cz_s, uint32_t, H1_4) + +void HELPER(sme_mova_cz_d)(void *za, void *vn, void *vg, uint32_t desc) +{ + int i, oprsz = simd_oprsz(desc) / 8; + uint8_t *pg = vg; + uint64_t *n = vn; + uint64_t *a = za; + + for (i = 0; i < oprsz; i++) { + if (pg[H1(i)] & 1) { + a[tile_vslice_index(i)] = n[i]; + } + } +} + +void HELPER(sme_mova_cz_q)(void *za, void *vn, void *vg, uint32_t desc) +{ + int i, oprsz = simd_oprsz(desc) / 16; + uint16_t *pg = vg; + Int128 *n = vn; + Int128 *a = za; + + /* + * Int128 is used here simply to copy 16 bytes, and to simplify + * the address arithmetic. + */ + for (i = 0; i < oprsz; i++) { + if (pg[H2(i)] & 1) { + a[tile_vslice_index(i)] = n[i]; + } + } +} + +#undef DO_MOVA_C + +/* + * Move ZArray column to Zreg vector. + */ +#define DO_MOVA_Z(NAME, TYPE, H) \ +void HELPER(NAME)(void *vd, void *za, void *vg, uint32_t desc) \ +{ \ + int i, oprsz = simd_oprsz(desc); \ + for (i = 0; i < oprsz; ) { \ + uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + *(TYPE *)(vd + H(i)) = *(TYPE *)(za + tile_vslice_offset(i)); \ + } \ + i += sizeof(TYPE); \ + pg >>= sizeof(TYPE); \ + } while (i & 15); \ + } \ +} + +DO_MOVA_Z(sme_mova_zc_b, uint8_t, H1) +DO_MOVA_Z(sme_mova_zc_h, uint16_t, H1_2) +DO_MOVA_Z(sme_mova_zc_s, uint32_t, H1_4) + +void HELPER(sme_mova_zc_d)(void *vd, void *za, void *vg, uint32_t desc) +{ + int i, oprsz = simd_oprsz(desc) / 8; + uint8_t *pg = vg; + uint64_t *d = vd; + uint64_t *a = za; + + for (i = 0; i < oprsz; i++) { + if (pg[H1(i)] & 1) { + d[i] = a[tile_vslice_index(i)]; + } + } +} + +void HELPER(sme_mova_zc_q)(void *vd, void *za, void *vg, uint32_t desc) +{ + int i, oprsz = simd_oprsz(desc) / 16; + uint16_t *pg = vg; + Int128 *d = vd; + Int128 *a = za; + + /* + * Int128 is used here simply to copy 16 bytes, and to simplify + * the address arithmetic. + */ + for (i = 0; i < oprsz; i++, za += sizeof(ARMVectorReg)) { + if (pg[H2(i)] & 1) { + d[i] = a[tile_vslice_index(i)]; + } + } +} + +#undef DO_MOVA_Z diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 0c6379e6e8..df16170469 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -3565,6 +3565,18 @@ void HELPER(sve_sel_zpzz_d)(void *vd, void *vn, void *vm, } } +void HELPER(sve_sel_zpzz_q)(void *vd, void *vn, void *vm, + void *vg, uint32_t desc) +{ + intptr_t i, opr_sz = simd_oprsz(desc) / 16; + Int128 *d = vd, *n = vn, *m = vm; + uint16_t *pg = vg; + + for (i = 0; i < opr_sz; i += 1) { + d[i] = (pg[H2(i)] & 1 ? n : m)[i]; + } +} + /* Two operand comparison controlled by a predicate. * ??? It is very tempting to want to be able to expand this inline * with x86 instructions, e.g. diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 971504559b..79c33d35c2 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -35,6 +35,74 @@ #include "decode-sme.c.inc" +/* + * Resolve tile.size[index] to a host pointer, where tile and index + * are always decoded together, dependent on the element size. + */ +static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs, + int tile_index, bool vertical) +{ + int tile = tile_index >> (4 - esz); + int index = esz == MO_128 ? 0 : extract32(tile_index, 0, 4 - esz); + int pos, len, offset; + TCGv_i32 tmp; + TCGv_ptr addr; + + /* Compute the final index, which is Rs+imm. */ + tmp = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(tmp, cpu_reg(s, rs)); + tcg_gen_addi_i32(tmp, tmp, index); + + /* Prepare a power-of-two modulo via extraction of @len bits. */ + len = ctz32(streaming_vec_reg_size(s)) - esz; + + if (vertical) { + /* + * Compute the byte offset of the index within the tile: + * (index % (svl / size)) * size + * = (index % (svl >> esz)) << esz + * Perform the power-of-two modulo via extraction of the low @len bits. + * Perform the multiply by shifting left by @pos bits. + * Perform these operations simultaneously via deposit into zero. + */ + pos = esz; + tcg_gen_deposit_z_i32(tmp, tmp, pos, len); + + /* + * For big-endian, adjust the indexed column byte offset within + * the uint64_t host words that make up env->zarray[]. + */ + if (HOST_BIG_ENDIAN && esz < MO_64) { + tcg_gen_xori_i32(tmp, tmp, 8 - (1 << esz)); + } + } else { + /* + * Compute the byte offset of the index within the tile: + * (index % (svl / size)) * (size * sizeof(row)) + * = (index % (svl >> esz)) << (esz + log2(sizeof(row))) + */ + pos = esz + ctz32(sizeof(ARMVectorReg)); + tcg_gen_deposit_z_i32(tmp, tmp, pos, len); + + /* Row slices are always aligned and need no endian adjustment. */ + } + + /* The tile byte offset within env->zarray is the row. */ + offset = tile * sizeof(ARMVectorReg); + + /* Include the byte offset of zarray to make this relative to env. */ + offset += offsetof(CPUARMState, zarray); + tcg_gen_addi_i32(tmp, tmp, offset); + + /* Add the byte offset to env to produce the final pointer. */ + addr = tcg_temp_new_ptr(); + tcg_gen_ext_i32_ptr(addr, tmp); + tcg_temp_free_i32(tmp); + tcg_gen_add_ptr(addr, addr, cpu_env); + + return addr; +} + static bool trans_ZERO(DisasContext *s, arg_ZERO *a) { if (!dc_isar_feature(aa64_sme, s)) { @@ -46,3 +114,62 @@ static bool trans_ZERO(DisasContext *s, arg_ZERO *a) } return true; } + +static bool trans_MOVA(DisasContext *s, arg_MOVA *a) +{ + static gen_helper_gvec_4 * const h_fns[5] = { + gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h, + gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d, + gen_helper_sve_sel_zpzz_q + }; + static gen_helper_gvec_3 * const cz_fns[5] = { + gen_helper_sme_mova_cz_b, gen_helper_sme_mova_cz_h, + gen_helper_sme_mova_cz_s, gen_helper_sme_mova_cz_d, + gen_helper_sme_mova_cz_q, + }; + static gen_helper_gvec_3 * const zc_fns[5] = { + gen_helper_sme_mova_zc_b, gen_helper_sme_mova_zc_h, + gen_helper_sme_mova_zc_s, gen_helper_sme_mova_zc_d, + gen_helper_sme_mova_zc_q, + }; + + TCGv_ptr t_za, t_zr, t_pg; + TCGv_i32 t_desc; + int svl; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sme_smza_enabled_check(s)) { + return true; + } + + t_za = get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v); + t_zr = vec_full_reg_ptr(s, a->zr); + t_pg = pred_full_reg_ptr(s, a->pg); + + svl = streaming_vec_reg_size(s); + t_desc = tcg_constant_i32(simd_desc(svl, svl, 0)); + + if (a->v) { + /* Vertical slice -- use sme mova helpers. */ + if (a->to_vec) { + zc_fns[a->esz](t_zr, t_za, t_pg, t_desc); + } else { + cz_fns[a->esz](t_za, t_zr, t_pg, t_desc); + } + } else { + /* Horizontal slice -- reuse sve sel helpers. */ + if (a->to_vec) { + h_fns[a->esz](t_zr, t_za, t_zr, t_pg, t_desc); + } else { + h_fns[a->esz](t_za, t_zr, t_za, t_pg, t_desc); + } + } + + tcg_temp_free_ptr(t_za); + tcg_temp_free_ptr(t_zr); + tcg_temp_free_ptr(t_pg); + + return true; +} From patchwork Fri Jul 8 15:15:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588539 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp773241mab; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 20/45] target/arm: Implement SME LD1, ST1 Date: Fri, 8 Jul 2022 20:45:15 +0530 Message-Id: <20220708151540.18136-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We cannot reuse the SVE functions for LD[1-4] and ST[1-4], because those functions accept only a Zreg register number. For SME, we want to pass a pointer into ZA storage. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 82 +++++ target/arm/sme.decode | 9 + target/arm/sme_helper.c | 595 +++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 70 +++++ 4 files changed, 756 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 154bc73d2e..95f6e88bdd 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -33,3 +33,85 @@ DEF_HELPER_FLAGS_4(sme_mova_cz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sme_mova_zc_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sme_mova_cz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sme_mova_zc_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sme_ld1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 241b4895b7..900e3f2a07 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -37,3 +37,12 @@ MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5 \ &mova to_vec=1 rs=%mova_rs MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \ &mova to_vec=1 rs=%mova_rs esz=4 + +### SME Memory + +&ldst esz rs pg rn rm za_imm v:bool st:bool + +LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ + &ldst rs=%mova_rs +LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ + &ldst esz=4 rs=%mova_rs diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index e88244423d..10fd1ed910 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -19,10 +19,14 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "internals.h" #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" +#include "exec/cpu_ldst.h" +#include "exec/exec-all.h" #include "qemu/int128.h" #include "vec_internal.h" +#include "sve_ldst_internal.h" /* ResetSVEState */ void arm_reset_sve_state(CPUARMState *env) @@ -233,3 +237,594 @@ void HELPER(sme_mova_zc_q)(void *vd, void *za, void *vg, uint32_t desc) } #undef DO_MOVA_Z + +/* + * Clear elements in a tile slice comprising len bytes. + */ + +typedef void ClearFn(void *ptr, size_t off, size_t len); + +static void clear_horizontal(void *ptr, size_t off, size_t len) +{ + memset(ptr + off, 0, len); +} + +static void clear_vertical_b(void *vptr, size_t off, size_t len) +{ + for (size_t i = 0; i < len; ++i) { + *(uint8_t *)(vptr + tile_vslice_offset(i + off)) = 0; + } +} + +static void clear_vertical_h(void *vptr, size_t off, size_t len) +{ + for (size_t i = 0; i < len; i += 2) { + *(uint16_t *)(vptr + tile_vslice_offset(i + off)) = 0; + } +} + +static void clear_vertical_s(void *vptr, size_t off, size_t len) +{ + for (size_t i = 0; i < len; i += 4) { + *(uint32_t *)(vptr + tile_vslice_offset(i + off)) = 0; + } +} + +static void clear_vertical_d(void *vptr, size_t off, size_t len) +{ + for (size_t i = 0; i < len; i += 8) { + *(uint64_t *)(vptr + tile_vslice_offset(i + off)) = 0; + } +} + +static void clear_vertical_q(void *vptr, size_t off, size_t len) +{ + for (size_t i = 0; i < len; i += 16) { + memset(vptr + tile_vslice_offset(i + off), 0, 16); + } +} + +/* + * Copy elements from an array into a tile slice comprising len bytes. + */ + +typedef void CopyFn(void *dst, const void *src, size_t len); + +static void copy_horizontal(void *dst, const void *src, size_t len) +{ + memcpy(dst, src, len); +} + +static void copy_vertical_b(void *vdst, const void *vsrc, size_t len) +{ + const uint8_t *src = vsrc; + uint8_t *dst = vdst; + size_t i; + + for (i = 0; i < len; ++i) { + dst[tile_vslice_index(i)] = src[i]; + } +} + +static void copy_vertical_h(void *vdst, const void *vsrc, size_t len) +{ + const uint16_t *src = vsrc; + uint16_t *dst = vdst; + size_t i; + + for (i = 0; i < len / 2; ++i) { + dst[tile_vslice_index(i)] = src[i]; + } +} + +static void copy_vertical_s(void *vdst, const void *vsrc, size_t len) +{ + const uint32_t *src = vsrc; + uint32_t *dst = vdst; + size_t i; + + for (i = 0; i < len / 4; ++i) { + dst[tile_vslice_index(i)] = src[i]; + } +} + +static void copy_vertical_d(void *vdst, const void *vsrc, size_t len) +{ + const uint64_t *src = vsrc; + uint64_t *dst = vdst; + size_t i; + + for (i = 0; i < len / 8; ++i) { + dst[tile_vslice_index(i)] = src[i]; + } +} + +static void copy_vertical_q(void *vdst, const void *vsrc, size_t len) +{ + for (size_t i = 0; i < len; i += 16) { + memcpy(vdst + tile_vslice_offset(i), vsrc + i, 16); + } +} + +/* + * Host and TLB primitives for vertical tile slice addressing. + */ + +#define DO_LD(NAME, TYPE, HOST, TLB) \ +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host) \ +{ \ + TYPE val = HOST(host); \ + *(TYPE *)(za + tile_vslice_offset(off)) = val; \ +} \ +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, \ + intptr_t off, target_ulong addr, uintptr_t ra) \ +{ \ + TYPE val = TLB(env, useronly_clean_ptr(addr), ra); \ + *(TYPE *)(za + tile_vslice_offset(off)) = val; \ +} + +#define DO_ST(NAME, TYPE, HOST, TLB) \ +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host) \ +{ \ + TYPE val = *(TYPE *)(za + tile_vslice_offset(off)); \ + HOST(host, val); \ +} \ +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, \ + intptr_t off, target_ulong addr, uintptr_t ra) \ +{ \ + TYPE val = *(TYPE *)(za + tile_vslice_offset(off)); \ + TLB(env, useronly_clean_ptr(addr), val, ra); \ +} + +/* + * The ARMVectorReg elements are stored in host-endian 64-bit units. + * For 128-bit quantities, the sequence defined by the Elem[] pseudocode + * corresponds to storing the two 64-bit pieces in little-endian order. + */ +#define DO_LDQ(HNAME, VNAME, BE, HOST, TLB) \ +static inline void HNAME##_host(void *za, intptr_t off, void *host) \ +{ \ + uint64_t val0 = HOST(host), val1 = HOST(host + 8); \ + uint64_t *ptr = za + off; \ + ptr[0] = BE ? val1 : val0, ptr[1] = BE ? val0 : val1; \ +} \ +static inline void VNAME##_v_host(void *za, intptr_t off, void *host) \ +{ \ + HNAME##_host(za, tile_vslice_offset(off), host); \ +} \ +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, \ + target_ulong addr, uintptr_t ra) \ +{ \ + uint64_t val0 = TLB(env, useronly_clean_ptr(addr), ra); \ + uint64_t val1 = TLB(env, useronly_clean_ptr(addr + 8), ra); \ + uint64_t *ptr = za + off; \ + ptr[0] = BE ? val1 : val0, ptr[1] = BE ? val0 : val1; \ +} \ +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off, \ + target_ulong addr, uintptr_t ra) \ +{ \ + HNAME##_tlb(env, za, tile_vslice_offset(off), addr, ra); \ +} + +#define DO_STQ(HNAME, VNAME, BE, HOST, TLB) \ +static inline void HNAME##_host(void *za, intptr_t off, void *host) \ +{ \ + uint64_t *ptr = za + off; \ + HOST(host, ptr[BE]); \ + HOST(host + 1, ptr[!BE]); \ +} \ +static inline void VNAME##_v_host(void *za, intptr_t off, void *host) \ +{ \ + HNAME##_host(za, tile_vslice_offset(off), host); \ +} \ +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, \ + target_ulong addr, uintptr_t ra) \ +{ \ + uint64_t *ptr = za + off; \ + TLB(env, useronly_clean_ptr(addr), ptr[BE], ra); \ + TLB(env, useronly_clean_ptr(addr + 8), ptr[!BE], ra); \ +} \ +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off, \ + target_ulong addr, uintptr_t ra) \ +{ \ + HNAME##_tlb(env, za, tile_vslice_offset(off), addr, ra); \ +} + +DO_LD(ld1b, uint8_t, ldub_p, cpu_ldub_data_ra) +DO_LD(ld1h_be, uint16_t, lduw_be_p, cpu_lduw_be_data_ra) +DO_LD(ld1h_le, uint16_t, lduw_le_p, cpu_lduw_le_data_ra) +DO_LD(ld1s_be, uint32_t, ldl_be_p, cpu_ldl_be_data_ra) +DO_LD(ld1s_le, uint32_t, ldl_le_p, cpu_ldl_le_data_ra) +DO_LD(ld1d_be, uint64_t, ldq_be_p, cpu_ldq_be_data_ra) +DO_LD(ld1d_le, uint64_t, ldq_le_p, cpu_ldq_le_data_ra) + +DO_LDQ(sve_ld1qq_be, sme_ld1q_be, 1, ldq_be_p, cpu_ldq_be_data_ra) +DO_LDQ(sve_ld1qq_le, sme_ld1q_le, 0, ldq_le_p, cpu_ldq_le_data_ra) + +DO_ST(st1b, uint8_t, stb_p, cpu_stb_data_ra) +DO_ST(st1h_be, uint16_t, stw_be_p, cpu_stw_be_data_ra) +DO_ST(st1h_le, uint16_t, stw_le_p, cpu_stw_le_data_ra) +DO_ST(st1s_be, uint32_t, stl_be_p, cpu_stl_be_data_ra) +DO_ST(st1s_le, uint32_t, stl_le_p, cpu_stl_le_data_ra) +DO_ST(st1d_be, uint64_t, stq_be_p, cpu_stq_be_data_ra) +DO_ST(st1d_le, uint64_t, stq_le_p, cpu_stq_le_data_ra) + +DO_STQ(sve_st1qq_be, sme_st1q_be, 1, stq_be_p, cpu_stq_be_data_ra) +DO_STQ(sve_st1qq_le, sme_st1q_le, 0, stq_le_p, cpu_stq_le_data_ra) + +#undef DO_LD +#undef DO_ST +#undef DO_LDQ +#undef DO_STQ + +/* + * Common helper for all contiguous predicated loads. + */ + +static inline QEMU_ALWAYS_INLINE +void sme_ld1(CPUARMState *env, void *za, uint64_t *vg, + const target_ulong addr, uint32_t desc, const uintptr_t ra, + const int esz, uint32_t mtedesc, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn, + ClearFn *clr_fn, + CopyFn *cpy_fn) +{ + const intptr_t reg_max = simd_oprsz(desc); + const intptr_t esize = 1 << esz; + intptr_t reg_off, reg_last; + SVEContLdSt info; + void *host; + int flags; + + /* Find the active elements. */ + if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) { + /* The entire predicate was false; no load occurs. */ + clr_fn(za, 0, reg_max); + return; + } + + /* Probe the page(s). Exit with exception for any invalid page. */ + sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, ra); + + /* Handle watchpoints for all active elements. */ + sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize, + BP_MEM_READ, ra); + + /* + * Handle mte checks for all active elements. + * Since TBI must be set for MTE, !mtedesc => !mte_active. + */ + if (mtedesc) { + sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, + mtedesc, ra); + } + + flags = info.page[0].flags | info.page[1].flags; + if (unlikely(flags != 0)) { +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + /* + * At least one page includes MMIO. + * Any bus operation can fail with cpu_transaction_failed, + * which for ARM will raise SyncExternal. Perform the load + * into scratch memory to preserve register state until the end. + */ + ARMVectorReg scratch = { }; + + reg_off = info.reg_off_first[0]; + reg_last = info.reg_off_last[1]; + if (reg_last < 0) { + reg_last = info.reg_off_split; + if (reg_last < 0) { + reg_last = info.reg_off_last[0]; + } + } + + do { + uint64_t pg = vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + tlb_fn(env, &scratch, reg_off, addr + reg_off, ra); + } + reg_off += esize; + } while (reg_off & 63); + } while (reg_off <= reg_last); + + cpy_fn(za, &scratch, reg_max); + return; +#endif + } + + /* The entire operation is in RAM, on valid pages. */ + + reg_off = info.reg_off_first[0]; + reg_last = info.reg_off_last[0]; + host = info.page[0].host; + + if (!vertical) { + memset(za, 0, reg_max); + } else if (reg_off) { + clr_fn(za, 0, reg_off); + } + + while (reg_off <= reg_last) { + uint64_t pg = vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } else if (vertical) { + clr_fn(za, reg_off, esize); + } + reg_off += esize; + } while (reg_off <= reg_last && (reg_off & 63)); + } + + /* + * Use the slow path to manage the cross-page misalignment. + * But we know this is RAM and cannot trap. + */ + reg_off = info.reg_off_split; + if (unlikely(reg_off >= 0)) { + tlb_fn(env, za, reg_off, addr + reg_off, ra); + } + + reg_off = info.reg_off_first[1]; + if (unlikely(reg_off >= 0)) { + reg_last = info.reg_off_last[1]; + host = info.page[1].host; + + do { + uint64_t pg = vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } else if (vertical) { + clr_fn(za, reg_off, esize); + } + reg_off += esize; + } while (reg_off & 63); + } while (reg_off <= reg_last); + } +} + +static inline QEMU_ALWAYS_INLINE +void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg, + target_ulong addr, uint32_t desc, uintptr_t ra, + const int esz, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn, + ClearFn *clr_fn, + CopyFn *cpy_fn) +{ + uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + int bit55 = extract64(addr, 55, 1); + + /* Remove mtedesc from the normal sve descriptor. */ + desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* Perform gross MTE suppression early. */ + if (!tbi_check(desc, bit55) || + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { + mtedesc = 0; + } + + sme_ld1(env, za, vg, addr, desc, ra, esz, mtedesc, vertical, + host_fn, tlb_fn, clr_fn, cpy_fn); +} + +#define DO_LD(L, END, ESZ) \ +void HELPER(sme_ld1##L##END##_h)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false, \ + sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb, \ + clear_horizontal, copy_horizontal); \ +} \ +void HELPER(sme_ld1##L##END##_v)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true, \ + sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb, \ + clear_vertical_##L, copy_vertical_##L); \ +} \ +void HELPER(sme_ld1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false, \ + sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb, \ + clear_horizontal, copy_horizontal); \ +} \ +void HELPER(sme_ld1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true, \ + sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb, \ + clear_vertical_##L, copy_vertical_##L); \ +} + +DO_LD(b, , MO_8) +DO_LD(h, _be, MO_16) +DO_LD(h, _le, MO_16) +DO_LD(s, _be, MO_32) +DO_LD(s, _le, MO_32) +DO_LD(d, _be, MO_64) +DO_LD(d, _le, MO_64) +DO_LD(q, _be, MO_128) +DO_LD(q, _le, MO_128) + +#undef DO_LD + +/* + * Common helper for all contiguous predicated stores. + */ + +static inline QEMU_ALWAYS_INLINE +void sme_st1(CPUARMState *env, void *za, uint64_t *vg, + const target_ulong addr, uint32_t desc, const uintptr_t ra, + const int esz, uint32_t mtedesc, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + const intptr_t reg_max = simd_oprsz(desc); + const intptr_t esize = 1 << esz; + intptr_t reg_off, reg_last; + SVEContLdSt info; + void *host; + int flags; + + /* Find the active elements. */ + if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) { + /* The entire predicate was false; no store occurs. */ + return; + } + + /* Probe the page(s). Exit with exception for any invalid page. */ + sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_STORE, ra); + + /* Handle watchpoints for all active elements. */ + sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize, + BP_MEM_WRITE, ra); + + /* + * Handle mte checks for all active elements. + * Since TBI must be set for MTE, !mtedesc => !mte_active. + */ + if (mtedesc) { + sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, + mtedesc, ra); + } + + flags = info.page[0].flags | info.page[1].flags; + if (unlikely(flags != 0)) { +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + /* + * At least one page includes MMIO. + * Any bus operation can fail with cpu_transaction_failed, + * which for ARM will raise SyncExternal. We cannot avoid + * this fault and will leave with the store incomplete. + */ + reg_off = info.reg_off_first[0]; + reg_last = info.reg_off_last[1]; + if (reg_last < 0) { + reg_last = info.reg_off_split; + if (reg_last < 0) { + reg_last = info.reg_off_last[0]; + } + } + + do { + uint64_t pg = vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + tlb_fn(env, za, reg_off, addr + reg_off, ra); + } + reg_off += esize; + } while (reg_off & 63); + } while (reg_off <= reg_last); + return; +#endif + } + + reg_off = info.reg_off_first[0]; + reg_last = info.reg_off_last[0]; + host = info.page[0].host; + + while (reg_off <= reg_last) { + uint64_t pg = vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } + reg_off += 1 << esz; + } while (reg_off <= reg_last && (reg_off & 63)); + } + + /* + * Use the slow path to manage the cross-page misalignment. + * But we know this is RAM and cannot trap. + */ + reg_off = info.reg_off_split; + if (unlikely(reg_off >= 0)) { + tlb_fn(env, za, reg_off, addr + reg_off, ra); + } + + reg_off = info.reg_off_first[1]; + if (unlikely(reg_off >= 0)) { + reg_last = info.reg_off_last[1]; + host = info.page[1].host; + + do { + uint64_t pg = vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } + reg_off += 1 << esz; + } while (reg_off & 63); + } while (reg_off <= reg_last); + } +} + +static inline QEMU_ALWAYS_INLINE +void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr, + uint32_t desc, uintptr_t ra, int esz, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + int bit55 = extract64(addr, 55, 1); + + /* Remove mtedesc from the normal sve descriptor. */ + desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* Perform gross MTE suppression early. */ + if (!tbi_check(desc, bit55) || + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { + mtedesc = 0; + } + + sme_st1(env, za, vg, addr, desc, ra, esz, mtedesc, + vertical, host_fn, tlb_fn); +} + +#define DO_ST(L, END, ESZ) \ +void HELPER(sme_st1##L##END##_h)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false, \ + sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb); \ +} \ +void HELPER(sme_st1##L##END##_v)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true, \ + sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb); \ +} \ +void HELPER(sme_st1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false, \ + sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb); \ +} \ +void HELPER(sme_st1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true, \ + sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb); \ +} + +DO_ST(b, , MO_8) +DO_ST(h, _be, MO_16) +DO_ST(h, _le, MO_16) +DO_ST(s, _be, MO_32) +DO_ST(s, _le, MO_32) +DO_ST(d, _be, MO_64) +DO_ST(d, _le, MO_64) +DO_ST(q, _be, MO_128) +DO_ST(q, _le, MO_128) + +#undef DO_ST diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 79c33d35c2..42d14b883a 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -173,3 +173,73 @@ static bool trans_MOVA(DisasContext *s, arg_MOVA *a) return true; } + +static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) +{ + typedef void GenLdSt1(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv, TCGv_i32); + + /* + * Indexed by [esz][be][v][mte][st], which is (except for load/store) + * also the order in which the elements appear in the function names, + * and so how we must concatenate the pieces. + */ + +#define FN_LS(F) { gen_helper_sme_ld1##F, gen_helper_sme_st1##F } +#define FN_MTE(F) { FN_LS(F), FN_LS(F##_mte) } +#define FN_HV(F) { FN_MTE(F##_h), FN_MTE(F##_v) } +#define FN_END(L, B) { FN_HV(L), FN_HV(B) } + + static GenLdSt1 * const fns[5][2][2][2][2] = { + FN_END(b, b), + FN_END(h_le, h_be), + FN_END(s_le, s_be), + FN_END(d_le, d_be), + FN_END(q_le, q_be), + }; + +#undef FN_LS +#undef FN_MTE +#undef FN_HV +#undef FN_END + + TCGv_ptr t_za, t_pg; + TCGv_i64 addr; + int svl, desc = 0; + bool be = s->be_data == MO_BE; + bool mte = s->mte_active[0]; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sme_smza_enabled_check(s)) { + return true; + } + + t_za = get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v); + t_pg = pred_full_reg_ptr(s, a->pg); + addr = tcg_temp_new_i64(); + + tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz); + tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); + + if (mte) { + desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); + desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); + desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); + desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st); + desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1); + desc <<= SVE_MTEDESC_SHIFT; + } else { + addr = clean_data_tbi(s, addr); + } + svl = streaming_vec_reg_size(s); + desc = simd_desc(svl, svl, desc); + + fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr, + tcg_constant_i32(desc)); + + tcg_temp_free_ptr(t_za); + tcg_temp_free_ptr(t_pg); + tcg_temp_free_i64(addr); + return true; +} From patchwork Fri Jul 8 15:15:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588541 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp775061mab; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 21/45] target/arm: Export unpredicated ld/st from translate-sve.c Date: Fri, 8 Jul 2022 20:45:16 +0530 Message-Id: <20220708151540.18136-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a TCGv_ptr base argument, which will be cpu_env for SVE. We will reuse this for SME save and restore array insns. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 3 +++ target/arm/translate-sve.c | 48 ++++++++++++++++++++++++++++---------- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 2a7fe6e9e7..ad3762d1ac 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -195,4 +195,7 @@ void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs, int64_t shift, uint32_t opr_sz, uint32_t max_sz); +void gen_sve_ldr(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm); +void gen_sve_str(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm); + #endif /* TARGET_ARM_TRANSLATE_A64_H */ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 95016e49e9..fd1a173637 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4306,7 +4306,8 @@ TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz, * The load should begin at the address Rn + IMM. */ -static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) +void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs, + int len, int rn, int imm) { int len_align = QEMU_ALIGN_DOWN(len, 8); int len_remain = len % 8; @@ -4332,7 +4333,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) t0 = tcg_temp_new_i64(); for (i = 0; i < len_align; i += 8) { tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); - tcg_gen_st_i64(t0, cpu_env, vofs + i); + tcg_gen_st_i64(t0, base, vofs + i); tcg_gen_addi_i64(clean_addr, clean_addr, 8); } tcg_temp_free_i64(t0); @@ -4345,6 +4346,12 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) clean_addr = new_tmp_a64_local(s); tcg_gen_mov_i64(clean_addr, t0); + if (base != cpu_env) { + TCGv_ptr b = tcg_temp_local_new_ptr(); + tcg_gen_mov_ptr(b, base); + base = b; + } + gen_set_label(loop); t0 = tcg_temp_new_i64(); @@ -4352,7 +4359,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) tcg_gen_addi_i64(clean_addr, clean_addr, 8); tp = tcg_temp_new_ptr(); - tcg_gen_add_ptr(tp, cpu_env, i); + tcg_gen_add_ptr(tp, base, i); tcg_gen_addi_ptr(i, i, 8); tcg_gen_st_i64(t0, tp, vofs); tcg_temp_free_ptr(tp); @@ -4360,6 +4367,11 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); tcg_temp_free_ptr(i); + + if (base != cpu_env) { + tcg_temp_free_ptr(base); + assert(len_remain == 0); + } } /* @@ -4388,13 +4400,14 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) default: g_assert_not_reached(); } - tcg_gen_st_i64(t0, cpu_env, vofs + len_align); + tcg_gen_st_i64(t0, base, vofs + len_align); tcg_temp_free_i64(t0); } } /* Similarly for stores. */ -static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) +void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs, + int len, int rn, int imm) { int len_align = QEMU_ALIGN_DOWN(len, 8); int len_remain = len % 8; @@ -4420,7 +4433,7 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) t0 = tcg_temp_new_i64(); for (i = 0; i < len_align; i += 8) { - tcg_gen_ld_i64(t0, cpu_env, vofs + i); + tcg_gen_ld_i64(t0, base, vofs + i); tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); tcg_gen_addi_i64(clean_addr, clean_addr, 8); } @@ -4434,11 +4447,17 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) clean_addr = new_tmp_a64_local(s); tcg_gen_mov_i64(clean_addr, t0); + if (base != cpu_env) { + TCGv_ptr b = tcg_temp_local_new_ptr(); + tcg_gen_mov_ptr(b, base); + base = b; + } + gen_set_label(loop); t0 = tcg_temp_new_i64(); tp = tcg_temp_new_ptr(); - tcg_gen_add_ptr(tp, cpu_env, i); + tcg_gen_add_ptr(tp, base, i); tcg_gen_ld_i64(t0, tp, vofs); tcg_gen_addi_ptr(i, i, 8); tcg_temp_free_ptr(tp); @@ -4449,12 +4468,17 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); tcg_temp_free_ptr(i); + + if (base != cpu_env) { + tcg_temp_free_ptr(base); + assert(len_remain == 0); + } } /* Predicate register stores can be any multiple of 2. */ if (len_remain) { t0 = tcg_temp_new_i64(); - tcg_gen_ld_i64(t0, cpu_env, vofs + len_align); + tcg_gen_ld_i64(t0, base, vofs + len_align); switch (len_remain) { case 2: @@ -4486,7 +4510,7 @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size = vec_full_reg_size(s); int off = vec_full_reg_offset(s, a->rd); - do_ldr(s, off, size, a->rn, a->imm * size); + gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4499,7 +4523,7 @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size = pred_full_reg_size(s); int off = pred_full_reg_offset(s, a->rd); - do_ldr(s, off, size, a->rn, a->imm * size); + gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4512,7 +4536,7 @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size = vec_full_reg_size(s); int off = vec_full_reg_offset(s, a->rd); - do_str(s, off, size, a->rn, a->imm * size); + gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4525,7 +4549,7 @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size = pred_full_reg_size(s); int off = pred_full_reg_offset(s, a->rd); - do_str(s, off, size, a->rn, a->imm * size); + gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } From patchwork Fri Jul 8 15:15:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588540 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp773493mab; Fri, 8 Jul 2022 08:42:24 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uyYhrg7RwsiMdd0cvK7PMR/43dUb4xvSIpbCa4Ixy+BEa5us52uKLqfSIZjQv58+dluJtf X-Received: by 2002:ac8:5801:0:b0:31d:4c67:6f3 with SMTP id g1-20020ac85801000000b0031d4c6706f3mr3595315qtg.46.1657294943940; Fri, 08 Jul 2022 08:42:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657294943; cv=none; d=google.com; s=arc-20160816; b=zT1xnJOrIvwRBGU8O6azIr7zYLM0jLeFR3Cwceg7v8R+ZvO1m+lsqmL0wEm46vm2LU 2+838oG+e3F3uG9DRE1w9bDApe5M6fcdkO9lx8K5Qd71detJfffiFQEbN59Z9sWv/8Ms 22tRGrDoB/3gfEEvNXnwCEXFo9yEywkDIaE7pTIG7vMKy8FXvSPoz2TTs55ZOZkaurb+ VBN6oBOu169fioWH1RhW9CseLDbjSJe2ZwznFw+/PlsoMbb0jaVqxlV88MDxHDdP+ErD jQil7jgKxe5EfNfC6dUJ2azUox9UbBg8THRb9FPbi2V4EOyQYRlRuYyXwrKolSKdwdz4 JqkA== ARC-Message-Signature: i=1; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 22/45] target/arm: Implement SME LDR, STR Date: Fri, 8 Jul 2022 20:45:17 +0530 Message-Id: <20220708151540.18136-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can reuse the SVE functions for LDR and STR, passing in the base of the ZA vector and a zero offset. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme.decode | 7 +++++++ target/arm/translate-sme.c | 24 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 900e3f2a07..f1ebd857a5 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -46,3 +46,10 @@ LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ &ldst rs=%mova_rs LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ &ldst esz=4 rs=%mova_rs + +&ldstr rv rn imm +@ldstr ....... ... . ...... .. ... rn:5 . imm:4 \ + &ldstr rv=%mova_rs + +LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr +STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 42d14b883a..35c2644812 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -243,3 +243,27 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) tcg_temp_free_i64(addr); return true; } + +typedef void GenLdStR(DisasContext *, TCGv_ptr, int, int, int, int); + +static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn) +{ + int svl = streaming_vec_reg_size(s); + int imm = a->imm; + TCGv_ptr base; + + if (!sme_za_enabled_check(s)) { + return true; + } + + /* ZA[n] equates to ZA0H.B[n]. */ + base = get_tile_rowcol(s, MO_8, a->rv, imm, false); + + fn(s, base, 0, svl, a->rn, imm * svl); + + tcg_temp_free_ptr(base); + return true; +} + +TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr) +TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str) From patchwork Fri Jul 8 15:15:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588542 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp775150mab; Fri, 8 Jul 2022 08:44:30 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uV907qN1B+6sqiSnz9QIYw4pU5jfQdGhy/7kq3gjEIYPEwOXBqkiWxERMAKSX9xAuLz5rP X-Received: by 2002:a05:622a:34a:b0:31b:5a46:8783 with SMTP id r10-20020a05622a034a00b0031b5a468783mr3473735qtw.326.1657295069965; Fri, 08 Jul 2022 08:44:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657295069; cv=none; d=google.com; s=arc-20160816; b=qWDmt7ZMgqWkORKYP9N86Acoy2tqdUfElQKS+an4V3m7+ev5J4/tZH80LRsITISAiM 7AH1E8+ntoCEnBy0r3PdEYT2xsJ2CRQkIn+B+ddhuJgD+XXFcIvbYPpzUWADAy5CfOwA WhQyKT+LmX45/oqsTe0DQql5zBl1c1zLdnSYG6iPwRTZ0dLeFkhrShhex9dBse/AagzD aGHZqRQ53n/t5S6Va95t1LZT6s2JBwqpW0o65274kDv/7PzNasd4mvSx0ORapzDAfWQQ jh8vHH7rdhNjUtTz6I0c73ZWiMFr4FftPMfLnG3jEcHJiLw5zW/639r+eYKRd/YUA43Q EbLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1nuOMyOTVmZTm/vLrdu3i09qThjbDYLsicba1sLQlZY=; b=CZpcdP32XElMaJFCEEO6BbmJeysJBAJ1cPhArIOqdc/nGZlgXXwp2Yt/PYs56dIRVu cytEPISBsbR9RbTgZm+ZIYgex8JTSU6UqbH/vPaFX3zpM4ThFdAYiUuJGl1oWXa5pkbo 1a6K0wi8zZyI3eYgO59Co6bX3Yv6+pwyNsC+d5rZNbwWQNkZfy+10MgFb7Ffsevwun3U PMiob49VpnDu38eMcofvROdu6zBL2/B6da249Nhce8vbSqGhOTT+PBzAyS3pVFXRc0yV adUEkr1WjoZJX4XosPiXTlGhpczPq8PDO3thlZ72D9y0M4SNtoYCMqj55OFEF1mnAr+Z rj1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DdERSY0v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 23/45] target/arm: Implement SME ADDHA, ADDVA Date: Fri, 8 Jul 2022 20:45:18 +0530 Message-Id: <20220708151540.18136-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 5 +++ target/arm/sme.decode | 11 +++++ target/arm/sme_helper.c | 90 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 31 +++++++++++++ 4 files changed, 137 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 95f6e88bdd..753e9e624c 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -115,3 +115,8 @@ DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index f1ebd857a5..8cb6c4053c 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -53,3 +53,14 @@ LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr + +### SME Add Vector to Array + +&adda zad zn pm pn +@adda_32 ........ .. ..... . pm:3 pn:3 zn:5 ... zad:2 &adda +@adda_64 ........ .. ..... . pm:3 pn:3 zn:5 .. zad:3 &adda + +ADDHA_s 11000000 10 01000 0 ... ... ..... 000 .. @adda_32 +ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32 +ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64 +ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 10fd1ed910..f1e924db74 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -828,3 +828,93 @@ DO_ST(q, _be, MO_128) DO_ST(q, _le, MO_128) #undef DO_ST + +void HELPER(sme_addha_s)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_oprsz(desc) / 4; + uint64_t *pn = vpn, *pm = vpm; + uint32_t *zda = vzda, *zn = vzn; + + for (row = 0; row < oprsz; ) { + uint64_t pa = pn[row >> 4]; + do { + if (pa & 1) { + for (col = 0; col < oprsz; ) { + uint64_t pb = pm[col >> 4]; + do { + if (pb & 1) { + zda[tile_vslice_index(row) + H4(col)] += zn[H4(col)]; + } + pb >>= 4; + } while (++col & 15); + } + } + pa >>= 4; + } while (++row & 15); + } +} + +void HELPER(sme_addha_d)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_oprsz(desc) / 8; + uint8_t *pn = vpn, *pm = vpm; + uint64_t *zda = vzda, *zn = vzn; + + for (row = 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + for (col = 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + zda[tile_vslice_index(row) + col] += zn[col]; + } + } + } + } +} + +void HELPER(sme_addva_s)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_oprsz(desc) / 4; + uint64_t *pn = vpn, *pm = vpm; + uint32_t *zda = vzda, *zn = vzn; + + for (row = 0; row < oprsz; ) { + uint64_t pa = pn[row >> 4]; + do { + if (pa & 1) { + uint32_t zn_row = zn[H4(row)]; + for (col = 0; col < oprsz; ) { + uint64_t pb = pm[col >> 4]; + do { + if (pb & 1) { + zda[tile_vslice_index(row) + H4(col)] += zn_row; + } + pb >>= 4; + } while (++col & 15); + } + } + pa >>= 4; + } while (++row & 15); + } +} + +void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_oprsz(desc) / 8; + uint8_t *pn = vpn, *pm = vpm; + uint64_t *zda = vzda, *zn = vzn; + + for (row = 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + uint64_t zn_row = zn[row]; + for (col = 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + zda[tile_vslice_index(row) + col] += zn_row; + } + } + } + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 35c2644812..d3b9cdd5c4 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -267,3 +267,34 @@ static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn) TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr) TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str) + +static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz, + gen_helper_gvec_4 *fn) +{ + int svl = streaming_vec_reg_size(s); + uint32_t desc = simd_desc(svl, svl, 0); + TCGv_ptr za, zn, pn, pm; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za = get_tile_rowcol(s, esz, 31, a->zad, false); + zn = vec_full_reg_ptr(s, a->zn); + pn = pred_full_reg_ptr(s, a->pn); + pm = pred_full_reg_ptr(s, a->pm); + + fn(za, zn, pn, pm, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + return true; +} + +TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addha_s) +TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) +TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d) +TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d) From patchwork Fri Jul 8 15:15:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588528 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp763164mab; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.16.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:16:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v6 24/45] target/arm: Implement FMOPA, FMOPS (non-widening) Date: Fri, 8 Jul 2022 20:45:19 +0530 Message-Id: <20220708151540.18136-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 5 +++ target/arm/sme.decode | 9 +++++ target/arm/sme_helper.c | 69 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 32 ++++++++++++++++++ 4 files changed, 115 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 753e9e624c..f50d0fe1d6 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -120,3 +120,8 @@ DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 8cb6c4053c..ba4774d174 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -64,3 +64,12 @@ ADDHA_s 11000000 10 01000 0 ... ... ..... 000 .. @adda_32 ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32 ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64 ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 + +### SME Outer Product + +&op zad zn zm pm pn sub:bool +@op_32 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 .. zad:2 &op +@op_64 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 . zad:3 &op + +FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 +FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index f1e924db74..7dc76b6a1c 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -25,6 +25,7 @@ #include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "qemu/int128.h" +#include "fpu/softfloat.h" #include "vec_internal.h" #include "sve_ldst_internal.h" @@ -918,3 +919,71 @@ void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn, } } } + +void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_maxsz(desc); + uint32_t neg = simd_data(desc) << 31; + uint16_t *pn = vpn, *pm = vpm; + float_status fpst; + + /* + * Make a copy of float_status because this operation does not + * update the cumulative fp exception status. It also produces + * default nans. + */ + fpst = *(float_status *)vst; + set_default_nan_mode(true, &fpst); + + for (row = 0; row < oprsz; ) { + uint16_t pa = pn[H2(row >> 4)]; + do { + if (pa & 1) { + void *vza_row = vza + tile_vslice_offset(row); + uint32_t n = *(uint32_t *)(vzn + H1_4(row)) ^ neg; + + for (col = 0; col < oprsz; ) { + uint16_t pb = pm[H2(col >> 4)]; + do { + if (pb & 1) { + uint32_t *a = vza_row + H1_4(col); + uint32_t *m = vzm + H1_4(col); + *a = float32_muladd(n, *m, *a, 0, vst); + } + col += 4; + pb >>= 4; + } while (col & 15); + } + } + row += 4; + pa >>= 4; + } while (row & 15); + } +} + +void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_oprsz(desc) / 8; + uint64_t neg = (uint64_t)simd_data(desc) << 63; + uint64_t *za = vza, *zn = vzn, *zm = vzm; + uint8_t *pn = vpn, *pm = vpm; + float_status fpst = *(float_status *)vst; + + set_default_nan_mode(true, &fpst); + + for (row = 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + uint64_t *za_row = &za[tile_vslice_index(row)]; + uint64_t n = zn[row] ^ neg; + + for (col = 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + uint64_t *a = &za_row[col]; + *a = float64_muladd(n, zm[col], *a, 0, &fpst); + } + } + } + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index d3b9cdd5c4..fa8f343a7d 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -298,3 +298,35 @@ TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addha_s) TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d) TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d) + +static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, + gen_helper_gvec_5_ptr *fn) +{ + int svl = streaming_vec_reg_size(s); + uint32_t desc = simd_desc(svl, svl, a->sub); + TCGv_ptr za, zn, zm, pn, pm, fpst; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za = get_tile_rowcol(s, esz, 31, a->zad, false); + zn = vec_full_reg_ptr(s, a->zn); + zm = vec_full_reg_ptr(s, a->zm); + pn = pred_full_reg_ptr(s, a->pn); + pm = pred_full_reg_ptr(s, a->pm); + fpst = fpstatus_ptr(FPST_FPCR); + + fn(za, zn, zm, pn, pm, fpst, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + tcg_temp_free_ptr(fpst); + return true; +} + +TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s) +TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_fmopa_d) From patchwork Fri Jul 8 15:15:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588525 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp760561mab; Fri, 8 Jul 2022 08:26:38 -0700 (PDT) X-Google-Smtp-Source: AGRyM1t90L0CLwulHXTh7a84GKSvFVyaAzphfxlFiU2974417L0T7eKmJVKpH6lrRCHkGCn2Xfc/ X-Received: by 2002:ad4:5964:0:b0:472:f02e:b39d with SMTP id eq4-20020ad45964000000b00472f02eb39dmr3185269qvb.124.1657293998544; Fri, 08 Jul 2022 08:26:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657293998; cv=none; d=google.com; s=arc-20160816; b=bk8IBCPO+Oh1sVr6QZ9K4zOWThW7sWLDm6QFOBS1K4geQ7TAoOS/LcJPuNzE/9dFnH u5EbavRGV87TCuoP79YkADHiqGSqeMsTBuWhDAx2OfwFT8MI3R9K1ErmlS2MI4EXN03s IaQATzWTGWp9oA/hjtBEFbdqGujhQE7A36dp6ShlfmaMQUp+qRwnvXL/466ygkB3FV2e sjiGQiy7AT/XzNCChq5uWwO90vOEzkovqZh4byn5eG5uDcOH+vMgyVJaQoTCVv0lyDL6 HQSFHW3Lg9d1jiLvmEADQjNohLjlzunzdwngw9iGS0zKsWhMyIXP7+P+dTn++8LKjbDG AVjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ixcykaZZg1mCTysoeSKW2RpHUNDMDNdzI+zk42sFn7c=; b=KuYJkhAUR/w9WlMecwq9NbWsnfPcThJs4b52rlee/f5wlYPAldT/2ltg4UIGvyQ4Jx U2mzF/xv4cGt3F7iwdKRJ7zei4xUjMfHwda40keRFZ+qXhjAUBCnxDi9V0AeAFaOwH2c fDK8GUOL3b6FKs7wmQ/Nw3c6HasPiWvzn0Rl837pYVqj0AqiEck5xgkIUSX79MUA2n5g Rn0BxgS4wBsaREHS2X1Sb/9MafM73LNAEjvLlk2CWm4Ro5TMHuHfONQgIW8CRMBHXHTA fFxjag9PJHVhvBb2q01bxQS4t7ricpFRxf7fKubTQD1ijBNEF9l8n74lu2v3pkXUD4R0 6niw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="UoT9a7/S"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v6 25/45] target/arm: Implement BFMOPA, BFMOPS Date: Fri, 8 Jul 2022 20:45:20 +0530 Message-Id: <20220708151540.18136-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 2 ++ target/arm/sme.decode | 2 ++ target/arm/sme_helper.c | 56 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 30 ++++++++++++++++++++ 4 files changed, 90 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index f50d0fe1d6..1d68fb8c74 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -125,3 +125,5 @@ DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index ba4774d174..afd9c0dffd 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -73,3 +73,5 @@ ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 + +BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 7dc76b6a1c..690a53eee2 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -987,3 +987,59 @@ void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn, } } } + +/* + * Alter PAIR as needed for controlling predicates being false, + * and for NEG on an enabled row element. + */ +static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_t neg) +{ + /* + * The pseudocode uses a conditional negate after the conditional zero. + * It is simpler here to unconditionally negate before conditional zero. + */ + pair ^= neg; + if (!(pg & 1)) { + pair &= 0xffff0000u; + } + if (!(pg & 4)) { + pair &= 0x0000ffffu; + } + return pair; +} + +void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_maxsz(desc); + uint32_t neg = simd_data(desc) * 0x80008000u; + uint16_t *pn = vpn, *pm = vpm; + + for (row = 0; row < oprsz; ) { + uint16_t prow = pn[H2(row >> 4)]; + do { + void *vza_row = vza + tile_vslice_offset(row); + uint32_t n = *(uint32_t *)(vzn + H1_4(row)); + + n = f16mop_adj_pair(n, prow, neg); + + for (col = 0; col < oprsz; ) { + uint16_t pcol = pm[H2(col >> 4)]; + do { + if (prow & pcol & 0b0101) { + uint32_t *a = vza_row + H1_4(col); + uint32_t m = *(uint32_t *)(vzm + H1_4(col)); + + m = f16mop_adj_pair(m, pcol, 0); + *a = bfdotadd(*a, n, m); + + col += 4; + pcol >>= 4; + } + } while (col & 15); + } + row += 4; + prow >>= 4; + } while (row & 15); + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index fa8f343a7d..ecb7583c55 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -299,6 +299,33 @@ TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d) TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d) +static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz, + gen_helper_gvec_5 *fn) +{ + int svl = streaming_vec_reg_size(s); + uint32_t desc = simd_desc(svl, svl, a->sub); + TCGv_ptr za, zn, zm, pn, pm; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za = get_tile_rowcol(s, esz, 31, a->zad, false); + zn = vec_full_reg_ptr(s, a->zn); + zm = vec_full_reg_ptr(s, a->zm); + pn = pred_full_reg_ptr(s, a->pn); + pm = pred_full_reg_ptr(s, a->pm); + + fn(za, zn, zm, pn, pm, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + return true; +} + static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, gen_helper_gvec_5_ptr *fn) { @@ -330,3 +357,6 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s) TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_fmopa_d) + +/* TODO: FEAT_EBF16 */ +TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa) From patchwork Fri Jul 8 15:15:21 2022 Content-Type: text/plain; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v6 26/45] target/arm: Implement FMOPA, FMOPS (widening) Date: Fri, 8 Jul 2022 20:45:21 +0530 Message-Id: <20220708151540.18136-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 2 ++ target/arm/sme.decode | 1 + target/arm/sme_helper.c | 74 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 1 + 4 files changed, 78 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 1d68fb8c74..4d5d05db3a 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -121,6 +121,8 @@ DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, diff --git a/target/arm/sme.decode b/target/arm/sme.decode index afd9c0dffd..e8d27fd8a0 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -75,3 +75,4 @@ FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 +FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 690a53eee2..302f89c30b 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -1008,6 +1008,80 @@ static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_t neg) return pair; } +static float32 f16_dotadd(float32 sum, uint32_t e1, uint32_t e2, + float_status *s_std, float_status *s_odd) +{ + float64 e1r = float16_to_float64(e1 & 0xffff, true, s_std); + float64 e1c = float16_to_float64(e1 >> 16, true, s_std); + float64 e2r = float16_to_float64(e2 & 0xffff, true, s_std); + float64 e2c = float16_to_float64(e2 >> 16, true, s_std); + float64 t64; + float32 t32; + + /* + * The ARM pseudocode function FPDot performs both multiplies + * and the add with a single rounding operation. Emulate this + * by performing the first multiply in round-to-odd, then doing + * the second multiply as fused multiply-add, and rounding to + * float32 all in one step. + */ + t64 = float64_mul(e1r, e2r, s_odd); + t64 = float64r32_muladd(e1c, e2c, t64, 0, s_std); + + /* This conversion is exact, because we've already rounded. */ + t32 = float64_to_float32(t64, s_std); + + /* The final accumulation step is not fused. */ + return float32_add(sum, t32, s_std); +} + +void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_maxsz(desc); + uint32_t neg = simd_data(desc) * 0x80008000u; + uint16_t *pn = vpn, *pm = vpm; + float_status fpst_odd, fpst_std; + + /* + * Make a copy of float_status because this operation does not + * update the cumulative fp exception status. It also produces + * default nans. Make a second copy with round-to-odd -- see above. + */ + fpst_std = *(float_status *)vst; + set_default_nan_mode(true, &fpst_std); + fpst_odd = fpst_std; + set_float_rounding_mode(float_round_to_odd, &fpst_odd); + + for (row = 0; row < oprsz; ) { + uint16_t prow = pn[H2(row >> 4)]; + do { + void *vza_row = vza + tile_vslice_offset(row); + uint32_t n = *(uint32_t *)(vzn + H1_4(row)); + + n = f16mop_adj_pair(n, prow, neg); + + for (col = 0; col < oprsz; ) { + uint16_t pcol = pm[H2(col >> 4)]; + do { + if (prow & pcol & 0b0101) { + uint32_t *a = vza_row + H1_4(col); + uint32_t m = *(uint32_t *)(vzm + H1_4(col)); + + m = f16mop_adj_pair(m, pcol, 0); + *a = f16_dotadd(*a, n, m, &fpst_std, &fpst_odd); + + col += 4; + pcol >>= 4; + } + } while (col & 15); + } + row += 4; + prow >>= 4; + } while (row & 15); + } +} + void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, void *vpm, uint32_t desc) { diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index ecb7583c55..c2953b22ce 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -355,6 +355,7 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, return true; } +TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_h) TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s) TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_fmopa_d) From patchwork Fri Jul 8 15:15:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588532 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp767251mab; Fri, 8 Jul 2022 08:34:26 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vajytal/ZwQYC6Vae5nRfBb8dDg4L/RYFFnH4ki2/djES814lKSP/T47PXEQ/M1K216EO8 X-Received: by 2002:a05:620a:199d:b0:6af:1eb8:d0cf with SMTP id bm29-20020a05620a199d00b006af1eb8d0cfmr2755109qkb.124.1657294465965; Fri, 08 Jul 2022 08:34:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657294465; cv=none; d=google.com; s=arc-20160816; b=O3SrH2HrHo0Q0LsZU2yqSOaUTyvaQwg6279o1Zf2uXAjhBHcBKrcOx8x+IRdN6eL3l urI10bpSiCJAvqxy5iFAL6B6QCIpalUZ00ZBNUEMoxCZIPvWWX1nlYEEN1xz5g2hWDRu 6QVC/9Ir3qD4cNXSJc1b+NldzGVSGeSVb9RvgVZH9JVgh4QOKXznxk5SSDh8a7ANNa94 bvAQmknJwImaUXkKRqycO+DKQh2SnS8ARPxXG46QVWGFDj3uljNMfz+cbT/I58I4GiyF Jr1g5C759hPWewltUzn3oHeb11f2ApYKfCmAXIxCo7Af1jA+J+fifv3r7IQVNeh3gYHw mN/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hXhGi/aw89RWj52AXFgmx3W0yCI8A/e6P49IWgiTRQs=; b=isrouv9rDWOywASQ+2jpAPsul1q8qA4CSKgGLE+mKsdx+lUJzSVgCLBg4Nz2uD+dkZ DQZZ0UIiGxV/tf7qN9+LrdySGQOedJyROfGEDTdBsYynklvRRm6QlhNhjQR2so/uiZ38 isXPQB+VUodkTRKZP9hDGvlvK/Tvzqn5OjtVL2WkZAVYsRcIemAZxWDXsX4c8tISWA4v eg4FoZEmSZxtgpaeLY/WzU/fUiAGomzg6lbDUcR6Rrkivkg9/PLml/fHmwsbi2n7xl22 ZWlaldttwbrox+TPW+tZOvq02gFmPHXdtipS7YWgLGTIUDxZ0g5VzjLmmVZDp9g5t4nL LxKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gycKuKBN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 27/45] target/arm: Implement SME integer outer product Date: Fri, 8 Jul 2022 20:45:22 +0530 Message-Id: <20220708151540.18136-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 16 ++++++++ target/arm/sme.decode | 10 +++++ target/arm/sme_helper.c | 82 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 10 +++++ 4 files changed, 118 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 4d5d05db3a..d2d544a696 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -129,3 +129,19 @@ DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_smopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_umopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_sumopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_usmopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_smopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_umopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_sumopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_usmopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index e8d27fd8a0..628804e37a 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -76,3 +76,13 @@ FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32 + +SMOPA_s 1010000 0 10 0 ..... ... ... ..... . 00 .. @op_32 +SUMOPA_s 1010000 0 10 1 ..... ... ... ..... . 00 .. @op_32 +USMOPA_s 1010000 1 10 0 ..... ... ... ..... . 00 .. @op_32 +UMOPA_s 1010000 1 10 1 ..... ... ... ..... . 00 .. @op_32 + +SMOPA_d 1010000 0 11 0 ..... ... ... ..... . 0 ... @op_64 +SUMOPA_d 1010000 0 11 1 ..... ... ... ..... . 0 ... @op_64 +USMOPA_d 1010000 1 11 0 ..... ... ... ..... . 0 ... @op_64 +UMOPA_d 1010000 1 11 1 ..... ... ... ..... . 0 ... @op_64 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 302f89c30b..f891306bb9 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -1117,3 +1117,85 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, } while (row & 15); } } + +typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool); + +static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm, + uint8_t *pn, uint8_t *pm, + uint32_t desc, IMOPFn *fn) +{ + intptr_t row, col, oprsz = simd_oprsz(desc) / 8; + bool neg = simd_data(desc); + + for (row = 0; row < oprsz; ++row) { + uint8_t pa = pn[H1(row)]; + uint64_t *za_row = &za[tile_vslice_index(row)]; + uint64_t n = zn[row]; + + for (col = 0; col < oprsz; ++col) { + uint8_t pb = pm[H1(col)]; + uint64_t *a = &za_row[col]; + + *a = fn(n, zm[col], *a, pa & pb, neg); + } + } +} + +#define DEF_IMOP_32(NAME, NTYPE, MTYPE) \ +static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \ +{ \ + uint32_t sum0 = 0, sum1 = 0; \ + /* Apply P to N as a mask, making the inactive elements 0. */ \ + n &= expand_pred_b(p); \ + sum0 += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \ + sum0 += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \ + sum0 += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \ + sum0 += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \ + sum1 += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \ + sum1 += (NTYPE)(n >> 40) * (MTYPE)(m >> 40); \ + sum1 += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \ + sum1 += (NTYPE)(n >> 56) * (MTYPE)(m >> 56); \ + if (neg) { \ + sum0 = (uint32_t)a - sum0, sum1 = (uint32_t)(a >> 32) - sum1; \ + } else { \ + sum0 = (uint32_t)a + sum0, sum1 = (uint32_t)(a >> 32) + sum1; \ + } \ + return ((uint64_t)sum1 << 32) | sum0; \ +} + +#define DEF_IMOP_64(NAME, NTYPE, MTYPE) \ +static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \ +{ \ + uint64_t sum = 0; \ + /* Apply P to N as a mask, making the inactive elements 0. */ \ + n &= expand_pred_h(p); \ + sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \ + sum += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \ + sum += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \ + sum += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \ + return neg ? a - sum : a + sum; \ +} + +DEF_IMOP_32(smopa_s, int8_t, int8_t) +DEF_IMOP_32(umopa_s, uint8_t, uint8_t) +DEF_IMOP_32(sumopa_s, int8_t, uint8_t) +DEF_IMOP_32(usmopa_s, uint8_t, int8_t) + +DEF_IMOP_64(smopa_d, int16_t, int16_t) +DEF_IMOP_64(umopa_d, uint16_t, uint16_t) +DEF_IMOP_64(sumopa_d, int16_t, uint16_t) +DEF_IMOP_64(usmopa_d, uint16_t, int16_t) + +#define DEF_IMOPH(NAME) \ + void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, \ + void *vpm, uint32_t desc) \ + { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); } + +DEF_IMOPH(smopa_s) +DEF_IMOPH(umopa_s) +DEF_IMOPH(sumopa_s) +DEF_IMOPH(usmopa_s) +DEF_IMOPH(smopa_d) +DEF_IMOPH(umopa_d) +DEF_IMOPH(sumopa_d) +DEF_IMOPH(usmopa_d) diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index c2953b22ce..7b87a9df63 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -361,3 +361,13 @@ TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_f /* TODO: FEAT_EBF16 */ TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa) + +TRANS_FEAT(SMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_smopa_s) +TRANS_FEAT(UMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_umopa_s) +TRANS_FEAT(SUMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_sumopa_s) +TRANS_FEAT(USMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_usmopa_s) + +TRANS_FEAT(SMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_smopa_d) +TRANS_FEAT(UMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_umopa_d) +TRANS_FEAT(SUMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_sumopa_d) +TRANS_FEAT(USMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_usmopa_d) From patchwork Fri Jul 8 15:15:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588536 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp770255mab; Fri, 8 Jul 2022 08:38:09 -0700 (PDT) X-Google-Smtp-Source: AGRyM1u+sOT06TJJou+JnhsgU3E0KbDXw/riKIvvkbt8DyESR70AxIjS/syrRjuMkxrNM7lkgNsi X-Received: by 2002:a0c:b456:0:b0:470:7aff:7e8c with SMTP id e22-20020a0cb456000000b004707aff7e8cmr3063291qvf.53.1657294689485; Fri, 08 Jul 2022 08:38:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657294689; cv=none; d=google.com; s=arc-20160816; b=xThjD5eSaRpQugu4fNgf5eSr5MXdqR8ee6mY1UiKaIGiBLesrTVqbC8Mx5W58/VBFy XOtkcOSGEzf+tIOl5e0gziyxTWQbDSWFNnlEaAjCr0+0N7GnSYtPVWswvyC7L+HR1xAu uw7WKOF5YBC7p1KTwe0FXz7cfdLlS3P2vj9gcKwHqN4cAZcOZuVADptiR2jpw8q3DCbr E4IChhm2NC21LNFniOTE8CG6/5AlRv1FAU2Qyts66aWOkHuJP86nfOrl1w0YfdUxYUGI 2SW75eJ14NGlnvF2bGaFXOWbQsGZwTJw3UD3RodCKLj+eA2FE5DC1HQEzAlFQyE9c8Cu 1/gQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=z4hqPmoRZ7cVUM8Y9hb593g0CFOYpdMYGSA5G3fCVmQ=; b=RK6/KlfgY6IuVA1Fy+Oqhn7djbW08gjmDi2e/KuoYA17rI0cqJgILEdRlpyI2Qph1y 49cGtWbPjcU26BHIAZssGlF/W8NGeImUeeKRPE1UcEbnLBS9CSKxPWIGzZn/+xq2qLvZ s5+Dh8Jd1I5redy6YTuymOkS5OHmO39XyUknRUCWa+QuwY5HYicIQeHSQNEZqP0sO3r2 7JJrJRMH4PURWuu64QzEeIvraL7zUWYzp8eXyIuAj2KXbkihO0/r85EXV3gxJjCSxnZe XGyRDlDYySc+NY4dPyz92PAyny2X4drNn5kuCibidUPovN4KZmQv4gYlVHky/YgYWp4l 0NgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TW36E2ZK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 28/45] target/arm: Implement PSEL Date: Fri, 8 Jul 2022 20:45:23 +0530 Message-Id: <20220708151540.18136-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve.decode | 20 +++++++++++++ target/arm/translate-sve.c | 57 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 95af08c139..966803cbb7 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1674,3 +1674,23 @@ BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2 ### SVE2 floating-point bfloat16 dot-product (indexed) BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=2 + +### SVE broadcast predicate element + +&psel esz pd pn pm rv imm +%psel_rv 16:2 !function=plus_12 +%psel_imm_b 22:2 19:2 +%psel_imm_h 22:2 20:1 +%psel_imm_s 22:2 +%psel_imm_d 23:1 +@psel ........ .. . ... .. .. pn:4 . pm:4 . pd:4 \ + &psel rv=%psel_rv + +PSEL 00100101 .. 1 ..1 .. 01 .... 0 .... 0 .... \ + @psel esz=0 imm=%psel_imm_b +PSEL 00100101 .. 1 .10 .. 01 .... 0 .... 0 .... \ + @psel esz=1 imm=%psel_imm_h +PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \ + @psel esz=2 imm=%psel_imm_s +PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ + @psel esz=3 imm=%psel_imm_d diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index fd1a173637..24ffb69a2a 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7419,3 +7419,60 @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel) TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false) TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true) + +static bool trans_PSEL(DisasContext *s, arg_psel *a) +{ + int vl = vec_full_reg_size(s); + int pl = pred_gvec_reg_size(s); + int elements = vl >> a->esz; + TCGv_i64 tmp, didx, dbit; + TCGv_ptr ptr; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sve_access_check(s)) { + return true; + } + + tmp = tcg_temp_new_i64(); + dbit = tcg_temp_new_i64(); + didx = tcg_temp_new_i64(); + ptr = tcg_temp_new_ptr(); + + /* Compute the predicate element. */ + tcg_gen_addi_i64(tmp, cpu_reg(s, a->rv), a->imm); + if (is_power_of_2(elements)) { + tcg_gen_andi_i64(tmp, tmp, elements - 1); + } else { + tcg_gen_remu_i64(tmp, tmp, tcg_constant_i64(elements)); + } + + /* Extract the predicate byte and bit indices. */ + tcg_gen_shli_i64(tmp, tmp, a->esz); + tcg_gen_andi_i64(dbit, tmp, 7); + tcg_gen_shri_i64(didx, tmp, 3); + if (HOST_BIG_ENDIAN) { + tcg_gen_xori_i64(didx, didx, 7); + } + + /* Load the predicate word. */ + tcg_gen_trunc_i64_ptr(ptr, didx); + tcg_gen_add_ptr(ptr, ptr, cpu_env); + tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm)); + + /* Extract the predicate bit and replicate to MO_64. */ + tcg_gen_shr_i64(tmp, tmp, dbit); + tcg_gen_andi_i64(tmp, tmp, 1); + tcg_gen_neg_i64(tmp, tmp); + + /* Apply to either copy the source, or write zeros. */ + tcg_gen_gvec_ands(MO_64, pred_full_reg_offset(s, a->pd), + pred_full_reg_offset(s, a->pn), tmp, pl, pl); + + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(dbit); + tcg_temp_free_i64(didx); + tcg_temp_free_ptr(ptr); + return true; +} From patchwork Fri Jul 8 15:15:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588548 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp780927mab; Fri, 8 Jul 2022 08:51:11 -0700 (PDT) X-Google-Smtp-Source: AGRyM1ts1IRv4UbEmWeNo2o4C3LTH9+ENICr5I3SoMorns7WyJF/2AwbL9gnrA8k+27enaXbxNTc X-Received: by 2002:a37:a254:0:b0:6b5:5007:dc8c with SMTP id l81-20020a37a254000000b006b55007dc8cmr2836499qke.712.1657295471649; Fri, 08 Jul 2022 08:51:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657295471; cv=none; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 29/45] target/arm: Implement REVD Date: Fri, 8 Jul 2022 20:45:24 +0530 Message-Id: <20220708151540.18136-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 2 ++ target/arm/sve.decode | 1 + target/arm/sve_helper.c | 16 ++++++++++++++++ target/arm/translate-sve.c | 2 ++ 4 files changed, 21 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index ab0333400f..cc4e1d8948 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -719,6 +719,8 @@ DEF_HELPER_FLAGS_4(sve_revh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_revw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_revd_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(sve_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_rbit_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_rbit_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 966803cbb7..a9e48f07b4 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -652,6 +652,7 @@ REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn +REVD 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_e0 # SVE vector splice (predicated, destructive) SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index df16170469..d6f7ef94fe 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -931,6 +931,22 @@ DO_ZPZ_D(sve_revh_d, uint64_t, hswap64) DO_ZPZ_D(sve_revw_d, uint64_t, wswap64) +void HELPER(sme_revd_q)(void *vd, void *vn, void *vg, uint32_t desc) +{ + intptr_t i, opr_sz = simd_oprsz(desc) / 8; + uint64_t *d = vd, *n = vn; + uint8_t *pg = vg; + + for (i = 0; i < opr_sz; i += 2) { + if (pg[H1(i)] & 1) { + uint64_t n0 = n[i + 0]; + uint64_t n1 = n[i + 1]; + d[i + 0] = n1; + d[i + 1] = n0; + } + } +} + DO_ZPZ(sve_rbit_b, uint8_t, H1, revbit8) DO_ZPZ(sve_rbit_h, uint16_t, H1_2, revbit16) DO_ZPZ(sve_rbit_s, uint32_t, H1_4, revbit32) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 24ffb69a2a..9ed3b267fd 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -2901,6 +2901,8 @@ TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0) TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz, a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0) +TRANS_FEAT(REVD, aa64_sme, gen_gvec_ool_arg_zpz, gen_helper_sme_revd_q, a, 0) + TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz, gen_helper_sve_splice, a, a->esz) From patchwork Fri Jul 8 15:15:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588545 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp778181mab; Fri, 8 Jul 2022 08:47:58 -0700 (PDT) X-Google-Smtp-Source: AGRyM1teT5lGmJ0VJxfSTvNjDv1nRrChsYhNJTiCw15s77fQNIjtzJr6WxqQnAUmxT74raGQYciw X-Received: by 2002:a05:6214:29cc:b0:473:2246:40a6 with SMTP id gh12-20020a05621429cc00b00473224640a6mr3110159qvb.87.1657295278616; Fri, 08 Jul 2022 08:47:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657295278; cv=none; d=google.com; s=arc-20160816; b=yot80fgJKEVMP+4L/AkIHEjrDJwbbbcdt1W/FfCCDjfmZLBvvXLKMcjxy8KXxioJn3 2zPI83za1oi7y2Fw9t5Haosa53odFYukwFqd0UmLPiu2dQlCtohzd4br6yde+rn2HJDU /hUX0DIn32Rz5KQElMBmfvPlJhKk1v4aPRuQhlpTEs43+2Ab3avR5i9B8neA6Y3RBdBE EFi5Eg88xbFOom9JvIrt//XLOpwlJyGytXqU23kkXjRoXxa2GKhniC+7SiObErgy8cQ7 x9H51Vz97PPZSh2oxIxQg1h0yggwJ04n+WHLjc+2Nd6/YYKgCxt9dZZ6heWmf4FjgRgg SICg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xDxZQB7t7jC7e11iBt04ewldeYznmzQBar7IyZiGr2c=; b=CJu074JaMSwpNjctywDt0jG4WVFgTlmsYv+M6PaBBgs8T1E5QjAGmeDawahGTbGowX jc+VfgANtGS8rTgZdJRg+1WS9/+YiXs+HNyNcaIS5IONW4ZybF/f5WdBQkr8YUukoJ5f qp+euOqNQAnDqgOkXh8Vx9Uyeq/fGjGIMaO2taHY4ClM9BlIL251l/fHkZP5IKzqR1X+ ccud1uyiYQ2SutFye2gbCBVFpoLKIQPdkuLtyFbrIWDsWT+ICN8JMaZM5b9qnyM3Jpru FfdodWb4aA8tdznYgJQEkMKpRhO84Ny5WFwh5g+jbaX9+dRgfEtqj6LoNCLC8tHFjh4S 5dlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="CC/uRJhV"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 30/45] target/arm: Implement SCLAMP, UCLAMP Date: Fri, 8 Jul 2022 20:45:25 +0530 Message-Id: <20220708151540.18136-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 18 +++++++ target/arm/sve.decode | 5 ++ target/arm/translate-sve.c | 102 +++++++++++++++++++++++++++++++++++++ target/arm/vec_helper.c | 24 +++++++++ 4 files changed, 149 insertions(+) diff --git a/target/arm/helper.h b/target/arm/helper.h index 3a8ce42ab0..92f36d9dbb 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1019,6 +1019,24 @@ DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a9e48f07b4..14b3a69c36 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1695,3 +1695,8 @@ PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \ @psel esz=2 imm=%psel_imm_s PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ @psel esz=3 imm=%psel_imm_d + +### SVE clamp + +SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm +UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9ed3b267fd..41f8b12259 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7478,3 +7478,105 @@ static bool trans_PSEL(DisasContext *s, arg_psel *a) tcg_temp_free_ptr(ptr); return true; } + +static void gen_sclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a) +{ + tcg_gen_smax_i32(d, a, n); + tcg_gen_smin_i32(d, d, m); +} + +static void gen_sclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a) +{ + tcg_gen_smax_i64(d, a, n); + tcg_gen_smin_i64(d, d, m); +} + +static void gen_sclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n, + TCGv_vec m, TCGv_vec a) +{ + tcg_gen_smax_vec(vece, d, a, n); + tcg_gen_smin_vec(vece, d, d, m); +} + +static void gen_sclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m, + uint32_t a, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop[] = { + INDEX_op_smin_vec, INDEX_op_smax_vec, 0 + }; + static const GVecGen4 ops[4] = { + { .fniv = gen_sclamp_vec, + .fno = gen_helper_gvec_sclamp_b, + .opt_opc = vecop, + .vece = MO_8 }, + { .fniv = gen_sclamp_vec, + .fno = gen_helper_gvec_sclamp_h, + .opt_opc = vecop, + .vece = MO_16 }, + { .fni4 = gen_sclamp_i32, + .fniv = gen_sclamp_vec, + .fno = gen_helper_gvec_sclamp_s, + .opt_opc = vecop, + .vece = MO_32 }, + { .fni8 = gen_sclamp_i64, + .fniv = gen_sclamp_vec, + .fno = gen_helper_gvec_sclamp_d, + .opt_opc = vecop, + .vece = MO_64, + .prefer_i64 = TCG_TARGET_REG_BITS == 64 } + }; + tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); +} + +TRANS_FEAT(SCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_sclamp, a) + +static void gen_uclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a) +{ + tcg_gen_umax_i32(d, a, n); + tcg_gen_umin_i32(d, d, m); +} + +static void gen_uclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a) +{ + tcg_gen_umax_i64(d, a, n); + tcg_gen_umin_i64(d, d, m); +} + +static void gen_uclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n, + TCGv_vec m, TCGv_vec a) +{ + tcg_gen_umax_vec(vece, d, a, n); + tcg_gen_umin_vec(vece, d, d, m); +} + +static void gen_uclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m, + uint32_t a, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop[] = { + INDEX_op_umin_vec, INDEX_op_umax_vec, 0 + }; + static const GVecGen4 ops[4] = { + { .fniv = gen_uclamp_vec, + .fno = gen_helper_gvec_uclamp_b, + .opt_opc = vecop, + .vece = MO_8 }, + { .fniv = gen_uclamp_vec, + .fno = gen_helper_gvec_uclamp_h, + .opt_opc = vecop, + .vece = MO_16 }, + { .fni4 = gen_uclamp_i32, + .fniv = gen_uclamp_vec, + .fno = gen_helper_gvec_uclamp_s, + .opt_opc = vecop, + .vece = MO_32 }, + { .fni8 = gen_uclamp_i64, + .fniv = gen_uclamp_vec, + .fno = gen_helper_gvec_uclamp_d, + .opt_opc = vecop, + .vece = MO_64, + .prefer_i64 = TCG_TARGET_REG_BITS == 64 } + }; + tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); +} + +TRANS_FEAT(UCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_uclamp, a) diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 9a9c034e36..f59d3b26ea 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -2690,3 +2690,27 @@ void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, void *vm, } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +#define DO_CLAMP(NAME, TYPE) \ +void HELPER(NAME)(void *d, void *n, void *m, void *a, uint32_t desc) \ +{ \ + intptr_t i, opr_sz = simd_oprsz(desc); \ + for (i = 0; i < opr_sz; i += sizeof(TYPE)) { \ + TYPE aa = *(TYPE *)(a + i); \ + TYPE nn = *(TYPE *)(n + i); \ + TYPE mm = *(TYPE *)(m + i); \ + TYPE dd = MIN(MAX(aa, nn), mm); \ + *(TYPE *)(d + i) = dd; \ + } \ + clear_tail(d, opr_sz, simd_maxsz(desc)); \ +} + +DO_CLAMP(gvec_sclamp_b, int8_t) +DO_CLAMP(gvec_sclamp_h, int16_t) +DO_CLAMP(gvec_sclamp_s, int32_t) +DO_CLAMP(gvec_sclamp_d, int64_t) + +DO_CLAMP(gvec_uclamp_b, uint8_t) +DO_CLAMP(gvec_uclamp_h, uint16_t) +DO_CLAMP(gvec_uclamp_s, uint32_t) +DO_CLAMP(gvec_uclamp_d, uint64_t) From patchwork Fri Jul 8 15:15:26 2022 Content-Type: text/plain; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 31/45] target/arm: Reset streaming sve state on exception boundaries Date: Fri, 8 Jul 2022 20:45:26 +0530 Message-Id: <20220708151540.18136-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can handle both exception entry and exception return by hooking into aarch64_sve_change_el. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 73a5b2b86d..cfcad97ce0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11242,6 +11242,19 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, return; } + old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; + new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; + + /* + * Both AArch64.TakeException and AArch64.ExceptionReturn + * invoke ResetSVEState when taking an exception from, or + * returning to, AArch32 state when PSTATE.SM is enabled. + */ + if (old_a64 != new_a64 && FIELD_EX64(env->svcr, SVCR, SM)) { + arm_reset_sve_state(env); + return; + } + /* * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped * at ELx, or not available because the EL is in AArch32 state, then @@ -11254,10 +11267,8 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, * we already have the correct register contents when encountering the * vq0->vq0 transition between EL0->EL1. */ - old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; old_len = (old_a64 && !sve_exception_el(env, old_el) ? sve_vqm1_for_el(env, old_el) : 0); - new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; new_len = (new_a64 && !sve_exception_el(env, new_el) ? sve_vqm1_for_el(env, new_el) : 0); From patchwork Fri Jul 8 15:15:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588547 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp780911mab; Fri, 8 Jul 2022 08:51:10 -0700 (PDT) X-Google-Smtp-Source: AGRyM1twShp7a4xozYtwONVRrxRnO0o85PkJp5bnJJl5jDw0EEEzyvFoBXUda/thwrOW/J5O3G6v X-Received: by 2002:a05:620a:4055:b0:6b5:67b4:fe4c with SMTP id i21-20020a05620a405500b006b567b4fe4cmr1782527qko.492.1657295470332; Fri, 08 Jul 2022 08:51:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657295470; cv=none; d=google.com; s=arc-20160816; b=pusXpeKm6JZ3Sw9ViAZkdw8tNF3b/PP/woH9LV+8/4yJw3o7q3tgGdZAvERT8Sntot 5cWA34iJKvjEsJiOvsaIaG/wtyXTPqh2voXHXSmUymJT32EShY5n9K6yTgpFzzJcF3OQ vaLaoj678uLVL22jteFvZ+1j3GviYqGnEyp0asrKg5Yugk3hjHivwsRh5l7jwePHkEU4 PHYD5rkFPAR5C8ADiXyFOCJKBW6e19oYZOG0RbSz2q/ZFUafpDGLzYx8c6CFyL4QvNq4 14kM8ThPru58Y83bbBDFVPfCSQca3yTwd7ShjvUxTxzIg4jJvRWt7HBGXHcvkLcxoQ4K YYxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vrb9+6VIoq7Bg5bHZHKrK2kLLIpATDy32zLGrACiZHA=; b=lDTMeFlOdlbi1Hgc9591HAgNLTmnVPv1ppO5/nvte16HPfhomBVxWepKAtiLoNVsBR kb+mZc24qNj5ez+hONHPHAtjmketKCSPt9AWomoMmUkriS0lGCHbB2do39fqqFQV9fHj LLmeGndIRdvTQLtmLCs8CQTlpZNQ4Dvmwf+H61Do+vGGaD0l3mLTC+3MNqvWJh/mZtl1 kXJnfXMcpfGdpu3SlO3V9jdYCshX4cCAr3AqIzcOSjCM3k9Z9TZmRJJuIx7nw+VzfXN3 e2msTGCnOrFcPOIZcbTvT+EbJPjtxJXxkvZSG08I7l+/IXEYtpiswl9wEPaBHwbAb6By coZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JsNuTco9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 32/45] target/arm: Enable SME for -cpu max Date: Fri, 8 Jul 2022 20:45:27 +0530 Message-Id: <20220708151540.18136-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Note that SME remains effectively disabled for user-only, because we do not yet set CPACR_EL1.SMEN. This needs to wait until the kernel ABI is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 4 ++++ target/arm/cpu64.c | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 83b4410065..8e494c8bea 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -65,6 +65,10 @@ the following architecture extensions: - FEAT_SHA512 (Advanced SIMD SHA512 instructions) - FEAT_SM3 (Advanced SIMD SM3 instructions) - FEAT_SM4 (Advanced SIMD SM4 instructions) +- FEAT_SME (Scalable Matrix Extension) +- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) +- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions) +- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions) - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index b4fd4b7ec8..78e27f778a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1024,6 +1024,7 @@ static void aarch64_max_initfn(Object *obj) */ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */ + t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 = t; @@ -1074,6 +1075,16 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 = t; + t = cpu->isar.id_aa64smfr0; + t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ + t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ + t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ + t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ + t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ + t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ + t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ + cpu->isar.id_aa64smfr0 = t; + /* Replicate the same data to the 32-bit id registers. */ aa32_max_features(cpu); From patchwork Fri Jul 8 15:15:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588559 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp792498mab; Fri, 8 Jul 2022 09:04:32 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uVD9lJ50kkqSiaTcUk8GJyp8kZVJVZvmsYhrldohJOyABuhMsRgBpn+6Hsu1UrG9ATIzDc X-Received: by 2002:a37:9f88:0:b0:6b5:53f0:a71f with SMTP id i130-20020a379f88000000b006b553f0a71fmr2940320qke.179.1657296242408; Fri, 08 Jul 2022 09:04:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657296242; cv=none; d=google.com; s=arc-20160816; b=wP5MKaMsy9Cl7rrJoNyT9NtNg9rpzUBgoUpBpvdUx0TAMq8FJrsMKXBXnHrMlvFiJY 2/VAqDJj8a+wHvYRrPnoDq6XkDEwbYXQt/1Df4cZOQCHCd/IB3N7KVsgFwQKc9D0RPBX nXHPoESqtg9MWhQI7N7RHMw4TGvrYQTI4g2mxpo4A8UUgUv/kIpAROC5AihS1G424gZa FaXt5/w02mnohz80wTRSIvEcS5rWiCTNOmr6UoHCD3S1LGOQjixx8qQSAXKCs/3pYRNn tgTZZ82Yq1ro0bRVlAAzA3nJiENtN54vw2+g9EMNjztHwxSLyQopxfGGRuzwm0qRAcov f2Tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5PME71S11cSPKZ4C3ISqAJ4KA5QkjnbMhk+jE1tP2f8=; b=cA7xaoBOT2EzBKh0HltSM+Wx5V7ekxZ8D2ZVWFUFr+sqIuIwOlK9zfnZwyiaNEUuIM oiyx18+A4OwKigSjWcDs28bracTOL9GCSidrcD9E9ZCamG59U/izazso2irFYY8USy6X 6jWJpm4+FaPiEElcpOuZjNxEucWzOxENBcBsE+RNxHXGN119w5JF4pUPORHTGwKOcVCG ACklAesjylNOwSXylgdoJYdmVClroYpRaTXXdOgaxC29nttQf/5z/jHTpH6PJdqlxbFp RehIjLFlJ0DuRkD/xfz0tA0Y2C9Hw78yPfFHOEsE8D8P40a21IkIvhIlm0R2GVT37mOg Lvtg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SvXHXwwr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 33/45] linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS Date: Fri, 8 Jul 2022 20:45:28 +0530 Message-Id: <20220708151540.18136-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/target_cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h index 97a477bd3e..f90359faf2 100644 --- a/linux-user/aarch64/target_cpu.h +++ b/linux-user/aarch64/target_cpu.h @@ -34,10 +34,13 @@ static inline void cpu_clone_regs_parent(CPUARMState *env, unsigned flags) static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) { - /* Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is + /* + * Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is * different from AArch32 Linux, which uses TPIDRRO. */ env->cp15.tpidr_el[0] = newtls; + /* TPIDR2_EL0 is cleared with CLONE_SETTLS. */ + env->cp15.tpidr2_el0 = 0; } static inline abi_ulong get_sp_from_cpustate(CPUARMState *state) From patchwork Fri Jul 8 15:15:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588555 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp786769mab; Fri, 8 Jul 2022 08:59:32 -0700 (PDT) X-Google-Smtp-Source: AGRyM1spSsi7BamPP+pw1o3XpYDGW74xOfG2yeYC2nJZyBGMTmIxkZkd+y/wR91dnXmf/v+E/wAO X-Received: by 2002:a05:622a:390:b0:31d:3428:f982 with SMTP id j16-20020a05622a039000b0031d3428f982mr3691701qtx.656.1657295971961; Fri, 08 Jul 2022 08:59:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657295971; cv=none; d=google.com; s=arc-20160816; b=vnzwVuDP3M1By5RM+oeTIjdiXRNBHL13bge3C83jr4jXiIpSbm3jvGKs03PUWLCb73 DKDiTDgjF75pmb6uezWanckU5KNI4PDecP7JCs2IWXC6mE4bLe21nJz26QVjetTlfY/n mhjjOECEeqFEx9SF9WypltsdI5g5pUNgrmedoSibAFBV7ZHYj/HTPcnhQTZTgb3k4aZC slyTzNSigi/2zusIp1NzN2Qhd+QDyF/irqwvCxG9NP6vZKeeP77Tazy8e3RDN8cfALQ0 YQcZqfnf7xZ5YznJdUp0NzGRYAN43zHY+9tggldUSOxzQtSuDjWrTqYJ5TO/MTpL175y 4uBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QXu/KgUnFX9XdonKOb4RpodqXgfNtkqVhXPaRa0Wz+g=; b=kP409H+ZnztXMqS9XdD6JQdv+SMdtc4+Gvl0f5ZVfMFdgN+EmHDKASvnsi9QNeGvKG vkWIQBOJ+dhukLS/45hZlNfEWIFiEmKWDGYFbWggC5veNhvgHT57rZ/0ZYTGGZrxzvsn NRJfV4VyGoQqvV8RaLEX15zn61zSe87FA6ZbAcn5xSLX7+1ywUJ2H4hkuU4PY69uIR5j ivFq3h4r38RTu+Fk09tsFvlP5WSuljvAzRc3+4yML/tQocXV1gQ/7oRJvDUGcoi7ZZ7M 6ehw6ZbzpsgjqpuMFNMulypkdYnW1kDE4JlmnSNpZcnvm1OACeTyOAlZ+3VsD4C8IwdE DyMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iPqiAvNn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 34/45] linux-user/aarch64: Reset PSTATE.SM on syscalls Date: Fri, 8 Jul 2022 20:45:29 +0530 Message-Id: <20220708151540.18136-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index f7ef36cd9f..9875d609a9 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -89,6 +89,15 @@ void cpu_loop(CPUARMState *env) switch (trapnr) { case EXCP_SWI: + /* + * On syscall, PSTATE.ZA is preserved, along with the ZA matrix. + * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState. + */ + if (FIELD_EX64(env->svcr, SVCR, SM)) { + env->svcr = FIELD_DP64(env->svcr, SVCR, SM, 0); + arm_rebuild_hflags(env); + arm_reset_sve_state(env); + } ret = do_syscall(env, env->xregs[8], env->xregs[0], From patchwork Fri Jul 8 15:15:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588554 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp784619mab; Fri, 8 Jul 2022 08:56:18 -0700 (PDT) X-Google-Smtp-Source: AGRyM1s3mWTxUVC12DXvyODnRvhfQycs2dJjmOXhZGMv5ansy+fL5zFEatKI7XcMY0lQCuMStwlY X-Received: by 2002:a05:620a:2889:b0:6b5:3f21:a537 with SMTP id j9-20020a05620a288900b006b53f21a537mr2781412qkp.442.1657295778649; Fri, 08 Jul 2022 08:56:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657295778; cv=none; d=google.com; s=arc-20160816; b=i80i219qMfQEBHtJFKWLz8SF46TwLdXxOgoClEbX3J4ro0/TDPAoLZ8vWs7bXLkWsD KmWTbZkuFUOrFlPg7UveTx9i3OY813mvbGS5FrudYP1xOdeW4wPwPZMjXOuveNCjC55c 7xIFYXfeVAFfeRsrWfZz4mv7g1lEtY+n9yx6oeaNMM4SlJiI8Ijg1gFeQpu4oZO413Nh qVI4ieJGEThC/8/ZT3W5llfWzc5k4COFfzpoEHBnZRiyl8NaFpBvV3BWqzu7jgyEBB2E kdTCBG7Uq5nZ509wLGITIp5jWuGEwh7wnBwUmnR+0u9UNLhcGDyufA0N8+MQTd152TgS fhEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ObBO5dq04E0/5WroJlYaFhrT48czebw/dLTC4ZwRUvk=; b=AyvTdZjNQRZPVoDPWtf0G6ODM2wniYg+iHxmXwLyISDmrAsNSpgC0oX0T5rbz8vy7t W6QSBYXBqcQHdOUvRBVIIvehsiiD7kmjWX2XSAJke6uPsWnRfvKDjFF/nt75SorbbF60 JAp6ak08HYaQqSDexIDNf0Afq0bgcHAEKwwbsyi1G6Xs2lzyocKiWU0rg+H8u06dBaz4 pLIbjWEt3DQr6yT3qBVriaVfzBEHuRaUJpn8ztwhXhFuYeJUUQKqrfxwUSASAqRRsvu9 vRoRf4j/XDr41AFLGvAVsag2H7IayvspnLwXQ9tDg+sTAf2ezGebJHKTsIkr01U+ljS0 Upbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a0gTKm+Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 35/45] linux-user/aarch64: Add SM bit to SVE signal context Date: Fri, 8 Jul 2022 20:45:30 +0530 Message-Id: <20220708151540.18136-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Make sure to zero the currently reserved fields. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 7da0e36c6d..3cef2f44cf 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -78,7 +78,8 @@ struct target_extra_context { struct target_sve_context { struct target_aarch64_ctx head; uint16_t vl; - uint16_t reserved[3]; + uint16_t flags; + uint16_t reserved[2]; /* The actual SVE data immediately follows. It is laid out * according to TARGET_SVE_SIG_{Z,P}REG_OFFSET, based off of * the original struct pointer. @@ -101,6 +102,8 @@ struct target_sve_context { #define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \ (TARGET_SVE_SIG_PREG_OFFSET(VQ, 17)) +#define TARGET_SVE_SIG_FLAG_SM 1 + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -177,9 +180,13 @@ static void target_setup_sve_record(struct target_sve_context *sve, { int i, j; + memset(sve, 0, sizeof(*sve)); __put_user(TARGET_SVE_MAGIC, &sve->head.magic); __put_user(size, &sve->head.size); __put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl); + if (FIELD_EX64(env->svcr, SVCR, SM)) { + __put_user(TARGET_SVE_SIG_FLAG_SM, &sve->flags); + } /* Note that SVE regs are stored as a byte stream, with each byte element * at a subsequent address. This corresponds to a little-endian store From patchwork Fri Jul 8 15:15:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588529 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp763412mab; Fri, 8 Jul 2022 08:30:09 -0700 (PDT) X-Google-Smtp-Source: AGRyM1szvt0V2qxNc1u4SUZdarJm4lrDA/HGXyioCYPdlr8C0cGc+ImOBey8r5gqYxor8fXQBBBY X-Received: by 2002:a05:622a:1791:b0:317:76d8:d17f with SMTP id s17-20020a05622a179100b0031776d8d17fmr3543844qtk.82.1657294209590; Fri, 08 Jul 2022 08:30:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657294209; cv=none; d=google.com; s=arc-20160816; b=flFSfKapewFJtYiMs5p0G8Lj3znWZZpNH0xEfA/Jo627JEIU1TQPrDmHEW9H/+fvZ+ jR/gAfiV4oGd0frWKSOq15K4rGOpvl7JrauufPwh4/1pyyW0aJXhXGKA2NostjJdlxWB 56Z+dL9G9PHDvY9CdLWyiN2zQ3V//xKXI9m7oSjXDc5TkSAC0zqqyZ+5bttV8HFLGc1o RYFa3M5JYpdMydBrQkt8PAI04fiFKHwtzNVgOD2+PmV2xBlPt906iHaFsjxv39diU3o9 hWSCom1ucrr7C4hn8smuiKXM8nnqm583dtGp8g3yEfU17GwAfI8TG/lzpZlKBRPBDjGO mBIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=u6i1Exm7OWbV1UGGZQ+hkV1UWXfqGJYzldSUkhdBqXw=; b=aO13fRn51LGAbF6it2QRGkkvIj+chPiYMKzG88zYKz4BYVYBv5o+6llkc25hN4Sav+ 5Hs7TSFGMP7SHabOV7ROHQRRklc/oU5mb/swNG/ImS7DZmOlHV4GAU+7LJ3FNjiPjmwa TU04S8gljApc/XNPuAhGuKEWJhlRwIMuHa08Hm5Oeko+EpNlkJasNL4lqU6VNewPXDGx z2pjqYV+MGBIYx6WQtDWZ8g6cqbrjmOoKYita6y15BNeX3slOb3MowS+5I2yYtRYbTYd tN1T4zcgT9q1qHHCOetAMK8v/7w+jfxij1KupCvGX7bxR5rF3UlWjOis7I1YbJz+Rl3R FcAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rt0nNnyN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 36/45] linux-user/aarch64: Tidy target_restore_sigframe error return Date: Fri, 8 Jul 2022 20:45:31 +0530 Message-Id: <20220708151540.18136-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fold the return value setting into the goto, so each point of failure need not do both. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 3cef2f44cf..8b352abb97 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -287,7 +287,6 @@ static int target_restore_sigframe(CPUARMState *env, struct target_sve_context *sve = NULL; uint64_t extra_datap = 0; bool used_extra = false; - bool err = false; int vq = 0, sve_size = 0; target_restore_general_frame(env, sf); @@ -301,8 +300,7 @@ static int target_restore_sigframe(CPUARMState *env, switch (magic) { case 0: if (size != 0) { - err = true; - goto exit; + goto err; } if (used_extra) { ctx = NULL; @@ -314,8 +312,7 @@ static int target_restore_sigframe(CPUARMState *env, case TARGET_FPSIMD_MAGIC: if (fpsimd || size != sizeof(struct target_fpsimd_context)) { - err = true; - goto exit; + goto err; } fpsimd = (struct target_fpsimd_context *)ctx; break; @@ -329,13 +326,11 @@ static int target_restore_sigframe(CPUARMState *env, break; } } - err = true; - goto exit; + goto err; case TARGET_EXTRA_MAGIC: if (extra || size != sizeof(struct target_extra_context)) { - err = true; - goto exit; + goto err; } __get_user(extra_datap, &((struct target_extra_context *)ctx)->datap); @@ -348,8 +343,7 @@ static int target_restore_sigframe(CPUARMState *env, /* Unknown record -- we certainly didn't generate it. * Did we in fact get out of sync? */ - err = true; - goto exit; + goto err; } ctx = (void *)ctx + size; } @@ -358,17 +352,19 @@ static int target_restore_sigframe(CPUARMState *env, if (fpsimd) { target_restore_fpsimd_record(env, fpsimd); } else { - err = true; + goto err; } /* SVE data, if present, overwrites FPSIMD data. */ if (sve) { target_restore_sve_record(env, sve, vq); } - - exit: unlock_user(extra, extra_datap, 0); - return err; + return 0; + + err: + unlock_user(extra, extra_datap, 0); + return 1; } static abi_ulong get_sigframe(struct target_sigaction *ka, From patchwork Fri Jul 8 15:15:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588551 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp782895mab; Fri, 8 Jul 2022 08:53:51 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vkLp+AHBmdZG/BwxPXh6cliEziBXcO2PWSFWT3mge7+S5HKgQIddTkmDzAV55cLOLx1OiC X-Received: by 2002:ac8:7d0c:0:b0:31e:a990:e4c9 with SMTP id g12-20020ac87d0c000000b0031ea990e4c9mr884076qtb.525.1657295630989; Fri, 08 Jul 2022 08:53:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657295630; cv=none; d=google.com; s=arc-20160816; b=qtvNcMGlAcPfR2W31VASukS3uiwTShciLkYuO8JtISdc2GPhceemtziaFcI3KGn5+m L7uZmqp4yWzs4Jh/wasP19kaT+bVeMKmHnAvdkxAIzL977DjQ+KYx/P9MFR7w4B0jXL2 FxDIe9BEFKwt1/OAEFnuRE5hR+x4IFD+5HKIBpfJZtZfg5XuBFZ6RzsJhmO9uavxOiRY We6akeZ+MyrcKjJHIClj/FbNz2/uj85+CRjswhUfwUJ58is+OFSTF2e+4LV9kW0M4lyW TH0ZqQjuayv6ecO0/x+omDYshP2W+5byNzQwQH1ADBDpSmk9mNJ4OS1iSQfezNCwrFz7 iWqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=f5ee/kpTJRv70/KN+irqbHOKZ1TmVta3xQPxo1FwOpU=; b=EoEeKgGXBdlg8Xyqqpzt9rGaZnskqDO25rJv9EhbIOzy2rH7lJ+YArGSJ74w2rO/RK pjK7b3TLX8EOfO9ZsyWEjRXRguQV78waW8He24kHuw+3poA4mJjWy0hHYUqQZQD3dxS4 tx2rXpm2ZQ29f27l+IbJjhgyuv9VDRSisoGjodEZ9CEUfop+FTMKU3TI6Yxb9QWUCWDh rQ4h4H2EkVFgP9PP7y1sX5YVUCkObb0wkju3nz9trTNsf01tUO4sY1+bmhmeUESQCBAI YNJ5cKvxzE8I+oQZbDdRjaOrNETHgnZ7/rnRym9Qxjq3ahVPFTfm5vNp48XAwFInt/ov aIjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="m8lc/pwb"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 37/45] linux-user/aarch64: Do not allow duplicate or short sve records Date: Fri, 8 Jul 2022 20:45:32 +0530 Message-Id: <20220708151540.18136-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In parse_user_sigframe, the kernel rejects duplicate sve records, or records that are smaller than the header. We were silently allowing these cases to pass, dropping the record. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 8b352abb97..8fbe98d72f 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -318,10 +318,13 @@ static int target_restore_sigframe(CPUARMState *env, break; case TARGET_SVE_MAGIC: + if (sve || size < sizeof(struct target_sve_context)) { + goto err; + } if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { vq = sve_vq(env); sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); - if (!sve && size == sve_size) { + if (size == sve_size) { sve = (struct target_sve_context *)ctx; break; } From patchwork Fri Jul 8 15:15:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588538 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp772954mab; Fri, 8 Jul 2022 08:41:41 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vFrIHASI/oDs6yfJXKS5jimB6zJQgle3Xpsvj7DlrwUvzaVlNmg+U3yKppuzKff9so8Dxx X-Received: by 2002:a05:6214:621:b0:432:5e0d:cb64 with SMTP id a1-20020a056214062100b004325e0dcb64mr3184041qvx.65.1657294901295; Fri, 08 Jul 2022 08:41:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657294901; cv=none; d=google.com; s=arc-20160816; b=lE1F1xOH1Eu0kmUBrK+5962aYvY0nm7EwlXIfifEU9G2hccOq8z2XiqhYF1fuFzPYu BBFhNgS2DAX9qWdJOslJO6x9Eno8tsrp3ex/Idgid+UWtWB4bK0BP2C0y/+oLtRmvI5G oP5sTS9pRjGR6zKz054JQslo+Bc3oWJoYQ2EgGv6pK4IQTmeTfSq3+i3pKV86eIWNbPH o+6dVg8O3sJM8ZsxWxcsRIv0esILV6ixoFoDdvw7NcGBeGv+fBWXUsXMkxJ/0+vlhX/i hIZR7h/HRznpR8D5AqY6xHzeiNb7/MkFu9oV7Jz/2DlX485O+4zRtw+aOc0Q4ZpL5KHr 3Ibg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7xmxavNGvmm3BzQ45g11tA0Bzd0iytuo9+dpLfOmZxs=; b=oAGKPYp3TzPcoLvNb1DpAwuqotC4fvTc5gBf+uyv0uAZz8qqBK+bFPOQoDEL8G622b 7ZTITd7ZTp09soEvtf9n8294tWmZjdSla7GyATzPP/JoR9qrKL+oC1bgElv9ATwUJrSC pDvPFz13dMOQufLpeXdmU9SUjAi1AY1XHcwAljgH2m/r6RxJMdRlDyBXVhwXzW9FanRq DG/kTzPKvHpy0QhPGTnJ0pwRVoGCOBlvu14h/pobs/QqzXEMmjSL+i1ZOaMHUI3z1k9N KqgQtdfXhkp3KF4E4UTaQvtqri5Pcvqik1GQ/Cba13Md1SD2mh/lYsdG/7iqNW4h+dSS Um/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x6TsdGOq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 38/45] linux-user/aarch64: Verify extra record lock succeeded Date: Fri, 8 Jul 2022 20:45:33 +0530 Message-Id: <20220708151540.18136-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 8fbe98d72f..9ff79da4be 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -340,6 +340,9 @@ static int target_restore_sigframe(CPUARMState *env, __get_user(extra_size, &((struct target_extra_context *)ctx)->size); extra = lock_user(VERIFY_READ, extra_datap, extra_size, 0); + if (!extra) { + return 1; + } break; default: From patchwork Fri Jul 8 15:15:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588543 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp775939mab; Fri, 8 Jul 2022 08:45:28 -0700 (PDT) X-Google-Smtp-Source: AGRyM1taTkc3Q+RrJcacrJM4+N6IpojaYIRLXNhfDiziE2Vt1kMITFhGmpMusBPqlFPdvI3WJ+Q9 X-Received: by 2002:a05:620a:258a:b0:6a7:9479:655e with SMTP id x10-20020a05620a258a00b006a79479655emr2616250qko.681.1657295128010; Fri, 08 Jul 2022 08:45:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657295128; cv=none; d=google.com; s=arc-20160816; b=CKtDGo5ZobDRe7n3D91uo7jDtuc9L9gPFMAW91c3qiXDkSHVbakLkCcasklDGlMfav MztSmf/ANwpM8tAMI8e2u2IG8bgxMUiJ/3kw4c2pdJPTXpwhEHW3yHzrgbeQUvSco4lY ManpWzo1SXEmOqethEdALw0gE8imMO2KF12WAu7OXJ/2WOD5DvZjNeTNaCy0FRmsohb1 +PYi+vjEADz9hOyF5SqiZMEcfN4MWSG2vzvK63/40gD2aHT5LNirF2ZbUIuWNDMkqjxM BGg7r7+xRHTKnvKZzxvR/5VAkZt7rJYJhA/FQdOY5xrDoYkKmAvf3WWKiDZDyT9yDvz+ +ldQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=suiCkAICShG42hE+LmFGlXABJkWbjcp+Qv1m7n85pMU=; b=MC5/0Zba0oufc8Bv/yYD7ELyRVxOjpQPZsFQtfOD/F1LyY0zveWCaUGOqOsLIzqjPB zlzm7NAmjaksMWvKKZn7BGHyfD17f/VAekwfndKWX2rVgUHZjzPj2aBLCFSnE5owtcCp qRolqkzOS8np5hXsIblfrMutszJeQYFIkUMy7gB1/lWP4ek8+GXZc3CShUiH54PYjSwQ OrStiNPJDcBkBJV0LIr/kpE+m8T+pmARS78NXNSCNdohAyASd9GKJ438Xuaohwl8wf74 j6e9qCSSPzE01+lmYBExQJlsn9Pu3/h2zTIahPtWGFc4fuOSVlc7W4FIbmq32R2L3DnN 3yPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=n4Mt5u75; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id n17-20020a056a0007d100b0051bada81bc7sm29085774pfu.161.2022.07.08.08.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:17:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 39/45] linux-user/aarch64: Move sve record checks into restore Date: Fri, 8 Jul 2022 20:45:34 +0530 Message-Id: <20220708151540.18136-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the checks out of the parsing loop and into the restore function. This more closely mirrors the code structure in the kernel, and is slightly clearer. Reject rather than silently skip incorrect VL and SVE record sizes, bringing our checks in to line with those the kernel does. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 51 +++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 16 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 9ff79da4be..22d0b8b4ec 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -250,12 +250,36 @@ static void target_restore_fpsimd_record(CPUARMState *env, } } -static void target_restore_sve_record(CPUARMState *env, - struct target_sve_context *sve, int vq) +static bool target_restore_sve_record(CPUARMState *env, + struct target_sve_context *sve, + int size) { - int i, j; + int i, j, vl, vq; - /* Note that SVE regs are stored as a byte stream, with each byte element + if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) { + return false; + } + + __get_user(vl, &sve->vl); + vq = sve_vq(env); + + /* Reject mismatched VL. */ + if (vl != vq * TARGET_SVE_VQ_BYTES) { + return false; + } + + /* Accept empty record -- used to clear PSTATE.SM. */ + if (size <= sizeof(*sve)) { + return true; + } + + /* Reject non-empty but incomplete record. */ + if (size < TARGET_SVE_SIG_CONTEXT_SIZE(vq)) { + return false; + } + + /* + * Note that SVE regs are stored as a byte stream, with each byte element * at a subsequent address. This corresponds to a little-endian load * of our 64-bit hunks. */ @@ -277,6 +301,7 @@ static void target_restore_sve_record(CPUARMState *env, } } } + return true; } static int target_restore_sigframe(CPUARMState *env, @@ -287,7 +312,7 @@ static int target_restore_sigframe(CPUARMState *env, struct target_sve_context *sve = NULL; uint64_t extra_datap = 0; bool used_extra = false; - int vq = 0, sve_size = 0; + int sve_size = 0; target_restore_general_frame(env, sf); @@ -321,15 +346,9 @@ static int target_restore_sigframe(CPUARMState *env, if (sve || size < sizeof(struct target_sve_context)) { goto err; } - if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq = sve_vq(env); - sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); - if (size == sve_size) { - sve = (struct target_sve_context *)ctx; - break; - } - } - goto err; + sve = (struct target_sve_context *)ctx; + sve_size = size; + break; case TARGET_EXTRA_MAGIC: if (extra || size != sizeof(struct target_extra_context)) { @@ -362,8 +381,8 @@ static int target_restore_sigframe(CPUARMState *env, } /* SVE data, if present, overwrites FPSIMD data. */ - if (sve) { - target_restore_sve_record(env, sve, vq); + if (sve && !target_restore_sve_record(env, sve, sve_size)) { + goto err; } unlock_user(extra, extra_datap, 0); return 0; From patchwork Fri Jul 8 15:15:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588550 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp781462mab; Fri, 8 Jul 2022 08:51:54 -0700 (PDT) X-Google-Smtp-Source: AGRyM1vAGCo1WmNhYKtPSmDTvdcpQfR9fM5f3Mo+Qhe9e5sezpKreVa57LHt5DHW7EvaGhYjbBdw X-Received: by 2002:ad4:5964:0:b0:473:17a:797d with SMTP id eq4-20020ad45964000000b00473017a797dmr3276479qvb.94.1657295514870; Fri, 08 Jul 2022 08:51:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657295514; cv=none; d=google.com; s=arc-20160816; b=mNrEAeg/900wFMQBcAxQ/s6Xpogvj35IwdRsm6k0cYErWtUNTRasNAxigVEsE62ruq I5dKYnG2TDJl5IeNFJLCqC30JhY5i5kATktq/3LkSnrMOu13txxPxQMNHlU5oCEi2AZ+ mr9nCHLe3drxxcqd/hmCjCrIzxvS3a/dH/zIjpzwFSo0FEE1IrHGqoVqs67bAlK2xg+1 drVzQFuU44/TjpPk3T+pR7K2rt2zEDp4l9jidoMiLt0pZHDGfs73JMkb/pQ1++6PE0vz QwwEOkCeDpgv/sEv90vv0fFkHgv+9ucBB60IiCHhoGBUgFo64KWWbIDs7/2hcLNso+1S 2PWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=eZwyJS+DI6VXP8TVU6OuO37fm60h5FhLdjsLlNVqKXk=; b=E774+NZnCc8jA3QDQ19Vsp//LXE5+9ZwYnfKw/3+vF9DUXQsD0KDao0ta7WYBfK9t2 2CSExSs7SDro88b+5/U2vPGyYse97oIl8bExICNLRWXVz/lWdi72DNfVLF5SaAfSw5vm gaLMrTKsNnR4u6kVrN2DLc7cGluwP8pzU5Sy3Dyo2BNvVvilxlUNzOdw1py4VEGKKJNb OpDio4DWNm2m2d7l+LzCK/ZCf6G0bXpY6C7AKu5Y3iBMk+v2qiAoJx8wxIPZB5tZjdo/ 48yNROmELhd80BDMGP66IrW8Y96pB64axogkOJc5lISrjP/tA+Y6OFDRwYtK45XRSoCN HABg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l0eUZFbw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id cp2-20020a170902e78200b0015e8d4eb1d7sm30067741plb.33.2022.07.08.08.20.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:20:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 40/45] linux-user/aarch64: Implement SME signal handling Date: Fri, 8 Jul 2022 20:45:35 +0530 Message-Id: <20220708151540.18136-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Set the SM bit in the SVE record on signal delivery, create the ZA record. Restore SM and ZA state according to the records present on return. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 167 +++++++++++++++++++++++++++++++++--- 1 file changed, 154 insertions(+), 13 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 22d0b8b4ec..6a2c6e06d2 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -104,6 +104,22 @@ struct target_sve_context { #define TARGET_SVE_SIG_FLAG_SM 1 +#define TARGET_ZA_MAGIC 0x54366345 + +struct target_za_context { + struct target_aarch64_ctx head; + uint16_t vl; + uint16_t reserved[3]; + /* The actual ZA data immediately follows. */ +}; + +#define TARGET_ZA_SIG_REGS_OFFSET \ + QEMU_ALIGN_UP(sizeof(struct target_za_context), TARGET_SVE_VQ_BYTES) +#define TARGET_ZA_SIG_ZAV_OFFSET(VQ, N) \ + (TARGET_ZA_SIG_REGS_OFFSET + (VQ) * TARGET_SVE_VQ_BYTES * (N)) +#define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \ + TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES) + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -176,9 +192,9 @@ static void target_setup_end_record(struct target_aarch64_ctx *end) } static void target_setup_sve_record(struct target_sve_context *sve, - CPUARMState *env, int vq, int size) + CPUARMState *env, int size) { - int i, j; + int i, j, vq = sve_vq(env); memset(sve, 0, sizeof(*sve)); __put_user(TARGET_SVE_MAGIC, &sve->head.magic); @@ -207,6 +223,35 @@ static void target_setup_sve_record(struct target_sve_context *sve, } } +static void target_setup_za_record(struct target_za_context *za, + CPUARMState *env, int size) +{ + int vq = sme_vq(env); + int vl = vq * TARGET_SVE_VQ_BYTES; + int i, j; + + memset(za, 0, sizeof(*za)); + __put_user(TARGET_ZA_MAGIC, &za->head.magic); + __put_user(size, &za->head.size); + __put_user(vl, &za->vl); + + if (size == TARGET_ZA_SIG_CONTEXT_SIZE(0)) { + return; + } + assert(size == TARGET_ZA_SIG_CONTEXT_SIZE(vq)); + + /* + * Note that ZA vectors are stored as a byte stream, + * with each byte element at a subsequent address. + */ + for (i = 0; i < vl; ++i) { + uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i); + for (j = 0; j < vq * 2; ++j) { + __put_user_e(env->zarray[i].d[j], z + j, le); + } + } +} + static void target_restore_general_frame(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -252,16 +297,28 @@ static void target_restore_fpsimd_record(CPUARMState *env, static bool target_restore_sve_record(CPUARMState *env, struct target_sve_context *sve, - int size) + int size, int *svcr) { - int i, j, vl, vq; + int i, j, vl, vq, flags; + bool sm; - if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) { + __get_user(vl, &sve->vl); + __get_user(flags, &sve->flags); + + sm = flags & TARGET_SVE_SIG_FLAG_SM; + + /* The cpu must support Streaming or Non-streaming SVE. */ + if (sm + ? !cpu_isar_feature(aa64_sme, env_archcpu(env)) + : !cpu_isar_feature(aa64_sve, env_archcpu(env))) { return false; } - __get_user(vl, &sve->vl); - vq = sve_vq(env); + /* + * Note that we cannot use sve_vq() because that depends on the + * current setting of PSTATE.SM, not the state to be restored. + */ + vq = sve_vqm1_for_el_sm(env, 0, sm) + 1; /* Reject mismatched VL. */ if (vl != vq * TARGET_SVE_VQ_BYTES) { @@ -278,6 +335,8 @@ static bool target_restore_sve_record(CPUARMState *env, return false; } + *svcr = FIELD_DP64(*svcr, SVCR, SM, sm); + /* * Note that SVE regs are stored as a byte stream, with each byte element * at a subsequent address. This corresponds to a little-endian load @@ -304,15 +363,57 @@ static bool target_restore_sve_record(CPUARMState *env, return true; } +static bool target_restore_za_record(CPUARMState *env, + struct target_za_context *za, + int size, int *svcr) +{ + int i, j, vl, vq; + + if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) { + return false; + } + + __get_user(vl, &za->vl); + vq = sme_vq(env); + + /* Reject mismatched VL. */ + if (vl != vq * TARGET_SVE_VQ_BYTES) { + return false; + } + + /* Accept empty record -- used to clear PSTATE.ZA. */ + if (size <= TARGET_ZA_SIG_CONTEXT_SIZE(0)) { + return true; + } + + /* Reject non-empty but incomplete record. */ + if (size < TARGET_ZA_SIG_CONTEXT_SIZE(vq)) { + return false; + } + + *svcr = FIELD_DP64(*svcr, SVCR, ZA, 1); + + for (i = 0; i < vl; ++i) { + uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i); + for (j = 0; j < vq * 2; ++j) { + __get_user_e(env->zarray[i].d[j], z + j, le); + } + } + return true; +} + static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { struct target_aarch64_ctx *ctx, *extra = NULL; struct target_fpsimd_context *fpsimd = NULL; struct target_sve_context *sve = NULL; + struct target_za_context *za = NULL; uint64_t extra_datap = 0; bool used_extra = false; int sve_size = 0; + int za_size = 0; + int svcr = 0; target_restore_general_frame(env, sf); @@ -350,6 +451,14 @@ static int target_restore_sigframe(CPUARMState *env, sve_size = size; break; + case TARGET_ZA_MAGIC: + if (za || size < sizeof(struct target_za_context)) { + goto err; + } + za = (struct target_za_context *)ctx; + za_size = size; + break; + case TARGET_EXTRA_MAGIC: if (extra || size != sizeof(struct target_extra_context)) { goto err; @@ -381,9 +490,16 @@ static int target_restore_sigframe(CPUARMState *env, } /* SVE data, if present, overwrites FPSIMD data. */ - if (sve && !target_restore_sve_record(env, sve, sve_size)) { + if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) { goto err; } + if (za && !target_restore_za_record(env, za, za_size, &svcr)) { + goto err; + } + if (env->svcr != svcr) { + env->svcr = svcr; + arm_rebuild_hflags(env); + } unlock_user(extra, extra_datap, 0); return 0; @@ -451,7 +567,8 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, .total_size = offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__reserved), }; - int fpsimd_ofs, fr_ofs, sve_ofs = 0, vq = 0, sve_size = 0; + int fpsimd_ofs, fr_ofs, sve_ofs = 0, za_ofs = 0; + int sve_size = 0, za_size = 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; abi_ulong frame_addr, return_addr; @@ -461,11 +578,20 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, &layout); /* SVE state needs saving only if it exists. */ - if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq = sve_vq(env); - sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); + if (cpu_isar_feature(aa64_sve, env_archcpu(env)) || + cpu_isar_feature(aa64_sme, env_archcpu(env))) { + sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(sve_vq(env)), 16); sve_ofs = alloc_sigframe_space(sve_size, &layout); } + if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { + /* ZA state needs saving only if it is enabled. */ + if (FIELD_EX64(env->svcr, SVCR, ZA)) { + za_size = TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(env)); + } else { + za_size = TARGET_ZA_SIG_CONTEXT_SIZE(0); + } + za_ofs = alloc_sigframe_space(za_size, &layout); + } if (layout.extra_ofs) { /* Reserve space for the extra end marker. The standard end marker @@ -512,7 +638,10 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, target_setup_end_record((void *)frame + layout.extra_end_ofs); } if (sve_ofs) { - target_setup_sve_record((void *)frame + sve_ofs, env, vq, sve_size); + target_setup_sve_record((void *)frame + sve_ofs, env, sve_size); + } + if (za_ofs) { + target_setup_za_record((void *)frame + za_ofs, env, za_size); } /* Set up the stack frame for unwinding. */ @@ -536,6 +665,18 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, env->btype = 2; } + /* + * Invoke the signal handler with both SM and ZA disabled. + * When clearing SM, ResetSVEState, per SMSTOP. + */ + if (FIELD_EX64(env->svcr, SVCR, SM)) { + arm_reset_sve_state(env); + } + if (env->svcr) { + env->svcr = 0; + arm_rebuild_hflags(env); + } + if (info) { tswap_siginfo(&frame->info, info); env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info); From patchwork Fri Jul 8 15:15:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588561 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp796648mab; Fri, 8 Jul 2022 09:08:42 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tK4geISLg7WnoJ+WE99svWD4ZffO8H0ecPgbtLiG1Qyaw8Y9EZyDagjgm4sUXLM6MZK6O4 X-Received: by 2002:a0c:9107:0:b0:472:fae1:e9fa with SMTP id q7-20020a0c9107000000b00472fae1e9famr3489483qvq.88.1657296522647; Fri, 08 Jul 2022 09:08:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657296522; cv=none; d=google.com; s=arc-20160816; b=vTALSx1IUQ9FVK4QbTXwwwdVQjYoRee5Md28V/VhJq3wHLZlCvUIn6q88xNxBYZtgD 3+sbYTYkK0pi3Wi6tBRlS6ARqxGel3X30X43zzrrviq+h1oWD3DeKRIiZqK58Rt5QfD4 bA02ka4hnCWmkPgDDaI9VfrIh1sHFVthpxpUv4LZm8azeKm7VVFLFX7/hI06m78swGqy ARKrKbjqcW9DfvrLN5DIY4pbi9fdaWloj8nJZ7RxReW17dWRSFy9RzTlwXsA2barCQLu kqNK4QAzrALS3yp7kXtdCQnmn8Hor8fmaOdLS78JpinZa9V5We2X/GRrrnA97V+yBtpw qQ9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=V2fLCOd7w5RVaZMEE/2yClzk5I5RfuvEjcRKKU0Ql6A=; b=FB2fY+587PGwOwFf53AjEABXxptivb457UF9U/ll/n0T5xbeBo9p6SkTbcDMNDwfms OhfN9xedUs2nvrunAtVN+zv/v0oqA+TjfRR3VMNx2eS6nigwzmdkQlbS2Chpz8sFcpWU spHJtBoZDX6TqQK/tKj5fWz0Yx+H4NIOadvLVaH4dckIYSe5kzhd0rTzWxw9B6OtX8tf b5M/K62nKtw8k9qinUlPV8cQBvz0aow44SasnIIzp7hkfMaijWy1gIHBkmuzN+Npjn/s t2ESZOBIXOSn4Ti+wWQ7+amyVrRdGvg9WI98fG+a3bgzZkIwf06aXTUncgGMwjmTChzh F27w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dytHw4yH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id cp2-20020a170902e78200b0015e8d4eb1d7sm30067741plb.33.2022.07.08.08.20.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:20:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 41/45] linux-user: Rename sve prctls Date: Fri, 8 Jul 2022 20:45:36 +0530 Message-Id: <20220708151540.18136-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add "sve" to the sve prctl functions, to distinguish them from the coming "sme" prctls with similar names. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 8 ++++---- linux-user/syscall.c | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h index 1d440ffbea..40481e6663 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -6,7 +6,7 @@ #ifndef AARCH64_TARGET_PRCTL_H #define AARCH64_TARGET_PRCTL_H -static abi_long do_prctl_get_vl(CPUArchState *env) +static abi_long do_prctl_sve_get_vl(CPUArchState *env) { ARMCPU *cpu = env_archcpu(env); if (cpu_isar_feature(aa64_sve, cpu)) { @@ -14,9 +14,9 @@ static abi_long do_prctl_get_vl(CPUArchState *env) } return -TARGET_EINVAL; } -#define do_prctl_get_vl do_prctl_get_vl +#define do_prctl_sve_get_vl do_prctl_sve_get_vl -static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) +static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2) { /* * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT. @@ -47,7 +47,7 @@ static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) } return -TARGET_EINVAL; } -#define do_prctl_set_vl do_prctl_set_vl +#define do_prctl_sve_set_vl do_prctl_sve_set_vl static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) { diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 669add74c1..cbde82c907 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6362,11 +6362,11 @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) #ifndef do_prctl_set_fp_mode #define do_prctl_set_fp_mode do_prctl_inval1 #endif -#ifndef do_prctl_get_vl -#define do_prctl_get_vl do_prctl_inval0 +#ifndef do_prctl_sve_get_vl +#define do_prctl_sve_get_vl do_prctl_inval0 #endif -#ifndef do_prctl_set_vl -#define do_prctl_set_vl do_prctl_inval1 +#ifndef do_prctl_sve_set_vl +#define do_prctl_sve_set_vl do_prctl_inval1 #endif #ifndef do_prctl_reset_keys #define do_prctl_reset_keys do_prctl_inval1 @@ -6431,9 +6431,9 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, case PR_SET_FP_MODE: return do_prctl_set_fp_mode(env, arg2); case PR_SVE_GET_VL: - return do_prctl_get_vl(env); + return do_prctl_sve_get_vl(env); case PR_SVE_SET_VL: - return do_prctl_set_vl(env, arg2); + return do_prctl_sve_set_vl(env, arg2); case PR_PAC_RESET_KEYS: if (arg3 || arg4 || arg5) { return -TARGET_EINVAL; From patchwork Fri Jul 8 15:15:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588534 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp767677mab; Fri, 8 Jul 2022 08:34:59 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tFaOz8idJR+J5uUqy4jC8xiQtpNk8C5ZNJIfF+iy2AKFz7feERY0BzmFS8ei5/4xA7KUUm X-Received: by 2002:a0c:9a99:0:b0:473:2958:2b19 with SMTP id y25-20020a0c9a99000000b0047329582b19mr3269922qvd.96.1657294499389; Fri, 08 Jul 2022 08:34:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657294499; cv=none; d=google.com; s=arc-20160816; b=fQZSIN52EejA9NC/prsVVQ2S3KSbRHsKZGuuzncuvj3ENsgt8ATj8t7K78qtxd0oiX FMPkAsO0xluqGfsNnUIdEMMpq3yvJ3JTh97ehkjAeexCcMF69EE5ObBB5xjlzufm08et LbgjgxeWlQj70HBVe7vkBhDshwtPrV/HzVw0Jpzwj6Zfe4RCt0lC/YQJ8MsOt3nyqFc8 YyTH9j7hqE/Dh3kaUrx4lJ5Xa3L8QH7HfWVBdHIPlBeUkKpvhmh20RG2wsXwyX3qbIxu g2Iv/jYfhH3v6HvzVFWS1Ej4al6I1lKVn3R1HBF8BLMhGgjdCsAVp2MLHQBujMukCqmC AOPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QT+j4xhm70EdfcVhkO7HkP89Z4Z0asvpHZ6p48VqoaU=; b=EUOBIoMVkMQJ5XkqzqGo4yYCFdu5mnXCAhHZIvgaGkTPp9Qv62f2f762YK6W697jXi sp4segIXnrECVvvo7Lz83Bo1hqps44t8XljFxhhVVdyTtwtIfqIIZAOODqbrFn0UccFD lup6zrpS85QYVAJjVNQa/HIvlTKmPKyQu/w0OL1B3h/JzqnnkvE1GlTfOVUpQPQ7X/h7 m1YTcrRdo/sH7F+dTQ1vBP7SnqF1Xs12oSYQkHKv9FdyCyaE9lBaZf87sJsxFHQwn0mG 65Yc6z1ezEAwkjB17Pw/0jv5an4KIfUVAx9Uj8/uzaFBeaFUVP6WuPkG2twvPFYAmddu xo9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ECNVhHBn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id cp2-20020a170902e78200b0015e8d4eb1d7sm30067741plb.33.2022.07.08.08.20.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:20:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 42/45] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL Date: Fri, 8 Jul 2022 20:45:37 +0530 Message-Id: <20220708151540.18136-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These prctl set the Streaming SVE vector length, which may be completely different from the Normal SVE vector length. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 54 +++++++++++++++++++++++++++++++ linux-user/syscall.c | 16 +++++++++ 2 files changed, 70 insertions(+) diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h index 40481e6663..907c314146 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -10,6 +10,7 @@ static abi_long do_prctl_sve_get_vl(CPUArchState *env) { ARMCPU *cpu = env_archcpu(env); if (cpu_isar_feature(aa64_sve, cpu)) { + /* PSTATE.SM is always unset on syscall entry. */ return sve_vq(env) * 16; } return -TARGET_EINVAL; @@ -27,6 +28,7 @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2) && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { uint32_t vq, old_vq; + /* PSTATE.SM is always unset on syscall entry. */ old_vq = sve_vq(env); /* @@ -49,6 +51,58 @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2) } #define do_prctl_sve_set_vl do_prctl_sve_set_vl +static abi_long do_prctl_sme_get_vl(CPUArchState *env) +{ + ARMCPU *cpu = env_archcpu(env); + if (cpu_isar_feature(aa64_sme, cpu)) { + return sme_vq(env) * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_sme_get_vl do_prctl_sme_get_vl + +static abi_long do_prctl_sme_set_vl(CPUArchState *env, abi_long arg2) +{ + /* + * We cannot support either PR_SME_SET_VL_ONEXEC or PR_SME_VL_INHERIT. + * Note the kernel definition of sve_vl_valid allows for VQ=512, + * i.e. VL=8192, even though the architectural maximum is VQ=16. + */ + if (cpu_isar_feature(aa64_sme, env_archcpu(env)) + && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { + int vq, old_vq; + + old_vq = sme_vq(env); + + /* + * Bound the value of vq, so that we know that it fits into + * the 4-bit field in SMCR_EL1. Because PSTATE.SM is cleared + * on syscall entry, we are not modifying the current SVE + * vector length. + */ + vq = MAX(arg2 / 16, 1); + vq = MIN(vq, 16); + env->vfp.smcr_el[1] = + FIELD_DP64(env->vfp.smcr_el[1], SMCR, LEN, vq - 1); + + /* Delay rebuilding hflags until we know if ZA must change. */ + vq = sve_vqm1_for_el_sm(env, 0, true) + 1; + + if (vq != old_vq) { + /* + * PSTATE.ZA state is cleared on any change to SVL. + * We need not call arm_rebuild_hflags because PSTATE.SM was + * cleared on syscall entry, so this hasn't changed VL. + */ + env->svcr = FIELD_DP64(env->svcr, SVCR, ZA, 0); + arm_rebuild_hflags(env); + } + return vq * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_sme_set_vl do_prctl_sme_set_vl + static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) { ARMCPU *cpu = env_archcpu(env); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index cbde82c907..991b85e6b4 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6343,6 +6343,12 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr) #ifndef PR_SET_SYSCALL_USER_DISPATCH # define PR_SET_SYSCALL_USER_DISPATCH 59 #endif +#ifndef PR_SME_SET_VL +# define PR_SME_SET_VL 63 +# define PR_SME_GET_VL 64 +# define PR_SME_VL_LEN_MASK 0xffff +# define PR_SME_VL_INHERIT (1 << 17) +#endif #include "target_prctl.h" @@ -6383,6 +6389,12 @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) #ifndef do_prctl_set_unalign #define do_prctl_set_unalign do_prctl_inval1 #endif +#ifndef do_prctl_sme_get_vl +#define do_prctl_sme_get_vl do_prctl_inval0 +#endif +#ifndef do_prctl_sme_set_vl +#define do_prctl_sme_set_vl do_prctl_inval1 +#endif static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5) @@ -6434,6 +6446,10 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, return do_prctl_sve_get_vl(env); case PR_SVE_SET_VL: return do_prctl_sve_set_vl(env, arg2); + case PR_SME_GET_VL: + return do_prctl_sme_get_vl(env); + case PR_SME_SET_VL: + return do_prctl_sme_set_vl(env, arg2); case PR_PAC_RESET_KEYS: if (arg3 || arg4 || arg5) { return -TARGET_EINVAL; From patchwork Fri Jul 8 15:15:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588557 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp789145mab; Fri, 8 Jul 2022 09:01:38 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uea7I9fAedJ4YqhcoMhF+2xvSFpKvN/kZmCP/qEhpViEdg0Jvk4XkCWl9azW7TOxxzpuSf X-Received: by 2002:a1f:294c:0:b0:374:834f:366b with SMTP id p73-20020a1f294c000000b00374834f366bmr430281vkp.21.1657296098317; Fri, 08 Jul 2022 09:01:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657296098; cv=none; d=google.com; s=arc-20160816; b=IXKrCmFHwYEZS1pzvc2tuXoMQ3UGjOR/EtHxSTGUdsCOAyfo7nRPJ2gRafe/4Z3H2c Tall+qq4D2ywdCjvr7zM76mHuEZWTbDnIAOcRdZvzvTyDx7YXsMmGMvBFQbDfJVwm4pe ZyVxxBh8iLuimksg7iqmiDLu2uCX0ixx73YwytYHGKX/CS5WOCv1B+L9Jr6G71KBxhEI hrBLJLVUzkZammdeaudsYras9yfhcHDTtJxGV9VMKzJ0QXVpwsfhUAal9AQMlximTwMi +nhZRPG05dmQT3SxDs8gser9zUr7rakgHHdosa4MZf7VnHjL6PYkM92ZLmMinboyxYdF GIow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=H9uf8O4CUiqyVcmvjic8DcvLpWT2fCMJa8CUUeRGTi0=; b=ePPtb2dy6jJzbWjGiG8yUtnLMOrDbvdIrPBB4uqJYJQo7pUQGEjJPCbEJnrHFZSLF8 AuAHT7K83bup7IiOLKhJFLTlBFNo3WVBuJLzPP3O9tnArEDyPAwuBIFK6rOXu2srVIzd abGDe9JqZTR7pR6GGNg9384YvLGp0Ip6VxxwmB2LEzFg0c0veM/fW78Cuj/zqKIPpl0D QGcRMGhKUN20ToMMgJfG6eY5z6fbLYTGw4ZBSQFAvtbHEf7nGl0qCg26sH8/6jKlG8Ts dZ6r0b0yY872Ghb9vVngnpLHCjcWHO464g6dyDIYECADt4Cnt47wFUfOwvhYD+tBVhy5 IYpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GB4PC84G; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id cp2-20020a170902e78200b0015e8d4eb1d7sm30067741plb.33.2022.07.08.08.20.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:20:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 43/45] target/arm: Only set ZEN in reset if SVE present Date: Fri, 8 Jul 2022 20:45:38 +0530 Message-Id: <20220708151540.18136-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There's no reason to set CPACR_EL1.ZEN if SVE disabled. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9c58be8b14..9b54443843 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -204,11 +204,10 @@ static void arm_cpu_reset(DeviceState *dev) /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, CPACR_EL1, FPEN, 3); - /* and to the SVE instructions */ - env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, - CPACR_EL1, ZEN, 3); - /* with reasonable vector length */ + /* and to the SVE instructions, with default vector length */ if (cpu_isar_feature(aa64_sve, cpu)) { + env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, ZEN, 3); env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; } /* From patchwork Fri Jul 8 15:15:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 588560 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:bb16:0:0:0:0 with SMTP id jd22csp793875mab; Fri, 8 Jul 2022 09:05:46 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uzbVz6dOeDir2z7DKGW5dsqo7VMXyiTQW9SztBF6BzFJyrvHeGtyZCEOdOsR9XJFECPwQI X-Received: by 2002:a05:622a:38a:b0:31e:a1ae:89f9 with SMTP id j10-20020a05622a038a00b0031ea1ae89f9mr3618690qtx.532.1657296346182; Fri, 08 Jul 2022 09:05:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657296346; cv=none; d=google.com; s=arc-20160816; b=PiTllf1W6kQ4b5DsEpi9smIL1fmXhROBNxZBs7+aWqhBYSO/HRKi617OC06X5MiNf5 847JUWPs7PG3jnWuUIa67OMEggeExz0ADPnWyTM/ph8v72ed5x0GhKNw49JNdG3Y38u6 ebj+SrOs1xnv6qdQt+5OxaWgWaV9yrvs5Ec2F5QvEgvbQ1iTr+wVHhnCMf/khJt1o1Wo X7iSbYPZ1+ztAgpzZ6sIYnwqcAtK2oJRYirW5yoEKqzllLKBsX51wvgPmc3UxioJSeWi jtNZPnku82wf4w+GlufMbitiioPfHvlVurntyE4CvX8wM+DormNn704J0uM/Bv5YeGVG Y2aA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ojyZOIf2uqXDhLYPW4II9jqD/RYb57Q1CkTjNakDECE=; b=zvSQprVD5w9PsB7ACPDUd76igggcrzq02u5Bd7glQdalTwvUzPnhNtuYjPTiTpmzAo UQnzq4OBBLuIIDcKPcoXtTPAhZmERIHJUx2i6VPQRO3ROLXqIziLHplfAVq7ceB3euWC G+jWbvKBTxdxFKBPBwzUDKbp2gt272tUv1+hmPe9Vl6LV62ixB2xkQgaEhwgfFGOHr0t +jc535rBfdldbFHlN+JuDbCwjQxfvrxFcu/EPiEPYYcKxtYtEwCPljCGtetjF4A55NLy 62iLdu2iunG5spxDIxWC/tZMLhl46hcb3Fn/ZIVOsFnRZwePEvkg+fQnR/btebtzvkWt QP5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ugm1HCxk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id cp2-20020a170902e78200b0015e8d4eb1d7sm30067741plb.33.2022.07.08.08.21.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:21:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 44/45] target/arm: Enable SME for user-only Date: Fri, 8 Jul 2022 20:45:39 +0530 Message-Id: <20220708151540.18136-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9b54443843..5de7e097e9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -210,6 +210,17 @@ static void arm_cpu_reset(DeviceState *dev) CPACR_EL1, ZEN, 3); env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; } + /* and for SME instructions, with default vector length, and TPIDR2 */ + if (cpu_isar_feature(aa64_sme, cpu)) { + env->cp15.sctlr_el[1] |= SCTLR_EnTP2; + env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, SMEN, 3); + env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; + if (cpu_isar_feature(aa64_sme_fa64, cpu)) { + env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], + SMCR, FA64, 1); + } + } /* * Enable 48-bit address space (TODO: take reserved_va into account). * Enable TBI0 but not TBI1. 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id cp2-20020a170902e78200b0015e8d4eb1d7sm30067741plb.33.2022.07.08.08.21.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 08:21:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 45/45] linux-user/aarch64: Add SME related hwcap entries Date: Fri, 8 Jul 2022 20:45:40 +0530 Message-Id: <20220708151540.18136-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220708151540.18136-1-richard.henderson@linaro.org> References: <20220708151540.18136-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/elfload.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 1de77c7959..ce902dbd56 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -605,6 +605,18 @@ enum { ARM_HWCAP2_A64_RNG = 1 << 16, ARM_HWCAP2_A64_BTI = 1 << 17, ARM_HWCAP2_A64_MTE = 1 << 18, + ARM_HWCAP2_A64_ECV = 1 << 19, + ARM_HWCAP2_A64_AFP = 1 << 20, + ARM_HWCAP2_A64_RPRES = 1 << 21, + ARM_HWCAP2_A64_MTE3 = 1 << 22, + ARM_HWCAP2_A64_SME = 1 << 23, + ARM_HWCAP2_A64_SME_I16I64 = 1 << 24, + ARM_HWCAP2_A64_SME_F64F64 = 1 << 25, + ARM_HWCAP2_A64_SME_I8I32 = 1 << 26, + ARM_HWCAP2_A64_SME_F16F32 = 1 << 27, + ARM_HWCAP2_A64_SME_B16F32 = 1 << 28, + ARM_HWCAP2_A64_SME_F32F32 = 1 << 29, + ARM_HWCAP2_A64_SME_FA64 = 1 << 30, }; #define ELF_HWCAP get_elf_hwcap() @@ -674,6 +686,14 @@ static uint32_t get_elf_hwcap2(void) GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG); GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI); GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE); + GET_FEATURE_ID(aa64_sme, (ARM_HWCAP2_A64_SME | + ARM_HWCAP2_A64_SME_F32F32 | + ARM_HWCAP2_A64_SME_B16F32 | + ARM_HWCAP2_A64_SME_F16F32 | + ARM_HWCAP2_A64_SME_I8I32)); + GET_FEATURE_ID(aa64_sme_f64f64, ARM_HWCAP2_A64_SME_F64F64); + GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64); + GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64); return hwcaps; }