From patchwork Thu Jul 7 13:24:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 588299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1113DC43334 for ; Thu, 7 Jul 2022 13:25:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235832AbiGGNZV (ORCPT ); Thu, 7 Jul 2022 09:25:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235860AbiGGNZK (ORCPT ); Thu, 7 Jul 2022 09:25:10 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 234CE31DEB; Thu, 7 Jul 2022 06:25:08 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id ABDD12222E; Thu, 7 Jul 2022 15:25:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1657200306; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=g0df1sTvycQkJsdAtaM7OC4dv6nK2I/GrDWXYw1cHHA=; b=LcylVWLk0BwLEFqQurrO71hN1dEXkvt/UZoImbS+g3lQWNkPL2tRhXpyjhTaCq+Rtt2ruS gNPXoCxV94axEgDjbX8l7c7JRo5atQoj0QxrTTjy6ECVfRezEshpHMkTE06UtuiXgEdwqF sCEHXddGOaFL8+41VSOYIJuFl868GxE= From: Michael Walle To: Rob Herring , Krzysztof Kozlowski , Claudiu Beznea , Nicolas Ferre , Alexandre Belloni Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Walle Subject: [PATCH v2 1/2] ARM: dts: lan966x: add clock gating register Date: Thu, 7 Jul 2022 15:24:59 +0200 Message-Id: <20220707132500.1708020-1-michael@walle.cc> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The clock controller supports an optional clock gating register. This is necessary to expose the USB device clock, for example. Add it. Signed-off-by: Michael Walle --- changes since v1: - none arch/arm/boot/dts/lan966x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 57cb67a180ec..bc102677ff91 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -65,7 +65,7 @@ clks: clock-controller@e00c00a8 { #clock-cells = <1>; clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; clock-names = "cpu", "ddr", "sys"; - reg = <0xe00c00a8 0x38>; + reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>; }; timer {