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Thu, 7 Jul 2022 21:03:10 +0000 From: Frank Li To: tglx@linutronix.de, maz@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kw@linux.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, jdmason@kudzu.us Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, kishon@ti.com, lorenzo.pieralisi@arm.com, ntb@lists.linux.dev Subject: [PATCH 1/3] irqchip: imx mu worked as msi controller Date: Thu, 7 Jul 2022 16:02:36 -0500 Message-Id: <20220707210238.917477-1-Frank.Li@nxp.com> X-Mailer: git-send-email 2.35.1 X-ClientProxiedBy: SJ0PR03CA0219.namprd03.prod.outlook.com (2603:10b6:a03:39f::14) To PAXPR04MB9186.eurprd04.prod.outlook.com (2603:10a6:102:232::18) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 988fb0de-400c-44d5-07ee-08da605c191a X-MS-TrafficTypeDiagnostic: DBBPR04MB7817:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This patch make mu worked as msi controller. So MU can do doorbell by using standard msi api. Signed-off-by: Frank Li --- drivers/irqchip/Kconfig | 7 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-imx-mu-msi.c | 490 +++++++++++++++++++++++++++++++ 3 files changed, 498 insertions(+) create mode 100644 drivers/irqchip/irq-imx-mu-msi.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 5e4e50122777d..4599471d880c0 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -470,6 +470,13 @@ config IMX_INTMUX help Support for the i.MX INTMUX interrupt multiplexer. +config IMX_MU_MSI + bool "i.MX MU work as MSI controller" + default y if ARCH_MXC + select IRQ_DOMAIN + help + MU work as MSI controller to do general doorbell + config LS1X_IRQ bool "Loongson-1 Interrupt Controller" depends on MACH_LOONGSON32 diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 5d8e21d3dc6d8..870423746c783 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -98,6 +98,7 @@ obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o +obj-$(CONFIG_IMX_MU_MSI) += irq-imx-mu-msi.o obj-$(CONFIG_MADERA_IRQ) += irq-madera.o obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o diff --git a/drivers/irqchip/irq-imx-mu-msi.c b/drivers/irqchip/irq-imx-mu-msi.c new file mode 100644 index 0000000000000..f7193a6c1245e --- /dev/null +++ b/drivers/irqchip/irq-imx-mu-msi.c @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * NXP MU worked as MSI controller + * + * Copyright (c) 2018 Pengutronix, Oleksij Rempel + * Copyright 2022 NXP + * Frank Li + * Peng Fan + * + * Based on drivers/mailbox/imx-mailbox.c + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define IMX_MU_CHANS 4 + +enum imx_mu_chan_type { + IMX_MU_TYPE_TX, /* Tx */ + IMX_MU_TYPE_RX, /* Rx */ + IMX_MU_TYPE_TXDB, /* Tx doorbell */ + IMX_MU_TYPE_RXDB, /* Rx doorbell */ +}; + +enum imx_mu_xcr { + IMX_MU_GIER, + IMX_MU_GCR, + IMX_MU_TCR, + IMX_MU_RCR, + IMX_MU_xCR_MAX, +}; + +enum imx_mu_xsr { + IMX_MU_SR, + IMX_MU_GSR, + IMX_MU_TSR, + IMX_MU_RSR, +}; + +enum imx_mu_type { + IMX_MU_V1, + IMX_MU_V2, + IMX_MU_V2_S4 = BIT(15), +}; + +/* Receive Interrupt Enable */ +#define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) +#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) + +struct imx_mu_dcfg { + enum imx_mu_type type; + u32 xTR; /* Transmit Register0 */ + u32 xRR; /* Receive Register0 */ + u32 xSR[4]; /* Status Registers */ + u32 xCR[4]; /* Control Registers */ +}; + +struct imx_mu_msi { + spinlock_t lock; + struct platform_device *pdev; + struct irq_domain *parent; + struct irq_domain *msi_domain; + void __iomem *regs; + phys_addr_t msiir_addr; + struct imx_mu_dcfg *cfg; + u32 msir_num; + struct imx_mu_msir *msir; + u32 irqs_num; + unsigned long used; + u32 gic_irq; + struct clk *clk; + struct device *pd_a; + struct device *pd_b; + struct device_link *pd_link_a; + struct device_link *pd_link_b; +}; + +static void imx_mu_write(struct imx_mu_msi *msi_data, u32 val, u32 offs) +{ + iowrite32(val, msi_data->regs + offs); +} + +static u32 imx_mu_read(struct imx_mu_msi *msi_data, u32 offs) +{ + return ioread32(msi_data->regs + offs); +} + +static u32 imx_mu_xcr_rmw(struct imx_mu_msi *msi_data, enum imx_mu_xcr type, u32 set, u32 clr) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&msi_data->lock, flags); + val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]); + val &= ~clr; + val |= set; + imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]); + spin_unlock_irqrestore(&msi_data->lock, flags); + + return val; +} + +static void imx_mu_msi_mask_irq(struct irq_data *data) +{ + struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data->parent_data); + + pci_msi_mask_irq(data); + imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(msi_data->cfg->type, data->hwirq)); +} + +static void imx_mu_msi_unmask_irq(struct irq_data *data) +{ + struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data->parent_data); + + pci_msi_unmask_irq(data); + imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, IMX_MU_xCR_RIEn(msi_data->cfg->type, data->hwirq), 0); +} + +static struct irq_chip imx_mu_msi_irq_chip = { + .name = "MU-MSI", + .irq_mask = imx_mu_msi_mask_irq, + .irq_unmask = imx_mu_msi_unmask_irq, +}; + +static struct msi_domain_ops its_pmsi_ops = { +}; + +static struct msi_domain_info imx_mu_msi_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | + MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSIX), + .ops = &its_pmsi_ops, + .chip = &imx_mu_msi_irq_chip, +}; + +static void imx_mu_msi_compose_msg(struct irq_data *data, struct msi_msg *msg) +{ + struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); + + msg->address_hi = upper_32_bits(msi_data->msiir_addr); + msg->address_lo = lower_32_bits(msi_data->msiir_addr + 4 * data->hwirq); + msg->data = data->hwirq; + + iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg); +} + +static int imx_mu_msi_set_affinity(struct irq_data *irq_data, + const struct cpumask *mask, bool force) + +{ + return IRQ_SET_MASK_OK; +} + +static struct irq_chip imx_mu_msi_parent_chip = { + .name = "MU", + .irq_compose_msi_msg = imx_mu_msi_compose_msg, + .irq_set_affinity = imx_mu_msi_set_affinity, +}; + +static int imx_mu_msi_domain_irq_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, + void *args) +{ + struct imx_mu_msi *msi_data = domain->host_data; + msi_alloc_info_t *info = args; + int pos, err = 0; + + pm_runtime_get_sync(&msi_data->pdev->dev); + + WARN_ON(nr_irqs != 1); + + spin_lock(&msi_data->lock); + pos = find_first_zero_bit(&msi_data->used, msi_data->irqs_num); + if (pos < msi_data->irqs_num) + __set_bit(pos, &msi_data->used); + else + err = -ENOSPC; + spin_unlock(&msi_data->lock); + + if (err) + return err; + + err = iommu_dma_prepare_msi(info->desc, msi_data->msiir_addr + pos * 4); + if (err) + return err; + + irq_domain_set_info(domain, virq, pos, + &imx_mu_msi_parent_chip, msi_data, + handle_simple_irq, NULL, NULL); + return 0; +} + +static void imx_mu_msi_domain_irq_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(d); + int pos; + + pos = d->hwirq; + if (pos < 0 || pos >= msi_data->irqs_num) { + pr_err("failed to teardown msi. Invalid hwirq %d\n", pos); + return; + } + + spin_lock(&msi_data->lock); + __clear_bit(pos, &msi_data->used); + spin_unlock(&msi_data->lock); + + pm_runtime_put(&msi_data->pdev->dev); +} + +static const struct irq_domain_ops imx_mu_msi_domain_ops = { + .alloc = imx_mu_msi_domain_irq_alloc, + .free = imx_mu_msi_domain_irq_free, +}; + +static void imx_mu_msi_irq_handler(struct irq_desc *desc) +{ + struct imx_mu_msi *msi_data = irq_desc_get_handler_data(desc); + u32 status; + int i; + + status = imx_mu_read(msi_data, msi_data->cfg->xSR[IMX_MU_RSR]); + + chained_irq_enter(irq_desc_get_chip(desc), desc); + for (i = 0; i < IMX_MU_CHANS; i++) { + if (status & IMX_MU_xSR_RFn(msi_data->cfg->type, i)) { + imx_mu_read(msi_data, msi_data->cfg->xRR + i * 4); + generic_handle_domain_irq(msi_data->parent, i); + } + } + chained_irq_exit(irq_desc_get_chip(desc), desc); +} + +static int imx_mu_msi_domains_init(struct imx_mu_msi *msi_data) +{ + /* Initialize MSI domain parent */ + msi_data->parent = irq_domain_add_linear(NULL, + msi_data->irqs_num, + &imx_mu_msi_domain_ops, + msi_data); + if (!msi_data->parent) { + dev_err(&msi_data->pdev->dev, "failed to create IRQ domain\n"); + return -ENOMEM; + } + + msi_data->msi_domain = platform_msi_create_irq_domain( + of_node_to_fwnode(msi_data->pdev->dev.of_node), + &imx_mu_msi_domain_info, + msi_data->parent); + + if (!msi_data->msi_domain) { + dev_err(&msi_data->pdev->dev, "failed to create MSI domain\n"); + irq_domain_remove(msi_data->parent); + return -ENOMEM; + } + + return 0; +} + +static int imx_mu_msi_teardown_hwirq(struct imx_mu_msi *msi_data) +{ + if (msi_data->gic_irq > 0) + irq_set_chained_handler_and_data(msi_data->gic_irq, NULL, NULL); + + return 0; +} + +static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { + .xTR = 0x0, + .xRR = 0x10, + .xSR = {0x20, 0x20, 0x20, 0x20}, + .xCR = {0x24, 0x24, 0x24, 0x24}, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { + .xTR = 0x20, + .xRR = 0x40, + .xSR = {0x60, 0x60, 0x60, 0x60}, + .xCR = {0x64, 0x64, 0x64, 0x64}, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { + .type = IMX_MU_V2, + .xTR = 0x200, + .xRR = 0x280, + .xSR = {0xC, 0x118, 0x124, 0x12C}, + .xCR = {0x110, 0x114, 0x120, 0x128}, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = { + .type = IMX_MU_V2 | IMX_MU_V2_S4, + .xTR = 0x200, + .xRR = 0x280, + .xSR = {0xC, 0x118, 0x124, 0x12C}, + .xCR = {0x110, 0x114, 0x120, 0x128}, +}; + +static const struct of_device_id imx_mu_msi_ids[] = { + { .compatible = "fsl,imx7ulp-mu-msi", .data = &imx_mu_cfg_imx7ulp }, + { .compatible = "fsl,imx6sx-mu-msi", .data = &imx_mu_cfg_imx6sx }, + { .compatible = "fsl,imx8ulp-mu-msi", .data = &imx_mu_cfg_imx8ulp }, + { .compatible = "fsl,imx8ulp-mu-msi-s4", .data = &imx_mu_cfg_imx8ulp_s4 }, + { }, +}; + +MODULE_DEVICE_TABLE(of, imx_mu_msi_ids); + +static int imx_mu_msi_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + struct imx_mu_msi *msi_data, *priv; + struct device *dev = &pdev->dev; + struct resource *res; + int ret; + + match = of_match_device(imx_mu_msi_ids, &pdev->dev); + if (!match) + return -ENODEV; + + priv = msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL); + if (!msi_data) + return -ENOMEM; + + msi_data->cfg = (struct imx_mu_dcfg *) match->data; + + msi_data->regs = devm_platform_ioremap_resource_byname(pdev, "a"); + if (IS_ERR(msi_data->regs)) { + dev_err(&pdev->dev, "failed to initialize 'regs'\n"); + return PTR_ERR(msi_data->regs); + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "b"); + if (!res) + return -EIO; + + msi_data->msiir_addr = res->start + msi_data->cfg->xTR; + + msi_data->pdev = pdev; + msi_data->irqs_num = IMX_MU_CHANS; + + msi_data->gic_irq = platform_get_irq(msi_data->pdev, 0); + if (msi_data->gic_irq <= 0) + return -ENODEV; + + platform_set_drvdata(pdev, msi_data); + + msi_data->clk = devm_clk_get(dev, NULL); + if (IS_ERR(msi_data->clk)) { + if (PTR_ERR(msi_data->clk) != -ENOENT) + return PTR_ERR(msi_data->clk); + + msi_data->clk = NULL; + } + + ret = clk_prepare_enable(msi_data->clk); + if (ret) { + dev_err(dev, "Failed to enable clock\n"); + return ret; + } + + priv->pd_a = dev_pm_domain_attach_by_name(dev, "a"); + if (IS_ERR(priv->pd_a)) + return PTR_ERR(priv->pd_a); + + priv->pd_link_a = device_link_add(dev, priv->pd_a, + DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + + if (!priv->pd_link_a) { + dev_err(dev, "Failed to add device_link to mu a.\n"); + return -EINVAL; + } + + priv->pd_b = dev_pm_domain_attach_by_name(dev, "b"); + if (IS_ERR(priv->pd_b)) + return PTR_ERR(priv->pd_b); + + priv->pd_link_b = device_link_add(dev, priv->pd_b, + DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + + if (!priv->pd_link_b) { + dev_err(dev, "Failed to add device_link to mu a.\n"); + return -EINVAL; + } + + ret = imx_mu_msi_domains_init(msi_data); + if (ret) + return ret; + + irq_set_chained_handler_and_data(msi_data->gic_irq, + imx_mu_msi_irq_handler, + msi_data); + + pm_runtime_enable(dev); + + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put_noidle(dev); + goto disable_runtime_pm; + } + + ret = pm_runtime_put_sync(dev); + if (ret < 0) + goto disable_runtime_pm; + + clk_disable_unprepare(msi_data->clk); + + return 0; + +disable_runtime_pm: + pm_runtime_disable(dev); + clk_disable_unprepare(msi_data->clk); + + return ret; +} + +static int __maybe_unused imx_mu_runtime_suspend(struct device *dev) +{ + struct imx_mu_msi *priv = dev_get_drvdata(dev); + + clk_disable_unprepare(priv->clk); + + return 0; +} + +static int __maybe_unused imx_mu_runtime_resume(struct device *dev) +{ + struct imx_mu_msi *priv = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(priv->clk); + if (ret) + dev_err(dev, "failed to enable clock\n"); + + return ret; +} + +static const struct dev_pm_ops imx_mu_pm_ops = { + SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend, + imx_mu_runtime_resume, NULL) +}; + +static int imx_mu_msi_remove(struct platform_device *pdev) +{ + struct imx_mu_msi *msi_data = platform_get_drvdata(pdev); + + imx_mu_msi_teardown_hwirq(msi_data); + + irq_domain_remove(msi_data->msi_domain); + irq_domain_remove(msi_data->parent); + + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_driver imx_mu_msi_driver = { + .driver = { + .name = "imx-mu-msi", + .of_match_table = imx_mu_msi_ids, + .pm = &imx_mu_pm_ops, + }, + .probe = imx_mu_msi_probe, + .remove = imx_mu_msi_remove, +}; + +module_platform_driver(imx_mu_msi_driver); + +MODULE_AUTHOR("Frank Li "); +MODULE_DESCRIPTION("Freescale Layerscape SCFG MSI controller driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Jul 7 21:02:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 588725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00BEFCCA482 for ; Thu, 7 Jul 2022 21:03:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236681AbiGGVDS (ORCPT ); Thu, 7 Jul 2022 17:03:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236312AbiGGVDR (ORCPT ); Thu, 7 Jul 2022 17:03:17 -0400 Received: from EUR01-HE1-obe.outbound.protection.outlook.com (mail-eopbgr130071.outbound.protection.outlook.com [40.107.13.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E051F205E7; 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Thu, 7 Jul 2022 21:03:15 +0000 From: Frank Li To: tglx@linutronix.de, maz@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kw@linux.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, jdmason@kudzu.us Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, kishon@ti.com, lorenzo.pieralisi@arm.com, ntb@lists.linux.dev Subject: [PATCH 2/3] dt-bindings: irqchip: imx mu work as msi controller Date: Thu, 7 Jul 2022 16:02:37 -0500 Message-Id: <20220707210238.917477-2-Frank.Li@nxp.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220707210238.917477-1-Frank.Li@nxp.com> References: <20220707210238.917477-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0219.namprd03.prod.outlook.com (2603:10b6:a03:39f::14) To PAXPR04MB9186.eurprd04.prod.outlook.com (2603:10a6:102:232::18) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4907db8c-5e64-45d1-19bf-08da605c1c1a X-MS-TrafficTypeDiagnostic: DBBPR04MB7817:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Frank Li --- .../interrupt-controller/fsl,mu-msi.yaml | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml new file mode 100644 index 0000000000000..b4ac583f60227 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX Messaging Unit (MU) + +maintainers: + - Frank Li + +description: | + The Messaging Unit module enables two processors within the SoC to + communicate and coordinate by passing messages (e.g. data, status + and control) through the MU interface. The MU also provides the ability + for one processor to signal the other processor using interrupts. + + Because the MU manages the messaging between processors, the MU uses + different clocks (from each side of the different peripheral buses). + Therefore, the MU must synchronize the accesses from one side to the + other. The MU accomplishes synchronization using two sets of matching + registers (Processor A-facing, Processor B-facing). + + MU can work as msi interrupt controller to do doorbell + +properties: + compatible: + oneOf: + - const: fsl,imx6sx-mu-msi + - const: fsl,imx7ulp-mu-msi + - const: fsl,imx8ulp-mu-msi + - const: fsl,imx8-mu-msi + - const: fsl,imx8ulp-mu-msi-s4 + - items: + - const: fsl,imx8ulp-mu-msi + - items: + - enum: + - fsl,imx7s-mu-msi + - fsl,imx8mq-mu-msi + - fsl,imx8mm-mu-msi + - fsl,imx8mn-mu-msi + - fsl,imx8mp-mu-msi + - fsl,imx8qm-mu-msi + - fsl,imx8qxp-mu-msi + - const: fsl,imx6sx-mu-msi + - description: MU work as msi controller + items: + - enum: + - fsl,imx8qm-mu-msi + - fsl,imx8qxp-mu-msi + - const: fsl,imx6sx-mu-msi + reg: + maxItems: 2 + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - const: tx + - const: rx + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - msi-controller + +additionalProperties: false + +examples: + - | + #include + + lsio_mu12: msi@5d270000 { + compatible = "fsl,imx6sx-mu-msi-db"; + msi-controller; + interrupt-controller; + reg = <0x5d270000 0x10000>, /* A side */ + <0x5d300000 0x10000>; /* B side */ + reg-names = "a", "b"; + interrupts = ; + power-domains = <&pd IMX_SC_R_MU_12A>, + <&pd IMX_SC_R_MU_12B>; + power-domain-names = "a", "b"; + }; From patchwork Thu Jul 7 21:02:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 588254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF600C433EF for ; Thu, 7 Jul 2022 21:03:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236312AbiGGVD1 (ORCPT ); Thu, 7 Jul 2022 17:03:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235829AbiGGVDZ (ORCPT ); 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Received: from PAXPR04MB9186.eurprd04.prod.outlook.com (2603:10a6:102:232::18) by DBBPR04MB7817.eurprd04.prod.outlook.com (2603:10a6:10:1ef::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5417.16; Thu, 7 Jul 2022 21:03:20 +0000 Received: from PAXPR04MB9186.eurprd04.prod.outlook.com ([fe80::e945:8bde:54e5:d83e]) by PAXPR04MB9186.eurprd04.prod.outlook.com ([fe80::e945:8bde:54e5:d83e%6]) with mapi id 15.20.5395.020; Thu, 7 Jul 2022 21:03:20 +0000 From: Frank Li To: tglx@linutronix.de, maz@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kw@linux.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, jdmason@kudzu.us Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, kishon@ti.com, lorenzo.pieralisi@arm.com, ntb@lists.linux.dev Subject: [PATCH 3/3] pcie: endpoint: pci-epf-vntb: add endpoint msi support Date: Thu, 7 Jul 2022 16:02:38 -0500 Message-Id: <20220707210238.917477-3-Frank.Li@nxp.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220707210238.917477-1-Frank.Li@nxp.com> References: <20220707210238.917477-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0219.namprd03.prod.outlook.com (2603:10b6:a03:39f::14) To PAXPR04MB9186.eurprd04.prod.outlook.com (2603:10a6:102:232::18) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8568611b-241c-4f05-9178-08da605c1f1c X-MS-TrafficTypeDiagnostic: DBBPR04MB7817:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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PTR:; CAT:NONE; SFS:(13230016)(4636009)(346002)(396003)(136003)(376002)(366004)(39860400002)(38100700002)(6512007)(38350700002)(186003)(66946007)(66476007)(66556008)(4326008)(8676002)(5660300002)(316002)(921005)(83380400001)(36756003)(2906002)(2616005)(6486002)(8936002)(478600001)(41300700001)(6506007)(86362001)(6666004)(52116002)(26005)(1076003)(7416002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jtgjzYc/+AUbVG1vPFzZEINklPJ8ThK+QHtI+ok6jt137AyEckPUysMqEWQyw5MNFrOa7Z/DEhQ74XdjBH/ZEPSKJ9S3OoWWET4YXYn5+uwelRSiAYM0oPr4oxzluQcT0R746dQFez/doo8iInx97VPrL2Ht0D2TWkwtB1dkwAslUHQ2xY8Jsu76JGe/2Doh2R38OcmTrw7DFRi1FXJCJpHRlzSP+BXtxdWDrpWc3H7duY+VxE31be6pJgKvLva+FD/MXrh2ftY3+bSJQUtB2JAFWDk+/S3UxNHLGpVOs0tNOxclHJwd0HT9qPg8/LdV50jjV1UQb8zBQV6MmKjY2uhNVot899u2CD5JJHQWNGSmxfvFV8MlgYNGf72YgORV29/095+XXIS3xW8Z0JiZTbk5lbpQJVauZewbQiaIHJN3ZJZN5JOgW8OVxHlnZRb/mt4bN7OzS+yUGGXok+vY/hc0bPG6XQYhy7+dWb+i0D5qmWZgZIuIOBoOxUmgsP0bQ3DgAOUErZ52iUE3xQz9UHUtFMbHKTzrVWA8mZUaxUz43ysTovbRYEofZpgSZTmLXfLLYjDcxGPLUNA11HkAwbMOZET4/oajShX0DvnbROCGp44jiGyub1kGmpEewKE3poOzTrlW32x+E83mTnR0p5y+ThY2ySn8tJrwJ8ZEAoesXKvhfmhdy+u9vF1zf+K1LrlEgMynBtpU0CrXV1ijARcneh8oAZAlOZeIHpvkSCZPjpcvdFDeItOLUBDibZERn8T/JvmkEI+6I+5JEyfckPss//is5dwVSq+L7I0HaDulbZg9SXKQTA5qYrDcUM8lzDfIXgCNtqKloyNgRN9W4ObvVo+TPTcnYwMZCpZldfvRKOOoOhSCcUQTBzCpiaffkhMPH9M6vWHniE858a/6bYCCdscvJEaUoNVeD+2lZy8vMsM7hyPJS8eP4JS7ln/1N2zTNFT6T+GSt3Y3idWggYWS3Ua/l/aipXyU4Rccbra8EnHDl7HMwX/H+PPUu97Dog2z1PDR38tl5DLo6tjQ2i+wl6VAgveemGy3pDfIj/bCu97SMw0R+9Uy8M/VgnuNjSymlS0MwIx9k4AdG0bfenvOLKlIQGLe97GcAPs6uhthWxe3dpc1eaoF/DMsNO63TXSqwooG6BzwOsne+mZHsq9+8wodr6kvk3L70ePkbENlq2qDLvpzohT7KK/VSJNkkR5LfcSr1zFmIEtDQBsDnsD6oHL6vMI25S7ZC0/BfIX91CLlKBAKSVhgt5GzTyXXbm0Mtv5FoeoPir+QX6hCKAPg1LIBaWdO0dBCKEbyaDEoq1npGqHNOjeTsmGubtJOgQvAHmj2/zInHx4iLFLEtqkLo9hmcXaDS6A6YRNvVZ7Nnv/xPL88cmpmY5TQGhK8ATsbufzL2f9tvoImabw216jEHQqXlHN1wOK8BcvgHvi1GLRXbyfz4Ddt6EP+Snhi1xP5aXb5oXUNOJhiryoOBcq/RIidc9/MPkJfskbQqk6dAVH2fjg9UAKBELzCm7dBVgyz1W/80wAzHODzcoeRT1RRl0FFsqQWLs/Yq3AP/WZT5Ki2xlxoJCbsts1puog2 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8568611b-241c-4f05-9178-08da605c1f1c X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9186.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jul 2022 21:03:20.5007 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: bWRf25z7w10b1u3vXa4M6yYg7ekdkdl9+2eQpFfBniB7scLdxUAQsbE2KwehC/nu7TSxXV7SeSPbd33/q+kklw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB7817 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch add msi support for ntb endpoint(EP) side. EP side driver query if system have msi controller. Setup doorbell address according to struct msi_msg. So PCIe host can write this doorbell address to EP side's irq. If no msi controller exist, failback software polling. Signed-off-by: Frank Li --- pci-epf-vntb.c is on ntb next branch git://github.com/jonmason/ntb.git drivers/pci/endpoint/functions/pci-epf-vntb.c | 134 +++++++++++++++--- 1 file changed, 112 insertions(+), 22 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c index 1466dd1904175..dcaebcda4d7ad 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -44,6 +44,7 @@ #include #include #include +#include static struct workqueue_struct *kpcintb_workqueue; @@ -143,6 +144,8 @@ struct epf_ntb { void __iomem *vpci_mw_addr[MAX_MW]; struct delayed_work cmd_handler; + + int msi_virqbase; }; #define to_epf_ntb(epf_group) container_of((epf_group), struct epf_ntb, group) @@ -253,7 +256,7 @@ static void epf_ntb_cmd_handler(struct work_struct *work) ntb = container_of(work, struct epf_ntb, cmd_handler.work); - for (i = 1; i < ntb->db_count; i++) { + for (i = 1; i < ntb->db_count && !ntb->epf_db_phy; i++) { if (readl(ntb->epf_db + i * 4)) { if (readl(ntb->epf_db + i * 4)) ntb->db |= 1 << (i - 1); @@ -454,11 +457,9 @@ static int epf_ntb_config_spad_bar_alloc(struct epf_ntb *ntb) ctrl->num_mws = ntb->num_mws; ntb->spad_size = spad_size; - ctrl->db_entry_size = 4; - for (i = 0; i < ntb->db_count; i++) { ntb->reg->db_data[i] = 1 + i; - ntb->reg->db_offset[i] = 0; + ntb->reg->db_offset[i] = 4 * i; } return 0; @@ -509,6 +510,28 @@ static int epf_ntb_configure_interrupt(struct epf_ntb *ntb) return 0; } +static int epf_ntb_db_size(struct epf_ntb *ntb) +{ + const struct pci_epc_features *epc_features; + size_t size = 4 * ntb->db_count; + u32 align; + + epc_features = pci_epc_get_features(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no); + align = epc_features->align; + + if (size < 128) + size = 128; + + if (align) + size = ALIGN(size, align); + else + size = roundup_pow_of_two(size); + + return size; +} + /** * epf_ntb_db_bar_init() - Configure Doorbell window BARs * @ntb: NTB device that facilitates communication between HOST and vHOST @@ -520,35 +543,33 @@ static int epf_ntb_db_bar_init(struct epf_ntb *ntb) struct device *dev = &ntb->epf->dev; int ret; struct pci_epf_bar *epf_bar; - void __iomem *mw_addr; + void __iomem *mw_addr = NULL; enum pci_barno barno; - size_t size = 4 * ntb->db_count; + size_t size; epc_features = pci_epc_get_features(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no); - align = epc_features->align; - if (size < 128) - size = 128; - - if (align) - size = ALIGN(size, align); - else - size = roundup_pow_of_two(size); + size = epf_ntb_db_size(ntb); barno = ntb->epf_ntb_bar[BAR_DB]; + epf_bar = &ntb->epf->bar[barno]; - mw_addr = pci_epf_alloc_space(ntb->epf, size, barno, align, 0); - if (!mw_addr) { - dev_err(dev, "Failed to allocate OB address\n"); - return -ENOMEM; + if (!ntb->epf_db_phy) { + mw_addr = pci_epf_alloc_space(ntb->epf, size, barno, align, 0); + if (!mw_addr) { + dev_err(dev, "Failed to allocate OB address\n"); + return -ENOMEM; + } + } else { + epf_bar->phys_addr = ntb->epf_db_phy; + epf_bar->barno = barno; + epf_bar->size = size; } ntb->epf_db = mw_addr; - epf_bar = &ntb->epf->bar[barno]; - ret = pci_epc_set_bar(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no, epf_bar); if (ret) { dev_err(dev, "Doorbell BAR set failed\n"); @@ -704,6 +725,74 @@ static int epf_ntb_init_epc_bar(struct epf_ntb *ntb) return 0; } +static void epf_ntb_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + struct epf_ntb *ntb = dev_get_drvdata(desc->dev); + struct epf_ntb_ctrl *reg = ntb->reg; + int size = epf_ntb_db_size(ntb); + u64 addr; + + addr = msg->address_hi; + addr <<= 32; + addr |= msg->address_lo; + + reg->db_data[desc->msi_index] = msg->data; + + if (desc->msi_index == 0) + ntb->epf_db_phy = round_down(addr, size); + + reg->db_offset[desc->msi_index] = addr - ntb->epf_db_phy; +} + +static irqreturn_t epf_ntb_interrupt_handler(int irq, void *data) +{ + struct epf_ntb *ntb = data; + int index; + + index = irq - ntb->msi_virqbase; + ntb->db |= 1 << (index - 1); + ntb_db_event(&ntb->ntb, index); + + return IRQ_HANDLED; +} + +static void epf_ntb_epc_msi_init(struct epf_ntb *ntb) +{ + struct irq_domain *domain; + struct device *dev = &ntb->epf->dev; + int ret; + int i; + int virq; + + domain = dev_get_msi_domain(ntb->epf->epc->dev.parent); + if (!domain) + return; + + dev_set_msi_domain(dev, domain); + + if (platform_msi_domain_alloc_irqs(&ntb->epf->dev, + ntb->db_count, + epf_ntb_write_msi_msg)) { + dev_info(dev, "Can't allocate MSI, failure back to poll mode\n"); + return; + } + + dev_info(dev, "vntb use MSI as doorbell\n"); + + for (i = 0; i < ntb->db_count; i++) { + virq = msi_get_virq(dev, i); + ret = devm_request_irq(dev, virq, + epf_ntb_interrupt_handler, 0, + "ntb", ntb); + + if (ret) + dev_err(dev, "request irq failure\n"); + + if (!i) + ntb->msi_virqbase = virq; + } +} + /** * epf_ntb_epc_init() - Initialize NTB interface * @ntb: NTB device that facilitates communication between HOST and vHOST2 @@ -1299,14 +1388,15 @@ static int epf_ntb_bind(struct pci_epf *epf) goto err_bar_alloc; } + epf_set_drvdata(epf, ntb); + epf_ntb_epc_msi_init(ntb); + ret = epf_ntb_epc_init(ntb); if (ret) { dev_err(dev, "Failed to initialize EPC\n"); goto err_bar_alloc; } - epf_set_drvdata(epf, ntb); - pci_space[0] = (ntb->vntb_pid << 16) | ntb->vntb_vid; pci_vntb_table[0].vendor = ntb->vntb_vid; pci_vntb_table[0].device = ntb->vntb_pid;