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Wysocki" , "Len Brown" , Pavel Machek , Robert Moore , Pierre Gondois , "Sudeep Holla" CC: Perry Yuan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , , "H. Peter Anvin" , , , , Subject: [PATCH v4 2/2] ACPI: CPPC: Don't require _OSC if X86_FEATURE_CPPC is supported Date: Tue, 5 Jul 2022 13:29:15 -0500 Message-ID: <20220705182915.11663-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220705182915.11663-1-mario.limonciello@amd.com> References: <20220705182915.11663-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b9f072e7-b717-4feb-6c69-08da5eb44d10 X-MS-TrafficTypeDiagnostic: MW2PR12MB2442:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xFqlybkspjqX6k/KbMjYSxxFQy/rxc08l5iYam9cl54ctzRESN4+N+G5PrjhOMiPXQ0bQG/jhgM46gQXJmJKjqJJG7lzqVRU7urkRiZtl32qultQp/9EEu8utQS+uJ5TBXhRuvOfcSukZwrCWX+MIVf42i+jwFTQHmngqGDRx8FNefX6gu0DO3zHp3wKtSB4OUa0KIHBxUML5v+AWLptgJsLnVG3sQ5Caw//ex4BsfGgVqY8ztzMzrEYwZED7cMh0K8FYM7/DcTaIcZ4hSQd9WmCCY4t333i15ty5W96eDrsLFPzrXNU1XP9JZO6xQPyxCJEAYIlVFNbZJAZvdK8yc+qDAHP1Bah5kEHsQfMFZKUh2n77FyFGbNTvgApcNY62pfn9ltQfokcF0DCqfhBPxWjW7eOptg/ww76F2SiirS69a3w8RjNEXAT+YJ2XfCH1NRSOfmxgcrzJrjwASvyEOedgvf4RgGQ7Oj2rlT38ZVfQzns8u+QrcQ8XNxQqUzVQswgwgsuhXDHruUsaIm5vqOSQCp6mlAy1JMit9MfQIbBKabdTJyBAIkFqTAkmuyRMYFNaZK4ta4RxqP6qpTc2uLwOavRxbTvvbtjLawpexZtVNGmeIdwgRm8+XXTpKdtgmIj/6fD0i2b61zuGrrCW3ojOlOimkokPusu+FXIh9LqPdp4PPJrL1wQ1MlBYXC0cwEudW3GasIqTWx26n9BCbhMKMGO/CYXotoXr9n3Szh+l2b+NnIMyrWZtt/I8UPCgUXyhZMKwc0Bb4GMKgLtofBzJAdpQ458jDO2nPO9qsIcC9h4dvmzO17To8CvwTgf1MXNK3a3+ZoPhIlGT6OAZjzCXFzU1e3nnhfv4PQdx+X+x8IM8iDA48ejamafIeBG X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(376002)(396003)(136003)(39860400002)(346002)(46966006)(36840700001)(40470700004)(1076003)(8936002)(86362001)(478600001)(82310400005)(44832011)(356005)(70206006)(70586007)(4326008)(8676002)(36860700001)(82740400003)(34020700004)(5660300002)(40480700001)(2616005)(7416002)(40460700003)(26005)(81166007)(186003)(16526019)(316002)(36756003)(47076005)(7696005)(54906003)(2906002)(336012)(426003)(41300700001)(83380400001)(6666004)(110136005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jul 2022 18:29:30.5455 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9f072e7-b717-4feb-6c69-08da5eb44d10 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2442 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org commit 72f2ecb7ece7 ("ACPI: bus: Set CPPC _OSC bits for all and when CPPC_LIB is supported") added support for claiming to support CPPC in _OSC on non-Intel platforms. This unfortunately caused a regression on a vartiety of AMD platforms in the field because a number of AMD platforms don't set the `_OSC` bit 5 or 6 to indicate CPPC or CPPC v2 support. As these AMD platforms already claim CPPC support via a dedicated MSR from `X86_FEATURE_CPPC`, use this enable this feature rather than requiring the `_OSC` on platforms with a dedicated MSR. If there is additional breakage on the shared memory designs also missing this _OSC, additional follow up changes may be needed. Fixes: 72f2ecb7ece7 ("Set CPPC _OSC bits for all and when CPPC_LIB is supported") Reported-by: Perry Yuan Signed-off-by: Mario Limonciello --- v3->v4 * Explicitly check for AMD before using X86_FEATURE_CPPC v2->v3 * Rebase on top of solution for _CPC regression on some Intel systemss * Refactor to avoid #ifdef CONFIG_X86 arch/x86/kernel/acpi/cppc.c | 10 ++++++++++ drivers/acpi/cppc_acpi.c | 16 +++++++++++++++- include/acpi/cppc_acpi.h | 1 + 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c index 8b8cbf22461a4..734b96454896b 100644 --- a/arch/x86/kernel/acpi/cppc.c +++ b/arch/x86/kernel/acpi/cppc.c @@ -11,6 +11,16 @@ /* Refer to drivers/acpi/cppc_acpi.c for the description of functions */ +bool cpc_supported_by_cpu(void) +{ + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_AMD: + case X86_VENDOR_HYGON: + return boot_cpu_has(X86_FEATURE_CPPC); + } + return false; +} + bool cpc_ffh_supported(void) { return true; diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index d64facbda0fb7..6ff1901d7d436 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -577,6 +577,19 @@ bool __weak cpc_ffh_supported(void) return false; } +/** + * cpc_supported_by_cpu() - check if CPPC is supported by CPU + * + * Check if the architectural support for CPPC is present even + * if the _OSC hasn't prescribed it + * + * Return: true for supported, false for not supported + */ +bool __weak cpc_supported_by_cpu(void) +{ + return false; +} + /** * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace * @@ -686,7 +699,8 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr) if (!osc_sb_cppc2_support_acked) { pr_debug("CPPC v2 _OSC not acked\n"); - return -ENODEV; + if (!cpc_supported_by_cpu()) + return -ENODEV; } /* Parse the ACPI _CPC table for this CPU. */ diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index c6108581d97dc..d389bab54241d 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -145,6 +145,7 @@ extern bool cppc_allow_fast_switch(void); extern int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data); extern unsigned int cppc_get_transition_latency(int cpu); extern bool cpc_ffh_supported(void); +extern bool cpc_supported_by_cpu(void); extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); #else /* !CONFIG_ACPI_CPPC_LIB */