From patchwork Wed Jul 6 14:52:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 587788 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2689CCA482 for ; Wed, 6 Jul 2022 14:52:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231697AbiGFOwn (ORCPT ); Wed, 6 Jul 2022 10:52:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233393AbiGFOw1 (ORCPT ); Wed, 6 Jul 2022 10:52:27 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C96E625E82 for ; Wed, 6 Jul 2022 07:52:26 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id w2so2427196ljj.7 for ; Wed, 06 Jul 2022 07:52:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8RbT729/NK/J3aZcEME2h8k43LmZZ+ZCamZPbQqvBkw=; b=hkNxFhxVPmr2OSV43R7kX0VItWyrk0s/R5UB8rc1B5Jmj4ElrbJlMF1PQjdzDmPI1e RsExrvVhLLbi1DG+c2XxN3OEXh5gQSaLYWzIxwP6vLEriJnrDiLGdw+yXk4mbxw01Ya2 2jLmYEN26Bl3rb1CfBoPIHZFCaOhRNMIV2PKpwz7sJBbFh7NMt4obsJtT+swham02g3j bkc4IPEDXlG8vIHsSW8ZZLkryGHrZAhU5g+B9uWIGcld+3xyLLCA2PIxe7xcrEQBrLOl 2yC5ARRh3mruQ3lz2BirmBpTXBkM9Ziw89Z3rnAKaqA4YjBRv0hkVu/OYXXPrcL51hbK W/dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8RbT729/NK/J3aZcEME2h8k43LmZZ+ZCamZPbQqvBkw=; b=CaHar30h+ZRzOqqf9MbrU/ta4l3mLFWeT/l1CdF7gW25WoAaTR136CC3I7qhOGV6Ap wCyOB3ulY8aGPcPv0BhtyOSo3jcdD5RDTPP0yuptBEVHKR8v3YAvcfeWiXHn3FgUSBln KCaG3veDHYaMwQVcsojBgk2KiTdUfsKlK2HfOxCsgKz9ShcVpn8ov5Y3+K7EMXdFkikf tWSyn1Y8dXZ9sboSQtiZQ7NKabWi4c4sjkN6fXOz671RZAypNGRAfhJX8WlgXUnBlK5/ O7y5/RpWNQqGwO4JumQ+0WMRn751uecoRoefJyoz9/p7byD/V7byQgM9EhMGeG5AA/n7 vT0Q== X-Gm-Message-State: AJIora/f3ZL8uo7BZQTYBeiOaiRMPsWvbzq9+S9Z1QXh1arGJLqR9TKE 3pOMymU8Fm77tCDAXsVVbIpHzQ== X-Google-Smtp-Source: AGRyM1vqFw7qQvdl0zt0pIdJF37OotKd8BH1Pqwi8aIWe4/HT+CDDVwuOttF8QA5UYJQHTVPRGS63w== X-Received: by 2002:a05:651c:4d0:b0:25b:b6f4:ae2d with SMTP id e16-20020a05651c04d000b0025bb6f4ae2dmr23587703lji.472.1657119145197; Wed, 06 Jul 2022 07:52:25 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v25-20020a056512049900b004855e979abcsm556617lfq.99.2022.07.06.07.52.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 07:52:24 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 1/4] dt-bindings: display/msm/gpu: allow specifying several IOMMU nodes Date: Wed, 6 Jul 2022 17:52:19 +0300 Message-Id: <20220706145222.1565238-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220706145222.1565238-1-dmitry.baryshkov@linaro.org> References: <20220706145222.1565238-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Different platforms require different amounts of IOMMUs. The APQ8064 uses 64 IOMMU instances for GPU, adjust the schema accordingly. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 3397bc31d087..346aabdccf7b 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -58,7 +58,8 @@ properties: - const: ocmem iommus: - maxItems: 1 + minItems: 1 + maxItems: 64 sram: $ref: /schemas/types.yaml#/definitions/phandle-array From patchwork Wed Jul 6 14:52:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 588234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70CF2CCA483 for ; Wed, 6 Jul 2022 14:52:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233393AbiGFOwq (ORCPT ); Wed, 6 Jul 2022 10:52:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233575AbiGFOw3 (ORCPT ); Wed, 6 Jul 2022 10:52:29 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56BFC248D2 for ; Wed, 6 Jul 2022 07:52:28 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id r9so18756090ljp.9 for ; Wed, 06 Jul 2022 07:52:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mWYa/JkrXaVyDqQ/AUIdjm9Zadu3uW7Es8evksI4JMM=; b=nERqmQSL/Sc95hbch1fUd+1YIJJKoAoxd5LsP6r7mwfI8nOkG5rzaw00oL/4prG7NW Mh2X4WCl6FTODYsm+9mEAVMgTWjDNeXWB+vKiwEtOeDe5QFq5dOQi4LHz0bjbnl/59HW iPdgDNyuPofN9+LkhhhCVEOfSu0FNzHNomDtkjVXJcWMztTGTZkAvwspoZYDKXu4mVcT zhfmWfvOf58fIT1Jr6PGC7Znm3KcqgKcGWbjAjQ1lZBjdJjccwTWrGyXc43FT5A8RyE/ gSkA2r6BQVSaAB7SFPquNl/o99zqvuyRz6pd46abT+i4L4bSQUQDbfIBRUPVmduLygWR 4XJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mWYa/JkrXaVyDqQ/AUIdjm9Zadu3uW7Es8evksI4JMM=; b=ITtW2jYBOUDWH0AO9xa8ZkBjLuTpBJBF+4YpELDpRm4PQUIu6tXPARKz04hgVpfvGu kYyEcfzu2Qwp1NoRw/jUYP8GvAhXK08kIoEMIn1p8CZm54uGfvTXEObjZPYSph/fq/P3 jp3C2JKkpHF9kkxlQ/K3eScutE2YQAYnc9h/gkjrTU1xmf46GWs2Fua+di5As1U65bT/ uSDCgQ4iHWpluR/y7OqLp7fV2leqyh+0jwQd7Ndof5isRSo/Pz87GLkU5SuZpm6EK2XT xSQ0/8JUwpDLAnneBugwv9Nft2M1GoHE6Aizlx+n0XRjMaaEm78b1ux/CKRNywd1AeS1 ln/w== X-Gm-Message-State: AJIora8+t3fp7l89jGPMb/t7z1nrq+AW1cJtKXPva4fLfA+Ta5g5Eayv VygUMjsQnMOlt02EhofYx6Dxtg== X-Google-Smtp-Source: AGRyM1siQ8prPMCEpPsf2tjnXe3IHRkBfsg1LyW8G4wrbodaZchvocP37Mu2sxympGNIK81TjehE8w== X-Received: by 2002:a05:651c:1798:b0:25d:3043:58e0 with SMTP id bn24-20020a05651c179800b0025d304358e0mr6628027ljb.310.1657119146681; Wed, 06 Jul 2022 07:52:26 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v25-20020a056512049900b004855e979abcsm556617lfq.99.2022.07.06.07.52.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 07:52:25 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 2/4] dt-bindings: display/msm/gpu: document using the amd,imageon adreno too Date: Wed, 6 Jul 2022 17:52:20 +0300 Message-Id: <20220706145222.1565238-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220706145222.1565238-1-dmitry.baryshkov@linaro.org> References: <20220706145222.1565238-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The DT binding desribes using amd,imageon only for Imageon 2xx GPUs. We have been using amd,imageon with newer (Adreno) GPUs to describe the headless setup, when the platform does not (yet) have the display DT nodes (and no display support). Document this trick in the schema. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 346aabdccf7b..e006da95462c 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -16,9 +16,13 @@ properties: - description: | The driver is parsing the compat string for Adreno to figure out the gpu-id and patch level. + Optional amd,imageon compatibility string enables using Adreno + without the display node. items: - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$' - const: qcom,adreno + - const: amd,imageon + minItems: 2 - description: | The driver is parsing the compat string for Imageon to figure out the gpu-id and patch level. @@ -148,6 +152,8 @@ allOf: description: GPU 3D engine clock - const: rbbmtimer description: GPU RBBM Timer for Adreno 5xx series + - const: rbcpr + description: GPU RB CPR clock minItems: 2 maxItems: 7 From patchwork Wed Jul 6 14:52:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 588235 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B0ECC433EF for ; Wed, 6 Jul 2022 14:52:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233263AbiGFOwk (ORCPT ); Wed, 6 Jul 2022 10:52:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233613AbiGFOwa (ORCPT ); Wed, 6 Jul 2022 10:52:30 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9944325C7E for ; Wed, 6 Jul 2022 07:52:29 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id t25so26339361lfg.7 for ; Wed, 06 Jul 2022 07:52:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YGpi0SFFoJ3mrUdF5aNGfF/1+tRI0LBYVB6N+5rOpcE=; b=ud+8DDk6zQxQpEHyhB/JSyKIIwzFovGR4WW9/ItDk367a5uJJnQJWjRANSrhIgyESE 1km53xbY/qlz8V7A+bxfcmQ9aCCsjfEGMlt3MvpWj0UJOu3EvNzGr8hhB6NiHfFihU9K CKXy/4JLoMazyQf0KjgNrll1S2qKVzqh5fW6KvmBdmsqRL7AFoPlzm/uv/zLmid5BVLq JVNEvnC7KiGIp3GgxtEXIro8bzdMAZT3zO6RWE5MTq1ODJRPwp7u3TPcjKZG/55312IY Ycaq+rs1nMg2OSRhDZJNERnnNvTRP+sJrZ9uiQF8CbHu9zOBl8K1IIeOpGmBF1ltAVST niGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YGpi0SFFoJ3mrUdF5aNGfF/1+tRI0LBYVB6N+5rOpcE=; b=Nq2rlreZ0+Bj8ed8+v8x+WC6Gdi/LFBdkCa85ts0Tn/EzPVvWgzrpOIWo1NUopE9GB Yptyp7zYq0AqnblkTNz7nx5O9ayPmvOvYe1Z+Rslv8uG5OlvvGiZLl/b9B5GRqgFN2re enGSvrC8x0z9STYwt48+QhvcVeyECR73/V6nLMgjCyt+hejp7e4fxEmjzwA/N01n3fxD FujQlxsFYWoZZB2RW8kRvVSGNo6JzSKyDgb+ptRaf5rZMQR74GaoSiZ1ZJYA99UTn5rD WggUsial/fZ3W9Ny9caghl/giNXkaHY9nG95dEJg31mvK+y4H2Pjussg8l8bifYlMMtI ipTQ== X-Gm-Message-State: AJIora+OJqv9h7t02zM/jJGm+XvrXOqogXMpe6ygfCfv2/CsawsiQUlg Ji/yJzA5dcWykEWqEv7tlhLltw== X-Google-Smtp-Source: AGRyM1vI6k4XLJFvekZaqNekF4y59n9LrP4o4IJNI70b4dAoY11lzc8ZBQXaxV2QO6gEJp2+Bpsoww== X-Received: by 2002:ac2:5fa8:0:b0:481:4470:413a with SMTP id s8-20020ac25fa8000000b004814470413amr24354447lfe.449.1657119147993; Wed, 06 Jul 2022 07:52:27 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v25-20020a056512049900b004855e979abcsm556617lfq.99.2022.07.06.07.52.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 07:52:27 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 3/4] dt-bindings: display/msm/gmu: account for different GMU variants Date: Wed, 6 Jul 2022 17:52:21 +0300 Message-Id: <20220706145222.1565238-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220706145222.1565238-1-dmitry.baryshkov@linaro.org> References: <20220706145222.1565238-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Make display/msm/gmu.yaml describe all existing GMU variants rather than just the 630.2 (SDM845) version of it. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/msm/gmu.yaml | 166 +++++++++++++++--- 1 file changed, 146 insertions(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index fe55611d2603..67fdeeabae0c 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -20,35 +20,24 @@ description: | properties: compatible: items: - - enum: - - qcom,adreno-gmu-630.2 + - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' - const: qcom,adreno-gmu reg: - items: - - description: Core GMU registers - - description: GMU PDC registers - - description: GMU PDC sequence registers + minItems: 3 + maxItems: 4 reg-names: - items: - - const: gmu - - const: gmu_pdc - - const: gmu_pdc_seq + minItems: 3 + maxItems: 4 clocks: - items: - - description: GMU clock - - description: GPU CX clock - - description: GPU AXI clock - - description: GPU MEMNOC clock + minItems: 4 + maxItems: 7 clock-names: - items: - - const: gmu - - const: cxo - - const: axi - - const: memnoc + minItems: 4 + maxItems: 7 interrupts: items: @@ -76,6 +65,9 @@ properties: operating-points-v2: true + opp-table: + type: object + required: - compatible - reg @@ -91,6 +83,140 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-618.0 + - qcom,adreno-gmu-630.2 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: GMU PDC registers + - description: GMU PDC sequence registers + reg-names: + items: + - const: gmu + - const: gmu_pdc + - const: gmu_pdc_seq + clocks: + items: + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + clock-names: + items: + - const: gmu + - const: cxo + - const: axi + - const: memnoc + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-635.0 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: Resource controller registers + - description: GMU PDC registers + reg-names: + items: + - const: gmu + - const: rscc + - const: gmu_pdc + clocks: + items: + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GPU AHB clock + - description: GPU HUB CX clock + - description: GPU SMMU vote clock + clock-names: + items: + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: ahb + - const: hub + - const: smmu_vote + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-640.1 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: GMU PDC registers + - description: GMU PDC sequence registers + reg-names: + items: + - const: gmu + - const: gmu_pdc + - const: gmu_pdc_seq + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-650.2 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: Resource controller registers + - description: GMU PDC registers + - description: GMU PDC sequence registers + reg-names: + items: + - const: gmu + - const: rscc + - const: gmu_pdc + - const: gmu_pdc_seq + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-640.1 + - qcom,adreno-gmu-650.2 + then: + properties: + clocks: + items: + - description: GPU AHB clock + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + clock-names: + items: + - const: ahb + - const: gmu + - const: cxo + - const: axi + - const: memnoc + examples: - | #include From patchwork Wed Jul 6 14:52:22 2022 Content-Type: text/plain; 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Wed, 06 Jul 2022 07:52:29 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v25-20020a056512049900b004855e979abcsm556617lfq.99.2022.07.06.07.52.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 07:52:28 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 4/4] dt-bindings: display/msm/mdp4: require 4 IOMMUs Date: Wed, 6 Jul 2022 17:52:22 +0300 Message-Id: <20220706145222.1565238-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220706145222.1565238-1-dmitry.baryshkov@linaro.org> References: <20220706145222.1565238-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org APQ8064, the only supported mdp4 platform, uses 4 IOMMUs for the MDP4 device. Update schema accordingly. When we have other MDP4 platforms, this spec can be updated accordingly. Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/mdp4.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/mdp4.yaml b/Documentation/devicetree/bindings/display/msm/mdp4.yaml index f63f60fea27c..58c13f5277b6 100644 --- a/Documentation/devicetree/bindings/display/msm/mdp4.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdp4.yaml @@ -36,7 +36,7 @@ properties: maxItems: 1 iommus: - maxItems: 1 + maxItems: 4 ports: $ref: /schemas/graph.yaml#/properties/ports