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[209.132.180.67]) by mx.google.com with ESMTP id j2si13175938pgb.55.2019.01.21.10.11.07; Mon, 21 Jan 2019 10:11:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OCuJ6wpn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727580AbfAUSLF (ORCPT + 21 others); Mon, 21 Jan 2019 13:11:05 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:32916 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727280AbfAUSLE (ORCPT ); Mon, 21 Jan 2019 13:11:04 -0500 Received: by mail-wm1-f65.google.com with SMTP id r24so6744990wmh.0 for ; Mon, 21 Jan 2019 10:11:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=rr48OMtFtYAts8unhrp77d2MML3lOZEKyN4GG17Fu14=; b=OCuJ6wpnk3QRcu+4gk24PANfAHsoj3OPTSjC3LWVyWA1maOM/nnXF0zEKMjKBZ1j4x kyo3SOcjcU1zHJJBYcz03zQJzyl2Bn4Q17di1FbCNjrliE6op0Y2b2HlCaDlbNsC8lbH 8tA8OCOgixTRfEEw1ylFZ0w9uB7SPTwrvsSQg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=rr48OMtFtYAts8unhrp77d2MML3lOZEKyN4GG17Fu14=; b=Jbes7EQXL7Dc6WSycYlYZ3yLlXfXNmgjLJDt5nAX9ly95IPyBgxNXbBRqx50CgadHi J6gB6P9/ePRseCsNrgm+29y7WZ8DY/FSH/QDSKdXK+0Q5/Fzjb99VScjY5w0lwK97rva S+PJ0tXb2FnW2W61fc83kexhZ4yTlVSVAlFlgUPp7tzgAT/eTszf0UhvW+HSaQ88/l3J S7gOYgOyxVdpSBu3ovRanez7zqPC+d574jAdu/JTjb5XyJxOiRgSIN+zuGJUZl6+G9er j0fEg47mProjNFAMZ2lJT+KBk1tVdEV1wSHT0K24Jptr05oevfjG41S2Xq0qvZj0ltAh KhQg== X-Gm-Message-State: AJcUukfxmKmp0PMaVzVw6+zoBLr7kgrhWdbH5fm6VnTv4gaiKwuR349n AlYmO4GS4H481i/iVqEnHXFeIQ2iBeg= X-Received: by 2002:a1c:ae15:: with SMTP id x21mr431632wme.146.1548094260798; Mon, 21 Jan 2019 10:11:00 -0800 (PST) Received: from localhost ([49.248.61.1]) by smtp.gmail.com with ESMTPSA id a132sm61670483wmh.5.2019.01.21.10.10.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Jan 2019 10:11:00 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, tdas@codeaurora.org, swboyd@chromium.org, dianders@chromium.org, mka@chromium.org, David Brown , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v3 1/1] arm64: dts: sdm845: wireup the thermal trip points to cpufreq Date: Mon, 21 Jan 2019 23:38:34 +0530 Message-Id: <6a21a9ee7663e1b32d8ea81ac5e51d187aed25fb.1548093127.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since all cpus in the big and little clusters, respectively, are in the same frequency domain, use all of them for mitigation in the cooling-map. We end up with two cooling devices - one each for the big and little clusters. We throttle lightly at the first trip point, just removing the boost frequency. At the next trip point we allow ourselves to be throttled to any extent. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 225 +++++++++++++++++++++++++-- 1 file changed, 209 insertions(+), 16 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index c27cbd3bcb0a..878f661d16eb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -99,6 +100,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x0>; enable-method = "psci"; + #cooling-cells = <2>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -114,6 +116,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x100>; enable-method = "psci"; + #cooling-cells = <2>; next-level-cache = <&L2_100>; L2_100: l2-cache { compatible = "cache"; @@ -126,6 +129,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x200>; enable-method = "psci"; + #cooling-cells = <2>; next-level-cache = <&L2_200>; L2_200: l2-cache { compatible = "cache"; @@ -138,6 +142,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x300>; enable-method = "psci"; + #cooling-cells = <2>; next-level-cache = <&L2_300>; L2_300: l2-cache { compatible = "cache"; @@ -150,6 +155,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x400>; enable-method = "psci"; + #cooling-cells = <2>; next-level-cache = <&L2_400>; L2_400: l2-cache { compatible = "cache"; @@ -162,6 +168,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x500>; enable-method = "psci"; + #cooling-cells = <2>; next-level-cache = <&L2_500>; L2_500: l2-cache { compatible = "cache"; @@ -174,6 +181,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x600>; enable-method = "psci"; + #cooling-cells = <2>; next-level-cache = <&L2_600>; L2_600: l2-cache { compatible = "cache"; @@ -186,6 +194,7 @@ compatible = "qcom,kryo385"; reg = <0x0 0x700>; enable-method = "psci"; + #cooling-cells = <2>; next-level-cache = <&L2_700>; L2_700: l2-cache { compatible = "cache"; @@ -1691,18 +1700,41 @@ thermal-sensors = <&tsens0 1>; trips { - cpu_alert0: trip0 { + cpu0_alert1: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit0: trip1 { + cpu0_alert0: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT 1>, + <&CPU1 THERMAL_NO_LIMIT 1>, + <&CPU2 THERMAL_NO_LIMIT 1>, + <&CPU3 THERMAL_NO_LIMIT 1>; + }; + map1 { + trip = <&cpu0_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu1-thermal { @@ -1712,18 +1744,41 @@ thermal-sensors = <&tsens0 2>; trips { - cpu_alert1: trip0 { + cpu1_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit1: trip1 { + cpu1_alert1: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT 1>, + <&CPU1 THERMAL_NO_LIMIT 1>, + <&CPU2 THERMAL_NO_LIMIT 1>, + <&CPU3 THERMAL_NO_LIMIT 1>; + }; + map1 { + trip = <&cpu1_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu2-thermal { @@ -1733,18 +1788,41 @@ thermal-sensors = <&tsens0 3>; trips { - cpu_alert2: trip0 { + cpu2_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit2: trip1 { + cpu2_alert1: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT 1>, + <&CPU1 THERMAL_NO_LIMIT 1>, + <&CPU2 THERMAL_NO_LIMIT 1>, + <&CPU3 THERMAL_NO_LIMIT 1>; + }; + map1 { + trip = <&cpu2_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu3-thermal { @@ -1754,18 +1832,41 @@ thermal-sensors = <&tsens0 4>; trips { - cpu_alert3: trip0 { + cpu3_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit3: trip1 { + cpu3_alert1: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT 1>, + <&CPU1 THERMAL_NO_LIMIT 1>, + <&CPU2 THERMAL_NO_LIMIT 1>, + <&CPU3 THERMAL_NO_LIMIT 1>; + }; + map1 { + trip = <&cpu3_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu4-thermal { @@ -1775,18 +1876,41 @@ thermal-sensors = <&tsens0 7>; trips { - cpu_alert4: trip0 { + cpu4_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit4: trip1 { + cpu4_alert1: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu4_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT 1>, + <&CPU5 THERMAL_NO_LIMIT 1>, + <&CPU6 THERMAL_NO_LIMIT 1>, + <&CPU7 THERMAL_NO_LIMIT 1>; + }; + map1 { + trip = <&cpu4_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu5-thermal { @@ -1796,18 +1920,41 @@ thermal-sensors = <&tsens0 8>; trips { - cpu_alert5: trip0 { + cpu5_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit5: trip1 { + cpu5_alert1: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu5_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT 1>, + <&CPU5 THERMAL_NO_LIMIT 1>, + <&CPU6 THERMAL_NO_LIMIT 1>, + <&CPU7 THERMAL_NO_LIMIT 1>; + }; + map1 { + trip = <&cpu5_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu6-thermal { @@ -1817,18 +1964,41 @@ thermal-sensors = <&tsens0 9>; trips { - cpu_alert6: trip0 { + cpu6_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit6: trip1 { + cpu6_alert1: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu6_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT 1>, + <&CPU5 THERMAL_NO_LIMIT 1>, + <&CPU6 THERMAL_NO_LIMIT 1>, + <&CPU7 THERMAL_NO_LIMIT 1>; + }; + map1 { + trip = <&cpu6_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu7-thermal { @@ -1838,18 +2008,41 @@ thermal-sensors = <&tsens0 10>; trips { - cpu_alert7: trip0 { + cpu7_alert0: trip-point@0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit7: trip1 { + cpu7_alert1: trip-point@1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_crit: cpu_crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu7_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT 1>, + <&CPU5 THERMAL_NO_LIMIT 1>, + <&CPU6 THERMAL_NO_LIMIT 1>, + <&CPU7 THERMAL_NO_LIMIT 1>; + }; + map1 { + trip = <&cpu7_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; };