From patchwork Tue Jun 28 14:23:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 586626 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78872C433EF for ; Tue, 28 Jun 2022 14:24:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345716AbiF1OY0 (ORCPT ); Tue, 28 Jun 2022 10:24:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235217AbiF1OYZ (ORCPT ); Tue, 28 Jun 2022 10:24:25 -0400 Received: from relay07.th.seeweb.it (relay07.th.seeweb.it [5.144.164.168]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F9352CCB4; Tue, 28 Jun 2022 07:24:24 -0700 (PDT) Received: from localhost.localdomain (abxi223.neoplus.adsl.tpnet.pl [83.9.2.223]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id CB60B3F682; Tue, 28 Jun 2022 16:24:21 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/3] dt-bindings: thermal: tsens: Add msm8992/4 compatibles Date: Tue, 28 Jun 2022 16:23:57 +0200 Message-Id: <20220628142359.93100-1-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the compatibles for msm8992/4 TSENS hardware. Signed-off-by: Konrad Dybcio --- No changes. Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 038d81338fcf..0dad9e662161 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -38,6 +38,8 @@ properties: items: - enum: - qcom,msm8976-tsens + - qcom,msm8992-tsens + - qcom,msm8994-tsens - qcom,qcs404-tsens - const: qcom,tsens-v1 From patchwork Tue Jun 28 14:23:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 585605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 424E6CCA47F for ; Tue, 28 Jun 2022 14:24:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346104AbiF1OY2 (ORCPT ); Tue, 28 Jun 2022 10:24:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345863AbiF1OY1 (ORCPT ); Tue, 28 Jun 2022 10:24:27 -0400 Received: from relay07.th.seeweb.it (relay07.th.seeweb.it [5.144.164.168]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8BF22DA8D; Tue, 28 Jun 2022 07:24:25 -0700 (PDT) Received: from localhost.localdomain (abxi223.neoplus.adsl.tpnet.pl [83.9.2.223]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id 91FF63F6B1; Tue, 28 Jun 2022 16:24:23 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/3] thermal: qcom: tsens-v1: Use GENMASK macro for bitmasks Date: Tue, 28 Jun 2022 16:23:58 +0200 Message-Id: <20220628142359.93100-2-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628142359.93100-1-konrad.dybcio@somainline.org> References: <20220628142359.93100-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the masks to use GENMASK. Tested by objdumping and making sure the output is identical pre- and post this patch. Signed-off-by: Konrad Dybcio --- Changes since v3: * Add this patch drivers/thermal/qcom/tsens-v1.c | 107 ++++++++++++++++---------------- 1 file changed, 54 insertions(+), 53 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 573e261ccca7..d6f0dec4bfa1 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -3,6 +3,7 @@ * Copyright (c) 2019, Linaro Limited */ +#include #include #include #include @@ -22,34 +23,34 @@ #define TM_HIGH_LOW_Sn_INT_THRESHOLD_OFF 0x0090 /* eeprom layout data for msm8956/76 (v1) */ -#define MSM8976_BASE0_MASK 0xff -#define MSM8976_BASE1_MASK 0xff +#define MSM8976_BASE0_MASK GENMASK(7, 0) +#define MSM8976_BASE1_MASK GENMASK(7, 0) #define MSM8976_BASE1_SHIFT 8 -#define MSM8976_S0_P1_MASK 0x3f00 -#define MSM8976_S1_P1_MASK 0x3f00000 -#define MSM8976_S2_P1_MASK 0x3f -#define MSM8976_S3_P1_MASK 0x3f000 -#define MSM8976_S4_P1_MASK 0x3f00 -#define MSM8976_S5_P1_MASK 0x3f00000 -#define MSM8976_S6_P1_MASK 0x3f -#define MSM8976_S7_P1_MASK 0x3f000 -#define MSM8976_S8_P1_MASK 0x1f8 -#define MSM8976_S9_P1_MASK 0x1f8000 -#define MSM8976_S10_P1_MASK 0xf8000000 -#define MSM8976_S10_P1_MASK_1 0x1 - -#define MSM8976_S0_P2_MASK 0xfc000 -#define MSM8976_S1_P2_MASK 0xfc000000 -#define MSM8976_S2_P2_MASK 0xfc0 -#define MSM8976_S3_P2_MASK 0xfc0000 -#define MSM8976_S4_P2_MASK 0xfc000 -#define MSM8976_S5_P2_MASK 0xfc000000 -#define MSM8976_S6_P2_MASK 0xfc0 -#define MSM8976_S7_P2_MASK 0xfc0000 -#define MSM8976_S8_P2_MASK 0x7e00 -#define MSM8976_S9_P2_MASK 0x7e00000 -#define MSM8976_S10_P2_MASK 0x7e +#define MSM8976_S0_P1_MASK GENMASK(13, 8) +#define MSM8976_S1_P1_MASK GENMASK(25, 20) +#define MSM8976_S2_P1_MASK GENMASK(5, 0) +#define MSM8976_S3_P1_MASK GENMASK(17, 12) +#define MSM8976_S4_P1_MASK GENMASK(13, 8) +#define MSM8976_S5_P1_MASK GENMASK(25, 20) +#define MSM8976_S6_P1_MASK GENMASK(5, 0) +#define MSM8976_S7_P1_MASK GENMASK(17, 12) +#define MSM8976_S8_P1_MASK GENMASK(8, 3) +#define MSM8976_S9_P1_MASK GENMASK(20, 15) +#define MSM8976_S10_P1_MASK GENMASK(31, 27) +#define MSM8976_S10_P1_MASK_1 GENMASK(0, 0) + +#define MSM8976_S0_P2_MASK GENMASK(19, 14) +#define MSM8976_S1_P2_MASK GENMASK(31, 26) +#define MSM8976_S2_P2_MASK GENMASK(11, 6) +#define MSM8976_S3_P2_MASK GENMASK(23, 18) +#define MSM8976_S4_P2_MASK GENMASK(19, 14) +#define MSM8976_S5_P2_MASK GENMASK(31, 26) +#define MSM8976_S6_P2_MASK GENMASK(11, 6) +#define MSM8976_S7_P2_MASK GENMASK(23, 18) +#define MSM8976_S8_P2_MASK GENMASK(14, 9) +#define MSM8976_S9_P2_MASK GENMASK(26, 21) +#define MSM8976_S10_P2_MASK GENMASK(6, 1) #define MSM8976_S0_P1_SHIFT 8 #define MSM8976_S1_P1_SHIFT 20 @@ -76,7 +77,7 @@ #define MSM8976_S9_P2_SHIFT 21 #define MSM8976_S10_P2_SHIFT 1 -#define MSM8976_CAL_SEL_MASK 0x3 +#define MSM8976_CAL_SEL_MASK GENMASK(1, 0) #define MSM8976_CAL_DEGC_PT1 30 #define MSM8976_CAL_DEGC_PT2 120 @@ -84,34 +85,34 @@ #define MSM8976_SLOPE_DEFAULT 3200 /* eeprom layout data for qcs404/405 (v1) */ -#define BASE0_MASK 0x000007f8 -#define BASE1_MASK 0x0007f800 +#define BASE0_MASK GENMASK(10, 3) +#define BASE1_MASK GENMASK(18, 11) #define BASE0_SHIFT 3 #define BASE1_SHIFT 11 -#define S0_P1_MASK 0x0000003f -#define S1_P1_MASK 0x0003f000 -#define S2_P1_MASK 0x3f000000 -#define S3_P1_MASK 0x000003f0 -#define S4_P1_MASK 0x003f0000 -#define S5_P1_MASK 0x0000003f -#define S6_P1_MASK 0x0003f000 -#define S7_P1_MASK 0x3f000000 -#define S8_P1_MASK 0x000003f0 -#define S9_P1_MASK 0x003f0000 - -#define S0_P2_MASK 0x00000fc0 -#define S1_P2_MASK 0x00fc0000 -#define S2_P2_MASK_1_0 0xc0000000 -#define S2_P2_MASK_5_2 0x0000000f -#define S3_P2_MASK 0x0000fc00 -#define S4_P2_MASK 0x0fc00000 -#define S5_P2_MASK 0x00000fc0 -#define S6_P2_MASK 0x00fc0000 -#define S7_P2_MASK_1_0 0xc0000000 -#define S7_P2_MASK_5_2 0x0000000f -#define S8_P2_MASK 0x0000fc00 -#define S9_P2_MASK 0x0fc00000 +#define S0_P1_MASK GENMASK(5, 0) +#define S1_P1_MASK GENMASK(17, 12) +#define S2_P1_MASK GENMASK(29, 24) +#define S3_P1_MASK GENMASK(9, 4) +#define S4_P1_MASK GENMASK(21, 16) +#define S5_P1_MASK GENMASK(5, 0) +#define S6_P1_MASK GENMASK(17, 12) +#define S7_P1_MASK GENMASK(29, 24) +#define S8_P1_MASK GENMASK(9, 4) +#define S9_P1_MASK GENMASK(21, 16) + +#define S0_P2_MASK GENMASK(11, 6) +#define S1_P2_MASK GENMASK(23, 18) +#define S2_P2_MASK_1_0 GENMASK(31, 30) +#define S2_P2_MASK_5_2 GENMASK(3, 0) +#define S3_P2_MASK GENMASK(15, 10) +#define S4_P2_MASK GENMASK(27, 22) +#define S5_P2_MASK GENMASK(11, 6) +#define S6_P2_MASK GENMASK(23, 18) +#define S7_P2_MASK_1_0 GENMASK(31, 30) +#define S7_P2_MASK_5_2 GENMASK(3, 0) +#define S8_P2_MASK GENMASK(15, 10) +#define S9_P2_MASK GENMASK(27, 22) #define S0_P1_SHIFT 0 #define S0_P2_SHIFT 6 @@ -139,7 +140,7 @@ #define S9_P1_SHIFT 16 #define S9_P2_SHIFT 22 -#define CAL_SEL_MASK 7 +#define CAL_SEL_MASK GENMASK(2, 0) #define CAL_SEL_SHIFT 0 static void compute_intercept_slope_8976(struct tsens_priv *priv, From patchwork Tue Jun 28 14:23:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 586625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78363C43334 for ; Tue, 28 Jun 2022 14:24:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346381AbiF1OYi (ORCPT ); Tue, 28 Jun 2022 10:24:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235217AbiF1OY3 (ORCPT ); Tue, 28 Jun 2022 10:24:29 -0400 Received: from relay05.th.seeweb.it (relay05.th.seeweb.it [5.144.164.166]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 186B52CDC3; Tue, 28 Jun 2022 07:24:28 -0700 (PDT) Received: from localhost.localdomain (abxi223.neoplus.adsl.tpnet.pl [83.9.2.223]) by m-r2.th.seeweb.it (Postfix) with ESMTPA id F1DB53F713; Tue, 28 Jun 2022 16:24:24 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Amit Kucheria , Thara Gopinath , Andy Gross , Bjorn Andersson , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/3] thermal: qcom: tsens-v1: Add support for MSM8992/4 TSENS Date: Tue, 28 Jun 2022 16:23:59 +0200 Message-Id: <20220628142359.93100-3-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628142359.93100-1-konrad.dybcio@somainline.org> References: <20220628142359.93100-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org MSM8994, despite being heavily based on MSM8974, uses the 1.2 version of TSENS. Also, 8994 being 8994, it has a custom way of calculating the slope. MSM8992 in turn is a cut-down version of MSM8994 and uses the same TSENS hardware, albeit with a different set of sensors. Also tested on 8976 (by a person who didn't want to be named) to make sure the 11->16 max_sensors changes didn't break anything. Signed-off-by: Konrad Dybcio --- Changes since v3: * Use GENMASK drivers/thermal/qcom/tsens-v1.c | 299 ++++++++++++++++++++++++++++++-- drivers/thermal/qcom/tsens.c | 6 + drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 294 insertions(+), 13 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index d6f0dec4bfa1..00b5428b4bca 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -143,6 +143,99 @@ #define CAL_SEL_MASK GENMASK(2, 0) #define CAL_SEL_SHIFT 0 +/* eeprom layout data for 8994 */ +#define MSM8994_BASE0_MASK GENMASK(9, 0) +#define MSM8994_BASE1_MASK GENMASK(19, 10) +#define MSM8994_BASE0_SHIFT 0 +#define MSM8994_BASE1_SHIFT 10 + +#define MSM8994_S0_MASK GENMASK(23, 20) +#define MSM8994_S1_MASK GENMASK(27, 24) +#define MSM8994_S2_MASK GENMASK(31, 28) +#define MSM8994_S3_MASK GENMASK(3, 0) +#define MSM8994_S4_MASK GENMASK(7, 4) +#define MSM8994_S5_MASK GENMASK(11, 8) +#define MSM8994_S6_MASK GENMASK(15, 12) +#define MSM8994_S7_MASK GENMASK(19, 16) +#define MSM8994_S8_MASK GENMASK(23, 20) +#define MSM8994_S9_MASK GENMASK(27, 24) +#define MSM8994_S10_MASK GENMASK(31, 28) +#define MSM8994_S11_MASK GENMASK(3, 0) +#define MSM8994_S12_MASK GENMASK(7, 4) +#define MSM8994_S13_MASK GENMASK(11, 8) +#define MSM8994_S14_MASK GENMASK(15, 12) +#define MSM8994_S15_MASK GENMASK(19, 16) + +#define MSM8994_S0_SHIFT 20 +#define MSM8994_S1_SHIFT 24 +#define MSM8994_S2_SHIFT 28 +#define MSM8994_S3_SHIFT 0 +#define MSM8994_S4_SHIFT 4 +#define MSM8994_S5_SHIFT 8 +#define MSM8994_S6_SHIFT 12 +#define MSM8994_S7_SHIFT 16 +#define MSM8994_S8_SHIFT 20 +#define MSM8994_S9_SHIFT 24 +#define MSM8994_S10_SHIFT 28 +#define MSM8994_S11_SHIFT 0 +#define MSM8994_S12_SHIFT 4 +#define MSM8994_S13_SHIFT 8 +#define MSM8994_S14_SHIFT 12 +#define MSM8994_S15_SHIFT 16 + +#define MSM8994_CAL_SEL_MASK GENMASK(22, 20) +#define MSM8994_CAL_SEL_SHIFT 20 + +#define MSM8994_BASE0_REDUN_MASK GENMASK(30, 21) +#define MSM8994_BASE1_BIT0_REDUN_MASK GENMASK(31, 31) +#define MSM8994_BASE1_BIT1_9_REDUN_MASK GENMASK(8, 0) +#define MSM8994_BASE0_REDUN_SHIFT 21 +#define MSM8994_BASE1_BIT0_REDUN_SHIFT_COMPUTE 31 + +#define MSM8994_S0_REDUN_MASK GENMASK(12, 9) +#define MSM8994_S1_REDUN_MASK GENMASK(16, 13) +#define MSM8994_S2_REDUN_MASK GENMASK(20, 17) +#define MSM8994_S3_REDUN_MASK GENMASK(24, 21) +#define MSM8994_S4_REDUN_MASK GENMASK(28, 25) +#define MSM8994_S5_REDUN_MASK_BIT0_2 GENMASK(31, 29) +#define MSM8994_S5_REDUN_MASK_BIT3 GENMASK(23, 23) +#define MSM8994_S6_REDUN_MASK GENMASK(27, 24) +#define MSM8994_S7_REDUN_MASK GENMASK(31, 28) +#define MSM8994_S8_REDUN_MASK GENMASK(3, 0) +#define MSM8994_S9_REDUN_MASK GENMASK(7, 4) +#define MSM8994_S10_REDUN_MASK GENMASK(11, 8) +#define MSM8994_S11_REDUN_MASK GENMASK(15, 12) +#define MSM8994_S12_REDUN_MASK GENMASK(19, 16) +#define MSM8994_S13_REDUN_MASK GENMASK(23, 20) +#define MSM8994_S14_REDUN_MASK GENMASK(27, 24) +#define MSM8994_S15_REDUN_MASK GENMASK(31, 28) + +#define MSM8994_S0_REDUN_SHIFT 9 +#define MSM8994_S1_REDUN_SHIFT 13 +#define MSM8994_S2_REDUN_SHIFT 17 +#define MSM8994_S3_REDUN_SHIFT 21 +#define MSM8994_S4_REDUN_SHIFT 25 +#define MSM8994_S5_REDUN_SHIFT_BIT0_2 29 +#define MSM8994_S5_REDUN_SHIFT_BIT3 23 +#define MSM8994_S6_REDUN_SHIFT 24 +#define MSM8994_S7_REDUN_SHIFT 28 +#define MSM8994_S8_REDUN_SHIFT 0 +#define MSM8994_S9_REDUN_SHIFT 4 +#define MSM8994_S10_REDUN_SHIFT 8 +#define MSM8994_S11_REDUN_SHIFT 12 +#define MSM8994_S12_REDUN_SHIFT 16 +#define MSM8994_S13_REDUN_SHIFT 20 +#define MSM8994_S14_REDUN_SHIFT 24 +#define MSM8994_S15_REDUN_SHIFT 28 + +#define MSM8994_REDUN_SEL_MASK GENMASK(2, 0) +#define MSM8994_CAL_SEL_REDUN_MASK GENMASK(31, 29) +#define MSM8994_CAL_SEL_REDUN_SHIFT 29 + +#define BKP_SEL 0x3 +#define BKP_REDUN_SEL 0xe0000000 +#define BKP_REDUN_SHIFT 29 + static void compute_intercept_slope_8976(struct tsens_priv *priv, u32 *p1, u32 *p2, u32 mode) { @@ -167,6 +260,29 @@ static void compute_intercept_slope_8976(struct tsens_priv *priv, } } +/* HW-specific calculations forwardported from msm-3.10 kernel */ +static void compute_intercept_slope_8994(struct tsens_priv *priv, + u32 base0, u32 base1, u32 *p, u32 mode) +{ + int adc_code_of_tempx, i, num, den, slope; + + /* slope (m, dy/dx) = SLOPE_FACTOR * (adc_code2 - adc_code1)/(temp_120_degc - temp_30_degc) */ + num = base1 - base0; + num *= SLOPE_FACTOR; + den = CAL_DEGC_PT2 - CAL_DEGC_PT1; + slope = num / den; + + for (i = 0; i < priv->num_sensors; i++) { + adc_code_of_tempx = base0 + p[i]; + priv->sensor[i].offset = (adc_code_of_tempx * SLOPE_FACTOR) - + (CAL_DEGC_PT1 * priv->sensor[i].slope); + priv->sensor[i].slope = (mode == TWO_PT_CALIB) ? slope : SLOPE_DEFAULT; + + dev_dbg(priv->dev, "%s: offset:%d, slope:%d\n", __func__, + priv->sensor[i].offset, priv->sensor[i].slope); + } +} + static int calibrate_v1(struct tsens_priv *priv) { u32 base0 = 0, base1 = 0; @@ -298,14 +414,145 @@ static int calibrate_8976(struct tsens_priv *priv) return 0; } -/* v1.x: msm8956,8976,qcs404,405 */ +static int calibrate_8994(struct tsens_priv *priv) +{ + int base0 = 0, base1 = 0, i; + u32 p[16] = { [0 ... 15] = 532 }; /* HW-specific, undocumented magic value */ + int mode = 0; + u32 *calib0, *calib1, *calib2, *calib_mode, *calib_rsel; + u32 calib_redun_sel; + + /* 0x40d0-0x40dc */ + calib0 = (u32 *)qfprom_read(priv->dev, "calib"); + if (IS_ERR(calib0)) + return PTR_ERR(calib0); + + dev_dbg(priv->dev, "%s: calib0: [0] = %u, [1] = %u, [2] = %u\n", + __func__, calib0[0], calib0[1], calib0[2]); + + /* 0x41c0-0x41c8 */ + calib1 = (u32 *)qfprom_read(priv->dev, "calib_redun1_2"); + if (IS_ERR(calib1)) + return PTR_ERR(calib1); + + dev_dbg(priv->dev, "%s: calib1: [0] = %u, [1] = %u\n", + __func__, calib1[0], calib1[1]); + + /* 0x41cc-0x41d0 */ + calib2 = (u32 *)qfprom_read(priv->dev, "calib_redun3"); + if (IS_ERR(calib2)) + return PTR_ERR(calib2); + + dev_dbg(priv->dev, "%s: calib2: [0] = %u\n", __func__, calib2[0]); + + /* 0x4440-0x4448 */ + calib_mode = (u32 *)qfprom_read(priv->dev, "calib_redun4_5"); + if (IS_ERR(calib_mode)) + return PTR_ERR(calib_mode); + + dev_dbg(priv->dev, "%s: calib_mode: [0] = %u, [1] = %u\n", + __func__, calib1[0], calib1[1]); + + /* 0x4464-0x4468 */ + calib_rsel = (u32 *)qfprom_read(priv->dev, "calib_rsel"); + if (IS_ERR(calib_mode)) + return PTR_ERR(calib_mode); + + dev_dbg(priv->dev, "%s: calib_rsel: [0] = %u\n", __func__, calib_rsel[0]); + + calib_redun_sel = calib_rsel[0] & MSM8994_CAL_SEL_REDUN_MASK; + calib_redun_sel >>= MSM8994_CAL_SEL_REDUN_SHIFT; + + if (calib_redun_sel == BKP_SEL) { + dev_dbg(priv->dev, "%s: Calibrating in REDUN mode, calib_redun_sel = %u", + __func__, calib_redun_sel); + mode = calib_mode[1] & MSM8994_REDUN_SEL_MASK; + + if (mode == TWO_PT_CALIB) { + dev_dbg(priv->dev, "%s: REDUN TWO_PT mode, mode = %u", __func__, mode); + base0 = (calib1[0] & MSM8994_BASE0_REDUN_MASK) >> MSM8994_BASE0_REDUN_SHIFT; + base1 = (calib1[0] & MSM8994_BASE1_BIT0_REDUN_MASK) >> MSM8994_BASE1_BIT0_REDUN_SHIFT_COMPUTE; + base1 |= calib1[1] & MSM8994_BASE1_BIT1_9_REDUN_MASK; + p[0] = (calib1[1] & MSM8994_S0_REDUN_MASK) >> MSM8994_S0_REDUN_SHIFT; + p[1] = (calib1[1] & MSM8994_S1_REDUN_MASK) >> MSM8994_S1_REDUN_SHIFT; + p[2] = (calib1[1] & MSM8994_S2_REDUN_MASK) >> MSM8994_S2_REDUN_SHIFT; + p[3] = (calib1[1] & MSM8994_S3_REDUN_MASK) >> MSM8994_S3_REDUN_SHIFT; + p[4] = (calib1[1] & MSM8994_S4_REDUN_MASK) >> MSM8994_S4_REDUN_SHIFT; + p[5] = (calib1[1] & MSM8994_S5_REDUN_MASK_BIT0_2) >> MSM8994_S5_REDUN_SHIFT_BIT0_2; + p[5] |= (calib2[0] & MSM8994_S5_REDUN_MASK_BIT3) >> MSM8994_S5_REDUN_SHIFT_BIT3; + p[6] = (calib2[0] & MSM8994_S6_REDUN_MASK) >> MSM8994_S6_REDUN_SHIFT; + p[7] = (calib2[0] & MSM8994_S7_REDUN_MASK) >> MSM8994_S7_REDUN_SHIFT; + p[8] = (calib2[0] & MSM8994_S8_REDUN_MASK) >> MSM8994_S8_REDUN_SHIFT; + p[9] = (calib2[0] & MSM8994_S9_REDUN_MASK) >> MSM8994_S9_REDUN_SHIFT; + p[10] = (calib2[0] & MSM8994_S10_REDUN_MASK) >> MSM8994_S10_REDUN_SHIFT; + p[11] = (calib2[0] & MSM8994_S11_REDUN_MASK) >> MSM8994_S11_REDUN_SHIFT; + p[12] = (calib2[0] & MSM8994_S12_REDUN_MASK) >> MSM8994_S12_REDUN_SHIFT; + p[13] = (calib2[0] & MSM8994_S13_REDUN_MASK) >> MSM8994_S13_REDUN_SHIFT; + p[14] = (calib2[0] & MSM8994_S14_REDUN_MASK) >> MSM8994_S14_REDUN_SHIFT; + p[15] = (calib2[0] & MSM8994_S15_REDUN_MASK) >> MSM8994_S15_REDUN_SHIFT; + } else { + dev_dbg(priv->dev, "%s: REDUN NON-TWO_PT mode, mode = %u", __func__, mode); + } + } else { + dev_dbg(priv->dev, "%s: Calibrating in NOT-REDUN mode, calib_redun_sel = %u", + __func__, calib_redun_sel); + mode = (calib0[2] & MSM8994_CAL_SEL_MASK) >> MSM8994_CAL_SEL_SHIFT; + + if (mode == TWO_PT_CALIB) { + dev_dbg(priv->dev, "%s: NOT-REDUN TWO_PT mode, mode = %u", __func__, mode); + base0 = (calib0[0] & MSM8994_BASE0_MASK) >> MSM8994_BASE0_SHIFT; + base1 = (calib0[0] & MSM8994_BASE1_MASK) >> MSM8994_BASE1_SHIFT; + p[0] = (calib0[0] & MSM8994_S0_MASK) >> MSM8994_S0_SHIFT; + p[1] = (calib0[0] & MSM8994_S1_MASK) >> MSM8994_S1_SHIFT; + p[2] = (calib0[1] & MSM8994_S2_MASK) >> MSM8994_S2_SHIFT; + p[3] = (calib0[1] & MSM8994_S3_MASK) >> MSM8994_S3_SHIFT; + p[4] = (calib0[1] & MSM8994_S4_MASK) >> MSM8994_S4_SHIFT; + p[5] = (calib0[1] & MSM8994_S5_MASK) >> MSM8994_S5_SHIFT; + p[6] = (calib0[1] & MSM8994_S6_MASK) >> MSM8994_S6_SHIFT; + p[7] = (calib0[1] & MSM8994_S7_MASK) >> MSM8994_S7_SHIFT; + p[8] = (calib0[1] & MSM8994_S8_MASK) >> MSM8994_S8_SHIFT; + p[9] = (calib0[1] & MSM8994_S9_MASK) >> MSM8994_S9_SHIFT; + p[10] = (calib0[1] & MSM8994_S10_MASK) >> MSM8994_S10_SHIFT; + p[11] = (calib0[2] & MSM8994_S11_MASK) >> MSM8994_S11_SHIFT; + p[12] = (calib0[2] & MSM8994_S12_MASK) >> MSM8994_S12_SHIFT; + p[13] = (calib0[2] & MSM8994_S13_MASK) >> MSM8994_S13_SHIFT; + p[14] = (calib0[2] & MSM8994_S14_MASK) >> MSM8994_S14_SHIFT; + p[15] = (calib0[2] & MSM8994_S15_MASK) >> MSM8994_S15_SHIFT; + } else { + dev_dbg(priv->dev, "%s: NOT-REDUN NON-TWO_PT mode, mode = %u", __func__, mode); + for (i = 0; i < 16; i++) + p[i] = 532; + } + } + + /* 8992 features less sensors and remaps some */ + if (priv->num_sensors == 13) { + p[6] = p[7]; + p[7] = p[9]; + p[8] = p[10]; + p[9] = p[11]; + p[10] = p[12]; + p[11] = p[13]; + p[12] = p[14]; + } + + compute_intercept_slope_8994(priv, base0, base1, p, mode); + kfree(calib0); + kfree(calib1); + kfree(calib2); + kfree(calib_mode); + + return 0; +} + +/* v1.x: msm8956/8976, msm8994 (v1.2), qcs404/qcs405 */ static struct tsens_features tsens_v1_feat = { .ver_major = VER_1_X, .crit_int = 0, .adc = 1, .srot_split = 1, - .max_sensors = 11, + .max_sensors = 16, }; static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { @@ -324,12 +571,12 @@ static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0), /* UPPER/LOWER TEMPERATURE THRESHOLDS */ - REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9), - REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19), + REG_FIELD_FOR_EACH_SENSOR16(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9), + REG_FIELD_FOR_EACH_SENSOR16(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19), /* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */ - REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20), - REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21), + REG_FIELD_FOR_EACH_SENSOR16(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20), + REG_FIELD_FOR_EACH_SENSOR16(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21), [LOW_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 0, 0), [LOW_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 1, 1), [LOW_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 2, 2), @@ -350,14 +597,14 @@ static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { /* NO CRITICAL INTERRUPT SUPPORT on v1 */ /* Sn_STATUS */ - REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9), - REG_FIELD_FOR_EACH_SENSOR11(VALID, TM_Sn_STATUS_OFF, 14, 14), + REG_FIELD_FOR_EACH_SENSOR16(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9), + REG_FIELD_FOR_EACH_SENSOR16(VALID, TM_Sn_STATUS_OFF, 14, 14), /* xxx_STATUS bits: 1 == threshold violated */ - REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10), - REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11), - REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12), + REG_FIELD_FOR_EACH_SENSOR16(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10), + REG_FIELD_FOR_EACH_SENSOR16(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11), + REG_FIELD_FOR_EACH_SENSOR16(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12), /* No CRITICAL field on v1.x */ - REG_FIELD_FOR_EACH_SENSOR11(MAX_STATUS, TM_Sn_STATUS_OFF, 13, 13), + REG_FIELD_FOR_EACH_SENSOR16(MAX_STATUS, TM_Sn_STATUS_OFF, 13, 13), /* TRDY: 1=ready, 0=in progress */ [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), @@ -389,3 +636,31 @@ struct tsens_plat_data data_8976 = { .feat = &tsens_v1_feat, .fields = tsens_v1_regfields, }; + +static const struct tsens_ops ops_8992 = { + .init = init_common, + .calibrate = calibrate_8994, + .get_temp = get_temp_tsens_valid, +}; + +struct tsens_plat_data data_8992 = { + .num_sensors = 13, + .ops = &ops_8992, + .hw_ids = (unsigned int []){ 0, 1, 2, 3, 4, 5, 7, 9, 10, 11, 12, 13, 14 }, + .feat = &tsens_v1_feat, + .fields = tsens_v1_regfields, +}; + +static const struct tsens_ops ops_8994 = { + .init = init_common, + .calibrate = calibrate_8994, + .get_temp = get_temp_tsens_valid, +}; + +struct tsens_plat_data data_8994 = { + .num_sensors = 16, + .ops = &ops_8994, + .hw_ids = (unsigned int []){ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, + .feat = &tsens_v1_feat, + .fields = tsens_v1_regfields, +}; diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 7963ee33bf75..7f1411e7b114 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -985,6 +985,12 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,msm8974-tsens", .data = &data_8974, + }, { + .compatible = "qcom,msm8992-tsens", + .data = &data_8992, + }, { + .compatible = "qcom,msm8994-tsens", + .data = &data_8994, }, { .compatible = "qcom,msm8976-tsens", .data = &data_8976, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 1471a2c00f15..ca2b0ac914c1 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -590,7 +590,7 @@ extern struct tsens_plat_data data_8960; extern struct tsens_plat_data data_8916, data_8939, data_8974, data_9607; /* TSENS v1 targets */ -extern struct tsens_plat_data data_tsens_v1, data_8976; +extern struct tsens_plat_data data_tsens_v1, data_8976, data_8992, data_8994; /* TSENS v2 targets */ extern struct tsens_plat_data data_8996, data_tsens_v2;