From patchwork Thu Jun 23 12:04:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 584351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BB6BCCA47C for ; Thu, 23 Jun 2022 12:04:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231190AbiFWMEZ (ORCPT ); Thu, 23 Jun 2022 08:04:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231337AbiFWMEY (ORCPT ); Thu, 23 Jun 2022 08:04:24 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71DD64925B for ; Thu, 23 Jun 2022 05:04:22 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id j22so16418582ljg.0 for ; Thu, 23 Jun 2022 05:04:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eLo0cmj8iEhVelCOHSSbw79s0qehpremV7AWxy+/lLQ=; b=tcTGwolRBv0D4qD9ejpmCeDs1hoaOeSmTcyx4lu6JHFxpbx4pM0D2TZv/6vemKt2ga jed1TsXSemb7bDoHCe4Uflr9k1oX7vMkFRG5XSxrSxFVfB/MvughH8zna/mCK4Xemn9c omUbRcPyySluNVhjn5tvH/PrIaHyT932/S+k49hRZa+V7Snbc0dGa4nzImRoVFQBuk8G GRQPHKKy4DQW6QTAsVo2XbV6uwUN4YXJWW9N/v5cre54uIwuw1h7MauVgW3cmlzJlmwO FIhqPkkWi5y+hb9tSL2BUS4z2FEFJ6CBusFgTOqEr1Ic8LGPfPKudT6Wm6gbWCOwjp+k jDXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eLo0cmj8iEhVelCOHSSbw79s0qehpremV7AWxy+/lLQ=; b=LOcCCXIO+ikQJd1rdyBqatnxItmhgvOlvqZTMCP7mzXU/qRKOvEJp5//rYCcXaxu+U o00Z84EA+O/gFq3ofXprKMyoRE/iem61He+Ms5f/j6iASJH/p6IchT8a2jkL3cGDbkQN MlTLn8K8Pzv/VK/KI8eDqgmEQmM7lc8JYeS9pkeFECYUj43cNCIk9BERrZSKDHGcMKTe 4ESZZcIez1wbJ2aF8JEvbeHgKb+MkBgGNKxmheRdC1sti1PwRzflzrfdT9QpBLgSKq4Q EyfWTarRz+D4B772hgDzGCAhtw4Zo/bXmINReTbq9aAkTRWuYVSldoJiAydsUE7j9Fpp TjRA== X-Gm-Message-State: AJIora8V72z5Cg/HlLxSP2xgWvZHHwyq4xForxd+/TofGzkb3EdBxMVL mtPCfEqrlDWFX+u+NYIXhsrJMg== X-Google-Smtp-Source: AGRyM1vhm4tEf25uqRF7DTxCNaFF4kdl9eUiq3K6lXVVrAMG+iaWY8gJoIKfW0f0Qeatk1pBR+Wsyw== X-Received: by 2002:a2e:b6c6:0:b0:25a:93bb:f801 with SMTP id m6-20020a2eb6c6000000b0025a93bbf801mr1502777ljo.489.1655985860818; Thu, 23 Jun 2022 05:04:20 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id 18-20020ac25f52000000b0047f6b4a53cdsm1799888lfz.172.2022.06.23.05.04.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 05:04:20 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 02/15] dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8960 Date: Thu, 23 Jun 2022 15:04:05 +0300 Message-Id: <20220623120418.250589-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> References: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define clock/clock-names properties of the MMCC device node to be used on MSM8960/APQ8064 platform. Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/qcom,mmcc.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml index d02fe6dc79b5..c13243682365 100644 --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml @@ -82,6 +82,37 @@ then: - clock-names allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,mmcc-apq8064 + - qcom,mmcc-msm8960 + then: + properties: + clocks: + items: + - description: Board PXO source + - description: PLL 3 clock + - description: PLL 3 Vote clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: DSI phy instance 2 dsi clock + - description: DSI phy instance 2 byte clock + - description: HDMI phy PLL clock + + clock-names: + items: + - const: pxo + - const: pll3 + - const: pll8_vote + - const: dsi1pll + - const: dsi1pllbyte + - const: dsi2pll + - const: dsi2pllbyte + - const: hdmipll + - if: properties: compatible: From patchwork Thu Jun 23 12:04:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 584350 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAAB5C43334 for ; Thu, 23 Jun 2022 12:04:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231550AbiFWME3 (ORCPT ); Thu, 23 Jun 2022 08:04:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231439AbiFWME0 (ORCPT ); Thu, 23 Jun 2022 08:04:26 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A643548E42 for ; Thu, 23 Jun 2022 05:04:23 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id j21so19876724lfe.1 for ; Thu, 23 Jun 2022 05:04:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gdP9CJH7RxrDJbJ3aC/127OzAOgW3yLRRayvoCqdrNA=; b=R1CZ6pvPH1ojBxabn3YYwGDCnwCGWqBC9efsi1bRJkbBXiUC3PrEdeqYfgpEQZSFfO cQJlEkj4lR1x2Cl9j1LKOtLR8z3BZoO61cbvV3uM6TPsA1suM7cVgC6s0EC9IbiQ7Gef tV8GHB/jKGIqqY7glS3f8pCvlrD5w3br9guxiT3gALdtpWRw26WdU01GLd7r8xAZiVKk TOWGgrOFcbEoTocyibSE4PiToBlSRFgZs9fVvTivePKLaH+p7EGPwk47Cb2QiMVMBWeK IQueSNepQKSwmxWb9k9zXqTTr6m84yucp+h8WO525bKygIV5OmnuSlbect3F7SblEMCs pJvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gdP9CJH7RxrDJbJ3aC/127OzAOgW3yLRRayvoCqdrNA=; b=7v51KbGUn8U9KrFszaBgCfJMlK6BPAtD7Ak4LGTcZ6DWHyb3teKRI9V8+NGcm5CV9l bABtJAqNtwQu7kbFF8UZuevPpDwTDEg49EVGs6V169biUtY/+fdjeZJ2KUHkdWamZl9e 8Nt5ttNJZuP3FAKwnMbU7Vw60MsZWZS7xEnmR1e4sgTfTrundWqi9VyBFxcQT1Mq+ydm 2cYMV9n0SmO1Su2OAplDeK8/Qsby8/6VoqSWA5/zo2GyTcqIhkXr0QKluPbfpyosVpjK XaKbCFmW/W9HeO1bEhl6kG6ZYG7qC5oaMu/kG1R2wRo2wdr+lLC6snbzYP6EQxbPG2Mh SoWA== X-Gm-Message-State: AJIora8DWpqzo0LnyJAB9M6oSa51pX0IYSo5AmIpQBiNpcN3NxZ2/m09 MXXDxnJ8yMH/5Ho5Ans7H/vdag== X-Google-Smtp-Source: AGRyM1u8JcEhvSorV+lIE5XDnPy70m/VkntPGziLhooM7PujgxP9emfPuYCB0KSO580pkxwNfmgNSw== X-Received: by 2002:a05:6512:acc:b0:47f:769e:6aef with SMTP id n12-20020a0565120acc00b0047f769e6aefmr5242524lfu.26.1655985861974; Thu, 23 Jun 2022 05:04:21 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id 18-20020ac25f52000000b0047f6b4a53cdsm1799888lfz.172.2022.06.23.05.04.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 05:04:21 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 03/15] clk: qcom: gcc-msm8960: use ARRAY_SIZE instead of specifying num_parents Date: Thu, 23 Jun 2022 15:04:06 +0300 Message-Id: <20220623120418.250589-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> References: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-msm8960.c | 96 +++++++++++++++++----------------- 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c index a6e13b91e4c8..cf1bccab2fa5 100644 --- a/drivers/clk/qcom/gcc-msm8960.c +++ b/drivers/clk/qcom/gcc-msm8960.c @@ -349,7 +349,7 @@ static struct clk_rcg gsbi1_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -400,7 +400,7 @@ static struct clk_rcg gsbi2_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -451,7 +451,7 @@ static struct clk_rcg gsbi3_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi3_uart_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -502,7 +502,7 @@ static struct clk_rcg gsbi4_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -553,7 +553,7 @@ static struct clk_rcg gsbi5_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -604,7 +604,7 @@ static struct clk_rcg gsbi6_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -655,7 +655,7 @@ static struct clk_rcg gsbi7_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -706,7 +706,7 @@ static struct clk_rcg gsbi8_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi8_uart_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -755,7 +755,7 @@ static struct clk_rcg gsbi9_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi9_uart_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -804,7 +804,7 @@ static struct clk_rcg gsbi10_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi10_uart_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -853,7 +853,7 @@ static struct clk_rcg gsbi11_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi11_uart_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -902,7 +902,7 @@ static struct clk_rcg gsbi12_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi12_uart_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -964,7 +964,7 @@ static struct clk_rcg gsbi1_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1013,7 +1013,7 @@ static struct clk_rcg gsbi2_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1062,7 +1062,7 @@ static struct clk_rcg gsbi3_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi3_qup_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1111,7 +1111,7 @@ static struct clk_rcg gsbi4_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1160,7 +1160,7 @@ static struct clk_rcg gsbi5_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1209,7 +1209,7 @@ static struct clk_rcg gsbi6_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1258,7 +1258,7 @@ static struct clk_rcg gsbi7_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1307,7 +1307,7 @@ static struct clk_rcg gsbi8_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi8_qup_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1356,7 +1356,7 @@ static struct clk_rcg gsbi9_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi9_qup_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1405,7 +1405,7 @@ static struct clk_rcg gsbi10_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi10_qup_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1454,7 +1454,7 @@ static struct clk_rcg gsbi11_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi11_qup_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1503,7 +1503,7 @@ static struct clk_rcg gsbi12_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi12_qup_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1565,7 +1565,7 @@ static struct clk_rcg gp0_src = { .hw.init = &(struct clk_init_data){ .name = "gp0_src", .parent_names = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1614,7 +1614,7 @@ static struct clk_rcg gp1_src = { .hw.init = &(struct clk_init_data){ .name = "gp1_src", .parent_names = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1663,7 +1663,7 @@ static struct clk_rcg gp2_src = { .hw.init = &(struct clk_init_data){ .name = "gp2_src", .parent_names = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1715,7 +1715,7 @@ static struct clk_rcg prng_src = { .hw.init = &(struct clk_init_data){ .name = "prng_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, }, @@ -1777,7 +1777,7 @@ static struct clk_rcg sdc1_src = { .hw.init = &(struct clk_init_data){ .name = "sdc1_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1825,7 +1825,7 @@ static struct clk_rcg sdc2_src = { .hw.init = &(struct clk_init_data){ .name = "sdc2_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1873,7 +1873,7 @@ static struct clk_rcg sdc3_src = { .hw.init = &(struct clk_init_data){ .name = "sdc3_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1921,7 +1921,7 @@ static struct clk_rcg sdc4_src = { .hw.init = &(struct clk_init_data){ .name = "sdc4_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1969,7 +1969,7 @@ static struct clk_rcg sdc5_src = { .hw.init = &(struct clk_init_data){ .name = "sdc5_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -2022,7 +2022,7 @@ static struct clk_rcg tsif_ref_src = { .hw.init = &(struct clk_init_data){ .name = "tsif_ref_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2076,7 +2076,7 @@ static struct clk_rcg usb_hs1_xcvr_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2125,7 +2125,7 @@ static struct clk_rcg usb_hs3_xcvr_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hs3_xcvr_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2174,7 +2174,7 @@ static struct clk_rcg usb_hs4_xcvr_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hs4_xcvr_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2223,7 +2223,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hsic_xcvr_fs_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2241,7 +2241,7 @@ static struct clk_branch usb_hsic_xcvr_fs_clk = { .hw.init = &(struct clk_init_data){ .name = "usb_hsic_xcvr_fs_clk", .parent_names = usb_hsic_xcvr_fs_src_p, - .num_parents = 1, + .num_parents = ARRAY_SIZE(usb_hsic_xcvr_fs_src_p), .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -2256,7 +2256,7 @@ static struct clk_branch usb_hsic_system_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .parent_names = usb_hsic_xcvr_fs_src_p, - .num_parents = 1, + .num_parents = ARRAY_SIZE(usb_hsic_xcvr_fs_src_p), .name = "usb_hsic_system_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2318,7 +2318,7 @@ static struct clk_rcg usb_fs1_xcvr_fs_src = { .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_fs_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2336,7 +2336,7 @@ static struct clk_branch usb_fs1_xcvr_fs_clk = { .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_fs_clk", .parent_names = usb_fs1_xcvr_fs_src_p, - .num_parents = 1, + .num_parents = ARRAY_SIZE(usb_fs1_xcvr_fs_src_p), .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -2351,7 +2351,7 @@ static struct clk_branch usb_fs1_system_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .parent_names = usb_fs1_xcvr_fs_src_p, - .num_parents = 1, + .num_parents = ARRAY_SIZE(usb_fs1_xcvr_fs_src_p), .name = "usb_fs1_system_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2385,7 +2385,7 @@ static struct clk_rcg usb_fs2_xcvr_fs_src = { .hw.init = &(struct clk_init_data){ .name = "usb_fs2_xcvr_fs_src", .parent_names = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2403,7 +2403,7 @@ static struct clk_branch usb_fs2_xcvr_fs_clk = { .hw.init = &(struct clk_init_data){ .name = "usb_fs2_xcvr_fs_clk", .parent_names = usb_fs2_xcvr_fs_src_p, - .num_parents = 1, + .num_parents = ARRAY_SIZE(usb_fs2_xcvr_fs_src_p), .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -2419,7 +2419,7 @@ static struct clk_branch usb_fs2_system_clk = { .hw.init = &(struct clk_init_data){ .name = "usb_fs2_system_clk", .parent_names = usb_fs2_xcvr_fs_src_p, - .num_parents = 1, + .num_parents = ARRAY_SIZE(usb_fs2_xcvr_fs_src_p), .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -2873,7 +2873,7 @@ static struct clk_rcg ce3_src = { .hw.init = &(struct clk_init_data){ .name = "ce3_src", .parent_names = gcc_pxo_pll8_pll3, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2935,7 +2935,7 @@ static struct clk_rcg sata_clk_src = { .hw.init = &(struct clk_init_data){ .name = "sata_clk_src", .parent_names = gcc_pxo_pll8_pll3, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, From patchwork Thu Jun 23 12:04:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 584347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26E8DCCA488 for ; Thu, 23 Jun 2022 12:04:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231614AbiFWMEj (ORCPT ); Thu, 23 Jun 2022 08:04:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231629AbiFWMEg (ORCPT ); Thu, 23 Jun 2022 08:04:36 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 486DD49918 for ; Thu, 23 Jun 2022 05:04:28 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id c30so23019577ljr.9 for ; Thu, 23 Jun 2022 05:04:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bIQD0JLz3hwfzeywuJjz4RFSXqLmEyBqYNGSe42ZS8o=; b=e682+5BxHtsPh62hwY6pVO3CHBpdSjURVWAaC6F2eh6wxnCIgQcG2RWhXu0/n12hk9 +0smeNhje0RFu8+4lWjGaCK9/3bPxx27S8q89YxpYtzlfLBpvTVywxoExNR29r/Gwc7X kl/py0CEnTSwIcxQmuJYJU46xhB/Ts3sK68RQlUhOXStq9UcM1HLAxjUsN92vrJrRpg6 D0e2+5raCuzw+fTCj22gCvxS7mUq/wFd1OjseIpL7kAsebtMJ/tuUKml9sy/MzHxQ426 7nJq9RxbuqV8lQBtp0HGXYFAhiXA7rSUmT1C0bc7X4FJ9evvO+T5RbQ07zPRgbXHabHh K4ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bIQD0JLz3hwfzeywuJjz4RFSXqLmEyBqYNGSe42ZS8o=; b=deXtfZ8pqUcC4ZNKGpIR/ln9AFUw+nAnBfFrwITMR4NPUL3zox0OAw12rskpPpqb55 yTrzIwote360uUMOPYgVTtAgJW+DTyPciUNMcB+MK5KeQSumqibfBR9ibeyPRMr6EdG4 CBeI4hrZZshPM0uOe4hNhKaSvRIgWlqNsaqTAUnHf9B+PnyfkT4G8c9JCA39EOozlpsl 43iPP9REg8XcfiPbmPBGLVclkeXTLvb1K2+8tRPK1EldwfWdpOkP/r/k6rbR182D0TjF Wv0oDvBCX7PqqsbufSlVzcYlik4I3YL5kd6kb+ISc1OS4RwvOHsIyHkyw8b7Q7ozj8Bf Pt+w== X-Gm-Message-State: AJIora9h2XksaiIGf3gYIwD9Ipl1WL8/0RZ6yc/bAeP4MrC4z3Bi6Q4H 1YGB3xgAX8Wm4ZdsC1a6LU+Pnw== X-Google-Smtp-Source: AGRyM1tvi4J5mES8sTS2kkvUsYmYy1IvJelxL4zehStAIPVZVbt3iDuhCkxnvWSyJ7plCStgAMc57g== X-Received: by 2002:a2e:a90d:0:b0:25a:7edb:4034 with SMTP id j13-20020a2ea90d000000b0025a7edb4034mr4550229ljq.129.1655985865110; Thu, 23 Jun 2022 05:04:25 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id 18-20020ac25f52000000b0047f6b4a53cdsm1799888lfz.172.2022.06.23.05.04.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 05:04:24 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 07/15] clk: qcom: mmcc-msm8960: use ARRAY_SIZE instead of specifying num_parents Date: Thu, 23 Jun 2022 15:04:10 +0300 Message-Id: <20220623120418.250589-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> References: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/mmcc-msm8960.c | 84 ++++++++++++++++----------------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c index aaaad65b6458..d5c989a71e13 100644 --- a/drivers/clk/qcom/mmcc-msm8960.c +++ b/drivers/clk/qcom/mmcc-msm8960.c @@ -193,7 +193,7 @@ static struct clk_rcg camclk0_src = { .hw.init = &(struct clk_init_data){ .name = "camclk0_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, }, @@ -242,7 +242,7 @@ static struct clk_rcg camclk1_src = { .hw.init = &(struct clk_init_data){ .name = "camclk1_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, }, @@ -291,7 +291,7 @@ static struct clk_rcg camclk2_src = { .hw.init = &(struct clk_init_data){ .name = "camclk2_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, }, @@ -346,7 +346,7 @@ static struct clk_rcg csi0_src = { .hw.init = &(struct clk_init_data){ .name = "csi0_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, }, @@ -410,7 +410,7 @@ static struct clk_rcg csi1_src = { .hw.init = &(struct clk_init_data){ .name = "csi1_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, }, @@ -474,7 +474,7 @@ static struct clk_rcg csi2_src = { .hw.init = &(struct clk_init_data){ .name = "csi2_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, }, @@ -619,7 +619,7 @@ static struct clk_pix_rdi csi_pix_clk = { .hw.init = &(struct clk_init_data){ .name = "csi_pix_clk", .parent_names = pix_rdi_parents, - .num_parents = 3, + .num_parents = ARRAY_SIZE(pix_rdi_parents), .ops = &clk_ops_pix_rdi, }, }, @@ -636,7 +636,7 @@ static struct clk_pix_rdi csi_pix1_clk = { .hw.init = &(struct clk_init_data){ .name = "csi_pix1_clk", .parent_names = pix_rdi_parents, - .num_parents = 3, + .num_parents = ARRAY_SIZE(pix_rdi_parents), .ops = &clk_ops_pix_rdi, }, }, @@ -653,7 +653,7 @@ static struct clk_pix_rdi csi_rdi_clk = { .hw.init = &(struct clk_init_data){ .name = "csi_rdi_clk", .parent_names = pix_rdi_parents, - .num_parents = 3, + .num_parents = ARRAY_SIZE(pix_rdi_parents), .ops = &clk_ops_pix_rdi, }, }, @@ -670,7 +670,7 @@ static struct clk_pix_rdi csi_rdi1_clk = { .hw.init = &(struct clk_init_data){ .name = "csi_rdi1_clk", .parent_names = pix_rdi_parents, - .num_parents = 3, + .num_parents = ARRAY_SIZE(pix_rdi_parents), .ops = &clk_ops_pix_rdi, }, }, @@ -687,7 +687,7 @@ static struct clk_pix_rdi csi_rdi2_clk = { .hw.init = &(struct clk_init_data){ .name = "csi_rdi2_clk", .parent_names = pix_rdi_parents, - .num_parents = 3, + .num_parents = ARRAY_SIZE(pix_rdi_parents), .ops = &clk_ops_pix_rdi, }, }, @@ -726,7 +726,7 @@ static struct clk_rcg csiphytimer_src = { .hw.init = &(struct clk_init_data){ .name = "csiphytimer_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, }, @@ -742,7 +742,7 @@ static struct clk_branch csiphy0_timer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .parent_names = csixphy_timer_src, - .num_parents = 1, + .num_parents = ARRAY_SIZE(csixphy_timer_src), .name = "csiphy0_timer_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -758,7 +758,7 @@ static struct clk_branch csiphy1_timer_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .parent_names = csixphy_timer_src, - .num_parents = 1, + .num_parents = ARRAY_SIZE(csixphy_timer_src), .name = "csiphy1_timer_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -774,7 +774,7 @@ static struct clk_branch csiphy2_timer_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .parent_names = csixphy_timer_src, - .num_parents = 1, + .num_parents = ARRAY_SIZE(csixphy_timer_src), .name = "csiphy2_timer_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -836,7 +836,7 @@ static struct clk_dyn_rcg gfx2d0_src = { .hw.init = &(struct clk_init_data){ .name = "gfx2d0_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_dyn_rcg_ops, }, }, @@ -896,7 +896,7 @@ static struct clk_dyn_rcg gfx2d1_src = { .hw.init = &(struct clk_init_data){ .name = "gfx2d1_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_dyn_rcg_ops, }, }, @@ -997,7 +997,7 @@ static struct clk_dyn_rcg gfx3d_src = { .hw.init = &(struct clk_init_data){ .name = "gfx3d_src", .parent_names = mmcc_pxo_pll8_pll2_pll3, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll3), .ops = &clk_dyn_rcg_ops, }, }, @@ -1006,7 +1006,7 @@ static struct clk_dyn_rcg gfx3d_src = { static const struct clk_init_data gfx3d_8064_init = { .name = "gfx3d_src", .parent_names = mmcc_pxo_pll8_pll2_pll15, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll15), .ops = &clk_dyn_rcg_ops, }; @@ -1075,7 +1075,7 @@ static struct clk_dyn_rcg vcap_src = { .hw.init = &(struct clk_init_data){ .name = "vcap_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_dyn_rcg_ops, }, }, @@ -1154,7 +1154,7 @@ static struct clk_rcg ijpeg_src = { .hw.init = &(struct clk_init_data){ .name = "ijpeg_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, }, @@ -1202,7 +1202,7 @@ static struct clk_rcg jpegd_src = { .hw.init = &(struct clk_init_data){ .name = "jpegd_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, }, @@ -1282,7 +1282,7 @@ static struct clk_dyn_rcg mdp_src = { .hw.init = &(struct clk_init_data){ .name = "mdp_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_dyn_rcg_ops, }, }, @@ -1381,7 +1381,7 @@ static struct clk_dyn_rcg rot_src = { .hw.init = &(struct clk_init_data){ .name = "rot_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_dyn_rcg_ops, }, }, @@ -1444,7 +1444,7 @@ static struct clk_rcg tv_src = { .hw.init = &(struct clk_init_data){ .name = "tv_src", .parent_names = mmcc_pxo_hdmi, - .num_parents = 2, + .num_parents = ARRAY_SIZE(mmcc_pxo_hdmi), .ops = &clk_rcg_bypass_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -1461,7 +1461,7 @@ static struct clk_branch tv_enc_clk = { .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .parent_names = tv_src_name, - .num_parents = 1, + .num_parents = ARRAY_SIZE(tv_src_name), .name = "tv_enc_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1477,7 +1477,7 @@ static struct clk_branch tv_dac_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .parent_names = tv_src_name, - .num_parents = 1, + .num_parents = ARRAY_SIZE(tv_src_name), .name = "tv_dac_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1493,7 +1493,7 @@ static struct clk_branch mdp_tv_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .parent_names = tv_src_name, - .num_parents = 1, + .num_parents = ARRAY_SIZE(tv_src_name), .name = "mdp_tv_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1509,7 +1509,7 @@ static struct clk_branch hdmi_tv_clk = { .enable_mask = BIT(12), .hw.init = &(struct clk_init_data){ .parent_names = tv_src_name, - .num_parents = 1, + .num_parents = ARRAY_SIZE(tv_src_name), .name = "hdmi_tv_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1525,7 +1525,7 @@ static struct clk_branch rgb_tv_clk = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .parent_names = tv_src_name, - .num_parents = 1, + .num_parents = ARRAY_SIZE(tv_src_name), .name = "rgb_tv_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1541,7 +1541,7 @@ static struct clk_branch npl_tv_clk = { .enable_mask = BIT(16), .hw.init = &(struct clk_init_data){ .parent_names = tv_src_name, - .num_parents = 1, + .num_parents = ARRAY_SIZE(tv_src_name), .name = "npl_tv_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1615,7 +1615,7 @@ static struct clk_dyn_rcg vcodec_src = { .hw.init = &(struct clk_init_data){ .name = "vcodec_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_dyn_rcg_ops, }, }, @@ -1666,7 +1666,7 @@ static struct clk_rcg vpe_src = { .hw.init = &(struct clk_init_data){ .name = "vpe_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, }, @@ -1734,7 +1734,7 @@ static struct clk_rcg vfe_src = { .hw.init = &(struct clk_init_data){ .name = "vfe_src", .parent_names = mmcc_pxo_pll8_pll2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, }, @@ -2068,7 +2068,7 @@ static struct clk_rcg dsi1_src = { .hw.init = &(struct clk_init_data){ .name = "dsi1_src", .parent_names = mmcc_pxo_dsi2_dsi1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), .ops = &clk_rcg_bypass2_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -2116,7 +2116,7 @@ static struct clk_rcg dsi2_src = { .hw.init = &(struct clk_init_data){ .name = "dsi2_src", .parent_names = mmcc_pxo_dsi2_dsi1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), .ops = &clk_rcg_bypass2_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -2155,7 +2155,7 @@ static struct clk_rcg dsi1_byte_src = { .hw.init = &(struct clk_init_data){ .name = "dsi1_byte_src", .parent_names = mmcc_pxo_dsi1_dsi2_byte, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), .ops = &clk_rcg_bypass2_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -2194,7 +2194,7 @@ static struct clk_rcg dsi2_byte_src = { .hw.init = &(struct clk_init_data){ .name = "dsi2_byte_src", .parent_names = mmcc_pxo_dsi1_dsi2_byte, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), .ops = &clk_rcg_bypass2_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -2233,7 +2233,7 @@ static struct clk_rcg dsi1_esc_src = { .hw.init = &(struct clk_init_data){ .name = "dsi1_esc_src", .parent_names = mmcc_pxo_dsi1_dsi2_byte, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), .ops = &clk_rcg_esc_ops, }, }, @@ -2271,7 +2271,7 @@ static struct clk_rcg dsi2_esc_src = { .hw.init = &(struct clk_init_data){ .name = "dsi2_esc_src", .parent_names = mmcc_pxo_dsi1_dsi2_byte, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), .ops = &clk_rcg_esc_ops, }, }, @@ -2318,7 +2318,7 @@ static struct clk_rcg dsi1_pixel_src = { .hw.init = &(struct clk_init_data){ .name = "dsi1_pixel_src", .parent_names = mmcc_pxo_dsi2_dsi1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), .ops = &clk_rcg_pixel_ops, }, }, @@ -2365,7 +2365,7 @@ static struct clk_rcg dsi2_pixel_src = { .hw.init = &(struct clk_init_data){ .name = "dsi2_pixel_src", .parent_names = mmcc_pxo_dsi2_dsi1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), .ops = &clk_rcg_pixel_ops, }, }, From patchwork Thu Jun 23 12:04:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 584349 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7107FCCA485 for ; Thu, 23 Jun 2022 12:04:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231691AbiFWMEh (ORCPT ); Thu, 23 Jun 2022 08:04:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231430AbiFWMEa (ORCPT ); Thu, 23 Jun 2022 08:04:30 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E58E0488B7 for ; Thu, 23 Jun 2022 05:04:26 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id s14so16297850ljs.3 for ; Thu, 23 Jun 2022 05:04:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wgNRajidUBsVnzZirjYFoTrI0Y1nfrcAjaj1yhGj2t8=; b=nrj9LZK6VwCvN0CaZ3KFeqCp+CTwx6BDSq/wzPzbuEWB84C7jHzpUbfDZCGPGYSdWs k0bX1CSJltLl8I6yJ9y7bSaujXGc4FJEOUEg4f31adfNBtYHb4drjZgXFhFyHpGVSHGz ar158o+Vm7EqNoO+CHSHzIVatUTceXMjSxJw+fP9s/FnqUM6TUWGwnsIYZVTCD6EizMK veniAJMJOTPTP19x+qUtEuMfCTzICmHYsGqsyCP4Y2swEy5G+bx6xrNVHYUb0ynHqgLy qHpLK9lMNHSowsc3hanL2HZaA3aCa7ufzqP2AfB++tadksgzRiqE6aM/YdAlZBIG/zHS t55A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wgNRajidUBsVnzZirjYFoTrI0Y1nfrcAjaj1yhGj2t8=; b=SmO8tf6gNzUxnwrc3P9PMmzw5KKY3cdfgVFjzySxd6iD+7hQXSt27zUqeR2h/grrJR PyYwMNmZk/dE5DWvOtQ/3mEXVaYp7GlbQq2qMR+3miN97ZO8ZfD3y2PF+HTC/39LR26W ibCt/OlIJO4M/G/HF4qpugZ9FQ6WJoJkwOPEgMOCU4pyRyS/rk0SKMHssJv8CNVHMo9t jowXWX2sodQYkZmQ7i5M2fcZsg7s3jah8cfCP0EeR0/ANsgG1QiNBYkg5XDerVuFwYAq lOpULOSLNJi8ABPv/CdvdQqtf+hV99ZPNJc9VQ3tTmxw3ipGbrSkJOgIHrzKOfiHiFEU OLlQ== X-Gm-Message-State: AJIora9s6AP6YXMW0ktlK9AzBeK0SXUiDRADK/roNM3Q79gF+3PEWPwv 727KodZASBsktUSkg3U0JYwGlA== X-Google-Smtp-Source: AGRyM1tkX9ODmrhCNqyy3YTz8DKNqpMcK/+d/JgqX2aBn7ledReT+up+NSfvqEZ2bJEhrUFZvd5nJw== X-Received: by 2002:a05:651c:229:b0:25a:8352:cef1 with SMTP id z9-20020a05651c022900b0025a8352cef1mr4577910ljn.291.1655985865778; Thu, 23 Jun 2022 05:04:25 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id 18-20020ac25f52000000b0047f6b4a53cdsm1799888lfz.172.2022.06.23.05.04.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 05:04:25 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 08/15] clk: qcom: mmcc-msm8960: move clock parent tables down Date: Thu, 23 Jun 2022 15:04:11 +0300 Message-Id: <20220623120418.250589-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> References: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Move clock parent tables down, after the PLL declrataions, so that we can use pll hw clock fields in the next commit. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/mmcc-msm8960.c | 92 ++++++++++++++++----------------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c index d5c989a71e13..0cab41da80ff 100644 --- a/drivers/clk/qcom/mmcc-msm8960.c +++ b/drivers/clk/qcom/mmcc-msm8960.c @@ -41,6 +41,52 @@ enum { #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n } +static struct clk_pll pll2 = { + .l_reg = 0x320, + .m_reg = 0x324, + .n_reg = 0x328, + .config_reg = 0x32c, + .mode_reg = 0x31c, + .status_reg = 0x334, + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll2", + .parent_names = (const char *[]){ "pxo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_pll pll15 = { + .l_reg = 0x33c, + .m_reg = 0x340, + .n_reg = 0x344, + .config_reg = 0x348, + .mode_reg = 0x338, + .status_reg = 0x350, + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll15", + .parent_names = (const char *[]){ "pxo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static const struct pll_config pll15_config = { + .l = 33, + .m = 1, + .n = 3, + .vco_val = 0x2 << 16, + .vco_mask = 0x3 << 16, + .pre_div_val = 0x0, + .pre_div_mask = BIT(19), + .post_div_val = 0x0, + .post_div_mask = 0x3 << 20, + .mn_ena_mask = BIT(22), + .main_output_mask = BIT(23), +}; + static const struct parent_map mmcc_pxo_pll8_pll2_map[] = { { P_PXO, 0 }, { P_PLL8, 2 }, @@ -105,52 +151,6 @@ static const char * const mmcc_pxo_dsi1_dsi2_byte[] = { "dsi2pllbyte", }; -static struct clk_pll pll2 = { - .l_reg = 0x320, - .m_reg = 0x324, - .n_reg = 0x328, - .config_reg = 0x32c, - .mode_reg = 0x31c, - .status_reg = 0x334, - .status_bit = 16, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll2", - .parent_names = (const char *[]){ "pxo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_pll pll15 = { - .l_reg = 0x33c, - .m_reg = 0x340, - .n_reg = 0x344, - .config_reg = 0x348, - .mode_reg = 0x338, - .status_reg = 0x350, - .status_bit = 16, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll15", - .parent_names = (const char *[]){ "pxo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static const struct pll_config pll15_config = { - .l = 33, - .m = 1, - .n = 3, - .vco_val = 0x2 << 16, - .vco_mask = 0x3 << 16, - .pre_div_val = 0x0, - .pre_div_mask = BIT(19), - .post_div_val = 0x0, - .post_div_mask = 0x3 << 20, - .mn_ena_mask = BIT(22), - .main_output_mask = BIT(23), -}; - static struct freq_tbl clk_tbl_cam[] = { { 6000000, P_PLL8, 4, 1, 16 }, { 8000000, P_PLL8, 4, 1, 12 }, From patchwork Thu Jun 23 12:04:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 584344 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5361BCCA47C for ; Thu, 23 Jun 2022 12:04:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231767AbiFWMEl (ORCPT ); Thu, 23 Jun 2022 08:04:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231646AbiFWMEg (ORCPT ); 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Thu, 23 Jun 2022 05:04:26 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 09/15] clk: qcom: mmcc-msm8960: use parent_hws/_data instead of parent_names Date: Thu, 23 Jun 2022 15:04:12 +0300 Message-Id: <20220623120418.250589-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> References: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/mmcc-msm8960.c | 322 ++++++++++++++++++++------------ 1 file changed, 203 insertions(+), 119 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c index 0cab41da80ff..6bf908a51f53 100644 --- a/drivers/clk/qcom/mmcc-msm8960.c +++ b/drivers/clk/qcom/mmcc-msm8960.c @@ -51,7 +51,9 @@ static struct clk_pll pll2 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll2", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "pxo", .name = "pxo_board" }, + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -67,7 +69,9 @@ static struct clk_pll pll15 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll15", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "pxo", .name = "pxo_board" }, + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -93,10 +97,10 @@ static const struct parent_map mmcc_pxo_pll8_pll2_map[] = { { P_PLL2, 1 } }; -static const char * const mmcc_pxo_pll8_pll2[] = { - "pxo", - "pll8_vote", - "pll2", +static const struct clk_parent_data mmcc_pxo_pll8_pll2[] = { + { .fw_name = "pxo", .name = "pxo_board" }, + { .fw_name = "pll8_vote", .name = "pll8_vote" }, + { .hw = &pll2.clkr.hw }, }; static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = { @@ -106,11 +110,11 @@ static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = { { P_PLL3, 3 } }; -static const char * const mmcc_pxo_pll8_pll2_pll15[] = { - "pxo", - "pll8_vote", - "pll2", - "pll15", +static const struct clk_parent_data mmcc_pxo_pll8_pll2_pll15[] = { + { .fw_name = "pxo", .name = "pxo_board" }, + { .fw_name = "pll8_vote", .name = "pll8_vote" }, + { .hw = &pll2.clkr.hw }, + { .hw = &pll15.clkr.hw }, }; static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = { @@ -120,11 +124,11 @@ static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = { { P_PLL15, 3 } }; -static const char * const mmcc_pxo_pll8_pll2_pll3[] = { - "pxo", - "pll8_vote", - "pll2", - "pll3", +static const struct clk_parent_data mmcc_pxo_pll8_pll2_pll3[] = { + { .fw_name = "pxo", .name = "pxo_board" }, + { .fw_name = "pll8_vote", .name = "pll8_vote" }, + { .hw = &pll2.clkr.hw }, + { .fw_name = "pll3", .name = "pll3" }, }; static const struct parent_map mmcc_pxo_dsi2_dsi1_map[] = { @@ -133,10 +137,10 @@ static const struct parent_map mmcc_pxo_dsi2_dsi1_map[] = { { P_DSI1_PLL_DSICLK, 3 }, }; -static const char * const mmcc_pxo_dsi2_dsi1[] = { - "pxo", - "dsi2pll", - "dsi1pll", +static const struct clk_parent_data mmcc_pxo_dsi2_dsi1[] = { + { .fw_name = "pxo", .name = "pxo_board" }, + { .fw_name = "dsi2pll", .name = "dsi2pll" }, + { .fw_name = "dsi1pll", .name = "dsi1pll" }, }; static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = { @@ -145,10 +149,10 @@ static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = { { P_DSI2_PLL_BYTECLK, 2 }, }; -static const char * const mmcc_pxo_dsi1_dsi2_byte[] = { - "pxo", - "dsi1pllbyte", - "dsi2pllbyte", +static const struct clk_parent_data mmcc_pxo_dsi1_dsi2_byte[] = { + { .fw_name = "pxo", .name = "pxo_board" }, + { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" }, + { .fw_name = "dsi2pllbyte", .name = "dsi2pllbyte" }, }; static struct freq_tbl clk_tbl_cam[] = { @@ -192,7 +196,7 @@ static struct clk_rcg camclk0_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "camclk0_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, @@ -207,7 +211,9 @@ static struct clk_branch camclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camclk0_clk", - .parent_names = (const char *[]){ "camclk0_src" }, + .parent_hws = (const struct clk_hw*[]){ + &camclk0_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -241,7 +247,7 @@ static struct clk_rcg camclk1_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "camclk1_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, @@ -256,7 +262,9 @@ static struct clk_branch camclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camclk1_clk", - .parent_names = (const char *[]){ "camclk1_src" }, + .parent_hws = (const struct clk_hw*[]){ + &camclk1_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -290,7 +298,7 @@ static struct clk_rcg camclk2_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "camclk2_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, @@ -305,7 +313,9 @@ static struct clk_branch camclk2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camclk2_clk", - .parent_names = (const char *[]){ "camclk2_src" }, + .parent_hws = (const struct clk_hw*[]){ + &camclk2_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -345,7 +355,7 @@ static struct clk_rcg csi0_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "csi0_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, @@ -359,7 +369,9 @@ static struct clk_branch csi0_clk = { .enable_reg = 0x0040, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "csi0_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi0_src.clkr.hw + }, .num_parents = 1, .name = "csi0_clk", .ops = &clk_branch_ops, @@ -375,7 +387,9 @@ static struct clk_branch csi0_phy_clk = { .enable_reg = 0x0040, .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "csi0_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi0_src.clkr.hw + }, .num_parents = 1, .name = "csi0_phy_clk", .ops = &clk_branch_ops, @@ -409,7 +423,7 @@ static struct clk_rcg csi1_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "csi1_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, @@ -423,7 +437,9 @@ static struct clk_branch csi1_clk = { .enable_reg = 0x0024, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "csi1_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi1_src.clkr.hw + }, .num_parents = 1, .name = "csi1_clk", .ops = &clk_branch_ops, @@ -439,7 +455,9 @@ static struct clk_branch csi1_phy_clk = { .enable_reg = 0x0024, .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "csi1_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi1_src.clkr.hw + }, .num_parents = 1, .name = "csi1_phy_clk", .ops = &clk_branch_ops, @@ -473,7 +491,7 @@ static struct clk_rcg csi2_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "csi2_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, @@ -487,7 +505,9 @@ static struct clk_branch csi2_clk = { .enable_reg = 0x022c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "csi2_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi2_src.clkr.hw + }, .num_parents = 1, .name = "csi2_clk", .ops = &clk_branch_ops, @@ -503,7 +523,9 @@ static struct clk_branch csi2_phy_clk = { .enable_reg = 0x022c, .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "csi2_src" }, + .parent_hws = (const struct clk_hw*[]){ + &csi2_src.clkr.hw + }, .num_parents = 1, .name = "csi2_phy_clk", .ops = &clk_branch_ops, @@ -602,10 +624,10 @@ static const struct clk_ops clk_ops_pix_rdi = { .determine_rate = __clk_mux_determine_rate, }; -static const char * const pix_rdi_parents[] = { - "csi0_clk", - "csi1_clk", - "csi2_clk", +static const struct clk_hw *pix_rdi_parents[] = { + &csi0_clk.clkr.hw, + &csi1_clk.clkr.hw, + &csi2_clk.clkr.hw, }; static struct clk_pix_rdi csi_pix_clk = { @@ -618,7 +640,7 @@ static struct clk_pix_rdi csi_pix_clk = { .enable_mask = BIT(26), .hw.init = &(struct clk_init_data){ .name = "csi_pix_clk", - .parent_names = pix_rdi_parents, + .parent_hws = pix_rdi_parents, .num_parents = ARRAY_SIZE(pix_rdi_parents), .ops = &clk_ops_pix_rdi, }, @@ -635,7 +657,7 @@ static struct clk_pix_rdi csi_pix1_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "csi_pix1_clk", - .parent_names = pix_rdi_parents, + .parent_hws = pix_rdi_parents, .num_parents = ARRAY_SIZE(pix_rdi_parents), .ops = &clk_ops_pix_rdi, }, @@ -652,7 +674,7 @@ static struct clk_pix_rdi csi_rdi_clk = { .enable_mask = BIT(13), .hw.init = &(struct clk_init_data){ .name = "csi_rdi_clk", - .parent_names = pix_rdi_parents, + .parent_hws = pix_rdi_parents, .num_parents = ARRAY_SIZE(pix_rdi_parents), .ops = &clk_ops_pix_rdi, }, @@ -669,7 +691,7 @@ static struct clk_pix_rdi csi_rdi1_clk = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "csi_rdi1_clk", - .parent_names = pix_rdi_parents, + .parent_hws = pix_rdi_parents, .num_parents = ARRAY_SIZE(pix_rdi_parents), .ops = &clk_ops_pix_rdi, }, @@ -686,7 +708,7 @@ static struct clk_pix_rdi csi_rdi2_clk = { .enable_mask = BIT(6), .hw.init = &(struct clk_init_data){ .name = "csi_rdi2_clk", - .parent_names = pix_rdi_parents, + .parent_hws = pix_rdi_parents, .num_parents = ARRAY_SIZE(pix_rdi_parents), .ops = &clk_ops_pix_rdi, }, @@ -725,15 +747,13 @@ static struct clk_rcg csiphytimer_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "csiphytimer_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, }, }; -static const char * const csixphy_timer_src[] = { "csiphytimer_src" }; - static struct clk_branch csiphy0_timer_clk = { .halt_reg = 0x01e8, .halt_bit = 17, @@ -741,8 +761,10 @@ static struct clk_branch csiphy0_timer_clk = { .enable_reg = 0x0160, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ - .parent_names = csixphy_timer_src, - .num_parents = ARRAY_SIZE(csixphy_timer_src), + .parent_hws = (const struct clk_hw*[]){ + &csiphytimer_src.clkr.hw, + }, + .num_parents = 1, .name = "csiphy0_timer_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -757,8 +779,10 @@ static struct clk_branch csiphy1_timer_clk = { .enable_reg = 0x0160, .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ - .parent_names = csixphy_timer_src, - .num_parents = ARRAY_SIZE(csixphy_timer_src), + .parent_hws = (const struct clk_hw*[]){ + &csiphytimer_src.clkr.hw, + }, + .num_parents = 1, .name = "csiphy1_timer_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -773,8 +797,10 @@ static struct clk_branch csiphy2_timer_clk = { .enable_reg = 0x0160, .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ - .parent_names = csixphy_timer_src, - .num_parents = ARRAY_SIZE(csixphy_timer_src), + .parent_hws = (const struct clk_hw*[]){ + &csiphytimer_src.clkr.hw, + }, + .num_parents = 1, .name = "csiphy2_timer_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -835,7 +861,7 @@ static struct clk_dyn_rcg gfx2d0_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "gfx2d0_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_dyn_rcg_ops, }, @@ -850,7 +876,9 @@ static struct clk_branch gfx2d0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gfx2d0_clk", - .parent_names = (const char *[]){ "gfx2d0_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gfx2d0_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -895,7 +923,7 @@ static struct clk_dyn_rcg gfx2d1_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "gfx2d1_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_dyn_rcg_ops, }, @@ -910,7 +938,9 @@ static struct clk_branch gfx2d1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gfx2d1_clk", - .parent_names = (const char *[]){ "gfx2d1_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gfx2d1_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -996,7 +1026,7 @@ static struct clk_dyn_rcg gfx3d_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "gfx3d_src", - .parent_names = mmcc_pxo_pll8_pll2_pll3, + .parent_data = mmcc_pxo_pll8_pll2_pll3, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll3), .ops = &clk_dyn_rcg_ops, }, @@ -1005,7 +1035,7 @@ static struct clk_dyn_rcg gfx3d_src = { static const struct clk_init_data gfx3d_8064_init = { .name = "gfx3d_src", - .parent_names = mmcc_pxo_pll8_pll2_pll15, + .parent_data = mmcc_pxo_pll8_pll2_pll15, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll15), .ops = &clk_dyn_rcg_ops, }; @@ -1018,7 +1048,9 @@ static struct clk_branch gfx3d_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gfx3d_clk", - .parent_names = (const char *[]){ "gfx3d_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gfx3d_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1074,7 +1106,7 @@ static struct clk_dyn_rcg vcap_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "vcap_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_dyn_rcg_ops, }, @@ -1089,7 +1121,9 @@ static struct clk_branch vcap_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "vcap_clk", - .parent_names = (const char *[]){ "vcap_src" }, + .parent_hws = (const struct clk_hw*[]){ + &vcap_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1105,7 +1139,9 @@ static struct clk_branch vcap_npl_clk = { .enable_mask = BIT(13), .hw.init = &(struct clk_init_data){ .name = "vcap_npl_clk", - .parent_names = (const char *[]){ "vcap_src" }, + .parent_hws = (const struct clk_hw*[]){ + &vcap_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1153,7 +1189,7 @@ static struct clk_rcg ijpeg_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "ijpeg_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, @@ -1168,7 +1204,9 @@ static struct clk_branch ijpeg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "ijpeg_clk", - .parent_names = (const char *[]){ "ijpeg_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ijpeg_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1201,7 +1239,7 @@ static struct clk_rcg jpegd_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "jpegd_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, @@ -1216,7 +1254,9 @@ static struct clk_branch jpegd_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "jpegd_clk", - .parent_names = (const char *[]){ "jpegd_src" }, + .parent_hws = (const struct clk_hw*[]){ + &jpegd_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1281,7 +1321,7 @@ static struct clk_dyn_rcg mdp_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "mdp_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_dyn_rcg_ops, }, @@ -1296,7 +1336,9 @@ static struct clk_branch mdp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdp_clk", - .parent_names = (const char *[]){ "mdp_src" }, + .parent_hws = (const struct clk_hw*[]){ + &mdp_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1311,7 +1353,9 @@ static struct clk_branch mdp_lut_clk = { .enable_reg = 0x016c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "mdp_src" }, + .parent_hws = (const struct clk_hw*[]){ + &mdp_src.clkr.hw + }, .num_parents = 1, .name = "mdp_lut_clk", .ops = &clk_branch_ops, @@ -1328,7 +1372,9 @@ static struct clk_branch mdp_vsync_clk = { .enable_mask = BIT(6), .hw.init = &(struct clk_init_data){ .name = "mdp_vsync_clk", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "pxo", .name = "pxo_board" }, + }, .num_parents = 1, .ops = &clk_branch_ops }, @@ -1380,7 +1426,7 @@ static struct clk_dyn_rcg rot_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "rot_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_dyn_rcg_ops, }, @@ -1395,7 +1441,9 @@ static struct clk_branch rot_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "rot_clk", - .parent_names = (const char *[]){ "rot_src" }, + .parent_hws = (const struct clk_hw*[]){ + &rot_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1408,9 +1456,9 @@ static const struct parent_map mmcc_pxo_hdmi_map[] = { { P_HDMI_PLL, 3 } }; -static const char * const mmcc_pxo_hdmi[] = { - "pxo", - "hdmi_pll", +static const struct clk_parent_data mmcc_pxo_hdmi[] = { + { .fw_name = "pxo", .name = "pxo_board" }, + { .fw_name = "hdmipll", .name = "hdmi_pll" }, }; static struct freq_tbl clk_tbl_tv[] = { @@ -1443,7 +1491,7 @@ static struct clk_rcg tv_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "tv_src", - .parent_names = mmcc_pxo_hdmi, + .parent_data = mmcc_pxo_hdmi, .num_parents = ARRAY_SIZE(mmcc_pxo_hdmi), .ops = &clk_rcg_bypass_ops, .flags = CLK_SET_RATE_PARENT, @@ -1451,8 +1499,6 @@ static struct clk_rcg tv_src = { }, }; -static const char * const tv_src_name[] = { "tv_src" }; - static struct clk_branch tv_enc_clk = { .halt_reg = 0x01d4, .halt_bit = 9, @@ -1460,8 +1506,10 @@ static struct clk_branch tv_enc_clk = { .enable_reg = 0x00ec, .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ - .parent_names = tv_src_name, - .num_parents = ARRAY_SIZE(tv_src_name), + .parent_hws = (const struct clk_hw*[]){ + &tv_src.clkr.hw, + }, + .num_parents = 1, .name = "tv_enc_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1476,8 +1524,10 @@ static struct clk_branch tv_dac_clk = { .enable_reg = 0x00ec, .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ - .parent_names = tv_src_name, - .num_parents = ARRAY_SIZE(tv_src_name), + .parent_hws = (const struct clk_hw*[]){ + &tv_src.clkr.hw, + }, + .num_parents = 1, .name = "tv_dac_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1492,8 +1542,10 @@ static struct clk_branch mdp_tv_clk = { .enable_reg = 0x00ec, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ - .parent_names = tv_src_name, - .num_parents = ARRAY_SIZE(tv_src_name), + .parent_hws = (const struct clk_hw*[]){ + &tv_src.clkr.hw, + }, + .num_parents = 1, .name = "mdp_tv_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1508,8 +1560,10 @@ static struct clk_branch hdmi_tv_clk = { .enable_reg = 0x00ec, .enable_mask = BIT(12), .hw.init = &(struct clk_init_data){ - .parent_names = tv_src_name, - .num_parents = ARRAY_SIZE(tv_src_name), + .parent_hws = (const struct clk_hw*[]){ + &tv_src.clkr.hw, + }, + .num_parents = 1, .name = "hdmi_tv_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1524,8 +1578,10 @@ static struct clk_branch rgb_tv_clk = { .enable_reg = 0x0124, .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ - .parent_names = tv_src_name, - .num_parents = ARRAY_SIZE(tv_src_name), + .parent_hws = (const struct clk_hw*[]){ + &tv_src.clkr.hw, + }, + .num_parents = 1, .name = "rgb_tv_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1540,8 +1596,10 @@ static struct clk_branch npl_tv_clk = { .enable_reg = 0x0124, .enable_mask = BIT(16), .hw.init = &(struct clk_init_data){ - .parent_names = tv_src_name, - .num_parents = ARRAY_SIZE(tv_src_name), + .parent_hws = (const struct clk_hw*[]){ + &tv_src.clkr.hw, + }, + .num_parents = 1, .name = "npl_tv_clk", .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1556,7 +1614,9 @@ static struct clk_branch hdmi_app_clk = { .enable_reg = 0x005c, .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = (const struct clk_parent_data[]){ + { .fw_name = "pxo", .name = "pxo_board" }, + }, .num_parents = 1, .name = "hdmi_app_clk", .ops = &clk_branch_ops, @@ -1614,7 +1674,7 @@ static struct clk_dyn_rcg vcodec_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "vcodec_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_dyn_rcg_ops, }, @@ -1629,7 +1689,9 @@ static struct clk_branch vcodec_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "vcodec_clk", - .parent_names = (const char *[]){ "vcodec_src" }, + .parent_hws = (const struct clk_hw*[]){ + &vcodec_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1665,7 +1727,7 @@ static struct clk_rcg vpe_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "vpe_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, @@ -1680,7 +1742,9 @@ static struct clk_branch vpe_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "vpe_clk", - .parent_names = (const char *[]){ "vpe_src" }, + .parent_hws = (const struct clk_hw*[]){ + &vpe_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1733,7 +1797,7 @@ static struct clk_rcg vfe_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "vfe_src", - .parent_names = mmcc_pxo_pll8_pll2, + .parent_data = mmcc_pxo_pll8_pll2, .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2), .ops = &clk_rcg_ops, }, @@ -1748,7 +1812,9 @@ static struct clk_branch vfe_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "vfe_clk", - .parent_names = (const char *[]){ "vfe_src" }, + .parent_hws = (const struct clk_hw*[]){ + &vfe_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1763,7 +1829,9 @@ static struct clk_branch vfe_csi_clk = { .enable_reg = 0x0104, .enable_mask = BIT(12), .hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "vfe_src" }, + .parent_hws = (const struct clk_hw*[]){ + &vfe_src.clkr.hw + }, .num_parents = 1, .name = "vfe_csi_clk", .ops = &clk_branch_ops, @@ -2067,7 +2135,7 @@ static struct clk_rcg dsi1_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "dsi1_src", - .parent_names = mmcc_pxo_dsi2_dsi1, + .parent_data = mmcc_pxo_dsi2_dsi1, .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), .ops = &clk_rcg_bypass2_ops, .flags = CLK_SET_RATE_PARENT, @@ -2083,7 +2151,9 @@ static struct clk_branch dsi1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "dsi1_clk", - .parent_names = (const char *[]){ "dsi1_src" }, + .parent_hws = (const struct clk_hw*[]){ + &dsi1_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2115,7 +2185,7 @@ static struct clk_rcg dsi2_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "dsi2_src", - .parent_names = mmcc_pxo_dsi2_dsi1, + .parent_data = mmcc_pxo_dsi2_dsi1, .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), .ops = &clk_rcg_bypass2_ops, .flags = CLK_SET_RATE_PARENT, @@ -2131,7 +2201,9 @@ static struct clk_branch dsi2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "dsi2_clk", - .parent_names = (const char *[]){ "dsi2_src" }, + .parent_hws = (const struct clk_hw*[]){ + &dsi2_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2154,7 +2226,7 @@ static struct clk_rcg dsi1_byte_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "dsi1_byte_src", - .parent_names = mmcc_pxo_dsi1_dsi2_byte, + .parent_data = mmcc_pxo_dsi1_dsi2_byte, .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), .ops = &clk_rcg_bypass2_ops, .flags = CLK_SET_RATE_PARENT, @@ -2170,7 +2242,9 @@ static struct clk_branch dsi1_byte_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "dsi1_byte_clk", - .parent_names = (const char *[]){ "dsi1_byte_src" }, + .parent_hws = (const struct clk_hw*[]){ + &dsi1_byte_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2193,7 +2267,7 @@ static struct clk_rcg dsi2_byte_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "dsi2_byte_src", - .parent_names = mmcc_pxo_dsi1_dsi2_byte, + .parent_data = mmcc_pxo_dsi1_dsi2_byte, .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), .ops = &clk_rcg_bypass2_ops, .flags = CLK_SET_RATE_PARENT, @@ -2209,7 +2283,9 @@ static struct clk_branch dsi2_byte_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "dsi2_byte_clk", - .parent_names = (const char *[]){ "dsi2_byte_src" }, + .parent_hws = (const struct clk_hw*[]){ + &dsi2_byte_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2232,7 +2308,7 @@ static struct clk_rcg dsi1_esc_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "dsi1_esc_src", - .parent_names = mmcc_pxo_dsi1_dsi2_byte, + .parent_data = mmcc_pxo_dsi1_dsi2_byte, .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), .ops = &clk_rcg_esc_ops, }, @@ -2247,7 +2323,9 @@ static struct clk_branch dsi1_esc_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "dsi1_esc_clk", - .parent_names = (const char *[]){ "dsi1_esc_src" }, + .parent_hws = (const struct clk_hw*[]){ + &dsi1_esc_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2270,7 +2348,7 @@ static struct clk_rcg dsi2_esc_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "dsi2_esc_src", - .parent_names = mmcc_pxo_dsi1_dsi2_byte, + .parent_data = mmcc_pxo_dsi1_dsi2_byte, .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte), .ops = &clk_rcg_esc_ops, }, @@ -2285,7 +2363,9 @@ static struct clk_branch dsi2_esc_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "dsi2_esc_clk", - .parent_names = (const char *[]){ "dsi2_esc_src" }, + .parent_hws = (const struct clk_hw*[]){ + &dsi2_esc_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2317,7 +2397,7 @@ static struct clk_rcg dsi1_pixel_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "dsi1_pixel_src", - .parent_names = mmcc_pxo_dsi2_dsi1, + .parent_data = mmcc_pxo_dsi2_dsi1, .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), .ops = &clk_rcg_pixel_ops, }, @@ -2332,7 +2412,9 @@ static struct clk_branch dsi1_pixel_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdp_pclk1_clk", - .parent_names = (const char *[]){ "dsi1_pixel_src" }, + .parent_hws = (const struct clk_hw*[]){ + &dsi1_pixel_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2364,7 +2446,7 @@ static struct clk_rcg dsi2_pixel_src = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "dsi2_pixel_src", - .parent_names = mmcc_pxo_dsi2_dsi1, + .parent_data = mmcc_pxo_dsi2_dsi1, .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1), .ops = &clk_rcg_pixel_ops, }, @@ -2379,7 +2461,9 @@ static struct clk_branch dsi2_pixel_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdp_pclk2_clk", - .parent_names = (const char *[]){ "dsi2_pixel_src" }, + .parent_hws = (const struct clk_hw*[]){ + &dsi2_pixel_src.clkr.hw + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, From patchwork Thu Jun 23 12:04:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 584348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0D0DCCA48A for ; Thu, 23 Jun 2022 12:04:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231741AbiFWMEi (ORCPT ); Thu, 23 Jun 2022 08:04:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231420AbiFWMEe (ORCPT ); Thu, 23 Jun 2022 08:04:34 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E88FD488B9 for ; Thu, 23 Jun 2022 05:04:27 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id y32so32970526lfa.6 for ; Thu, 23 Jun 2022 05:04:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=phwT+Z6nWrWm8Hr0ddNtVBYpY/29m2pZjUGouNitf4c=; b=GQL8E4bhfx7Iai+2lcA/S84OUj1KpEBjIQE+ze7obNQQ6vaNEW4VwUMYD6X56Wxgj3 J9XvfjrrblfmJG99VkxuxAgxnfB1CZVReAj/Ztypv+2QjFgMQRyixmRbKFyAbGPaVRZl J4gura9cPiSojJCCrPK6e11Sl4NVj2+maHvwdyy1X0ZRwgi5NXpDijsOQtvq5irjwsfz 4kWmlXoP9Oxg4YgdgYkn24L3zhxrth3u/Vff3oRtCKIKodHrt2vFhrNSDtaWltE5CJeS tzz7c9WfyveFTxFml1X5RROitWAipVoBmDxNKKzaYx3Ia+iIGYa65S+Ht+WEU3wj/aDj lJRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=phwT+Z6nWrWm8Hr0ddNtVBYpY/29m2pZjUGouNitf4c=; b=SedI6RBc9J5YnJktpwRuzBT1EcLIqOHd8gvSR5TN6QhQ0HF4eeZTgJUOH+y6lHhPNN cby3WJHRvynpMyT0aHoWDydv0UTb0pzeVAgBjcA9mqo9qwqgejkUiu7oqIYiGUN5tIOq k93PKubCF2ZxLzMVPM8selCR6kauy5Gq5nFFuhXwfo7zHBszNOu+NRJ2HEPGzSCOTmYs 8QTwEhCBO6K0sDuk2FQUCtObi6l9GemaiJPIdohe+b+dG5x8b8Zn/HBL7OPcWNPRwrOY /lZAjyG9nEm9mOoxyxPa2V/6iifhz78M1Nhy21Z7xQ9XGxn4iGizZrpI273/k3D1/NwU pHgw== X-Gm-Message-State: AJIora/EXeBBcbpne7MXwftWV6IVmAQsg9tt6lRowG2CrHIJRPpWfTyR LfnNAQGwOj37nGJo8o5huLGTIkgyK1liHSSw X-Google-Smtp-Source: AGRyM1vsh64TMNAD9XuPmd3FfqFMpFJ0tlZrucUc2f64uUmXi21/MIvZq1NrLpYBdC650ejTtbzbow== X-Received: by 2002:a05:6512:2810:b0:47f:a76c:8770 with SMTP id cf16-20020a056512281000b0047fa76c8770mr1707701lfb.116.1655985867352; Thu, 23 Jun 2022 05:04:27 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id 18-20020ac25f52000000b0047f6b4a53cdsm1799888lfz.172.2022.06.23.05.04.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 05:04:26 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 10/15] ARM: dts: qcom: apq8064: add clocks to the LCC device node Date: Thu, 23 Jun 2022 15:04:13 +0300 Message-Id: <20220623120418.250589-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> References: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As we are converting this platform to use DT clock bindings, add clocks and clock-names properties to the LCC device tree node. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 0d323c208978..72b099ed4543 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -834,6 +834,20 @@ lcc: clock-controller@28000000 { reg = <0x28000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, <0>, + <0>, <0>, + <0>; + clock-names = "pxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; }; mmcc: clock-controller@4000000 { From patchwork Thu Jun 23 12:04:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 584346 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2851BCCA487 for ; Thu, 23 Jun 2022 12:04:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231694AbiFWMEo (ORCPT ); Thu, 23 Jun 2022 08:04:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231503AbiFWMEh (ORCPT ); Thu, 23 Jun 2022 08:04:37 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A102496A2 for ; Thu, 23 Jun 2022 05:04:30 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id q9so5020594ljp.4 for ; Thu, 23 Jun 2022 05:04:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CY/R0xFxG7Py4HYT1PPxbuqpWVbd/YtENkbXJ6Hu/gI=; b=qWF5I02mOgSa/6EheKom+AYbV93XG73Ty7LFbQLmHPnP9//1va4j+e+h8SH2IUOjx2 duCoO+EFt7R/NT0wrAdEc8Vdzw81Attg9obPOvpg1oFAyNKJEkM5mzbX5uDQoZLZnIC5 AJvfyyRdIxR7MScM4YNMrwVwKSDfCgn8g1d9feQG+JiRTjqjM41AxSjP9AybInDFwIzr qsYENfOi1+/TrRaNG1JwJoL+8LkkZ01yotFduy0kdhiZx6SqfEyLIkYsfVtt6WzkeiI+ ViFY4bpI4R9GQYtrdFIo59O4nox2AHAgmEqJxUNDbi02yS4tNrlgQSHKXC8KDQQJ2+w+ quXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CY/R0xFxG7Py4HYT1PPxbuqpWVbd/YtENkbXJ6Hu/gI=; b=YSsD3Imk/TVIFdVs+S/PaLJ3J/FRIvnqHxTrpDimxdEOw8XdLenmu+ygPOZtwpIudN 9WLNyDbGAWlHfNhbbX6ExYercg/TBtBEWf7KNufxHu7xTNvq+bwuxaqcbZBGuppZE2jR tzHe150Ek3r2BYVoBwrnGRJA+n/SbsFzIsT96msVTy0EeljP63dcoQlHA1+ZNDcn0us4 n+2dnIIPMOjclnmUw/cj20dEKFcn+gb+vTCy11Qbnfq+V1BjMwiZ+msAu3qLYDqRbV4J P6d/SmWeOXVYVJFQ5vIc73uFR99v0FUtTVl1b/IcLFxGNsHlpncOESfS1KehyzF8VaUL Eerg== X-Gm-Message-State: AJIora9VV28LFRiLWUzpvFefY0W10yF8D81z0WZjkIO6+uKzTEY1+kqs 6yf6mTXpU3rvp43E/O3WQTRiyg== X-Google-Smtp-Source: AGRyM1v4xU8frsl4EdzPmth7IQWf9+k5j4HpKc5Lfr4vZiEBleu3ornilOj2mxVdCh7cdA19hq/XCA== X-Received: by 2002:a2e:5342:0:b0:259:ac23:8d52 with SMTP id t2-20020a2e5342000000b00259ac238d52mr4637857ljd.488.1655985868269; Thu, 23 Jun 2022 05:04:28 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id 18-20020ac25f52000000b0047f6b4a53cdsm1799888lfz.172.2022.06.23.05.04.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 05:04:27 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 11/15] ARM: dts: qcom: msm8960: add clocks to the LCC device node Date: Thu, 23 Jun 2022 15:04:14 +0300 Message-Id: <20220623120418.250589-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> References: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As we are converting this platform to use DT clock bindings, add clocks and clock-names properties to the LCC device tree node. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-msm8960.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 4a2d74cf01d2..3d58846319ae 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -63,7 +63,7 @@ cxo_board { clock-output-names = "cxo_board"; }; - pxo_board { + pxo_board: pxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; @@ -137,6 +137,20 @@ lcc: clock-controller@28000000 { reg = <0x28000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, <0>, + <0>, <0>, + <0>; + clock-names = "pxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; }; clock-controller@4000000 { From patchwork Thu Jun 23 12:04:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 584345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D075CCA489 for ; Thu, 23 Jun 2022 12:04:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231646AbiFWMEp (ORCPT ); Thu, 23 Jun 2022 08:04:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231673AbiFWMEl (ORCPT ); Thu, 23 Jun 2022 08:04:41 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 741084CD47 for ; Thu, 23 Jun 2022 05:04:32 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id a11so14259355ljb.5 for ; Thu, 23 Jun 2022 05:04:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+ZSA6xHQZ9aqASlGuBjY/Lc+K6EWssVTLnudC8h7Ugc=; b=jEPdaVuSYHVAXI7PQcfhMs4Y48HYVRpwDx3OONIo7QHh2qHN6THTxsy+0wO7neM4QW lSbhb5hAp+p/xUydOV8w+tOmQUkPGz50ayN71VkENvO0xhls1Zy+D64YB27CTbuBjTb2 tCydXhELrmdwaNphsLdp0bXh9N76gERgiaDfGKgM4anRcgHCMlrAXODA86MxZDFlh/Ky hkBXBMDLzPTiRzOxKZJaiZukIbfEI2deubmkajDchSWwVGyN0JnDMNOHMKag2/Iiaon8 eh+qRooEG/E1BlNqWRUW+wIpholTv8Xldpm5Bt/wB3ADYORn1cT3PoIR4Spkroa7o/6/ Ev4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+ZSA6xHQZ9aqASlGuBjY/Lc+K6EWssVTLnudC8h7Ugc=; b=XAdvvAHohv0eOV4629Ls1exinJXQDAf5Cd5/yfjl/9JqvlVgSrxVlNWA6dBnpHwG4i TfjI4KgcyNf0VPJh3mcPERSLHO0e7mtBRMC8xdomsZ2NJWmgU4LIRZz0gaB+d63DKe3I LUhfaKmMJqPbHkCXSP8TJ0wLt84SARTl1Vs2CWPNm172nMNM5GejIyzRSCfiCqoW2YFU vmeRoVdJW/9nZn3WpqedWtAEYvG9e8N9nK+yd4ZJsQ7L6wnhKd9Boqq24RC87kVPct6q eq3l7eWDeqiz1RNz3YfCencBPCmw194WyBauc6RlJWb/ibTZJehU3r5LVslZwiWPGS7I X6EQ== X-Gm-Message-State: AJIora+TI3jWI7vNGHfHXZRbUW4K5ulMQFJ/ynI7zWV936nnxdppO37S mXtnKhyxXeSY3vFtPL9PWiyZ5Q== X-Google-Smtp-Source: AGRyM1vyTttTf9/+DOHZEFqBUI8Pj1xvEChHdF/WQ4rT74eb+M5p7WPr4E+2gOh2gRvp14Eyf/lSGg== X-Received: by 2002:a2e:a78a:0:b0:25a:8c6a:f3c7 with SMTP id c10-20020a2ea78a000000b0025a8c6af3c7mr3421276ljf.218.1655985871235; Thu, 23 Jun 2022 05:04:31 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id 18-20020ac25f52000000b0047f6b4a53cdsm1799888lfz.172.2022.06.23.05.04.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 05:04:30 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 15/15] ARM: dts: qcom: msm8960: add clocks to the MMCC device node Date: Thu, 23 Jun 2022 15:04:18 +0300 Message-Id: <20220623120418.250589-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> References: <20220623120418.250589-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As we are converting this platform to use DT clock bindings, add clocks and clock-names properties to the MMCC device tree node. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-msm8960.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index c7058da58be5..b65659801b6e 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -164,6 +164,22 @@ clock-controller@4000000 { #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; + clocks = <&pxo_board>, + <&gcc PLL3>, + <&gcc PLL8_VOTE>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "pxo", + "pll3", + "pll8_vote", + "dsi1pll", + "dsi1pllbyte", + "dsi2pll", + "dsi2pllbyte", + "hdmipll"; }; l2cc: clock-controller@2011000 {