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([2602:47:d49e:3c01:a3e0:8a80:7b85:aea6]) by smtp.gmail.com with ESMTPSA id q11-20020a056a00084b00b0051bc3a2355csm9907875pfk.64.2022.06.20.18.48.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 18:48:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: npiggin@gmail.com, qemu-ppc@nongnu.org Subject: [PATCH v2 1/3] util: Merge cacheflush.c and cacheinfo.c Date: Mon, 20 Jun 2022 18:48:35 -0700 Message-Id: <20220621014837.189139-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220621014837.189139-1-richard.henderson@linaro.org> References: <20220621014837.189139-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Combine the two files into cacheflush.c. There's a couple of bits that would be helpful to share between the two, and combining them seems better than exporting the bits. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- util/cacheflush.c | 202 +++++++++++++++++++++++++++++++++++++++++++++- util/cacheinfo.c | 200 --------------------------------------------- util/meson.build | 2 +- 3 files changed, 202 insertions(+), 202 deletions(-) delete mode 100644 util/cacheinfo.c diff --git a/util/cacheflush.c b/util/cacheflush.c index 4b57186d89..8096afd33c 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -1,5 +1,5 @@ /* - * Flush the host cpu caches. + * Info about, and flushing the host cpu caches. * * This work is licensed under the terms of the GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. @@ -9,8 +9,208 @@ #include "qemu/cacheflush.h" #include "qemu/cacheinfo.h" #include "qemu/bitops.h" +#include "qemu/host-utils.h" +#include "qemu/atomic.h" +int qemu_icache_linesize = 0; +int qemu_icache_linesize_log; +int qemu_dcache_linesize = 0; +int qemu_dcache_linesize_log; + +/* + * Operating system specific cache detection mechanisms. + */ + +#if defined(_WIN32) + +static void sys_cache_info(int *isize, int *dsize) +{ + SYSTEM_LOGICAL_PROCESSOR_INFORMATION *buf; + DWORD size = 0; + BOOL success; + size_t i, n; + + /* + * Check for the required buffer size first. Note that if the zero + * size we use for the probe results in success, then there is no + * data available; fail in that case. + */ + success = GetLogicalProcessorInformation(0, &size); + if (success || GetLastError() != ERROR_INSUFFICIENT_BUFFER) { + return; + } + + n = size / sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION); + size = n * sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION); + buf = g_new0(SYSTEM_LOGICAL_PROCESSOR_INFORMATION, n); + if (!GetLogicalProcessorInformation(buf, &size)) { + goto fail; + } + + for (i = 0; i < n; i++) { + if (buf[i].Relationship == RelationCache + && buf[i].Cache.Level == 1) { + switch (buf[i].Cache.Type) { + case CacheUnified: + *isize = *dsize = buf[i].Cache.LineSize; + break; + case CacheInstruction: + *isize = buf[i].Cache.LineSize; + break; + case CacheData: + *dsize = buf[i].Cache.LineSize; + break; + default: + break; + } + } + } + fail: + g_free(buf); +} + +#elif defined(__APPLE__) +# include +static void sys_cache_info(int *isize, int *dsize) +{ + /* There's only a single sysctl for both I/D cache line sizes. */ + long size; + size_t len = sizeof(size); + if (!sysctlbyname("hw.cachelinesize", &size, &len, NULL, 0)) { + *isize = *dsize = size; + } +} +#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) +# include +static void sys_cache_info(int *isize, int *dsize) +{ + /* There's only a single sysctl for both I/D cache line sizes. */ + int size; + size_t len = sizeof(size); + if (!sysctlbyname("machdep.cacheline_size", &size, &len, NULL, 0)) { + *isize = *dsize = size; + } +} +#else +/* POSIX */ + +static void sys_cache_info(int *isize, int *dsize) +{ +# ifdef _SC_LEVEL1_ICACHE_LINESIZE + int tmp_isize = (int) sysconf(_SC_LEVEL1_ICACHE_LINESIZE); + if (tmp_isize > 0) { + *isize = tmp_isize; + } +# endif +# ifdef _SC_LEVEL1_DCACHE_LINESIZE + int tmp_dsize = (int) sysconf(_SC_LEVEL1_DCACHE_LINESIZE); + if (tmp_dsize > 0) { + *dsize = tmp_dsize; + } +# endif +} +#endif /* sys_cache_info */ + + +/* + * Architecture (+ OS) specific cache detection mechanisms. + */ + +#if defined(__aarch64__) + +static void arch_cache_info(int *isize, int *dsize) +{ + if (*isize == 0 || *dsize == 0) { + uint64_t ctr; + + /* + * The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1, + * but (at least under Linux) these are marked protected by the + * kernel. However, CTR_EL0 contains the minimum linesize in the + * entire hierarchy, and is used by userspace cache flushing. + */ + asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr)); + if (*isize == 0) { + *isize = 4 << (ctr & 0xf); + } + if (*dsize == 0) { + *dsize = 4 << ((ctr >> 16) & 0xf); + } + } +} + +#elif defined(_ARCH_PPC) && defined(__linux__) +# include "elf.h" + +static void arch_cache_info(int *isize, int *dsize) +{ + if (*isize == 0) { + *isize = qemu_getauxval(AT_ICACHEBSIZE); + } + if (*dsize == 0) { + *dsize = qemu_getauxval(AT_DCACHEBSIZE); + } +} + +#else +static void arch_cache_info(int *isize, int *dsize) { } +#endif /* arch_cache_info */ + +/* + * ... and if all else fails ... + */ + +static void fallback_cache_info(int *isize, int *dsize) +{ + /* If we can only find one of the two, assume they're the same. */ + if (*isize) { + if (*dsize) { + /* Success! */ + } else { + *dsize = *isize; + } + } else if (*dsize) { + *isize = *dsize; + } else { +#if defined(_ARCH_PPC) + /* + * For PPC, we're going to use the cache sizes computed for + * flush_idcache_range. Which means that we must use the + * architecture minimum. + */ + *isize = *dsize = 16; +#else + /* Otherwise, 64 bytes is not uncommon. */ + *isize = *dsize = 64; +#endif + } +} + +static void __attribute__((constructor)) init_cache_info(void) +{ + int isize = 0, dsize = 0; + + sys_cache_info(&isize, &dsize); + arch_cache_info(&isize, &dsize); + fallback_cache_info(&isize, &dsize); + + assert((isize & (isize - 1)) == 0); + assert((dsize & (dsize - 1)) == 0); + + qemu_icache_linesize = isize; + qemu_icache_linesize_log = ctz32(isize); + qemu_dcache_linesize = dsize; + qemu_dcache_linesize_log = ctz32(dsize); + + qatomic64_init(); +} + + +/* + * Architecture (+ OS) specific cache flushing mechanisms. + */ + #if defined(__i386__) || defined(__x86_64__) || defined(__s390__) /* Caches are coherent and do not require flushing; symbol inline. */ diff --git a/util/cacheinfo.c b/util/cacheinfo.c deleted file mode 100644 index ab1644d490..0000000000 --- a/util/cacheinfo.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * cacheinfo.c - helpers to query the host about its caches - * - * Copyright (C) 2017, Emilio G. Cota - * License: GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#include "qemu/osdep.h" -#include "qemu/host-utils.h" -#include "qemu/atomic.h" -#include "qemu/cacheinfo.h" - -int qemu_icache_linesize = 0; -int qemu_icache_linesize_log; -int qemu_dcache_linesize = 0; -int qemu_dcache_linesize_log; - -/* - * Operating system specific detection mechanisms. - */ - -#if defined(_WIN32) - -static void sys_cache_info(int *isize, int *dsize) -{ - SYSTEM_LOGICAL_PROCESSOR_INFORMATION *buf; - DWORD size = 0; - BOOL success; - size_t i, n; - - /* Check for the required buffer size first. Note that if the zero - size we use for the probe results in success, then there is no - data available; fail in that case. */ - success = GetLogicalProcessorInformation(0, &size); - if (success || GetLastError() != ERROR_INSUFFICIENT_BUFFER) { - return; - } - - n = size / sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION); - size = n * sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION); - buf = g_new0(SYSTEM_LOGICAL_PROCESSOR_INFORMATION, n); - if (!GetLogicalProcessorInformation(buf, &size)) { - goto fail; - } - - for (i = 0; i < n; i++) { - if (buf[i].Relationship == RelationCache - && buf[i].Cache.Level == 1) { - switch (buf[i].Cache.Type) { - case CacheUnified: - *isize = *dsize = buf[i].Cache.LineSize; - break; - case CacheInstruction: - *isize = buf[i].Cache.LineSize; - break; - case CacheData: - *dsize = buf[i].Cache.LineSize; - break; - default: - break; - } - } - } - fail: - g_free(buf); -} - -#elif defined(__APPLE__) -# include -static void sys_cache_info(int *isize, int *dsize) -{ - /* There's only a single sysctl for both I/D cache line sizes. */ - long size; - size_t len = sizeof(size); - if (!sysctlbyname("hw.cachelinesize", &size, &len, NULL, 0)) { - *isize = *dsize = size; - } -} -#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) -# include -static void sys_cache_info(int *isize, int *dsize) -{ - /* There's only a single sysctl for both I/D cache line sizes. */ - int size; - size_t len = sizeof(size); - if (!sysctlbyname("machdep.cacheline_size", &size, &len, NULL, 0)) { - *isize = *dsize = size; - } -} -#else -/* POSIX */ - -static void sys_cache_info(int *isize, int *dsize) -{ -# ifdef _SC_LEVEL1_ICACHE_LINESIZE - int tmp_isize = (int) sysconf(_SC_LEVEL1_ICACHE_LINESIZE); - if (tmp_isize > 0) { - *isize = tmp_isize; - } -# endif -# ifdef _SC_LEVEL1_DCACHE_LINESIZE - int tmp_dsize = (int) sysconf(_SC_LEVEL1_DCACHE_LINESIZE); - if (tmp_dsize > 0) { - *dsize = tmp_dsize; - } -# endif -} -#endif /* sys_cache_info */ - -/* - * Architecture (+ OS) specific detection mechanisms. - */ - -#if defined(__aarch64__) - -static void arch_cache_info(int *isize, int *dsize) -{ - if (*isize == 0 || *dsize == 0) { - uint64_t ctr; - - /* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1, - but (at least under Linux) these are marked protected by the - kernel. However, CTR_EL0 contains the minimum linesize in the - entire hierarchy, and is used by userspace cache flushing. */ - asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr)); - if (*isize == 0) { - *isize = 4 << (ctr & 0xf); - } - if (*dsize == 0) { - *dsize = 4 << ((ctr >> 16) & 0xf); - } - } -} - -#elif defined(_ARCH_PPC) && defined(__linux__) -# include "elf.h" - -static void arch_cache_info(int *isize, int *dsize) -{ - if (*isize == 0) { - *isize = qemu_getauxval(AT_ICACHEBSIZE); - } - if (*dsize == 0) { - *dsize = qemu_getauxval(AT_DCACHEBSIZE); - } -} - -#else -static void arch_cache_info(int *isize, int *dsize) { } -#endif /* arch_cache_info */ - -/* - * ... and if all else fails ... - */ - -static void fallback_cache_info(int *isize, int *dsize) -{ - /* If we can only find one of the two, assume they're the same. */ - if (*isize) { - if (*dsize) { - /* Success! */ - } else { - *dsize = *isize; - } - } else if (*dsize) { - *isize = *dsize; - } else { -#if defined(_ARCH_PPC) - /* - * For PPC, we're going to use the cache sizes computed for - * flush_idcache_range. Which means that we must use the - * architecture minimum. - */ - *isize = *dsize = 16; -#else - /* Otherwise, 64 bytes is not uncommon. */ - *isize = *dsize = 64; -#endif - } -} - -static void __attribute__((constructor)) init_cache_info(void) -{ - int isize = 0, dsize = 0; - - sys_cache_info(&isize, &dsize); - arch_cache_info(&isize, &dsize); - fallback_cache_info(&isize, &dsize); - - assert((isize & (isize - 1)) == 0); - assert((dsize & (dsize - 1)) == 0); - - qemu_icache_linesize = isize; - qemu_icache_linesize_log = ctz32(isize); - qemu_dcache_linesize = dsize; - qemu_dcache_linesize_log = ctz32(dsize); - - qatomic64_init(); -} diff --git a/util/meson.build b/util/meson.build index 8f16018cd4..4939b0b91c 100644 --- a/util/meson.build +++ b/util/meson.build @@ -27,7 +27,7 @@ util_ss.add(files('envlist.c', 'path.c', 'module.c')) util_ss.add(files('host-utils.c')) util_ss.add(files('bitmap.c', 'bitops.c')) util_ss.add(files('fifo8.c')) -util_ss.add(files('cacheinfo.c', 'cacheflush.c')) +util_ss.add(files('cacheflush.c')) util_ss.add(files('error.c', 'error-report.c')) util_ss.add(files('qemu-print.c')) util_ss.add(files('id.c')) From patchwork Tue Jun 21 01:48:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 583608 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp1216659mab; Mon, 20 Jun 2022 18:50:13 -0700 (PDT) X-Google-Smtp-Source: AGRyM1ulEj7A2bLUjoTfGzcNeMBHpYkYHX66Q8siSFpqomlP2CckBL0YnTz0cvaqF3JTPXh/udNj X-Received: by 2002:a37:5e46:0:b0:6ab:90dc:d9d6 with SMTP id s67-20020a375e46000000b006ab90dcd9d6mr13100231qkb.131.1655776213361; Mon, 20 Jun 2022 18:50:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1655776213; cv=none; d=google.com; s=arc-20160816; b=m9Kk9Hck1gueuV5HqxKByU54lJ+dBFphGVeZVlA1fq9inBMq8ZG9vJMsipiBhKjN+H WE7++2XDM/WqM4obg5SsBKrzfAXjncQBgwbwZN6Q+Mwyo3FExvQlZSLD7ZyPkzI1K9vP qoNGsOP1DNaCJJ9kkcxL/ZXw8StsN5BMlzNs9mSxQR9AbYORCyG3lo6OjLxvoXTZxS1T SIlVW4OSlSLvjlfDA1AjrMpNAx8/J7P3KPJcJ7yZjLbwiJ3VBb9PFza/V9gg8ZPdCTeD T8cW6kMU695XXtYJ2S/zXzIBpzjTb1dJcyWRTRFpH2TJJkuwBxSNxQ9uqJbaJQovdu36 SlkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=L5ak+zhha2NejqhbdG/upUYuAV+/wGYDkUJ8k4RZozs=; b=mHVRmROp/YQgQc35TUUrdhnU2gkCXyD0fEeszQAMS5uILrfE/aWH5huECdZgyyzLmQ s3YtOtE5Vril+WT9jW6mpvs6T/mBpTUWSzPgcy5md34DbW+1TqUP6X42wqL38S+9ubE8 e2mrr6oBQYOTFCJiEqoeBirr7ukoH4kx7Uqr6x1F+yj1d0dhsPPtHqqj9Mybc3GuLjRy fsLycfNCbtn0esacqGaFWqXMrUrF9hLgBGthQkG4SRBCnF0Qj4PWvUcBTaYbbkKzFtgj EGEZdAME6jxC13CSyO2hEiwHkcmLbjbM7xjzL3R/Vxvbu27xZXQ0z/v9LhRcHwmj5c3J w4lQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JvVQs7i6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t4-20020a05622a180400b0030520f2cb89si9022240qtc.594.2022.06.20.18.50.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 20 Jun 2022 18:50:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JvVQs7i6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3T1w-0003TO-UC for patch@linaro.org; Mon, 20 Jun 2022 21:50:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34896) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3T0V-0003RM-G6 for qemu-devel@nongnu.org; Mon, 20 Jun 2022 21:48:43 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:55246) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o3T0T-0001ta-Ol for qemu-devel@nongnu.org; Mon, 20 Jun 2022 21:48:43 -0400 Received: by mail-pj1-x102b.google.com with SMTP id cv13so8984332pjb.4 for ; Mon, 20 Jun 2022 18:48:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L5ak+zhha2NejqhbdG/upUYuAV+/wGYDkUJ8k4RZozs=; b=JvVQs7i60aH4yf2xGlaVdht5d12XserxVPEhwGxZ1N/LTj/dkhDokaiP4gZ395NR64 ZOkYKuYIYf2U1cQRa3LcwFdzjWvfT01XtZodCHHmGyfsBrxkcGl7TJMO+jLAD4EoLdQ2 ytX+SEO808o/S7r6EQN9u/qscAWWGSeEjy3TGQEyhbqIn5sXgB20KLwZmbCLLEE/Nk7d PVlxZJokSR12EJZSsxkYjrCwdt6dKnemwCWZNbBjZr3LKkEo1M/8x+V3prNeUSXkz8wL P9pZHiOTNka9zqLbNaGBsbKCrdmQx8QuizF0w7ytN8OIUfqafyxwBoZNSAgV3uqHZVEH JoLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L5ak+zhha2NejqhbdG/upUYuAV+/wGYDkUJ8k4RZozs=; b=0iXsaZWp+lsGsNJ0d0e5ZVhg6bjZe7ZaHyy/rZihhYtkoPHj093nGZ6i7NgTJ4bGM3 KlqoD5sYf0asmb05CqewRlE0zvoeOwYPhPT3piDHNwD97Z8tn0pBLlmtpxu81iBc5miv lnYLkHPXGRlakn6dBfqxlu+UDwfIS55swiQtS50ppXH1MDZxXCpf7Q9GE8CVvVRSkEHA wPOZ6vBEueJIHy4fpicvsBX2j6SEq9reG2zfZlZKiMCm25kA8Rv1cYhzbkJwFOCNPn4Z MzczNcMSiypMz59Gqhta/s3GI0uMv0aC4P5RDDQcJqmmxQKCtoiNEBBa9IrUGCczS5/A eS1A== X-Gm-Message-State: AJIora+NJSb8zD4iAk3xjCA8+AlWsDj3LuyO7ZS+NgtyTBqbDgd/X82Z 0ALWFD6kEHHF04eiiPUqbQ4ktvwX1wMtow== X-Received: by 2002:a17:902:d652:b0:168:bffe:e5fe with SMTP id y18-20020a170902d65200b00168bffee5femr27193143plh.81.1655776120396; Mon, 20 Jun 2022 18:48:40 -0700 (PDT) Received: from stoup.. ([2602:47:d49e:3c01:a3e0:8a80:7b85:aea6]) by smtp.gmail.com with ESMTPSA id q11-20020a056a00084b00b0051bc3a2355csm9907875pfk.64.2022.06.20.18.48.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 18:48:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: npiggin@gmail.com, qemu-ppc@nongnu.org Subject: [PATCH v2 2/3] util/cacheflush: Merge aarch64 ctr_el0 usage Date: Mon, 20 Jun 2022 18:48:36 -0700 Message-Id: <20220621014837.189139-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220621014837.189139-1-richard.henderson@linaro.org> References: <20220621014837.189139-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Merge init_ctr_el0 into arch_cache_info. In flush_idcache_range, use the pre-computed line sizes from the global variables. Use CONFIG_DARWIN in preference to __APPLE__. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- util/cacheflush.c | 44 +++++++++++++++++++------------------------- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/util/cacheflush.c b/util/cacheflush.c index 8096afd33c..01b6cb7583 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -70,7 +70,7 @@ static void sys_cache_info(int *isize, int *dsize) g_free(buf); } -#elif defined(__APPLE__) +#elif defined(CONFIG_DARWIN) # include static void sys_cache_info(int *isize, int *dsize) { @@ -117,20 +117,25 @@ static void sys_cache_info(int *isize, int *dsize) * Architecture (+ OS) specific cache detection mechanisms. */ -#if defined(__aarch64__) - +#if defined(__aarch64__) && !defined(CONFIG_DARWIN) +/* Apple does not expose CTR_EL0, so we must use system interfaces. */ +static uint64_t save_ctr_el0; static void arch_cache_info(int *isize, int *dsize) { - if (*isize == 0 || *dsize == 0) { - uint64_t ctr; + uint64_t ctr; - /* - * The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1, - * but (at least under Linux) these are marked protected by the - * kernel. However, CTR_EL0 contains the minimum linesize in the - * entire hierarchy, and is used by userspace cache flushing. - */ - asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr)); + /* + * The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1, + * but (at least under Linux) these are marked protected by the + * kernel. However, CTR_EL0 contains the minimum linesize in the + * entire hierarchy, and is used by userspace cache flushing. + * + * We will also use this value in flush_idcache_range. + */ + asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr)); + save_ctr_el0 = ctr; + + if (*isize == 0 || *dsize == 0) { if (*isize == 0) { *isize = 4 << (ctr & 0xf); } @@ -228,17 +233,6 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) } #else -/* - * TODO: unify this with cacheinfo.c. - * We want to save the whole contents of CTR_EL0, so that we - * have more than the linesize, but also IDC and DIC. - */ -static uint64_t save_ctr_el0; -static void __attribute__((constructor)) init_ctr_el0(void) -{ - asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0)); -} - /* * This is a copy of gcc's __aarch64_sync_cache_range, modified * to fit this three-operand interface. @@ -248,8 +242,8 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) const unsigned CTR_IDC = 1u << 28; const unsigned CTR_DIC = 1u << 29; const uint64_t ctr_el0 = save_ctr_el0; - const uintptr_t icache_lsize = 4 << extract64(ctr_el0, 0, 4); - const uintptr_t dcache_lsize = 4 << extract64(ctr_el0, 16, 4); + const uintptr_t icache_lsize = qemu_icache_linesize; + const uintptr_t dcache_lsize = qemu_dcache_linesize; uintptr_t p; /* From patchwork Tue Jun 21 01:48:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 583610 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp1217789mab; Mon, 20 Jun 2022 18:52:43 -0700 (PDT) X-Google-Smtp-Source: AGRyM1tx0k7Pu91x+fk0rb2GIcH2F6IEasx48ged25TsO387hYhWxREFOuiJV1zPSoVoyyQTzeBz X-Received: by 2002:ac8:5a11:0:b0:305:26b4:cbce with SMTP id n17-20020ac85a11000000b0030526b4cbcemr21784640qta.241.1655776363849; Mon, 20 Jun 2022 18:52:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1655776363; cv=none; d=google.com; s=arc-20160816; b=jU3XmhMgRsHXYd4nAqzh4ia5/DtRh0m7nzEvBraBUZ1qKgkYkMm4Iz7LGeToVRFRPE QUdvjbujgJ/YyJSxKqmYSTWY2AwrW1uvR2iHnv/aP0rcL+MJUIivQcIvIafdilKfaD0B 6tQo50eIlZvTUKCBP+u/46YmZyt9LKEXHvLMAO5wYcVu1UaRJ1St9GlHBzn1fV/rPu37 ZA2qAEecNu8oJ0MJ/sWdA9QUVqu/9FPvrKtt7MD2xEZ2A3/KSVFyQBE388n8XzYM03us ZO1W4XSSTryF79/iMzUGFymhINmfbQXM9L7SZ3tSJxfHKCjVzaD4BDLlieQ+dWjkYN0T t7DA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YBQ+kqYkpbLgtv+WWFdZqAHxgkdKeAvGA4OIxoJYS3s=; b=KPClItM1gmsbN11b+0J0QaXaRayiy26/gcmAwTx7mmyMBpKeJWyCo2g+tjKfA24555 CruOKzs0GySUlq76zj/OrbS9b0gGey0NNeBvfbDTDnu7nn1zxOLWYuvO3zGIJIWpwwEJ OWy4BR75rGR35aUwzeRRGGcqfIQggOFRXAgdHR29JQHs8BdmhxoIDAfzaOBLKOvqloeC kTy24CdH8ZaCpKZ1hN+exjX1u784wcy9OYpZv8BybGPRlR+/V20HzI5Fmdz8YiGt4HsM psm/SjSS4sMLwpsFfpyEtVgQjsS2ZtLQnunIaFH9bvXCZH3IR/WjJVwnwjLlibALf8rK wMQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="FrjhT/hc"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d49e:3c01:a3e0:8a80:7b85:aea6]) by smtp.gmail.com with ESMTPSA id q11-20020a056a00084b00b0051bc3a2355csm9907875pfk.64.2022.06.20.18.48.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 18:48:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: npiggin@gmail.com, qemu-ppc@nongnu.org Subject: [PATCH v2 3/3] util/cacheflush: Optimize flushing when ppc host has coherent icache Date: Mon, 20 Jun 2022 18:48:37 -0700 Message-Id: <20220621014837.189139-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220621014837.189139-1-richard.henderson@linaro.org> References: <20220621014837.189139-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Nicholas Piggin On linux, the AT_HWCAP bit PPC_FEATURE_ICACHE_SNOOP indicates that we can use a simplified 3 instruction flush sequence. Signed-off-by: Nicholas Piggin Message-Id: <20220519141131.29839-1-npiggin@gmail.com> [rth: update after merging cacheflush.c and cacheinfo.c] Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- util/cacheflush.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/util/cacheflush.c b/util/cacheflush.c index 01b6cb7583..2c2c73e085 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -117,6 +117,10 @@ static void sys_cache_info(int *isize, int *dsize) * Architecture (+ OS) specific cache detection mechanisms. */ +#if defined(__powerpc__) +static bool have_coherent_icache; +#endif + #if defined(__aarch64__) && !defined(CONFIG_DARWIN) /* Apple does not expose CTR_EL0, so we must use system interfaces. */ static uint64_t save_ctr_el0; @@ -156,6 +160,7 @@ static void arch_cache_info(int *isize, int *dsize) if (*dsize == 0) { *dsize = qemu_getauxval(AT_DCACHEBSIZE); } + have_coherent_icache = qemu_getauxval(AT_HWCAP) & PPC_FEATURE_ICACHE_SNOOP; } #else @@ -298,8 +303,24 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) { uintptr_t p, b, e; - size_t dsize = qemu_dcache_linesize; - size_t isize = qemu_icache_linesize; + size_t dsize, isize; + + /* + * Some processors have coherent caches and support a simplified + * flushing procedure. See + * POWER9 UM, 4.6.2.2 Instruction Cache Block Invalidate (icbi) + * https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k + */ + if (have_coherent_icache) { + asm volatile ("sync\n\t" + "icbi 0,%0\n\t" + "isync" + : : "r"(rx) : "memory"); + return; + } + + dsize = qemu_dcache_linesize; + isize = qemu_icache_linesize; b = rw & ~(dsize - 1); e = (rw + len + dsize - 1) & ~(dsize - 1);