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Mon, 20 Jun 2022 12:37:32 +0000 From: Liu Ying To: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: kishon@ti.com, vkoul@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, krzysztof.kozlowski@linaro.org Subject: [PATCH v3 2/3] dt-bindings: phy: Add Freescale i.MX8qm Mixel LVDS PHY binding Date: Mon, 20 Jun 2022 20:38:53 +0800 Message-Id: <20220620123854.1138028-3-victor.liu@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220620123854.1138028-1-victor.liu@nxp.com> References: <20220620123854.1138028-1-victor.liu@nxp.com> X-ClientProxiedBy: SG2PR06CA0219.apcprd06.prod.outlook.com (2603:1096:4:68::27) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c5c744b8-3797-4047-1dda-08da52b9a59f X-MS-TrafficTypeDiagnostic: AM8PR04MB7873:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Liu Ying --- v2->v3: * Change compatible string from 'mixel,lvds-phy' to 'mixel,28fdsoi-lvds-1250-8ch-tx-pll' in patch 1/3. (Krzysztof) * Rename dt-binding file to 'fsl,imx8qm-lvds-phy.yaml'. (Krzysztof) v1->v2: * Set fsl,imx8qm-lvds-phy' and 'mixel,lvds-phy' as compatible's enum. (Krzysztof) * Skip 'clock-names' property. (Krzysztof) * Drop 'This patch' from commit message. (Krzysztof) .../bindings/phy/fsl,imx8qm-lvds-phy.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8qm-lvds-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8qm-lvds-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8qm-lvds-phy.yaml new file mode 100644 index 000000000000..8767e48c71a6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8qm-lvds-phy.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mixel LVDS PHY for Freescale i.MX8qm SoC + +maintainers: + - Liu Ying + +description: | + The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC. + It converts two groups of four 7/10 bits of CMOS data into two + groups of four data lanes of LVDS data streams. A phase-locked + transmit clock is transmitted in parallel with each group of + data streams over a fifth LVDS link. Every cycle of the transmit + clock, 56/80 bits of input data are sampled and transmitted + through the two groups of LVDS data streams. Together with the + transmit clocks, the two groups of LVDS data streams form two + LVDS channels. + + The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled + by Control and Status Registers(CSR) module in the SoC. The CSR + module, as a system controller, contains the PHY's registers. + +properties: + compatible: + enum: + - fsl,imx8qm-lvds-phy + - mixel,28fdsoi-lvds-1250-8ch-tx-pll + + "#phy-cells": + const: 1 + description: | + Cell allows setting the LVDS channel index of the PHY. + Index 0 is for LVDS channel0 and index 1 is for LVDS channel1. + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - "#phy-cells" + - clocks + - power-domains + +additionalProperties: false + +examples: + - | + #include + phy { + compatible = "fsl,imx8qm-lvds-phy"; + #phy-cells = <1>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + power-domains = <&pd IMX_SC_R_LVDS_0>; + };