From patchwork Fri Jun 17 14:47:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 582594 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 193F7CCA480 for ; Fri, 17 Jun 2022 14:47:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382881AbiFQOrY (ORCPT ); Fri, 17 Jun 2022 10:47:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382888AbiFQOrV (ORCPT ); Fri, 17 Jun 2022 10:47:21 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FAD5562D3 for ; Fri, 17 Jun 2022 07:47:19 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id s10so4959687ljh.12 for ; Fri, 17 Jun 2022 07:47:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JOBjrXoPoH1ofPIXqu96DbxIuUW2WoHytXZVgEy9tqQ=; b=CUlCysVkaum7qEAwP8IlB4QtfnbK66sIwJLAepVRt1Ht4HOYZ+d2iKSY7boaCWbQh6 ElDFnK7/V/9YSu+XUV9+dLH9/pkDn5GwQMvOUTQ1PcI4d7Aov6MMQP2NXHymFCDue3O/ Tcq84ow+y7EVuqCwaTswtK//ETfUdKAezfYWAHMwWNBiqA6zV1QXHAi+y/GNeEBOLEQe tQvHW4wPylB+Ngd1Kug5QgYOnovnDYAkwjkEteDjgRoBSRQE2YNw6H7/w6U+UCqofHX3 ruF1kVUyUfWJcOBFo4/kDUHS3a707qFDxitVNrezAXJjgd/58DKuLSgNOSoq+lml3MPj mGyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JOBjrXoPoH1ofPIXqu96DbxIuUW2WoHytXZVgEy9tqQ=; b=Ris/g5w4mwZ8dye7a0o2+NDZOzX4qWjb6uZPM1pBZCm5FiOxqm6BTHMsaUF3D/fyX0 8iLuYXoY4/iPrar7zEtIQZGCjd8JsKtpLYkz4Xw8HzwaSH7tJ9h8bd3MpPiD+zAfmLFw 5eWsjDM+cqITjX+xun0Sfg2W1OaRMqaKLoj2CjNFBKgEYm6+StlirhA9s1bQ+gpkdpVf 8O8XIhT65vFq1OAd/PitBue0CYcvqOOb1zlRpOj3R3COehPUqXceKJz+u3H5peM7SvH+ +NrEQB3ZD/WDA0K0Nqaujv72jRkD3DIiwV5Sa+uYc+rYYnZwB5zo2wMhHhbke6aBBQsL XUEA== X-Gm-Message-State: AJIora/4yLUmy48yKqYpCrnBsWy5lg77I41ThJWNM7ZTb4yMkVhdv20s RJJaa6hDk7AxAs1qsFOGwc7rog== X-Google-Smtp-Source: AGRyM1vTRxinlw1ys5/mB2Jj2rgEEFeP72Q+BPg7bTK+fQayywt4YGJIVqJNt+7qrN3ff+B3G94m3Q== X-Received: by 2002:a2e:b8d2:0:b0:255:93e3:6fb2 with SMTP id s18-20020a2eb8d2000000b0025593e36fb2mr5271126ljp.334.1655477237317; Fri, 17 Jun 2022 07:47:17 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id a5-20020a2eb165000000b002553ab60e17sm571867ljm.122.2022.06.17.07.47.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jun 2022 07:47:16 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/7] dt-bindings: clk: qcom,gcc-*: use qcom,gcc.yaml Date: Fri, 17 Jun 2022 17:47:08 +0300 Message-Id: <20220617144714.817765-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220617144714.817765-1-dmitry.baryshkov@linaro.org> References: <20220617144714.817765-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use qcom,gcc.yaml which contains a set of properties common to most Qualcomm GCC bindings. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,gcc-msm8976.yaml | 21 +++------------- .../bindings/clock/qcom,gcc-msm8994.yaml | 21 +++------------- .../bindings/clock/qcom,gcc-msm8996.yaml | 25 +++---------------- .../bindings/clock/qcom,gcc-msm8998.yaml | 25 +++---------------- .../bindings/clock/qcom,gcc-qcm2290.yaml | 25 +++---------------- .../bindings/clock/qcom,gcc-sc7180.yaml | 25 +++---------------- .../bindings/clock/qcom,gcc-sc7280.yaml | 21 +++------------- .../bindings/clock/qcom,gcc-sc8180x.yaml | 25 +++---------------- .../bindings/clock/qcom,gcc-sc8280xp.yaml | 21 +++------------- .../bindings/clock/qcom,gcc-sdm845.yaml | 25 +++---------------- .../bindings/clock/qcom,gcc-sdx55.yaml | 21 +++------------- .../bindings/clock/qcom,gcc-sdx65.yaml | 21 +++------------- .../bindings/clock/qcom,gcc-sm6115.yaml | 25 +++---------------- .../bindings/clock/qcom,gcc-sm6125.yaml | 25 +++---------------- .../bindings/clock/qcom,gcc-sm6350.yaml | 25 +++---------------- .../bindings/clock/qcom,gcc-sm8150.yaml | 25 +++---------------- .../bindings/clock/qcom,gcc-sm8250.yaml | 25 +++---------------- .../bindings/clock/qcom,gcc-sm8350.yaml | 21 +++------------- .../bindings/clock/qcom,gcc-sm8450.yaml | 21 +++------------- 19 files changed, 76 insertions(+), 367 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml index f3430b159caa..4b7d69518371 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml @@ -45,29 +45,16 @@ properties: description: Phandle to voltage regulator providing power to the GX domain. - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - - reg - clocks - clock-names - vdd_gfx-supply - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml index 22e67b238bb6..7b9fef6d9b23 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml @@ -32,28 +32,15 @@ properties: - const: xo - const: sleep - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml index 5a5b2214f0ca..70f7d3101bd3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml @@ -33,30 +33,13 @@ properties: - const: cxo2 - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml index 8151c0a05649..544a2335cf05 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml @@ -37,32 +37,15 @@ properties: - const: core_bi_pll_test_se # Optional clock minItems: 2 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml index 5de9c8263138..aec37e3f5e30 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml @@ -30,32 +30,15 @@ properties: - const: bi_tcxo - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml index a404c8fbee67..e4d490e65d14 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml @@ -33,32 +33,15 @@ properties: - const: bi_tcxo_ao - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml index 5693b8997570..ea61367e5abc 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml @@ -44,28 +44,15 @@ properties: - const: ufs_phy_tx_symbol_0_clk - const: usb3_phy_wrapper_gcc_usb30_pipe_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml index f03ef96e57fa..30b5d1215fa8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml @@ -32,32 +32,15 @@ properties: - const: bi_tcxo_ao - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml index 0bcdc69c6f89..e33dea86fb9e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml @@ -56,30 +56,17 @@ properties: - description: First EMAC controller reference clock - description: Second EMAC controller reference clock - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - protected-clocks: maxItems: 389 required: - compatible - clocks - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml index d902f137ab17..2b8a35d8739e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml @@ -37,30 +37,13 @@ properties: - const: pcie_0_pipe_clk - const: pcie_1_pipe_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: # Example for GCC for SDM845: diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml index b0d1c65aa354..13ffa16e0833 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml @@ -35,28 +35,15 @@ properties: - const: core_bi_pll_test_se # Optional clock minItems: 2 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml index 16c4cdc7b4d6..8a1419c4d465 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml @@ -20,9 +20,6 @@ properties: compatible: const: qcom,gcc-sdx65 - reg: - maxItems: 1 - clocks: items: - description: Board XO source @@ -43,25 +40,15 @@ properties: - const: core_bi_pll_test_se # Optional clock minItems: 5 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml index 26050da844d5..bb81a27a1b16 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml @@ -30,32 +30,15 @@ properties: - const: bi_tcxo - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml index ab12b391effc..03e84e15815c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml @@ -30,32 +30,15 @@ properties: - const: bi_tcxo - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml index 20926cd8293e..cbe98c01c085 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml @@ -32,32 +32,15 @@ properties: - const: bi_tcxo_ao - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml index 12766a866625..0333ccb07d8d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml @@ -31,32 +31,15 @@ properties: - const: bi_tcxo - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml index 80bd6caf5bc9..4e2a9cac0a91 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml @@ -31,32 +31,15 @@ properties: - const: bi_tcxo - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml index 1122700dcc2b..3edbeca70a9c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml @@ -54,28 +54,15 @@ properties: - const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock minItems: 2 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml index 58d98a766de6..102ce6862e24 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml @@ -46,28 +46,15 @@ properties: - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock minItems: 2 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | From patchwork Fri Jun 17 14:47:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 582593 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D767CCA47E for ; Fri, 17 Jun 2022 14:47:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382900AbiFQOr1 (ORCPT ); Fri, 17 Jun 2022 10:47:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382909AbiFQOrY (ORCPT ); Fri, 17 Jun 2022 10:47:24 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A58AA562D8 for ; Fri, 17 Jun 2022 07:47:21 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id p18so7327684lfr.1 for ; Fri, 17 Jun 2022 07:47:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1XfJMqbTrvbGcMadqMaMwRzo8TXWgiYVxdNJ7Eqss70=; b=vGnAFO/fURW0gLwkyY/HZyJ0ogR1nBEC+8q0lKZRgiYnOjLy6F2kotHhHPoMm+hdcM MJuI7NZ+cyaMPRMGKWD2CZGOwi0+W9T/vpb07INJF7f6r45IBZxnRanJYMTlIt5Rku5P fmUJH8j7eUsHzB7ldYoEaenYcHORWjeDI+3XccYWq7hkLn5/JNryzRA7VJlrg5OJJ+BL K3AYm0JKNg43Q1J44chOwbKEBZ464CBJZeB9UEXj7QAoSqdacFGrMcCDK3dbFgpB1HhY UTRtZK0T4hcmSswVqzfUM6yqH8kA2lQhEKGAEpdtutt1Y7q+vzgGAk0Enb1IVD5Q5CWH HnOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1XfJMqbTrvbGcMadqMaMwRzo8TXWgiYVxdNJ7Eqss70=; b=K8KFzzjUI2rYtislGyFqxeYyM8c+PgQNb/HH6W6TGjklW7htftz2CUa8P2agU+5Uit A23dZjc8/f4864LUQctM4pfVhMyC6OyCAgm/Q0UesAgtkFh4VM8zzpqElzxSmujsEExY WPHQrU56WyyZ7hCtw5o9n0yFsp9KGjCt/D4kshV405J2uM7nBhYzlUZgNJg3G9y/LGBb dd18FB13a0rV24JopVeSVtD4OclY8983WdOoKoZcu8Wdxfspfsxxk14yVzB09STVvOd/ myZfBcm5RDBuzVHyHBmCv5JEKoHOczBK79KHL/bGXJIPYBrRkfYKKC/lxtvI0AsKemmE T1mA== X-Gm-Message-State: AJIora8mDxIE7SnOtFzmZxGPWhgoVYPuI3Fe/mpXjM7U+pbbgF0XVeqP rpS9CRsgW1iGLjxcmTT9/rPJgg== X-Google-Smtp-Source: AGRyM1tZi+FF4ijFfSZQEgd2Yye+1ha66LiA4fTBBptbxQwfTbQ28e5634+KsiBBB3kIJTcnUZnnRA== X-Received: by 2002:a05:6512:22cf:b0:479:3f72:f977 with SMTP id g15-20020a05651222cf00b004793f72f977mr5753802lfu.255.1655477240030; Fri, 17 Jun 2022 07:47:20 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id a5-20020a2eb165000000b002553ab60e17sm571867ljm.122.2022.06.17.07.47.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jun 2022 07:47:19 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 4/7] clk: qcom: gcc-msm8916: move clock parent tables down Date: Fri, 17 Jun 2022 17:47:11 +0300 Message-Id: <20220617144714.817765-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220617144714.817765-1-dmitry.baryshkov@linaro.org> References: <20220617144714.817765-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move clock parent tables down, after the GPLL declrataions, so that we can use gpll hw clock fields in the next commit. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-msm8916.c | 216 ++++++++++++++++----------------- 1 file changed, 108 insertions(+), 108 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index 40c27ba6286f..7962edbdbcf6 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c @@ -42,6 +42,114 @@ enum { P_EXT_MCLK, }; +static struct clk_pll gpll0 = { + .l_reg = 0x21004, + .m_reg = 0x21008, + .n_reg = 0x2100c, + .config_reg = 0x21010, + .mode_reg = 0x21000, + .status_reg = 0x2101c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll0", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll0_vote = { + .enable_reg = 0x45000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_vote", + .parent_names = (const char *[]){ "gpll0" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static struct clk_pll gpll1 = { + .l_reg = 0x20004, + .m_reg = 0x20008, + .n_reg = 0x2000c, + .config_reg = 0x20010, + .mode_reg = 0x20000, + .status_reg = 0x2001c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll1", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll1_vote = { + .enable_reg = 0x45000, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gpll1_vote", + .parent_names = (const char *[]){ "gpll1" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static struct clk_pll gpll2 = { + .l_reg = 0x4a004, + .m_reg = 0x4a008, + .n_reg = 0x4a00c, + .config_reg = 0x4a010, + .mode_reg = 0x4a000, + .status_reg = 0x4a01c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll2", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll2_vote = { + .enable_reg = 0x45000, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "gpll2_vote", + .parent_names = (const char *[]){ "gpll2" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static struct clk_pll bimc_pll = { + .l_reg = 0x23004, + .m_reg = 0x23008, + .n_reg = 0x2300c, + .config_reg = 0x23010, + .mode_reg = 0x23000, + .status_reg = 0x2301c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "bimc_pll", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap bimc_pll_vote = { + .enable_reg = 0x45000, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "bimc_pll_vote", + .parent_names = (const char *[]){ "bimc_pll" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + static const struct parent_map gcc_xo_gpll0_map[] = { { P_XO, 0 }, { P_GPLL0, 1 }, @@ -256,114 +364,6 @@ static const char * const gcc_xo_gpll1_emclk_sleep[] = { "sleep_clk", }; -static struct clk_pll gpll0 = { - .l_reg = 0x21004, - .m_reg = 0x21008, - .n_reg = 0x2100c, - .config_reg = 0x21010, - .mode_reg = 0x21000, - .status_reg = 0x2101c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll0", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll0_vote = { - .enable_reg = 0x45000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0_vote", - .parent_names = (const char *[]){ "gpll0" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - -static struct clk_pll gpll1 = { - .l_reg = 0x20004, - .m_reg = 0x20008, - .n_reg = 0x2000c, - .config_reg = 0x20010, - .mode_reg = 0x20000, - .status_reg = 0x2001c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll1", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll1_vote = { - .enable_reg = 0x45000, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gpll1_vote", - .parent_names = (const char *[]){ "gpll1" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - -static struct clk_pll gpll2 = { - .l_reg = 0x4a004, - .m_reg = 0x4a008, - .n_reg = 0x4a00c, - .config_reg = 0x4a010, - .mode_reg = 0x4a000, - .status_reg = 0x4a01c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll2", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll2_vote = { - .enable_reg = 0x45000, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "gpll2_vote", - .parent_names = (const char *[]){ "gpll2" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - -static struct clk_pll bimc_pll = { - .l_reg = 0x23004, - .m_reg = 0x23008, - .n_reg = 0x2300c, - .config_reg = 0x23010, - .mode_reg = 0x23000, - .status_reg = 0x2301c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "bimc_pll", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap bimc_pll_vote = { - .enable_reg = 0x45000, - .enable_mask = BIT(3), - .hw.init = &(struct clk_init_data){ - .name = "bimc_pll_vote", - .parent_names = (const char *[]){ "bimc_pll" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - static struct clk_rcg2 pcnoc_bfdcd_clk_src = { .cmd_rcgr = 0x27000, .hid_width = 5, From patchwork Fri Jun 17 14:47:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 582592 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51C34CCA47E for ; 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Fri, 17 Jun 2022 07:47:22 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: qcom: msm8916: add clocks to the GCC device node Date: Fri, 17 Jun 2022 17:47:14 +0300 Message-Id: <20220617144714.817765-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220617144714.817765-1-dmitry.baryshkov@linaro.org> References: <20220617144714.817765-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As we are converting this platform to use DT clock bindings, add clocks and clock-names properties to the MMCC device tree node. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 05472510e29d..e905415b3456 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -934,6 +934,20 @@ gcc: clock-controller@1800000 { #reset-cells = <1>; #power-domain-cells = <1>; reg = <0x01800000 0x80000>; + clocks = <&rpmcc RPM_SMD_BB_CLK1_PIN>, + <&sleep_clk>, + <&dsi_phy0 1>, + <&dsi_phy0 0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "sleep_clk", + "dsi0pll", + "dsi0pllbyte", + "ext_mclk", + "ext_pri_i2s", + "ext_sec_i2s"; }; tcsr_mutex: hwlock@1905000 {