From patchwork Sun Jun 12 14:59:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Travkin X-Patchwork-Id: 581339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF691CCA481 for ; Sun, 12 Jun 2022 15:10:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237545AbiFLPKl (ORCPT ); Sun, 12 Jun 2022 11:10:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235438AbiFLPKh (ORCPT ); Sun, 12 Jun 2022 11:10:37 -0400 Received: from box.trvn.ru (box.trvn.ru [194.87.146.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 897865EDDE; Sun, 12 Jun 2022 08:10:34 -0700 (PDT) Received: from authenticated-user (box.trvn.ru [194.87.146.52]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by box.trvn.ru (Postfix) with ESMTPSA id B1FF841D02; Sun, 12 Jun 2022 20:00:15 +0500 (+05) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=trvn.ru; s=mail; t=1655046016; bh=/tYoU7VP1Rn/khkbkGNDTLOLEh/Vu49IcFrpgY0sx3I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=4ZKOeOxsXhGM+g8zP40BpLXslpi3ggurlZOVtBfMEY0mErOv8FOBpIdpoOF8wBvZc jYdiMefjlEkOBUnlJGPkK9/3r+zvT4TvrA2bcVNd6WxPGo7ovVXeQrJmx7SxJU6xZs a0OxMz8INL0JtdLXeojfThuDFJpFTIO38MZoBTVHUp8VxOoPrpDZF4Mba3hEKJH4Nf xviF0BHHuEP76oaQAzBseTw4ORw/gHpFJdp0hZMP8N+PDQyJm7PKhTKADXe05CAFE+ Mf3DJA9y4phttFbA0VYXGNx3LHzxnZixOO0/Zq6cQJJKevEm6y01yIP95rNn8+ZMBe NpPv+ujhW92jA== From: Nikita Travkin To: mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org Cc: bjorn.andersson@linaro.org, agross@kernel.org, tdas@codeaurora.org, joonwoop@codeaurora.org, svarbanov@mm-sol.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nikita Travkin Subject: [PATCH v2 1/4] clk: qcom: clk-rcg2: Fail Duty-Cycle configuration if MND divider is not enabled. Date: Sun, 12 Jun 2022 19:59:52 +0500 Message-Id: <20220612145955.385787-2-nikita@trvn.ru> In-Reply-To: <20220612145955.385787-1-nikita@trvn.ru> References: <20220612145955.385787-1-nikita@trvn.ru> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org In cases when MND is not enabled (e.g. when only Half Integer Divider is used), setting D registers makes no effect. Fail instead of making ineffective write. Fixes: 7f891faf596e ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG") Signed-off-by: Nikita Travkin Reviewed-by: Stephen Boyd --- drivers/clk/qcom/clk-rcg2.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 8e5dce09d162..2375e8122012 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -437,7 +437,7 @@ static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); - u32 notn_m, n, m, d, not2d, mask, duty_per; + u32 notn_m, n, m, d, not2d, mask, duty_per, cfg; int ret; /* Duty-cycle cannot be modified for non-MND RCGs */ @@ -448,6 +448,11 @@ static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty) regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m); regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); + regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); + + /* Duty-cycle cannot be modified if MND divider is in bypass mode. */ + if (!(cfg & CFG_MODE_MASK)) + return -EINVAL; n = (~(notn_m) + m) & mask; From patchwork Sun Jun 12 14:59:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Travkin X-Patchwork-Id: 581340 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 225BECCA47C for ; Sun, 12 Jun 2022 15:10:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237535AbiFLPKj (ORCPT ); Sun, 12 Jun 2022 11:10:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230238AbiFLPKg (ORCPT ); Sun, 12 Jun 2022 11:10:36 -0400 X-Greylist: delayed 616 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Sun, 12 Jun 2022 08:10:34 PDT Received: from box.trvn.ru (box.trvn.ru [194.87.146.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8962B5EDDA; Sun, 12 Jun 2022 08:10:34 -0700 (PDT) Received: from authenticated-user (box.trvn.ru [194.87.146.52]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by box.trvn.ru (Postfix) with ESMTPSA id A090E4B00F; Sun, 12 Jun 2022 20:00:17 +0500 (+05) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=trvn.ru; s=mail; t=1655046018; bh=jp2x8yViozN+IlCDICU84cGBy/PA8CqFPQjOLcNghP4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=0vV3m+5K8dSKvmJj7/SUdo6ffKiYXkTXdUrysE7DsUPQtw1doZEwx3DXzAceZjSbv Yn5/pATx4Wy9h2DJV+9xv5YbFqJClpyiggKQCOn9NWuz6fyLTlkahiQXtP+/b1HI16 Ror6F0itvSyCAmMXuXH1MoqSrrA4gQszRZRg3V1iWa2iTC8gnY1pwDuYESpPoPHVLl 9Ssm8YpDMUwWu0sr2BbiFcPIgh8QClI+639yhrC4ooPbBFeb8YavbLjObNYo+pKKTB xsi1x4dtvjQ8ECEmkTewlB6/+y7qXK+ptd1YXiuEB1DJr5R+3NTzC1/siWHDAhI27t 2hj5Z05qy8T+Q== From: Nikita Travkin To: mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org Cc: bjorn.andersson@linaro.org, agross@kernel.org, tdas@codeaurora.org, joonwoop@codeaurora.org, svarbanov@mm-sol.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nikita Travkin Subject: [PATCH v2 3/4] pinctrl: qcom: msm8916: Allow CAMSS GP clocks to be muxed Date: Sun, 12 Jun 2022 19:59:54 +0500 Message-Id: <20220612145955.385787-4-nikita@trvn.ru> In-Reply-To: <20220612145955.385787-1-nikita@trvn.ru> References: <20220612145955.385787-1-nikita@trvn.ru> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org GPIO 31, 32 can be muxed to GCC_CAMSS_GP(1,2)_CLK respectively but the function was never assigned to the pingroup (even though the function exists already). Add this mode to the related pins. Fixes: 5373a2c5abb6 ("pinctrl: qcom: Add msm8916 pinctrl driver") Signed-off-by: Nikita Travkin --- drivers/pinctrl/qcom/pinctrl-msm8916.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm8916.c b/drivers/pinctrl/qcom/pinctrl-msm8916.c index 396db12ae904..bf68913ba821 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8916.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c @@ -844,8 +844,8 @@ static const struct msm_pingroup msm8916_groups[] = { PINGROUP(28, pwr_modem_enabled_a, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, atest_combodac), PINGROUP(29, cci_i2c, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, atest_combodac), PINGROUP(30, cci_i2c, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), - PINGROUP(31, cci_timer0, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(32, cci_timer1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(31, cci_timer0, flash_strobe, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, cci_timer1, flash_strobe, NA, NA, NA, NA, NA, NA, NA), PINGROUP(33, cci_async, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), PINGROUP(34, pwr_nav_enabled_a, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), PINGROUP(35, pwr_crypto_enabled_a, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b), From patchwork Sun Jun 12 14:59:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Travkin X-Patchwork-Id: 581338 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF77DCCA487 for ; Sun, 12 Jun 2022 15:10:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234370AbiFLPKm (ORCPT ); Sun, 12 Jun 2022 11:10:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237475AbiFLPKh (ORCPT ); Sun, 12 Jun 2022 11:10:37 -0400 Received: from box.trvn.ru (box.trvn.ru [194.87.146.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D2BA5EDE1; Sun, 12 Jun 2022 08:10:34 -0700 (PDT) Received: from authenticated-user (box.trvn.ru [194.87.146.52]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by box.trvn.ru (Postfix) with ESMTPSA id 42F564B010; Sun, 12 Jun 2022 20:00:18 +0500 (+05) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=trvn.ru; s=mail; t=1655046018; bh=d75aH6lgsop7H0tTJMNEsXUOXMX4zeKLj6KVJaiEtl4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EaGNG4X9LzC4R+SBFyBhIoZYMfcgbDfpjypiC3F+s1ziY2oFYp4ZxR1c7NGzgKnXT R5FPPlTa5+0WGxD2r3iYW5Edq1GrlBGkl6qHcBeY8Oi2rTfOdH/lBWt/2OFntqtE5n Muc7aBr1Gd/NyrlN9Rid1o9+t8behBxbQ8q1ADSbX0IoN1xpLyOgmpa8hK9UvHj+44 RvHMh+N8eEB1DbfkGbrSN7/INyeQOcxBwWs/BSO6ybjdPie226PtZluC3UEF1bq4S9 SDiprayGYE5Q3fhIOvC7RIwBQ9zmojnLDoi4473YR/2Mb4wKajIIBuKfcUB4QWt/e8 RmeYtdHVNOckQ== From: Nikita Travkin To: mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org Cc: bjorn.andersson@linaro.org, agross@kernel.org, tdas@codeaurora.org, joonwoop@codeaurora.org, svarbanov@mm-sol.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nikita Travkin Subject: [PATCH v2 4/4] clk: qcom: gcc-msm8916: Add rates to the GP clocks Date: Sun, 12 Jun 2022 19:59:55 +0500 Message-Id: <20220612145955.385787-5-nikita@trvn.ru> In-Reply-To: <20220612145955.385787-1-nikita@trvn.ru> References: <20220612145955.385787-1-nikita@trvn.ru> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org msm8916 has (at least) 6 "General Purpose" clocks that can be muxed to SoC pins. These clocks are: GP_CLK{0, 1} : GPIO_{31, 32} (Belongs to CAMSS according to Linux) GP_CLK_{1-3}{A, B} : GPIO_{49-51, 97, 12, 13} (Belongs to GCC itself) GP_MN : GPIO_110 (Doesn't seem to be described in gcc, ignored in this patch) Those clocks may be used as e.g. PWM sources for external peripherals. Add more frequencies to the table for those clocks so it's possible for arbitrary peripherals to make use of them. Reviewed-by: Stephen Boyd Signed-off-by: Nikita Travkin --- drivers/clk/qcom/gcc-msm8916.c | 35 ++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index 17e4a5a2a9fd..9a46794f6eb8 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c @@ -765,7 +765,20 @@ static struct clk_rcg2 cci_clk_src = { }, }; +/* + * This is a frequency table for "General Purpose" clocks. + * These clocks can be muxed to the SoC pins and may be used by + * external devices. They're often used as PWM source. + * + * See comment at ftbl_gcc_gp1_3_clk. + */ static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = { + F(10000, P_XO, 16, 1, 120), + F(100000, P_XO, 16, 1, 12), + F(500000, P_GPLL0, 16, 1, 100), + F(1000000, P_GPLL0, 16, 1, 50), + F(2500000, P_GPLL0, 16, 1, 20), + F(5000000, P_GPLL0, 16, 1, 10), F(100000000, P_GPLL0, 8, 0, 0), F(200000000, P_GPLL0, 4, 0, 0), { } @@ -927,7 +940,29 @@ static struct clk_rcg2 crypto_clk_src = { }, }; +/* + * This is a frequency table for "General Purpose" clocks. + * These clocks can be muxed to the SoC pins and may be used by + * external devices. They're often used as PWM source. + * + * Please note that MND divider must be enabled for duty-cycle + * control to be possible. (M != N) Also since D register is configured + * with a value multiplied by 2, and duty cycle is calculated as + * (2 * D) % 2^W + * DutyCycle = ---------------- + * 2 * (N % 2^W) + * (where W = .mnd_width) + * N must be half or less than maximum value for the register. + * Otherwise duty-cycle control would be limited. + * (e.g. for 8-bit NMD N should be less than 128) + */ static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = { + F(10000, P_XO, 16, 1, 120), + F(100000, P_XO, 16, 1, 12), + F(500000, P_GPLL0, 16, 1, 100), + F(1000000, P_GPLL0, 16, 1, 50), + F(2500000, P_GPLL0, 16, 1, 20), + F(5000000, P_GPLL0, 16, 1, 10), F(19200000, P_XO, 1, 0, 0), { } };