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Thu, 9 Jun 2022 12:49:25 +0000 From: "Peng Fan (OSS)" To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sboyd@kernel.org, mturquette@baylibre.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: aisheng.dong@nxp.com, l.stach@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Peng Fan , Krzysztof Kozlowski Subject: [PATCH V4 2/7] dt-bindings: soc: add i.MX93 mediamix blk ctrl Date: Thu, 9 Jun 2022 20:50:55 +0800 Message-Id: <20220609125100.3496633-3-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609125100.3496633-1-peng.fan@oss.nxp.com> References: <20220609125100.3496633-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI2PR06CA0014.apcprd06.prod.outlook.com (2603:1096:4:186::11) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 28a14e0c-6dc3-4a11-7b43-08da4a167be0 X-MS-TrafficTypeDiagnostic: AM7PR04MB6952:EE_ X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Peng Fan Reviewed-by: Krzysztof Kozlowski --- .../soc/imx/fsl,imx93-media-blk-ctrl.yaml | 80 +++++++++++++++++++ include/dt-bindings/power/fsl,imx93-power.h | 6 ++ 2 files changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml new file mode 100644 index 000000000000..792ebecec22d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx93-media-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX93 Media blk-ctrl + +maintainers: + - Peng Fan + +description: + The i.MX93 MEDIAMIX domain contains control and status registers known + as MEDIAMIX Block Control (MEDIAMIX BLK_CTRL). These registers include + clocking, reset, and miscellaneous top-level controls for peripherals + within the MEDIAMIX domain + +properties: + compatible: + items: + - const: fsl,imx93-media-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 10 + + clock-names: + items: + - const: apb + - const: axi + - const: nic + - const: disp + - const: cam + - const: pxp + - const: lcdif + - const: isi + - const: csi + - const: dsi + +required: + - compatible + - reg + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + media_blk_ctrl: system-controller@4ac10000 { + compatible = "fsl,imx93-media-blk-ctrl", "syscon"; + reg = <0x4ac10000 0x10000>; + power-domains = <&mediamix>; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_NIC_MEDIA_GATE>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_PXP_GATE>, + <&clk IMX93_CLK_LCDIF_GATE>, + <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MIPI_CSI_GATE>, + <&clk IMX93_CLK_MIPI_DSI_GATE>; + clock-names = "apb", "axi", "nic", "disp", "cam", + "pxp", "lcdif", "isi", "csi", "dsi"; + #power-domain-cells = <1>; + }; diff --git a/include/dt-bindings/power/fsl,imx93-power.h b/include/dt-bindings/power/fsl,imx93-power.h index 27fb7df80f93..b3d2d9619d3a 100644 --- a/include/dt-bindings/power/fsl,imx93-power.h +++ b/include/dt-bindings/power/fsl,imx93-power.h @@ -8,4 +8,10 @@ #define IMX93_POWER_DOMAIN_MEDIAMIX 0 +#define IMX93_MEDIABLK_PD_MIPI_DSI 0 +#define IMX93_MEDIABLK_PD_MIPI_CSI 1 +#define IMX93_MEDIABLK_PD_PXP 2 +#define IMX93_MEDIABLK_PD_LCDIF 3 +#define IMX93_MEDIABLK_PD_ISI 4 + #endif From patchwork Thu Jun 9 12:50:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 580928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D18CFC433EF for ; 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Current supported power domain is mediamix power domain. Signed-off-by: Peng Fan --- drivers/soc/imx/Kconfig | 10 ++ drivers/soc/imx/Makefile | 1 + drivers/soc/imx/imx93-pd.c | 271 +++++++++++++++++++++++++++++++++++++ 3 files changed, 282 insertions(+) create mode 100644 drivers/soc/imx/imx93-pd.c diff --git a/drivers/soc/imx/Kconfig b/drivers/soc/imx/Kconfig index a840494e849a..5bfc1dfea28b 100644 --- a/drivers/soc/imx/Kconfig +++ b/drivers/soc/imx/Kconfig @@ -20,4 +20,14 @@ config SOC_IMX8M support, it will provide the SoC info like SoC family, ID and revision etc. +config SOC_IMX9 + tristate "i.MX9 SoC family support" + depends on ARCH_MXC || COMPILE_TEST + default ARCH_MXC && ARM64 + select SOC_BUS + select PM_GENERIC_DOMAINS + help + If you say yes here you get support for the NXP i.MX9 family + support. + endmenu diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile index 63cd29f6d4d2..e3ed07a6bcf9 100644 --- a/drivers/soc/imx/Makefile +++ b/drivers/soc/imx/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o obj-$(CONFIG_SOC_IMX8M) += imx8mp-blk-ctrl.o +obj-$(CONFIG_SOC_IMX9) += imx93-pd.o diff --git a/drivers/soc/imx/imx93-pd.c b/drivers/soc/imx/imx93-pd.c new file mode 100644 index 000000000000..d4f8a8941759 --- /dev/null +++ b/drivers/soc/imx/imx93-pd.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 NXP. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define IMX93_SRC_MEDIAMIX_OFF 0x2400 + +#define MIX_SLICE_SW_CTRL_OFF 0x20 +#define SLICE_SW_CTRL_PSW_CTRL_OFF_MASK BIT(4) +#define SLICE_SW_CTRL_PDN_SOFT_MASK BIT(31) + +#define MIX_FUNC_STAT_OFF 0xB4 + +#define FUNC_STAT_PSW_STAT_MASK BIT(0) +#define FUNC_STAT_RST_STAT_MASK BIT(2) +#define FUNC_STAT_ISO_STAT_MASK BIT(4) + +struct imx93_slice_info { + char *name; + u32 mix_off; +}; + +struct imx93_plat_data { + u32 num_slice; + struct imx93_slice_info *slices; +}; + +struct imx93_power_domain { + struct generic_pm_domain genpd; + struct device *dev; + void * __iomem base; + const struct imx93_slice_info *slice_info; + struct clk_bulk_data *clks; + int num_clks; +}; + +#define to_imx93_pd(_genpd) container_of(_genpd, struct imx93_power_domain, genpd) + +struct imx93_slice_info imx93_slice_infos[] = { + [IMX93_POWER_DOMAIN_MEDIAMIX] = { + .name = "mediamix", + .mix_off = IMX93_SRC_MEDIAMIX_OFF, + } +}; + +struct imx93_plat_data imx93_plat_data = { + .num_slice = ARRAY_SIZE(imx93_slice_infos), + .slices = imx93_slice_infos, +}; + +static int imx93_pd_on(struct generic_pm_domain *genpd) +{ + struct imx93_power_domain *domain = to_imx93_pd(genpd); + const struct imx93_slice_info *slice_info = domain->slice_info; + void * __iomem addr = domain->base + slice_info->mix_off; + u32 val; + int ret; + + ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks); + if (ret) { + dev_err(domain->dev, "failed to enable clocks for domain: %s\n", genpd->name); + return ret; + } + + val = readl(addr + MIX_SLICE_SW_CTRL_OFF); + val &= ~SLICE_SW_CTRL_PDN_SOFT_MASK; + writel(val, addr + MIX_SLICE_SW_CTRL_OFF); + + ret = readl_poll_timeout(addr + MIX_FUNC_STAT_OFF, val, + !(val & FUNC_STAT_ISO_STAT_MASK), 1, 10000); + if (ret) { + dev_err(domain->dev, "pd_on timeout: name: %s, stat: %x\n", genpd->name, val); + return ret; + } + + return 0; +} + +static int imx93_pd_off(struct generic_pm_domain *genpd) +{ + struct imx93_power_domain *domain = to_imx93_pd(genpd); + const struct imx93_slice_info *slice_info = domain->slice_info; + void * __iomem addr = domain->base + slice_info->mix_off; + int ret; + u32 val; + + /* Power off MIX */ + val = readl(addr + MIX_SLICE_SW_CTRL_OFF); + val |= SLICE_SW_CTRL_PDN_SOFT_MASK; + writel(val, addr + MIX_SLICE_SW_CTRL_OFF); + + ret = readl_poll_timeout(addr + MIX_FUNC_STAT_OFF, val, + val & FUNC_STAT_PSW_STAT_MASK, 1, 1000); + if (ret) { + dev_err(domain->dev, "pd_off timeout: name: %s, stat: %x\n", genpd->name, val); + return ret; + } + + clk_bulk_disable_unprepare(domain->num_clks, domain->clks); + + return 0; +}; + +static const struct of_device_id imx93_power_domain_ids[] = { + { .compatible = "fsl,imx93-src", .data = &imx93_plat_data, }, + {}, +}; + +static int imx93_pd_remove(struct platform_device *pdev) +{ + struct imx93_power_domain *pd = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + const struct imx93_plat_data *data = of_device_get_match_data(dev); + u32 num_domains = data->num_slice; + struct device_node *slice_np, *np; + int ret; + + slice_np = of_get_child_by_name(pdev->dev.of_node, "slice"); + + for_each_child_of_node(slice_np, np) { + struct imx93_power_domain *domain; + u32 index; + + if (!of_device_is_available(np)) + continue; + + ret = of_property_read_u32(np, "reg", &index); + if (ret) { + dev_err(dev, "Failed to read 'reg' property\n"); + of_node_put(np); + return ret; + } + + if (index >= num_domains) { + dev_warn(dev, "Domain index %d is out of bounds\n", index); + continue; + } + + domain = &pd[index]; + + of_genpd_del_provider(np); + + pm_genpd_remove(&domain->genpd); + clk_bulk_put_all(domain->num_clks, domain->clks); + }; + + return 0; +} + +static int imx93_pd_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct imx93_plat_data *data = of_device_get_match_data(dev); + const struct imx93_slice_info *slice_info = data->slices; + struct imx93_power_domain *pd; + u32 num_domains = data->num_slice; + struct device_node *slice_np, *np; + void __iomem *base; + bool is_off; + int ret; + + slice_np = of_get_child_by_name(dev->of_node, "slice"); + if (!slice_np) { + dev_err(dev, "No slices specified in DT\n"); + return -EINVAL; + } + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + pd = devm_kcalloc(dev, num_domains, sizeof(*pd), GFP_KERNEL); + if (!pd) + return -ENOMEM; + + platform_set_drvdata(pdev, pd); + + for_each_child_of_node(slice_np, np) { + struct imx93_power_domain *domain; + u32 index; + + if (!of_device_is_available(np)) + continue; + + ret = of_property_read_u32(np, "reg", &index); + if (ret) { + dev_err(dev, "Failed to read 'reg' property\n"); + of_node_put(np); + return ret; + } + + if (index >= num_domains) { + dev_warn(dev, "Domain index %d is out of bounds\n", index); + continue; + } + + domain = &pd[index]; + + domain->num_clks = of_clk_bulk_get_all(np, &domain->clks); + if (domain->num_clks < 0) { + return dev_err_probe(domain->dev, domain->num_clks, + "Failed to get %s's clocks\n", + slice_info[index].name); + } + + domain->genpd.name = slice_info[index].name; + domain->genpd.power_off = imx93_pd_off; + domain->genpd.power_on = imx93_pd_on; + domain->slice_info = &slice_info[index]; + domain->base = base; + + is_off = readl(domain->base + slice_info->mix_off + MIX_FUNC_STAT_OFF) & + FUNC_STAT_ISO_STAT_MASK; + /* Just to sync the status of hardware */ + if (!is_off) { + ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks); + if (ret) { + dev_err(domain->dev, "failed to enable clocks for domain: %s\n", + domain->genpd.name); + clk_bulk_put_all(domain->num_clks, domain->clks); + return 0; + } + } + + dev_info(dev, "%s: state: %x\n", domain->genpd.name, + readl(domain->base + MIX_FUNC_STAT_OFF)); + ret = pm_genpd_init(&domain->genpd, NULL, is_off); + if (ret) { + dev_err(dev, "failed to init genpd\n"); + clk_bulk_put_all(domain->num_clks, domain->clks); + return ret; + } + + ret = of_genpd_add_provider_simple(np, &domain->genpd); + if (ret) { + clk_bulk_put_all(domain->num_clks, domain->clks); + return ret; + } + } + + return 0; +} + +static const struct of_device_id imx93_dt_ids[] = { + { .compatible = "fsl,imx93-src", .data = &imx93_plat_data, }, + { } +}; + +static struct platform_driver imx93_power_domain_driver = { + .driver = { + .name = "imx93_power_domain", + .owner = THIS_MODULE, + .of_match_table = imx93_dt_ids, + }, + .probe = imx93_pd_probe, + .remove = imx93_pd_remove, +}; +module_platform_driver(imx93_power_domain_driver); + +MODULE_AUTHOR("Peng Fan "); +MODULE_DESCRIPTION("NXP i.MX93 power domain driver"); +MODULE_LICENSE("GPL v2"); From patchwork Thu Jun 9 12:51:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 580927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABB3BC43334 for ; Thu, 9 Jun 2022 12:50:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243805AbiFIMuK (ORCPT ); Thu, 9 Jun 2022 08:50:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245483AbiFIMuG (ORCPT ); Thu, 9 Jun 2022 08:50:06 -0400 Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2040.outbound.protection.outlook.com [40.107.21.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2F89138936; 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Thu, 9 Jun 2022 12:49:48 +0000 From: "Peng Fan (OSS)" To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sboyd@kernel.org, mturquette@baylibre.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: aisheng.dong@nxp.com, l.stach@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Peng Fan Subject: [PATCH V4 7/7] arm64: dts: imx93: add mediamix blk ctrl node Date: Thu, 9 Jun 2022 20:51:00 +0800 Message-Id: <20220609125100.3496633-8-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609125100.3496633-1-peng.fan@oss.nxp.com> References: <20220609125100.3496633-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI2PR06CA0014.apcprd06.prod.outlook.com (2603:1096:4:186::11) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1cdc3913-dc57-416c-efed-08da4a1689b8 X-MS-TrafficTypeDiagnostic: AM5PR0402MB2818:EE_ X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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gpio-ranges = <&iomuxc 0 0 32>; }; + + media_blk_ctrl: power-controller@4ac10000 { + compatible = "fsl,imx93-media-blk-ctrl", "syscon"; + reg = <0x4ac10000 0x10000>; + power-domains = <&mediamix>; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_NIC_MEDIA_GATE>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_PXP_GATE>, + <&clk IMX93_CLK_LCDIF_GATE>, + <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MIPI_CSI_GATE>, + <&clk IMX93_CLK_MIPI_DSI_GATE>; + clock-names = "apb", "axi", "nic", "disp", "cam", + "pxp", "lcdif", "isi", "csi", "dsi"; + #power-domain-cells = <1>; + status = "disabled"; + }; }; };