From patchwork Fri Jun 10 07:21:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 580879 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E16DC43334 for ; Fri, 10 Jun 2022 07:22:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346726AbiFJHWq (ORCPT ); Fri, 10 Jun 2022 03:22:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346721AbiFJHWm (ORCPT ); Fri, 10 Jun 2022 03:22:42 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF1393F333; Fri, 10 Jun 2022 00:22:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1654845718; bh=IQX8e4DimYSxfYiB0892MoZKJaCfS7TtVYY2navJcRE=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=CuMibIAZmB/ve2MuTr1f1+wZVderTUs7KGiC13adrseH2oLgJT4zT8wqkV4hqMauL 8W7TK1+u22oOoDY+LIJa8HI9JXrLrseZbbirKlJmpgTR57jaaVfz2mLGe9ob7FDjlf D3eeelWzAIdUfOHB8PbJG+WpyqqpqS1JuXdF7UJ4= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.195.3]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MuDXp-1nlLT91uOb-00ucv9; Fri, 10 Jun 2022 09:21:58 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski Subject: [PATCH v4 1/6] dt-bindings: timer: nuvoton,npcm7xx-timer: Allow specifying all clocks Date: Fri, 10 Jun 2022 09:21:36 +0200 Message-Id: <20220610072141.347795-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220610072141.347795-1-j.neuschaefer@gmx.net> References: <20220610072141.347795-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:yBVwif+DGktWM+o9r7sNiZrEwl/zKMtKSiq2+UCGtlsbNtgIk7x /bbX2sXzYaXAHSx44puYxomiEoqtXeh96nX3Juh/ZB+ZLZn7Na1fVtezN2XCv8yIcCHMfOp 6fh5zvIqvP5lpYYiQJ7clKDGsnJE+kiOYvK6wveqk+3IERfbN/R0A10m7PgewWhnTtZnhXG pxyEgviIcFGYC0xKZ2leg== X-UI-Out-Filterresults: notjunk:1;V03:K0:OysjaKN0sh4=:FlL2Ak8DjTMz8OOajXTmsw tDNGd70HsIgiPxXBYKsnztMa+Fk+Pml/h35M59WmgIjr6X7U/mOLkuQ2CqYDhU+5QtbWB9UTx nq2ioahzPVyDN57LmqmaFIppfYPuPZQz3APeIcRze5Qd7FnCtu4OhWynBIF+3J8ymqX1RjTxN fgoTN9Q/YbgvYTBFlVib8DB7ZSJkH/8Wnp4bcL0GfereOLuFkqzXWT82pCKgG6/CcRdO6APNO 1R/KMbXovtwtwuvHr9U4HVg4jjG86Lcb6FBhONxvyYH3nQTAtAmE/jpSoA7jNFfK8YsEuW0nC pxpCMS/iGnCkNaQD7uwxPRf5J5lOnpPzeKat0wsEq27rJbwhnDzgfm/3682Pe/1OrPRsXJRvi u56mUm4jdBx9VgD3xlauvcTHaFVap/4K+OFihvebbxT+oiR+OE1wJDINFPhwAuEGg8ap6oAbC jCaKogVszBpVuu1YBoz8dd1YoVOOPWH/CnRzgt3OUUsSGrkRr79o9cQlPp7mgPln6y8mnfYF8 b+9RWX1AYtt9Sf8pPCVs4Mra1Lp4tqVyEqqG8Z/b2bjbCJMtSbruwpExkvVWClZvhfGflRkBm 1+K6IVodoq+l8UNxpIKMA6UXhfjd5PNC75ZD5laQh0aobHF5SdjXMS0HM7XPaJ6BCnEbt8Ycu jfYp1Sj5wc1VD/NZg32B4hlS3/YGSBK3BA+B7p85BiFB7rQwOlGglNi7Wfy7A/KlwQ+6yCj2k seHkoCEKI9cJd11pQj5Z3+MVwEzs7SbugxIKmKM529HEXfKvR6+oqzRRHfnLr2m7a6dnnPDUW fHgmCami6/UnQ5crYy/O8IH2CzMEvWH5aFsZfCtpd9S0idSlkYOMxnkOTZHbG2NVUPOOOomo7 9IzKqpehLW3E009ZA8NoQKXcbIZA23AcI75h7CVRD2RMqjkNCgAUqwB0DINaC3CyrCkyIbqeN 8b7qgM8JDN0TAAGrqtBD+kZOphVKi/KJeT08BpqepDP6olk2r9fcmu/HCQhodinlbp/AoT1ex znrsGHZEmt8fmE3gExnaK0Xp0JVSqUZlQYMKsoOB8lhzR6lo7kVeJ0UnAGZrs35dljK6FJVVj BBjbXARDBPTVPT7acTieD/ZFkAbFNfWWZp1yyqGUjLXPrQqO1sU2WQ0Rw== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The timer module contains multiple timers. In the WPCM450 SoC, each timer runs off a clock can be gated individually. To model this correctly, the timer node in the devicetree needs to take multiple clock inputs. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Rob Herring --- v4: - no changes v3: - Add R-b tag v2: - no changes --- .../devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.35.1 diff --git a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml index 0cbc26a721514..023c999113c38 100644 --- a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml +++ b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml @@ -23,7 +23,13 @@ properties: - description: The timer interrupt of timer 0 clocks: - maxItems: 1 + items: + - description: The reference clock for timer 0 + - description: The reference clock for timer 1 + - description: The reference clock for timer 2 + - description: The reference clock for timer 3 + - description: The reference clock for timer 4 + minItems: 1 required: - compatible From patchwork Fri Jun 10 07:21:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 580878 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73C24CCA47B for ; Fri, 10 Jun 2022 07:22:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346723AbiFJHWr (ORCPT ); Fri, 10 Jun 2022 03:22:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346722AbiFJHWm (ORCPT ); Fri, 10 Jun 2022 03:22:42 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B65CC2252D; Fri, 10 Jun 2022 00:22:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1654845720; bh=j3UY4Dc5ZucxvZOdMQ7G7i2RlA13OGQcUuT05UZhmlk=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=lrCxQu9gPZP3aTtP+UdnRHWcryV1DB5W2tdNllB/hHoADU5AIO68QL4iVdWEPrdkN uhkduHL2Xr+UBH+N56b/a9IAxSGQa9tMpOh+daXNdh9Amk+1OwaRi8REfB/xke2xRB NlcaB0jBp1x1pR/OrJLhBaUFTQNO5sjxuz6XcS20= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.195.3]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MmDEm-1nHOWl3D28-00iBNh; Fri, 10 Jun 2022 09:21:59 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH v4 2/6] watchdog: npcm: Enable clock if provided Date: Fri, 10 Jun 2022 09:21:37 +0200 Message-Id: <20220610072141.347795-3-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220610072141.347795-1-j.neuschaefer@gmx.net> References: <20220610072141.347795-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:2PiAR+PAhe6XaqU2LmLRzu4DoKNpDPyrJc4JH5huBAJPKh+QUNk GEOzDpM+bZrgsa1BmNgoDOQ9r66cVZRKjcB3alQsW8GAJNY5NTAIFTyua7z/2ENIPnoKfBR BQ6JrUUmfgyglEnddnaRGGdiltOocyvmmNIeOACq9Jy9kcSLBtCwaTme7HPgmzagYVKKsg+ mHOzIFNgctCPazzIs/Esw== X-UI-Out-Filterresults: notjunk:1;V03:K0:D9zi4Na8zUY=:55BG0Xozf1f51tRz3AJXiU ZJOA8AbZhrjhSU9ZfCSIhITEd6u7YHNKiXNiuEuKOWWJ9jwkiNNdBibHFNTyYJWmoQQRmjO3a I0PIU6SV/2KbtdDQzO9+ABPcQ70vgZUtAKGQL+DMKrwqNYRzkIlTTqusqbKFEXHcvuO3E9x7l W8j8fAw+ogjXTujng5Unmmecd2yfeniwRt/2lBtrZNPgo0oAziP8O/Cu3n7NsSJhF7EQ8V9wF bqQovlPWTPdroQ+zbmpMMSv0JFpINjk7kNbV7IA1JDrdKFrIGy8QoT67cC6B8sqagok0+Cnwo Yj3GMi1dHWJrtyv8eapck4/pF8iTqA1zY+KKuSv5JLej+o/uOcgG8slLw6VsXdkBlR7CX+uyo a6+1+gn0u2MLcdTpHBdx1xtxE3lEjH6fC8uU0Ji0zKI+9Je+BC95+wf45UpZ/eon9MXJxJVEb uF82Z+fWMVmHZQLDRHhEVYCyA+b/izxpCREc3Zedx76FlPjpH0FCHhZyRPjzfj2dKTWkojcJd fhlndhVuJRdQUm0WIG6A7/XaursXc7hoKJLltyP+1TFPUBbctoGzlyBAHet9JHCETbJfoVAUP Prz8+Tdw2csBL+pwj9oN7xN2YY37b8KIwrfIk33NS+f5kWsSMaQ+sBD5OM6FvRFj0fGuIId00 Y6cJB6PLmBMc5Gjk9n9U7VJH3A+ZwF+q6NVuaZ+iPtHDGiObJJjueDP4LBPNUau0VuuaaAStP xlNahj37Ym13uG5ECZe87uDB0+uqp1NzImp4x1R8BRn/yiopZvA9X1DIftmMxEKPEYXtVsndm 1pdF6m35qjjV17DRN9O4hc+qE+JBTcLPD+/+8iUqt0eF8K9tkHAUMk56FfcKyVf7wODhPOeQ7 T0H54ZAPDlylAxeYTmjnkvJS+yqhxQQm9hIKzXvgcOHzlphzi9hsFwmavftBWUE57AWcOaRLK JheqBkeOer37bDkx94pCawOd8EOiVPKMqCLydSChrvVf5hHt/doNkVDQzpf6ab+ndGihtphix 80ZKWQhJLaRvAlz0Xfc8RicvePFT6R0XKPTcAB9xkrsLOUJ6hC+9mS677sIrwAiTTfYP2dTo0 3Tl3ZvxHzu0Mo1RhTCb5fBTxmHO/7RduiljXXG3hy07PHaj8E88uqhDzA== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On the Nuvoton WPCM450 SoC, with its upcoming clock driver, peripheral clocks are individually gated and ungated. Therefore, the watchdog driver must be able to ungate the watchdog clock. Signed-off-by: Jonathan Neuschäfer --- v4: - Don't disable clock in npcm_wdt_restart function v3: - https://lore.kernel.org/lkml/20220508194333.2170161-4-j.neuschaefer@gmx.net/ - Add enable/disable calls to npcm_wdt_restart handler - Not applied due to the above change: Acked-by: Guenter Roeck v2: - https://lore.kernel.org/lkml/20220429172030.398011-4-j.neuschaefer@gmx.net/ - Add clk_disable_unprepare call, suggested by Guenter Roeck v1: - https://lore.kernel.org/lkml/20220422183012.444674-4-j.neuschaefer@gmx.net/ --- drivers/watchdog/npcm_wdt.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.35.1 diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c index 28a24caa2627c..a5dd1c2301374 100644 --- a/drivers/watchdog/npcm_wdt.c +++ b/drivers/watchdog/npcm_wdt.c @@ -3,6 +3,7 @@ // Copyright (c) 2018 IBM Corp. #include +#include #include #include #include @@ -43,6 +44,7 @@ struct npcm_wdt { struct watchdog_device wdd; void __iomem *reg; + struct clk *clk; }; static inline struct npcm_wdt *to_npcm_wdt(struct watchdog_device *wdd) @@ -66,6 +68,9 @@ static int npcm_wdt_start(struct watchdog_device *wdd) struct npcm_wdt *wdt = to_npcm_wdt(wdd); u32 val; + if (wdt->clk) + clk_prepare_enable(wdt->clk); + if (wdd->timeout < 2) val = 0x800; else if (wdd->timeout < 3) @@ -100,6 +105,9 @@ static int npcm_wdt_stop(struct watchdog_device *wdd) writel(0, wdt->reg); + if (wdt->clk) + clk_disable_unprepare(wdt->clk); + return 0; } @@ -147,6 +155,10 @@ static int npcm_wdt_restart(struct watchdog_device *wdd, { struct npcm_wdt *wdt = to_npcm_wdt(wdd); + /* For reset, we start the WDT clock and leave it running. */ + if (wdt->clk) + clk_prepare_enable(wdt->clk); + writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, wdt->reg); udelay(1000); @@ -191,6 +203,10 @@ static int npcm_wdt_probe(struct platform_device *pdev) if (IS_ERR(wdt->reg)) return PTR_ERR(wdt->reg); + wdt->clk = devm_clk_get_optional(&pdev->dev, NULL); + if (IS_ERR(wdt->clk)) + return PTR_ERR(wdt->clk); + irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; From patchwork Fri Jun 10 07:21:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 580877 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F3DBC43334 for ; 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Fri, 10 Jun 2022 09:22:12 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck , Krzysztof Kozlowski , Krzysztof Kozlowski Subject: [PATCH v4 3/6] dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller Date: Fri, 10 Jun 2022 09:21:38 +0200 Message-Id: <20220610072141.347795-4-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220610072141.347795-1-j.neuschaefer@gmx.net> References: <20220610072141.347795-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:oBCOVoQiYTeIEeH6b1Ro7wMEWAN7NkTLykjMJfZGa+J7xGKQhzZ a6ne3cy/bSOv+OY/6OoQBHJu8Ufm3dUgzf14gUvrBIr7WhO2ToN//NDK6TXvFZxzUykzc8j 82pZHIeow6pL04QMpuARrnu63H1zAR1AOPFhl2y5+CmACK8h010dISuB998jGcRZxf+YroH EpG9ZjdNe/T4gr0EG2nWA== X-UI-Out-Filterresults: notjunk:1;V03:K0:KecseXm5aMc=:e6YrHlomRt8ARNEcnULCkk TcentPRMksSZqXLh7+RMzFwuv/ZpRCrmu2fK8F96k44BA6nmWCfeEn4eMabWZ7/Zax8bai9Kg IbOWuiBiT3rJRuagHnteIe/QFzPUVkrn/GpPHk0VBhoLwR/M0bDJYdbCZyoLeL5bFeXQVTdSP Tl9NvYL0FD7ILYmCMaS2SEnd0Iqp+HUO19Pxs9m0Gcglr35Km65WAGmy01uFsvEK81ryGQWtv i3yAP1Qvk0Q6Xm918V3HsSR6FPvpFS+JbHykS3Kks+yBU5SMwbQniJMPl19NiAY1d9+4zKrZq bIyIIhczlYzzT5rSf7eTXNY8Ew6/jG1TNA5i5l5BKI+j93IQvjtS3rJXKuOyyTU7bPSP4BKpj vu2nEpbxRjOe05fKY3B2SBOWhTt5T97LGyVe3apPFh1V3TFL0l5oAWm1XXOY9AwELJpLzSPHq TX8v2A7ov2ZYQSi7KbhPQhWOMS5tTZ1XTyB11wLZs7cdmhrJIC1k6Bo2u7hl9NRJYQEZzhkBC vXDf0fVk8Z0rCQSbx55ivI0ygP9zIcyiVY+yGyR6ix0IID2pCmxxKHLf+bJAnDr7Xt3cEJlXR 2KR5I02q2PUE/6ZFJBGZc3v8rFDGvXyu3TerRwMCv0mjv7pn4If3wHNsPA4SLKwgErYP9G6BO T5z6iuLPJYLqOB6DlXv/jI38u0TZuOrGCe1WNn5wLdRF2n2bIjB4ZDuxJVLNLgmRr4XAICLjo fXLUADEm9o6OoYfo2/MdsqyoL6t24CC+F8vAYwsiIQH0pdw2JTimg0oOt2XZXsZ8/y/YrqzOa kYEDD3dTgUbE9BxzH3btdY8op/qWZPcBcW+vHN2kBUtDtAmaJB/cN3kkLEkDxVjFNCMiTtyh9 Uv0mbd8hlwlKGIb0ChXTqZh1+EQnkqfVY+N/YBaXGRgTPs+SsfWxn9plU51Bw7grEWWd40sry 9OusBzIb+sEIhniqixK1s2H5cIvFizfevPtAMJPCVZnleprwR5PARHByExsQU7NFyqUXGdoF4 Nra0rWQgXqEFfp3Fy0zK3qkNu+ZVscnFXvIEccl8apVTM5roiUdH1RzRNagi84kqH8V1+KxvO xuRGachzOVfPugocd+yR7OAowWujGqBwuuh1tn4q9nVW7a0AdJXiNBh6Q== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Nuvoton WPCM450 SoC has a combined clock and reset controller. Add a devicetree binding for it, as well as definitions for the bit numbers used by it. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Krzysztof Kozlowski --- v4: - Add R-b tag v3: - Change clock-output-names and clock-names from "refclk" to "ref", suggested by Krzysztof Kozlowski v2: - https://lore.kernel.org/lkml/20220429172030.398011-5-j.neuschaefer@gmx.net/ - Various improvements, suggested by Krzysztof Kozlowski v1: - https://lore.kernel.org/lkml/20220422183012.444674-5-j.neuschaefer@gmx.net/ --- .../bindings/clock/nuvoton,wpcm450-clk.yaml | 66 ++++++++++++++++++ .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h -- 2.35.1 diff --git a/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml new file mode 100644 index 0000000000000..525024a58df4c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,wpcm450-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 clock controller + +maintainers: + - Jonathan Neuschäfer + +description: + The clock controller of the Nuvoton WPCM450 SoC supplies clocks and resets to + the rest of the chip. + +properties: + compatible: + const: nuvoton,wpcm450-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock oscillator (should be 48 MHz) + + clock-names: + items: + - const: ref + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + - | + #include + #include + + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "ref"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk: clock-controller@b0000200 { + reg = <0xb0000200 0x100>; + compatible = "nuvoton,wpcm450-clk"; + clocks = <&refclk>; + clock-names = "ref"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/nuvoton,wpcm450-clk.h b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h new file mode 100644 index 0000000000000..86e1c895921b7 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H +#define _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H + +/* Clocks based on CLKEN bits */ +#define WPCM450_CLK_FIU 0 +#define WPCM450_CLK_XBUS 1 +#define WPCM450_CLK_KCS 2 +#define WPCM450_CLK_SHM 4 +#define WPCM450_CLK_USB1 5 +#define WPCM450_CLK_EMC0 6 +#define WPCM450_CLK_EMC1 7 +#define WPCM450_CLK_USB0 8 +#define WPCM450_CLK_PECI 9 +#define WPCM450_CLK_AES 10 +#define WPCM450_CLK_UART0 11 +#define WPCM450_CLK_UART1 12 +#define WPCM450_CLK_SMB2 13 +#define WPCM450_CLK_SMB3 14 +#define WPCM450_CLK_SMB4 15 +#define WPCM450_CLK_SMB5 16 +#define WPCM450_CLK_HUART 17 +#define WPCM450_CLK_PWM 18 +#define WPCM450_CLK_TIMER0 19 +#define WPCM450_CLK_TIMER1 20 +#define WPCM450_CLK_TIMER2 21 +#define WPCM450_CLK_TIMER3 22 +#define WPCM450_CLK_TIMER4 23 +#define WPCM450_CLK_MFT0 24 +#define WPCM450_CLK_MFT1 25 +#define WPCM450_CLK_WDT 26 +#define WPCM450_CLK_ADC 27 +#define WPCM450_CLK_SDIO 28 +#define WPCM450_CLK_SSPI 29 +#define WPCM450_CLK_SMB0 30 +#define WPCM450_CLK_SMB1 31 + +/* Other clocks */ +#define WPCM450_CLK_USBPHY 32 + +#define WPCM450_NUM_CLKS 33 + +/* Resets based on IPSRST bits */ +#define WPCM450_RESET_FIU 0 +#define WPCM450_RESET_EMC0 6 +#define WPCM450_RESET_EMC1 7 +#define WPCM450_RESET_USB0 8 +#define WPCM450_RESET_USB1 9 +#define WPCM450_RESET_AES_PECI 10 +#define WPCM450_RESET_UART 11 +#define WPCM450_RESET_MC 12 +#define WPCM450_RESET_SMB2 13 +#define WPCM450_RESET_SMB3 14 +#define WPCM450_RESET_SMB4 15 +#define WPCM450_RESET_SMB5 16 +#define WPCM450_RESET_PWM 18 +#define WPCM450_RESET_TIMER 19 +#define WPCM450_RESET_ADC 27 +#define WPCM450_RESET_SDIO 28 +#define WPCM450_RESET_SSPI 29 +#define WPCM450_RESET_SMB0 30 +#define WPCM450_RESET_SMB1 31 + +#define WPCM450_NUM_RESETS 32 + +#endif /* _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H */