From patchwork Thu Jun 9 11:27:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 580536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 295DFCCA47B for ; Thu, 9 Jun 2022 11:27:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243752AbiFIL1t (ORCPT ); Thu, 9 Jun 2022 07:27:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243682AbiFIL1r (ORCPT ); Thu, 9 Jun 2022 07:27:47 -0400 Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B80616A520; Thu, 9 Jun 2022 04:27:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1654774066; x=1686310066; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LmOhtt+sTSzENhRVy269JX54eQelMXkrz6ZoDjQkje8=; b=DNfaqDHh+SjfmXNCXYlH9lmp7oKyjOizcJ+GX2O8Z9EsMOMqo62TQpXe lHz9EHlYHlVzKYk7alyLdQThEQ52gn0/k9dndOPJ5VsJ4ZvNOrXWtHC0v myoL9gH0TVf4eUC6XNi59dh5MLpceh42pnFJW5hH8TG59Fi+KpwhBZbtw usoyHs9bJz1eb5FMXMtu8Uif3pFkt28N2iJfKbMR4AJ/9P6ciqKV1q1+Q Um5XqXXFlqUEQcBiOEPQ7rlVislobos9IcJfZxLL+98OITyEM/9VmKRAG F8VeRBdD4u2hlKy37wMbQ/NKf1uZd2YcAn0tw1a+Vs4gc1FvJBXe7XGcu w==; From: Vincent Whitchurch To: , , CC: , Vincent Whitchurch , , , , , , Subject: [PATCH v4 1/4] dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support Date: Thu, 9 Jun 2022 13:27:35 +0200 Message-ID: <20220609112738.359385-2-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609112738.359385-1-vincent.whitchurch@axis.com> References: <20220609112738.359385-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The ARTPEC-8 has an MCT with 4 global and 8 local timer interrupts. The SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which share one MCT with one global and eight local timers. The Cortex-A53 and Cortex-A5 do not have cache-coherency between them, and therefore run two separate kernels. The Cortex-A53 boots first and starts the global free-running counter and also registers a clock events device using the global timer. (This global timer clock events is usually replaced by arch timer clock events for each of the cores.) When the A5 boots (via the A53), it should not use the global timer interrupts or write to the global timer registers. This is because even if there are four global comparators, the control bits for all four are in the same registers, and we would need to synchronize between the cpus. Instead, the global timer FRC (already started by the A53) should be used as the clock source, and one of the local timers which are not used by the A53 can be used for clock events on the A5. To support this hardware, add a compatible for the MCT as well as two new properties to describe the hardware-mandated sharing of the FRC and dedicating local timers to specific processors. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vincent Whitchurch --- Notes: v4: - Add Krzysztof's Reviewed-by. v3: - Add all required bindings for ARTPEC-8 in one patch - Rename and split local-timer-only to samsung,local-timers and samsung,frc-shared - Restrict above properties to the ARTPEC-8 compatible. - Rewrite descriptions of properties to hopefully describe hardware. v2: - Use devicetree property instead of module parameter. .../timer/samsung,exynos4210-mct.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index 9c81d00b12e0..829bd2227f7c 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -25,6 +25,7 @@ properties: - samsung,exynos4412-mct - items: - enum: + - axis,artpec8-mct - samsung,exynos3250-mct - samsung,exynos5250-mct - samsung,exynos5260-mct @@ -45,6 +46,19 @@ properties: reg: maxItems: 1 + samsung,frc-shared: + type: boolean + description: | + Indicates that the hardware requires that this processor share the + free-running counter with a different (main) processor. + + samsung,local-timers: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 16 + description: | + List of indices of local timers usable from this processor. + interrupts: description: | Interrupts should be put in specific order. This is, the local timer @@ -74,6 +88,17 @@ required: - reg allOf: + - if: + not: + properties: + compatible: + contains: + enum: + - axis,artpec8-mct + then: + properties: + samsung,local-timers: false + samsung,frc-shared: false - if: properties: compatible: @@ -101,6 +126,7 @@ allOf: compatible: contains: enum: + - axis,artpec8-mct - samsung,exynos5260-mct - samsung,exynos5420-mct - samsung,exynos5433-mct From patchwork Thu Jun 9 11:27:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 581589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DD07C433EF for ; Thu, 9 Jun 2022 11:27:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243716AbiFIL1s (ORCPT ); Thu, 9 Jun 2022 07:27:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243694AbiFIL1r (ORCPT ); Thu, 9 Jun 2022 07:27:47 -0400 Received: from smtp2.axis.com (smtp2.axis.com [195.60.68.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B98016A53E; Thu, 9 Jun 2022 04:27:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1654774066; x=1686310066; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=H+8MIR1OuQsaVNfsbihNB9tS+9/wynO4WohspQZNd1M=; b=TQv2zrl7+pSMh/Rq0arQ6pQbgTCWIgYIXG/RO8NVuPCq9WuCIIXYEuns sv9275G2um0dMO4febVH3LBbgF8RF04sZofN2dgWdfUi0uFAopgVm7MJC sLxLHEUYy7oU8FELxnFdO0lrd4oxQKk05vSGh8AFrtYeMYwN1lAKBKtpR HyaSERHvGBtQwyajTfKhD0GSJnIobOzPeZhywa3atfRrIVSa+eLfyxKnd 9zar1OKhHjiKiKW4UDCa2cNOYQFKK5nXMxF8tQFXM26YWd2uXmnnoafXY Pk+hB82hLiGQ3evmRKDhxJXeksx9bDyZlC2wcy/mGkRVuz4cDPlHv2AO/ Q==; From: Vincent Whitchurch To: , , CC: , Vincent Whitchurch , , , , , , Subject: [PATCH v4 2/4] clocksource/drivers/exynos_mct: Support frc-shared property Date: Thu, 9 Jun 2022 13:27:36 +0200 Message-ID: <20220609112738.359385-3-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609112738.359385-1-vincent.whitchurch@axis.com> References: <20220609112738.359385-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org When the FRC is shared with another main processor, the other processor is assumed to have started it and this processor should not write to the global registers. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vincent Whitchurch --- Notes: v4: - Add Krzysztof's Reviewed-by. v3: - Split FRC sharing handling from local timer indices handling - Remove addition of global variable. drivers/clocksource/exynos_mct.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index f29c812b70c9..12023831dedf 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -233,9 +233,16 @@ static cycles_t exynos4_read_current_timer(void) } #endif -static int __init exynos4_clocksource_init(void) +static int __init exynos4_clocksource_init(bool frc_shared) { - exynos4_mct_frc_start(); + /* + * When the frc is shared, the main processer should have already + * turned it on and we shouldn't be writing to TCON. + */ + if (frc_shared) + mct_frc.resume = NULL; + else + exynos4_mct_frc_start(); #if defined(CONFIG_ARM) exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; @@ -605,6 +612,7 @@ static int __init exynos4_timer_interrupts(struct device_node *np, static int __init mct_init_dt(struct device_node *np, unsigned int int_type) { + bool frc_shared = of_property_read_bool(np, "samsung,frc-shared"); int ret; ret = exynos4_timer_resources(np); @@ -615,10 +623,17 @@ static int __init mct_init_dt(struct device_node *np, unsigned int int_type) if (ret) return ret; - ret = exynos4_clocksource_init(); + ret = exynos4_clocksource_init(frc_shared); if (ret) return ret; + /* + * When the FRC is shared with a main processor, this secondary + * processor cannot use the global comparator. + */ + if (frc_shared) + return ret; + return exynos4_clockevent_init(); } From patchwork Thu Jun 9 11:27:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 581588 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8598EC43334 for ; Thu, 9 Jun 2022 11:27:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243775AbiFIL1v (ORCPT ); Thu, 9 Jun 2022 07:27:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243742AbiFIL1t (ORCPT ); Thu, 9 Jun 2022 07:27:49 -0400 Received: from smtp2.axis.com (smtp2.axis.com [195.60.68.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E366F16F91A; Thu, 9 Jun 2022 04:27:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1654774067; x=1686310067; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aM/0l4yjaBfnHy1XwDJmSDA6T8THC1eF8t5yyafz8mI=; b=HDpLTUmlD9btr45sL/u8o5ASkTWz17asLQSrKjgILmYKwpa5iVmKt5IZ xEPvfeGbDXStoxHV5YbInBldYmawKy1Ke2N7yccauGH8Eg9oG+LDHWn44 zA2tFWY25ab5QmB9NG/aLpxnFgevyA5hZX0PT68/umQfpE2K26Nj5VqJp eAzxSCiRy+PSZ5pOcuPSCY2MXwP6VxNobCVUyeHkOEhPvBCawD/rG63KO Nwr5gvZyEQy/crmZunGrDreCmacR64gvLxG5o0TgmTptTB62oLUnnG7b9 7MoKt908/0Gp7dbDP0/ET644C0h8YPYti/MCnyXjK8ihqAV8/jVbhTSHG w==; From: Vincent Whitchurch To: , , CC: , Vincent Whitchurch , , , , , , Subject: [PATCH v4 3/4] clocksource/drivers/exynos_mct: Support local-timers property Date: Thu, 9 Jun 2022 13:27:37 +0200 Message-ID: <20220609112738.359385-4-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609112738.359385-1-vincent.whitchurch@axis.com> References: <20220609112738.359385-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org If the device tree indicates that the hardware requires that the processor only use certain local timers, respect that. Signed-off-by: Vincent Whitchurch Reviewed-by: Krzysztof Kozlowski --- Notes: v4: - Add function documentation - Add const for local_idx - Rename irqidx -> irq_idx - Error out on invalid number of CPUs v3: - Use array in devicetree - Remove addition of global variable - Split out FRC sharing changes drivers/clocksource/exynos_mct.c | 62 ++++++++++++++++++++++++++++---- 1 file changed, 56 insertions(+), 6 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 12023831dedf..bfd60093ee1c 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -33,7 +33,7 @@ #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) -#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) +#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * (x))) #define EXYNOS4_MCT_L_MASK (0xffffff00) #define MCT_L_TCNTB_OFFSET (0x00) @@ -66,6 +66,8 @@ #define MCT_L0_IRQ 4 /* Max number of IRQ as per DT binding document */ #define MCT_NR_IRQS 20 +/* Max number of local timers */ +#define MCT_NR_LOCAL (MCT_NR_IRQS - MCT_L0_IRQ) enum { MCT_INT_SPI, @@ -456,7 +458,6 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) per_cpu_ptr(&percpu_mct_tick, cpu); struct clock_event_device *evt = &mevt->evt; - mevt->base = EXYNOS4_MCT_L_BASE(cpu); snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu); evt->name = mevt->name; @@ -527,8 +528,17 @@ static int __init exynos4_timer_resources(struct device_node *np) return 0; } +/** + * exynos4_timer_interrupts - initialize MCT interrupts + * @np: device node for MCT + * @int_type: interrupt type, MCT_INT_PPI or MCT_INT_SPI + * @local_idx: array mapping CPU numbers to local timer indices + * @nr_local: size of @local_idx array + */ static int __init exynos4_timer_interrupts(struct device_node *np, - unsigned int int_type) + unsigned int int_type, + const u32 *local_idx, + size_t nr_local) { int nr_irqs, i, err, cpu; @@ -561,13 +571,21 @@ static int __init exynos4_timer_interrupts(struct device_node *np, } else { for_each_possible_cpu(cpu) { int mct_irq; + unsigned int irq_idx; struct mct_clock_event_device *pcpu_mevt = per_cpu_ptr(&percpu_mct_tick, cpu); + if (cpu >= nr_local) { + err = -EINVAL; + goto out_irq; + } + + irq_idx = MCT_L0_IRQ + local_idx[cpu]; + pcpu_mevt->evt.irq = -1; - if (MCT_L0_IRQ + cpu >= ARRAY_SIZE(mct_irqs)) + if (irq_idx >= ARRAY_SIZE(mct_irqs)) break; - mct_irq = mct_irqs[MCT_L0_IRQ + cpu]; + mct_irq = mct_irqs[irq_idx]; irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); if (request_irq(mct_irq, @@ -583,6 +601,17 @@ static int __init exynos4_timer_interrupts(struct device_node *np, } } + for_each_possible_cpu(cpu) { + struct mct_clock_event_device *mevt = per_cpu_ptr(&percpu_mct_tick, cpu); + + if (cpu >= nr_local) { + err = -EINVAL; + goto out_irq; + } + + mevt->base = EXYNOS4_MCT_L_BASE(local_idx[cpu]); + } + /* Install hotplug callbacks which configure the timer on this CPU */ err = cpuhp_setup_state(CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, "clockevents/exynos4/mct_timer:starting", @@ -613,13 +642,34 @@ static int __init exynos4_timer_interrupts(struct device_node *np, static int __init mct_init_dt(struct device_node *np, unsigned int int_type) { bool frc_shared = of_property_read_bool(np, "samsung,frc-shared"); + u32 local_idx[MCT_NR_LOCAL] = {0}; + int nr_local; int ret; + nr_local = of_property_count_u32_elems(np, "samsung,local-timers"); + if (nr_local == 0) + return -EINVAL; + if (nr_local > 0) { + if (nr_local > ARRAY_SIZE(local_idx)) + return -EINVAL; + + ret = of_property_read_u32_array(np, "samsung,local-timers", + local_idx, nr_local); + if (ret) + return ret; + } else { + int i; + + nr_local = ARRAY_SIZE(local_idx); + for (i = 0; i < nr_local; i++) + local_idx[i] = i; + } + ret = exynos4_timer_resources(np); if (ret) return ret; - ret = exynos4_timer_interrupts(np, int_type); + ret = exynos4_timer_interrupts(np, int_type, local_idx, nr_local); if (ret) return ret; From patchwork Thu Jun 9 11:27:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 580537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4918CCA47B for ; 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From: Vincent Whitchurch To: , , CC: , Vincent Whitchurch , , , , , , Subject: [PATCH v4 4/4] clocksource/drivers/exynos_mct: Enable building on ARTPEC Date: Thu, 9 Jun 2022 13:27:38 +0200 Message-ID: <20220609112738.359385-5-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609112738.359385-1-vincent.whitchurch@axis.com> References: <20220609112738.359385-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This timer block is used on ARTPEC-8. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vincent Whitchurch --- Notes: v3: - Add Krzysztof's Reviewed-by. drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 3c0ee102fe73..b275583f946c 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -419,7 +419,7 @@ config ATMEL_TCB_CLKSRC config CLKSRC_EXYNOS_MCT bool "Exynos multi core timer driver" if COMPILE_TEST depends on ARM || ARM64 - depends on ARCH_EXYNOS || COMPILE_TEST + depends on ARCH_ARTPEC || ARCH_EXYNOS || COMPILE_TEST help Support for Multi Core Timer controller on Exynos SoCs.