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[209.51.188.17]) by mx.google.com with ESMTPS id w10-20020ac87e8a000000b00304f6971ca7si5656696qtj.192.2022.06.09.13.31.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 13:31:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l1YhcKHC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34778 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzOo4-0004Nt-CE for patch@linaro.org; Thu, 09 Jun 2022 16:31:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42912) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzOmB-0003P5-AW for qemu-devel@nongnu.org; Thu, 09 Jun 2022 16:29:07 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:41791) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzOm8-0008QK-V3 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 16:29:06 -0400 Received: by mail-pl1-x634.google.com with SMTP id s14so21129058plk.8 for ; Thu, 09 Jun 2022 13:29:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w/iHX6ANtN/zAKSj1imBD0tjZXjeiBLskpYlkOhgS0I=; b=l1YhcKHCsUdN75BWIz2PutUjbFgF20zXfGtsSwDGjhgVc3gHSEnd3DZUs4g0+joSvD +QwBlfNdXvcNV2ve38F4HPA6RXHap4DBW+TLV43gER1gM9fTMnOADik/sRP9yjcexvmf lghnzSZrdTgjXc/JR+DF4DKSNEAXHevtq6DN/BncymEVO6Yeko/GtqE7T+LU8hjKI6GC /fD1v2soX8uI5XSI1/5coEKM4GIzE7NQaKY+xwOmGFQl0NOpX9tWS4LDhDP1AtvfyNZk rrJvaqZpIN1U60R9OFCa8i2ivCOUyjULMpQBE8z9Q/atvL6r7cSoZSqxm1aRQuKCuV5N 6WTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w/iHX6ANtN/zAKSj1imBD0tjZXjeiBLskpYlkOhgS0I=; b=eIdsBp7o9VGqLIsG/F1MFFVEDUk0Yjyv4uNxMByHVeTCHytLi3qS1tG5FN5Gj+6syB 1Oj7PwpRbxUPNHKBTmG8utzWFYQGYYBoUT6Dl5oiO0u66jJmlyt251YJ+jPUgXiu58eb aV6nZ1Gs4TfIWnC3wbos6858zdz7bA+eBcFr44Z+O2Hv9JqvBdNchJrCdmI1+BtATH0R nBXCBqr88jXG25SOgCU6+ForwX9qfuyBJbcuIQmCDvJqhykuCOIMTX4Mv7dWeW6ve8HJ /oIG1rqMN4mUOWnaG2c3mVCqE3wS2rJbbgsT3Uh3o3ogpF5OOkYz+TxbqNerceFCGhBW t5mA== X-Gm-Message-State: AOAM533VEfjOMoMrZ4yNg7kE8H6JtybIhDHh8fuE9ilpP5u04sjmt8aq wQNMGHyod4rqCXLKvnpORliNIoNcwZ0Kjw== X-Received: by 2002:a17:90b:350b:b0:1e8:5177:fe7d with SMTP id ls11-20020a17090b350b00b001e85177fe7dmr5205317pjb.142.1654806543691; Thu, 09 Jun 2022 13:29:03 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 01/23] target/arm: Mark exception helpers as noreturn Date: Thu, 9 Jun 2022 13:28:39 -0700 Message-Id: <20220609202901.1177572-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index b1334e0c42..5161cdf73d 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -44,9 +44,9 @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) -DEF_HELPER_2(exception_internal, void, env, i32) -DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) -DEF_HELPER_2(exception_bkpt_insn, void, env, i32) +DEF_HELPER_2(exception_internal, noreturn, env, i32) +DEF_HELPER_4(exception_with_syndrome, noreturn, env, i32, i32, i32) +DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) From patchwork Thu Jun 9 20:28:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580317 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1124270max; Thu, 9 Jun 2022 13:30:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwgsVlUPCwpeMr0sZRBmMRwDKDdb8SPLu2Y9wmFTrFPFsrc4MAz1rEBPuJEqJlQmRfpA1S4 X-Received: by 2002:ac8:5890:0:b0:305:11be:b84c with SMTP id t16-20020ac85890000000b0030511beb84cmr3275525qta.610.1654806649188; Thu, 09 Jun 2022 13:30:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654806649; cv=none; d=google.com; s=arc-20160816; b=PQWcrZNQ+5hEx2jadjnHcsnMKNmiOffGKHiL0/x+Sgs6d0G3OZraku4U0na3AhROnq M9T5Ef30GLBt+RRMZkg7ZicNiFY+AdzuFB9KWGxXdVqVexZ2ncgWSkK1OQQndbO0idva 0XYgT6QiyhEhnW2PfDVcTW7Bn0MCgK08NrIPZ4w/uCwXdeOBum/LLlwVqyf1h3Ma9s7U vQyjQQhLxLcTqI1EVdKtvBfPbzSgghwrnQ3pTscSJcXEuQtqaU/gHJinYhan93qco8Jl UNyjafw0rIOksldaOOAEs/vYs80qdJ0sHHCKpJxkDrau2zvGGjONzDS/LpIA4TApaBRg qbFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=45/1OP9sKZiLrriwOZd01nWrvZCCplxvhdpmrJtm+Zo=; b=zVR6yRvPpdUiHUsI+GLjLxcssV7zv50s4/FdK7rALsWe5IK9simRd3OlJNMeX0BIuu 0b9GsZXoXsi6aup2Ocd2wS9IibPQkesHNB5uORKMhXtE/Psh4g6En9ZV58xh8HfxhCgJ tvkFEeuBIqD662o+LjuityqBGI4EwdwoqodR88czrPG4Gjcoq1MB5bt5rxl7rScpNqv9 x6+zdKHmIsIzeOC3gFhg9wWB+ZID6Masu7uOMv1ce3nmAM27E+6S9GipLdmsf7pOnQqn ntQKzEqjAyYplTwMMIvKC57siPRFlubB+yMeNQtpr6Zn/io9hO0NHTtHXVt+d/a5/kZo eT1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YDnrQ2v6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 02/23] target/arm: Add coproc parameter to syn_fp_access_trap Date: Thu, 9 Jun 2022 13:28:40 -0700 Message-Id: <20220609202901.1177572-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With ARMv8, this field is always RES0. With ARMv7, targeting EL2 and TA=0, it is always 0xA. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/syndrome.h | 7 ++++--- target/arm/translate-a64.c | 3 ++- target/arm/translate-vfp.c | 14 ++++++++++++-- 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 0cb26dde7d..c105f9e6ba 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -185,12 +185,13 @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; } -static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) +static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit, + int coproc) { - /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */ + /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */ return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | 0xa; + | (cv << 24) | (cond << 20) | coproc; } static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d438fb89e7..e752589090 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1162,7 +1162,8 @@ static bool fp_access_check(DisasContext *s) s->fp_access_checked = true; gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + syn_fp_access_trap(1, 0xe, false, 0), + s->fp_excp_el); return false; } s->fp_access_checked = true; diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 40a513b822..0f797c56fd 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -219,8 +219,18 @@ static void gen_update_fp_context(DisasContext *s) static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) { if (s->fp_excp_el) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); + /* + * The full syndrome is only used for HSR when HCPTR traps: + * For v8, when TA==0, coproc is RES0. + * For v7, any use of a Floating-point instruction or access + * to a Floating-point Extension register that is trapped to + * Hyp mode because of a trap configured in the HCPTR sets + * this field to 0xA. + */ + int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa; + uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc); + + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el); return false; } From patchwork Thu Jun 9 20:28:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580326 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1138026max; Thu, 9 Jun 2022 13:52:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyyIRAoMwyQ3JbMmO7mGNRhQOFDu/XhHe6KcWZ5wK38CJ7Q7jq6Em8J2tbp/HAZrgbFz00b X-Received: by 2002:a05:620a:4312:b0:6a6:5b66:5b9b with SMTP id u18-20020a05620a431200b006a65b665b9bmr29080639qko.224.1654807959401; Thu, 09 Jun 2022 13:52:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654807959; cv=none; d=google.com; s=arc-20160816; b=OhW5SYacSRSe62yov15jRmxm7MeDkxqipuNLNNqNTQPJMOI1ZkIh8yGJhMsQ3gqzV5 +4Q3y7dQKjDWuqhI7zZbUVoLsNpy0wxK40kWNwcyr8ADfwhAJGlF5xK2bjF36Sq5W/En 7EwLJNO8Ylo1rDlcp32uk0NLbKd/MEDqgJX6tb6GedHIXqgF2Ppeds4OIOveDuFfs3z3 /Gj9ZEuPfLFu/nDOFOXWH9T0vApwNgl7q1i/DsZZUADiH5Dp32lkYaP78pM89lHaaZEq PQPRetGVL6hbbZAt5lv4I6haoCBwrFS/Dd5246xStx9dF/qRL/7xV604vH4Xa30VpA9w tPdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=or4hVFMgSgQ4bkROq2u2MyvWBg+YN6u3/ulE0jHiq7E=; b=jobAg4jR3SZfRRco2X0YfxdKIUFqhphCrsDboOwum0T5s9BIaKbCTMTwLo49g7cnXl VPOg4KeOC6SIbW4pBMgSAVix/f7qFySMVLDEtQqc2B7hONx0WVg3uwpYFdfd0BB0VXpq f22Ppyr3m7V0HgH4RXc0vMFAc0gvYsoqRgm+PBLVylawJfaet0aGsN0p9aGZgF30PZ+E 33hNYlpuI4kQOf3hf3l8cTSGZYRb8N7kzV8+gnnvFUI7Z8xMKeAAY8elxU2EQl+ydYKz +d0zpFB9EVAhIF4kh+wEvo67x/MLx3FfsA4oNm72OdEbaHRdh3YQHMRSdHWrF/S8mL6B sVdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d7qOLqSz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 03/23] target/arm: Move exception_target_el out of line Date: Thu, 9 Jun 2022 13:28:41 -0700 Message-Id: <20220609202901.1177572-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the function to op_helper.c, near raise_exception. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 16 +--------------- target/arm/op_helper.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a1bae4588a..af9de2dbe5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1098,21 +1098,6 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx); -static inline int exception_target_el(CPUARMState *env) -{ - int target_el = MAX(1, arm_current_el(env)); - - /* - * No such thing as secure EL1 if EL3 is aarch32, - * so update the target EL to EL3 in this case. - */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { - target_el = 3; - } - - return target_el; -} - /* Determine if allocation tags are available. */ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, uint64_t sctlr) @@ -1339,6 +1324,7 @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); bool el_is_in_host(CPUARMState *env, int el); void aa32_max_features(ARMCPU *cpu); +int exception_target_el(CPUARMState *env); /* Powers of 2 for sve_vq_map et al. */ #define SVE_VQ_POW2_MAP \ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c4bd668870..97c8c9ec77 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -28,6 +28,21 @@ #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) +int exception_target_el(CPUARMState *env) +{ + int target_el = MAX(1, arm_current_el(env)); + + /* + * No such thing as secure EL1 if EL3 is aarch32, + * so update the target EL to EL3 in this case. + */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { + target_el = 3; + } + + return target_el; +} + void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t target_el) { From patchwork Thu Jun 9 20:28:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580319 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1128255max; Thu, 9 Jun 2022 13:36:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwZ0h1NgU534acwMhB1cSS1UdNlY1aEd33BBUx8UsIuRVuxcHUCRMOpsZ2ttDV88xyD9q05 X-Received: by 2002:a37:ef12:0:b0:6a6:b664:330d with SMTP id j18-20020a37ef12000000b006a6b664330dmr16608178qkk.152.1654806989270; Thu, 09 Jun 2022 13:36:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654806989; cv=none; d=google.com; s=arc-20160816; b=GV/3kwPfI0AALewb0oVEPCW3jTwIh2bZXvPqhROuUV5IGirzJhQGUoD7XRK66X4/PB zbru+lU1BRsTwqQdhv6nfJ1ss70kdR3cjumeCg2ua47m8IwwO/MI8HPYbZ4Ir45pGhZ5 jBuoRTbcHRuIufLPbPuemywdj5K4PEO1F3ZkdwxEgbECLbCWUOsVYWnliVrxUzRz895J bBFtmzqngQEI1gqTQBqreYLFEDT5naP3hCSoipKggisel1VOQKjkDxnLEfPnoQdmRBV2 5lGdT5W50r9/pdqN+pO3ETOkdp034OXijsDVoMkAGWgyUf1r+RPRqji129UN5DsG4/0l ZNiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MrEhOa+yMtE+t8fOZfBlrA2frjHLPNVyhuaexNOThYc=; b=XjmbjVsF5830fBt4AvzwRp3a1AkJqlBQIhXt52hbRJK5xnHjtDBn1BrL2XS2jwXWvn ZZVWlKbFbNvzsAy2bLgO7nk+fesiVxLH+1xg16yHIypQFTcJs8F6hlTyw4fzwYIZ9zcG g8YGK88x1mwoizNeQdrkGAh+FmWZkcSMawWCT5x70wvsSg9Pw7pjZVhai5J1L3OIRkZk L5khe7TXwCKph91J9zjsvshU/6mmRa3tDtl/Bi3QDvaM6I4K78KsOKnUCSqvu0F6Xykk l4HPmNA3kO83jTN/fBJ0fLQYt0N6WEucZk19mZqpdeAcIQppVPHLRP6mDplwU13pJb8Y L6wA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZV22uVUU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 04/23] target/arm: Move arm_singlestep_active out of line Date: Thu, 9 Jun 2022 13:28:42 -0700 Message-Id: <20220609202901.1177572-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the function to debug_helper.c, and the declaration to internals.h. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ---------- target/arm/internals.h | 1 + target/arm/debug_helper.c | 12 ++++++++++++ 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 78dbcb5592..bb1dc3289a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3106,16 +3106,6 @@ static inline bool arm_generate_debug_exceptions(CPUARMState *env) } } -/* Is single-stepping active? (Note that the "is EL_D AArch64?" check - * implicitly means this always returns false in pre-v8 CPUs.) - */ -static inline bool arm_singlestep_active(CPUARMState *env) -{ - return extract32(env->cp15.mdscr_el1, 0, 1) - && arm_el_is_aa64(env, arm_debug_target_el(env)) - && arm_generate_debug_exceptions(env); -} - static inline bool arm_sctlr_b(CPUARMState *env) { return diff --git a/target/arm/internals.h b/target/arm/internals.h index af9de2dbe5..64e2c1dfad 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1325,6 +1325,7 @@ bool el_is_in_host(CPUARMState *env, int el); void aa32_max_features(ARMCPU *cpu); int exception_target_el(CPUARMState *env); +bool arm_singlestep_active(CPUARMState *env); /* Powers of 2 for sve_vq_map et al. */ #define SVE_VQ_POW2_MAP \ diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 46893697cc..1abf41c5f8 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -11,6 +11,18 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" + +/* + * Is single-stepping active? (Note that the "is EL_D AArch64?" check + * implicitly means this always returns false in pre-v8 CPUs.) + */ +bool arm_singlestep_active(CPUARMState *env) +{ + return extract32(env->cp15.mdscr_el1, 0, 1) + && arm_el_is_aa64(env, arm_debug_target_el(env)) + && arm_generate_debug_exceptions(env); +} + /* Return true if the linked breakpoint entry lbn passes its checks */ static bool linked_bp_matches(ARMCPU *cpu, int lbn) { From patchwork Thu Jun 9 20:28:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580320 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1128817max; Thu, 9 Jun 2022 13:37:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzhMlK3kTMiZJO7z5Jgs4wI5LqSclbwEbUF/rMHX3H9mS0dkt56mnriR9aNtKKUm+RqxD/U X-Received: by 2002:ac8:5bcb:0:b0:304:ff2f:459f with SMTP id b11-20020ac85bcb000000b00304ff2f459fmr10572165qtb.545.1654807058473; Thu, 09 Jun 2022 13:37:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654807058; cv=none; d=google.com; s=arc-20160816; b=qbTZ/j/u8MLjT1lu/evIv6wk3nxzAweJaV5xPWiuQoxbxO0thCnuOhHBu6H6aZPjgO BWD3I0w5TTKfjIMvfR/1CfdMi2xXQK6BhCsjbvec1i/ptP2UMNW6Bjt7ms52eaqz0Ajn wwSzGXLtlOxNDGbe8iDZ/VcmvGxmw2ovoOtOOt39Dp8ti3EaCP/ATXmuFg3fVkWb48HE fVa8I+QAP+EKY1/Ck2QeyovbRT9sXKd4hNdcktjabtd7Wy0rpSwBU+pWFbiALi6ZQEDW VrD+AD1ocIieoPYdn4EfGYwud7/8PeYEqeikKExyEWpxptb54eTQvcxVwzC1HewnUVQl cCCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DvjfME7+Ka5kNm2PWO6mtYjQ90LhCIioEZBbUU3Qie4=; b=0k/Wt0u03mKYMxA4idgFU4I2G2k2ERRaFt2AIKQRplnNgk1DzXigiNmpGb/sFR0dMK uuhz1GwxhPseqalOAAJjhR4ddNyaZfcRE+mluTWiXIaHNPGaYPxJoqXVB3Y6ueRRn3Xq /YsdHCQzx0uRJDwQhxzGTexLGC29vpmcg19tkvejOxhhsZdEHivtUSQD/vW2D+dEJWsA wzAkWL9zxKoZnFp9zjspeKKvrdt4giqpqhy+KrUFdaPY8plbKi+FjC1Gy5dQ++Pkpc8r hc9fWBwFYtB0KFTxkDsu68lgTWGEvcm1Ue4LCOImXFc5KzNnh3CJ2PbzMFPAw3ELZ9Q1 2tPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HRyPnQsw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 05/23] target/arm: Move arm_generate_debug_exceptions out of line Date: Thu, 9 Jun 2022 13:28:43 -0700 Message-Id: <20220609202901.1177572-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move arm_generate_debug_exceptions and its two subroutines, {aa32,aa64}_generate_debug_exceptions into debug_helper.c, and the one interface declaration to internals.h. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 91 ------------------------------------- target/arm/internals.h | 1 + target/arm/debug_helper.c | 94 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+), 91 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bb1dc3289a..50b5a9c9fd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3015,97 +3015,6 @@ static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; } -/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ -static inline bool aa64_generate_debug_exceptions(CPUARMState *env) -{ - int cur_el = arm_current_el(env); - int debug_el; - - if (cur_el == 3) { - return false; - } - - /* MDCR_EL3.SDD disables debug events from Secure state */ - if (arm_is_secure_below_el3(env) - && extract32(env->cp15.mdcr_el3, 16, 1)) { - return false; - } - - /* - * Same EL to same EL debug exceptions need MDSCR_KDE enabled - * while not masking the (D)ebug bit in DAIF. - */ - debug_el = arm_debug_target_el(env); - - if (cur_el == debug_el) { - return extract32(env->cp15.mdscr_el1, 13, 1) - && !(env->daif & PSTATE_D); - } - - /* Otherwise the debug target needs to be a higher EL */ - return debug_el > cur_el; -} - -static inline bool aa32_generate_debug_exceptions(CPUARMState *env) -{ - int el = arm_current_el(env); - - if (el == 0 && arm_el_is_aa64(env, 1)) { - return aa64_generate_debug_exceptions(env); - } - - if (arm_is_secure(env)) { - int spd; - - if (el == 0 && (env->cp15.sder & 1)) { - /* SDER.SUIDEN means debug exceptions from Secure EL0 - * are always enabled. Otherwise they are controlled by - * SDCR.SPD like those from other Secure ELs. - */ - return true; - } - - spd = extract32(env->cp15.mdcr_el3, 14, 2); - switch (spd) { - case 1: - /* SPD == 0b01 is reserved, but behaves as 0b00. */ - case 0: - /* For 0b00 we return true if external secure invasive debug - * is enabled. On real hardware this is controlled by external - * signals to the core. QEMU always permits debug, and behaves - * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. - */ - return true; - case 2: - return false; - case 3: - return true; - } - } - - return el != 2; -} - -/* Return true if debugging exceptions are currently enabled. - * This corresponds to what in ARM ARM pseudocode would be - * if UsingAArch32() then - * return AArch32.GenerateDebugExceptions() - * else - * return AArch64.GenerateDebugExceptions() - * We choose to push the if() down into this function for clarity, - * since the pseudocode has it at all callsites except for the one in - * CheckSoftwareStep(), where it is elided because both branches would - * always return the same value. - */ -static inline bool arm_generate_debug_exceptions(CPUARMState *env) -{ - if (env->aarch64) { - return aa64_generate_debug_exceptions(env); - } else { - return aa32_generate_debug_exceptions(env); - } -} - static inline bool arm_sctlr_b(CPUARMState *env) { return diff --git a/target/arm/internals.h b/target/arm/internals.h index 64e2c1dfad..02fa70f75a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1326,6 +1326,7 @@ bool el_is_in_host(CPUARMState *env, int el); void aa32_max_features(ARMCPU *cpu); int exception_target_el(CPUARMState *env); bool arm_singlestep_active(CPUARMState *env); +bool arm_generate_debug_exceptions(CPUARMState *env); /* Powers of 2 for sve_vq_map et al. */ #define SVE_VQ_POW2_MAP \ diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 1abf41c5f8..20a0e4261a 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -12,6 +12,100 @@ #include "exec/helper-proto.h" +/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ +static bool aa64_generate_debug_exceptions(CPUARMState *env) +{ + int cur_el = arm_current_el(env); + int debug_el; + + if (cur_el == 3) { + return false; + } + + /* MDCR_EL3.SDD disables debug events from Secure state */ + if (arm_is_secure_below_el3(env) + && extract32(env->cp15.mdcr_el3, 16, 1)) { + return false; + } + + /* + * Same EL to same EL debug exceptions need MDSCR_KDE enabled + * while not masking the (D)ebug bit in DAIF. + */ + debug_el = arm_debug_target_el(env); + + if (cur_el == debug_el) { + return extract32(env->cp15.mdscr_el1, 13, 1) + && !(env->daif & PSTATE_D); + } + + /* Otherwise the debug target needs to be a higher EL */ + return debug_el > cur_el; +} + +static bool aa32_generate_debug_exceptions(CPUARMState *env) +{ + int el = arm_current_el(env); + + if (el == 0 && arm_el_is_aa64(env, 1)) { + return aa64_generate_debug_exceptions(env); + } + + if (arm_is_secure(env)) { + int spd; + + if (el == 0 && (env->cp15.sder & 1)) { + /* + * SDER.SUIDEN means debug exceptions from Secure EL0 + * are always enabled. Otherwise they are controlled by + * SDCR.SPD like those from other Secure ELs. + */ + return true; + } + + spd = extract32(env->cp15.mdcr_el3, 14, 2); + switch (spd) { + case 1: + /* SPD == 0b01 is reserved, but behaves as 0b00. */ + case 0: + /* + * For 0b00 we return true if external secure invasive debug + * is enabled. On real hardware this is controlled by external + * signals to the core. QEMU always permits debug, and behaves + * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. + */ + return true; + case 2: + return false; + case 3: + return true; + } + } + + return el != 2; +} + +/* + * Return true if debugging exceptions are currently enabled. + * This corresponds to what in ARM ARM pseudocode would be + * if UsingAArch32() then + * return AArch32.GenerateDebugExceptions() + * else + * return AArch64.GenerateDebugExceptions() + * We choose to push the if() down into this function for clarity, + * since the pseudocode has it at all callsites except for the one in + * CheckSoftwareStep(), where it is elided because both branches would + * always return the same value. + */ +bool arm_generate_debug_exceptions(CPUARMState *env) +{ + if (env->aarch64) { + return aa64_generate_debug_exceptions(env); + } else { + return aa32_generate_debug_exceptions(env); + } +} + /* * Is single-stepping active? (Note that the "is EL_D AArch64?" check * implicitly means this always returns false in pre-v8 CPUs.) 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 06/23] target/arm: Use is_a64 in arm_generate_debug_exceptions Date: Thu, 9 Jun 2022 13:28:44 -0700 Message-Id: <20220609202901.1177572-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the accessor rather than the raw structure member. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/debug_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 20a0e4261a..a18a09a0c3 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -99,7 +99,7 @@ static bool aa32_generate_debug_exceptions(CPUARMState *env) */ bool arm_generate_debug_exceptions(CPUARMState *env) { - if (env->aarch64) { + if (is_a64(env)) { return aa64_generate_debug_exceptions(env); } else { return aa32_generate_debug_exceptions(env); From patchwork Thu Jun 9 20:28:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580321 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1130900max; Thu, 9 Jun 2022 13:41:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz74ZdPfsfTkfGwPEevUPFij6tiFlaeLyfcxwVAtMD/Qt9XgnAfDh74iu/jCsfxDlNFDw9M X-Received: by 2002:a05:622a:174d:b0:305:1170:bfe5 with SMTP id l13-20020a05622a174d00b003051170bfe5mr3427288qtk.579.1654807279709; Thu, 09 Jun 2022 13:41:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654807279; cv=none; d=google.com; s=arc-20160816; b=fJBEr00CCLSE8ZdnIV1kN5FYIL9iEfIvU3uDTjKtcMd5lmOOTvCQytN2MhG/io0VYH HPbTinzl1ybkGXPEmydfuIezObXkHXVo/rR1wvJPbmBB115grETuWdl0V7DMKLz86JUd WtzdhHgz96xVRUnGmLFZ6aYubBoWkrCvBXxYxOBPYpQk04QIzm8xvnrOZzlbvYK/HOYr 8o1HwRZIQwovU6fkx+hfsrT9yacJpH7nPIIGECi5sKIY2P22ZnxorLoqLknqKQH/IibU h6tQKHpna3665ExmaCrh5QX5aPtfKFY/9p2RENY8+uxj1+T1mdCUSN4VEywCheA8wVPL RQ5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=kj2ZYfRQGSWcXMLkNM8zljFGjh4Y1FzFkf5hNzLBiyI=; b=tNa/4vwwDKTp37a2/aFin1zPipJxwueLj0eCrIv4glVrl0VF8ZMU2ZXX8Kst3sxbyb uqNEYNSewOqyRViK7ydHJrs+dRQcWEC45Q73GEupih4VbJdafFiQyTHI+YvVJVvE18dc g+iqpKXdoZdZgMbzzqrXeCxaIp6L3kTIfRTYffaFH5EHbnucf3gj7njSSE1fefn9u41w ZWO9DKz7ISFk2FouTePpv6sy9knQ/RECKYL1X1tx6bXSc4zIBNI/K5Y8WrsKkBhHLWfd +D1I96nwmJpcNqoln7ZmBhIEyJ400nlqNHumNl/XygT2vZybrh8Plrhfdlsk3MG4h4mo wDjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QmusMp69; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 07/23] target/arm: Move exception_bkpt_insn to debug_helper.c Date: Thu, 9 Jun 2022 13:28:45 -0700 Message-Id: <20220609202901.1177572-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/debug_helper.c | 31 +++++++++++++++++++++++++++++++ target/arm/op_helper.c | 29 ----------------------------- 2 files changed, 31 insertions(+), 29 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index a18a09a0c3..80dff0788b 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -430,6 +430,37 @@ void arm_debug_excp_handler(CPUState *cs) } } +/* + * Raise an EXCP_BKPT with the specified syndrome register value, + * targeting the correct exception level for debug exceptions. + */ +void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) +{ + int debug_el = arm_debug_target_el(env); + int cur_el = arm_current_el(env); + + /* FSR will only be used if the debug target EL is AArch32. */ + env->exception.fsr = arm_debug_exception_fsr(env); + /* + * FAR is UNKNOWN: clear vaddress to avoid potentially exposing + * values to the guest that it shouldn't be able to see at its + * exception/security level. + */ + env->exception.vaddress = 0; + /* + * Other kinds of architectural debug exception are ignored if + * they target an exception level below the current one (in QEMU + * this is checked by arm_generate_debug_exceptions()). Breakpoint + * instructions are special because they always generate an exception + * to somewhere: if they can't go to the configured debug exception + * level they are taken to the current exception level. + */ + if (debug_el < cur_el) { + debug_el = cur_el; + } + raise_exception(env, EXCP_BKPT, syndrome, debug_el); +} + #if !defined(CONFIG_USER_ONLY) vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 97c8c9ec77..2a8bdc2cbf 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -399,35 +399,6 @@ void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, raise_exception(env, excp, syndrome, target_el); } -/* Raise an EXCP_BKPT with the specified syndrome register value, - * targeting the correct exception level for debug exceptions. - */ -void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) -{ - int debug_el = arm_debug_target_el(env); - int cur_el = arm_current_el(env); - - /* FSR will only be used if the debug target EL is AArch32. */ - env->exception.fsr = arm_debug_exception_fsr(env); - /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing - * values to the guest that it shouldn't be able to see at its - * exception/security level. - */ - env->exception.vaddress = 0; - /* - * Other kinds of architectural debug exception are ignored if - * they target an exception level below the current one (in QEMU - * this is checked by arm_generate_debug_exceptions()). Breakpoint - * instructions are special because they always generate an exception - * to somewhere: if they can't go to the configured debug exception - * level they are taken to the current exception level. - */ - if (debug_el < cur_el) { - debug_el = cur_el; - } - raise_exception(env, EXCP_BKPT, syndrome, debug_el); -} - uint32_t HELPER(cpsr_read)(CPUARMState *env) { return cpsr_read(env) & ~CPSR_EXEC; From patchwork Thu Jun 9 20:28:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580330 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1144798max; Thu, 9 Jun 2022 14:02:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyytwv4zL1dhSWB1JC3PJARK1Uo8dfHCpART8+JSjfm0Et4Vb1+45fG7qKfzYFBaqdT75f0 X-Received: by 2002:a05:6214:f09:b0:46a:83fc:6a93 with SMTP id gw9-20020a0562140f0900b0046a83fc6a93mr22806269qvb.123.1654808532479; Thu, 09 Jun 2022 14:02:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654808532; cv=none; d=google.com; s=arc-20160816; b=Sh/KlWm03lOJt+fFWfmalnYmpgKjts57tuuZwEMf9pHUFlqeUyoSgjGygr2UdnHI8e XEr2MV20fGtT1aXpiOWJBmJdBl6y/Z9B9uPPEOC32FhZ7wPZN12lCQa4DdEoP9GUzgUg lugQDrFzj8CRWRdXo+6ln6KKeVTKh93cCSwM7hOBAxxHZpRSlALkIP5Ls0Oybzt0lsVD t8+h0maCDwmvQFfOBHnapng784bbrb7WiKA1ucNvtS8QEry3yJXfbws1ME5r41/W6ogz Xzimpy4WL07QJWZmzli1Yqlue64RD4I3FRYan2sMlTONjD7qG36Cl0tltBBs9XhtfxXt h9ZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BCzxefNxcQpSTLu01BysmYqWqiN0wU9rTXU9xeYcYo4=; b=MFpXVwGfa/gk13r1x22rFSfRsqD0CKsqLhu7nQShvTK/wKsxiiXGnRTbaS9yvW3qLI qZDLnAJ1gPXYZLkZ+PupYPAuNE2ZxDjaFUuOYvcoayay0mkqMMZr2ITTeWHaQ4YjUu/f g2HHmrVO58WuLvHNKjDrWZq4d9NGk9c4M/2DgvuHAxTt1HnS1QWKoFiKo+lpuIuxDvwe GNlR6V7EtMivkJFhy6HdSGXfRngURJwcHq3xr0Dms4xHxHx8FP1OBntKwWnrO9hbrY8k IxV0Z/xEOKVDYTuLDS1kyJ9+KirNmrM8hfJ0Fwm+JLnSfhN/rlW0SE9NX2Hc6F0+x81P yhww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I0oSIx0k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 08/23] target/arm: Move arm_debug_exception_fsr to debug_helper.c Date: Thu, 9 Jun 2022 13:28:46 -0700 Message-Id: <20220609202901.1177572-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function now now only used in debug_helper.c, so there is no reason to have a declaration in a header. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 25 ------------------------- target/arm/debug_helper.c | 26 ++++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 25 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 02fa70f75a..6f94f3019d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -793,31 +793,6 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; } -/* Return the FSR value for a debug exception (watchpoint, hardware - * breakpoint or BKPT insn) targeting the specified exception level. - */ -static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) -{ - ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; - int target_el = arm_debug_target_el(env); - bool using_lpae = false; - - if (target_el == 2 || arm_el_is_aa64(env, target_el)) { - using_lpae = true; - } else { - if (arm_feature(env, ARM_FEATURE_LPAE) && - (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { - using_lpae = true; - } - } - - if (using_lpae) { - return arm_fi_to_lfsc(&fi); - } else { - return arm_fi_to_sfsc(&fi); - } -} - /** * arm_num_brps: Return number of implemented breakpoints. * Note that the ID register BRPS field is "number of bps - 1", diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 80dff0788b..a743061e89 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -379,6 +379,32 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) return check_watchpoints(cpu); } +/* + * Return the FSR value for a debug exception (watchpoint, hardware + * breakpoint or BKPT insn) targeting the specified exception level. + */ +static uint32_t arm_debug_exception_fsr(CPUARMState *env) +{ + ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; + int target_el = arm_debug_target_el(env); + bool using_lpae = false; + + if (target_el == 2 || arm_el_is_aa64(env, target_el)) { + using_lpae = true; + } else { + if (arm_feature(env, ARM_FEATURE_LPAE) && + (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { + using_lpae = true; + } + } + + if (using_lpae) { + return arm_fi_to_lfsc(&fi); + } else { + return arm_fi_to_sfsc(&fi); + } +} + void arm_debug_excp_handler(CPUState *cs) { /* From patchwork Thu Jun 9 20:28:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580323 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1131535max; Thu, 9 Jun 2022 13:42:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwzIogX0N1b02g+520lYCpbj5kl9GmyLf01v4POiXLsxGIuew9b6BdE7fRaTisH/WK705Lt X-Received: by 2002:a37:594:0:b0:6a6:9b42:c47a with SMTP id 142-20020a370594000000b006a69b42c47amr23081755qkf.652.1654807348332; Thu, 09 Jun 2022 13:42:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654807348; cv=none; d=google.com; s=arc-20160816; b=SEqfDKQABsX2BRfjIjCAV5Vj2uUzg3Z/xzEqpVxWgWkfcGdAHD12S7SYeEQstKAVcR KuW6uUolP69ZIdmuj+gcJFwCP1EyE4/bSgF8CxVgvJ4sLKxLDTu3yOmg4hw67amZgMgb sZ8zu3mtxc0r8lrKG1ktKmbcapl2mFj7l4gJO+u33Lv6aMSgxW/Q5jZmt0iFyrChM7ks lsGIVOugOTloSsB3ualEn4nQSWzH+GF4adVWK+qBDVAaWhVlcebnMhAkrJwcCVvoH7RA rkfM1Ts/MyxhNUkh1uwk1osnD1PCG5lht0W5jmklVaE4fzL5wPn6/4R0zRqjQsPdmJsh RsSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pnz9a4ifMBmrgWuB+Ns8XkcntMH3zG5QAm9o9NexRzw=; b=QYUXTV1+mAGCNQA8E/AnZ3bLxTJ9lMTpUzJeO1h7GU/3pytVYiqHd/uzbSoyD116QK kt3EI8sEc9UC0uYWERV6byZz2UDv8cEeK5Y+6Y6znfP0EXbha+t06jPtDLRCfgDamk3S CFW8Xu1RLUvK6LA/Q6TLRpmIGHG28yQVZA4xwneOOAzVz0Q6InjVx7bWDtn59WvjzYqU L/PrcSFBI+woob8O6DWP8wpgXMdwQM1Wkbrm3IZQjxAiCO+f4nasj+mTPEAgYj1Q7sip G9JOkqJtbhx33+eD8Gv+wO2HMVyId/FPCEDuC51gByKz2dRCc39SEQlXsS6Yx+5uFNQ9 QeKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WM2AoqcE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 09/23] target/arm: Rename helper_exception_with_syndrome Date: Thu, 9 Jun 2022 13:28:47 -0700 Message-Id: <20220609202901.1177572-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename to helper_exception_with_syndrome_el, to emphasize that the target el is a parameter. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 2 +- target/arm/translate.h | 6 +++--- target/arm/op_helper.c | 6 +++--- target/arm/translate.c | 6 +++--- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 5161cdf73d..5a6802e3fa 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -45,7 +45,7 @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(exception_internal, noreturn, env, i32) -DEF_HELPER_4(exception_with_syndrome, noreturn, env, i32, i32, i32) +DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) DEF_HELPER_1(setend, void, env) diff --git a/target/arm/translate.h b/target/arm/translate.h index f473a21ed4..c57830126b 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -332,9 +332,9 @@ static inline void gen_ss_advance(DisasContext *s) static inline void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) { - gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp), - tcg_constant_i32(syndrome), - tcg_constant_i32(target_el)); + gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), + tcg_constant_i32(syndrome), + tcg_constant_i32(target_el)); } /* Generate an architectural singlestep exception */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 2a8bdc2cbf..8a6a3b8551 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -381,7 +381,7 @@ void HELPER(yield)(CPUARMState *env) * those EXCP values which are special cases for QEMU to interrupt * execution and not to be used for exceptions which are passed to * the guest (those must all have syndrome information and thus should - * use exception_with_syndrome). + * use exception_with_syndrome*). */ void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) { @@ -393,8 +393,8 @@ void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) } /* Raise an exception with the specified syndrome register value */ -void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el) +void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp, + uint32_t syndrome, uint32_t target_el) { raise_exception(env, excp, syndrome, target_el); } diff --git a/target/arm/translate.c b/target/arm/translate.c index 87a899d638..dc033600c0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1119,9 +1119,9 @@ static void gen_exception_el(DisasContext *s, int excp, uint32_t syn, { gen_set_condexec(s); gen_set_pc_im(s, s->pc_curr); - gen_helper_exception_with_syndrome(cpu_env, - tcg_constant_i32(excp), - tcg_constant_i32(syn), tcg_el); + gen_helper_exception_with_syndrome_el(cpu_env, + tcg_constant_i32(excp), + tcg_constant_i32(syn), tcg_el); s->base.is_jmp = DISAS_NORETURN; } From patchwork Thu Jun 9 20:28:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580325 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1137751max; Thu, 9 Jun 2022 13:52:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJybzVU/MeqOzZjwrixVL2EleyPQpLOAGEweNes5pS4ochShPnE1cbzi7pM2cPSfY/rnd2wd X-Received: by 2002:a05:622a:1343:b0:304:fd82:122d with SMTP id w3-20020a05622a134300b00304fd82122dmr12047800qtk.676.1654807937169; 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 10/23] target/arm: Introduce gen_exception_insn_el_v Date: Thu, 9 Jun 2022 13:28:48 -0700 Message-Id: <20220609202901.1177572-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function below gen_exception_insn that takes the target_el as a TCGv_i32, replacing gen_exception_el. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index dc033600c0..9cb31663dd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1086,8 +1086,8 @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) s->base.is_jmp = DISAS_NORETURN; } -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, - uint32_t syn, uint32_t target_el) +static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, + uint32_t syn, TCGv_i32 tcg_el) { if (s->aarch64) { gen_a64_set_pc_im(pc); @@ -1095,10 +1095,17 @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, gen_set_condexec(s); gen_set_pc_im(s, pc); } - gen_exception(excp, syn, target_el); + gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), + tcg_constant_i32(syn), tcg_el); s->base.is_jmp = DISAS_NORETURN; } +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, + uint32_t syn, uint32_t target_el) +{ + gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el)); +} + static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) { gen_set_condexec(s); @@ -1114,17 +1121,6 @@ void unallocated_encoding(DisasContext *s) default_exception_el(s)); } -static void gen_exception_el(DisasContext *s, int excp, uint32_t syn, - TCGv_i32 tcg_el) -{ - gen_set_condexec(s); - gen_set_pc_im(s, s->pc_curr); - gen_helper_exception_with_syndrome_el(cpu_env, - tcg_constant_i32(excp), - tcg_constant_i32(syn), tcg_el); - s->base.is_jmp = DISAS_NORETURN; -} - /* Force a TB lookup after an instruction that changes the CPU state. */ void gen_lookup_tb(DisasContext *s) { @@ -2847,7 +2843,8 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, tcg_el = tcg_constant_i32(3); } - gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el); + gen_exception_insn_el_v(s, s->pc_curr, EXCP_UDEF, + syn_uncategorized(), tcg_el); tcg_temp_free_i32(tcg_el); return false; } From patchwork Thu Jun 9 20:28:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580324 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1137295max; Thu, 9 Jun 2022 13:51:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzwZZz9mciuHQaUkzzXkOSYmVCyGW6TjfyQjkCCwfx29iluKWqi4FcKZPFmc8uA9LDu/FSi X-Received: by 2002:a05:6214:e48:b0:46b:8c08:f926 with SMTP id o8-20020a0562140e4800b0046b8c08f926mr19551881qvc.38.1654807890281; Thu, 09 Jun 2022 13:51:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654807890; cv=none; d=google.com; s=arc-20160816; b=xYDfaeau0rp0zI4lrXpfVdl6mvA2tZfmkUPMazxrbpiOF95MrJ/6rVnIWI//zXhyhn QH7DVj2yN75aGZeIkX5J3d/84Gb64ECXFT06WwNNPIOC3GrxcF90f4Vr54DqwWbaxyCr 9ofjaNXS2ujdce7eC50s30n42gPtP954Cv1HF/kzPhCG9cji2R8Kgu8tAIt3Dg7WqpcG /fBsfMEQjvR3vkPafRLM+GVKphIlZDMnMUtCYcOqJjFa6RMenIMt+Mmp31O/uBBky0/o pikDheVNlmU/hUhGPVI0dZMuYUNAQtsXnGV17ohgOBp+YFCrc8sxXU6iNfKzidt5Yrtv 9F6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9MAUNs6V4mRPp9A90sOBEHx7YdKEYigB5XZ+QV7oJR0=; b=F+X0FdmvyNO+aCnNGiyXeAIknzaYJPWsGfQKKX5kyUVV58MWj9mhZVxELU+3gYWaJO gQUVoEVGGghyx1ZqKPiMVnYstA2chGXb2YgkrYwgoWev0GQMnCDCric2K2Pzrqg3LpxX mu5ke8hE3i5mAcgW+YtuwaER0qeX5LCsRwucyrtIavjX67VF4KxVTIGO+/9YnqimNuvY b8y9eW/eFU8zjsmbjJExl/Qr4q2YXgAHK5VT4dPVilFag9SHDF+BIjHcdfu7d5aMMt8D 4kj7Ol3h6fceD5sx1h2cw2oXPGl7g6uTWETJZNuwdf/5/mLFRRK0qMDBeVMUXnDAPA8D SVvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dLa6MlYh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 11/23] target/arm: Rename gen_exception_insn to gen_exception_insn_el Date: Thu, 9 Jun 2022 13:28:49 -0700 Message-Id: <20220609202901.1177572-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.h | 4 ++-- target/arm/translate-a64.c | 36 ++++++++++++++++---------------- target/arm/translate-m-nocp.c | 16 +++++++------- target/arm/translate-mve.c | 4 ++-- target/arm/translate-vfp.c | 6 +++--- target/arm/translate.c | 39 ++++++++++++++++++----------------- 6 files changed, 53 insertions(+), 52 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index c57830126b..9ae76535ad 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -279,8 +279,8 @@ void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); MemOp pow2_align(unsigned i); void unallocated_encoding(DisasContext *s); -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, - uint32_t syn, uint32_t target_el); +void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, + uint32_t syn, uint32_t target_el); /* Return state of Alternate Half-precision flag, caller frees result */ static inline TCGv_i32 get_ahp_flag(void) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e752589090..14bc80dba0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1161,9 +1161,9 @@ static bool fp_access_check(DisasContext *s) assert(!s->fp_access_checked); s->fp_access_checked = true; - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false, 0), - s->fp_excp_el); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + syn_fp_access_trap(1, 0xe, false, 0), + s->fp_excp_el); return false; } s->fp_access_checked = true; @@ -1179,8 +1179,8 @@ bool sve_access_check(DisasContext *s) assert(!s->sve_access_checked); s->sve_access_checked = true; - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_sve_access_trap(), s->sve_excp_el); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + syn_sve_access_trap(), s->sve_excp_el); return false; } s->sve_access_checked = true; @@ -1816,8 +1816,8 @@ static void gen_sysreg_undef(DisasContext *s, bool isread, } else { syndrome = syn_uncategorized(); } - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome, - default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syndrome, + default_exception_el(s)); } /* MRS - move from system register @@ -2069,8 +2069,8 @@ static void disas_exc(DisasContext *s, uint32_t insn) switch (op2_ll) { case 1: /* SVC */ gen_ss_advance(s); - gen_exception_insn(s, s->base.pc_next, EXCP_SWI, - syn_aa64_svc(imm16), default_exception_el(s)); + gen_exception_insn_el(s, s->base.pc_next, EXCP_SWI, + syn_aa64_svc(imm16), default_exception_el(s)); break; case 2: /* HVC */ if (s->current_el == 0) { @@ -2083,8 +2083,8 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_a64_set_pc_im(s->pc_curr); gen_helper_pre_hvc(cpu_env); gen_ss_advance(s); - gen_exception_insn(s, s->base.pc_next, EXCP_HVC, - syn_aa64_hvc(imm16), 2); + gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC, + syn_aa64_hvc(imm16), 2); break; case 3: /* SMC */ if (s->current_el == 0) { @@ -2094,8 +2094,8 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_a64_set_pc_im(s->pc_curr); gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16))); gen_ss_advance(s); - gen_exception_insn(s, s->base.pc_next, EXCP_SMC, - syn_aa64_smc(imm16), 3); + gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC, + syn_aa64_smc(imm16), 3); break; default: unallocated_encoding(s); @@ -14725,8 +14725,8 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_illegalstate(), default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + syn_illegalstate(), default_exception_el(s)); return; } @@ -14757,9 +14757,9 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) if (s->btype != 0 && s->guarded_page && !btype_destination_ok(insn, s->bt, s->btype)) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_btitrap(s->btype), - default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + syn_btitrap(s->btype), + default_exception_el(s)); return; } } else { diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index 27363a7b4e..636bfb1788 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -143,8 +143,8 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); if (s->fp_excp_el != 0) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), s->fp_excp_el); + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); return true; } @@ -376,7 +376,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, if (!vfp_access_check_m(s, true)) { /* * This was only a conditional exception, so override - * gen_exception_insn()'s default to DISAS_NORETURN + * gen_exception_insn_el()'s default to DISAS_NORETURN */ s->base.is_jmp = DISAS_NEXT; break; @@ -532,7 +532,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, if (!vfp_access_check_m(s, true)) { /* * This was only a conditional exception, so override - * gen_exception_insn()'s default to DISAS_NORETURN + * gen_exception_insn_el()'s default to DISAS_NORETURN */ s->base.is_jmp = DISAS_NEXT; break; @@ -765,14 +765,14 @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a) } if (a->cp != 10) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), default_exception_el(s)); return true; } if (s->fp_excp_el != 0) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), s->fp_excp_el); + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); return true; } diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 4267d43cc7..5aec2a1555 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -100,8 +100,8 @@ bool mve_eci_check(DisasContext *s) return true; default: /* Reserved value: INVSTATE UsageFault */ - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), + default_exception_el(s)); return false; } } diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 0f797c56fd..82fdbcae53 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -230,7 +230,7 @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa; uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc); - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el); return false; } @@ -260,8 +260,8 @@ bool vfp_access_check_m(DisasContext *s, bool skip_context_update) * the encoding space handled by the patterns in m-nocp.decode, * and for them we may need to raise NOCP here. */ - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), s->fp_excp_el); + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); return false; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 9cb31663dd..44f462a3a3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1100,8 +1100,8 @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, s->base.is_jmp = DISAS_NORETURN; } -void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, - uint32_t syn, uint32_t target_el) +void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, + uint32_t syn, uint32_t target_el) { gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el)); } @@ -1117,8 +1117,8 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) void unallocated_encoding(DisasContext *s) { /* Unallocated and reserved encodings are uncategorized */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); } /* Force a TB lookup after an instruction that changes the CPU state. */ @@ -2869,8 +2869,8 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, undef: /* If we get here then some access check did not pass */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_uncategorized(), exc_target); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + syn_uncategorized(), exc_target); return false; } @@ -5094,7 +5094,8 @@ static void gen_srs(DisasContext *s, * For the UNPREDICTABLE cases we choose to UNDEF. */ if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), 3); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + syn_uncategorized(), 3); return; } @@ -8479,8 +8480,8 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) * Do the check-and-raise-exception by hand. */ if (s->fp_excp_el) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), s->fp_excp_el); + gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); return true; } } @@ -8582,8 +8583,8 @@ static bool trans_LE(DisasContext *s, arg_LE *a) tmp = load_cpu_field(v7m.ltpsize); tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc); tcg_temp_free_i32(tmp); - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), + default_exception_el(s)); gen_set_label(skipexc); } @@ -9053,8 +9054,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) * UsageFault exception. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), + default_exception_el(s)); return; } @@ -9063,8 +9064,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_illegalstate(), default_exception_el(s)); + gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, + syn_illegalstate(), default_exception_el(s)); return; } @@ -9633,8 +9634,8 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, - syn_illegalstate(), default_exception_el(dc)); + gen_exception_insn_el(dc, dc->pc_curr, EXCP_UDEF, + syn_illegalstate(), default_exception_el(dc)); return; } @@ -9707,8 +9708,8 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) */ tcg_remove_ops_after(dc->insn_eci_rewind); dc->condjmp = 0; - gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(dc)); + gen_exception_insn_el(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(), + default_exception_el(dc)); } arm_post_translate_insn(dc); From patchwork Thu Jun 9 20:28:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580327 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1140877max; Thu, 9 Jun 2022 13:57:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzvCTxb5GtDLP0YFkGwBOmfrgr5lYwuX17cYebiWrRJjjE65kIY3gRieghdJYSjwr8s3VFh X-Received: by 2002:a05:6214:21eb:b0:464:5c48:4bc8 with SMTP id p11-20020a05621421eb00b004645c484bc8mr31644731qvj.23.1654808235503; Thu, 09 Jun 2022 13:57:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654808235; cv=none; d=google.com; s=arc-20160816; b=nO13xdEv24T24vYoqPjBpzbtI0W6k3KcE2eYGHY9xSH+c/lcY/rUzNrQFnjjwaQ4Hh L3xI5xRH3IHs3lzcRmmONNTehf0O6T3BU1NifGldJGL9CzIa+PkhAkNpDXGItOkEUxzt ws0r7JqTjyJYckbVFeGnhfxdTQpDLHsKI3zp5A+U0yyuNDFxx0NuqhUA450r6j1xDASw ZjsmWE7wLBAoGY1oae/9cbHQBmdRF9csz9Uj1EMdPcR/ctuacweZjxF+Ps6ZKbseoa/M 0MKSFAp9y0fbEY5IW4UOdmPaZSqAN/qwdi9QZ8KZvVggTo091GK/OxoQJi3MUJYZm/Nh om0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UBq9cvT3mNZnwBfSHCh8l7KhDANOXMY80ZzRcK7glgg=; b=f688w4ktMGoA274EJGnrvqoRznIUgQglLnHEr4MCFMRrNN6P/u66OJYw/40tyGjR8J w6cleNFHGQNVpu3Yq/wJVEhTTDcyc6yj7fne0AqCmJdPa0Amm4LjhNJtEiHYCeaBFBlt emVEsdGz4mZIlk4ojT9gjcb7RaOzM0i6FKib+djra8MlGewnlAGYeDaT9Gv9lBi+yIun VqqV4U1DC7gU+0NAaCpHguW9+CKrBQ1bdlWStY/mMd6TaDQS6K91IFwozf3vbq1/x4W2 +KyjPp636M3ZG8R1LDUn8FZtz0nj6Z3755sMyAue6/smpDeobhE6F10gvMDWMTYiRiPx dxuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RnxSB7Ki; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 12/23] target/arm: Introduce gen_exception_insn Date: Thu, 9 Jun 2022 13:28:50 -0700 Message-Id: <20220609202901.1177572-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a new wrapper function that passes the default exception target to gen_exception_insn_el. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.h | 1 + target/arm/translate-a64.c | 15 ++++++--------- target/arm/translate-m-nocp.c | 3 +-- target/arm/translate-mve.c | 3 +-- target/arm/translate.c | 29 +++++++++++++---------------- 5 files changed, 22 insertions(+), 29 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 9ae76535ad..4575af6e1c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -281,6 +281,7 @@ MemOp pow2_align(unsigned i); void unallocated_encoding(DisasContext *s); void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, uint32_t syn, uint32_t target_el); +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn); /* Return state of Alternate Half-precision flag, caller frees result */ static inline TCGv_i32 get_ahp_flag(void) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 14bc80dba0..0581118f56 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1816,8 +1816,7 @@ static void gen_sysreg_undef(DisasContext *s, bool isread, } else { syndrome = syn_uncategorized(); } - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syndrome, - default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome); } /* MRS - move from system register @@ -2069,8 +2068,8 @@ static void disas_exc(DisasContext *s, uint32_t insn) switch (op2_ll) { case 1: /* SVC */ gen_ss_advance(s); - gen_exception_insn_el(s, s->base.pc_next, EXCP_SWI, - syn_aa64_svc(imm16), default_exception_el(s)); + gen_exception_insn(s, s->base.pc_next, EXCP_SWI, + syn_aa64_svc(imm16)); break; case 2: /* HVC */ if (s->current_el == 0) { @@ -14725,8 +14724,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, - syn_illegalstate(), default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate()); return; } @@ -14757,9 +14755,8 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) if (s->btype != 0 && s->guarded_page && !btype_destination_ok(insn, s->bt, s->btype)) { - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, - syn_btitrap(s->btype), - default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_btitrap(s->btype)); return; } } else { diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index 636bfb1788..4029d7fdd4 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -765,8 +765,7 @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a) } if (a->cp != 10) { - gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized()); return true; } diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 5aec2a1555..0cf1b5ea4f 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -100,8 +100,7 @@ bool mve_eci_check(DisasContext *s) return true; default: /* Reserved value: INVSTATE UsageFault */ - gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized()); return false; } } diff --git a/target/arm/translate.c b/target/arm/translate.c index 44f462a3a3..c7d422b541 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1106,6 +1106,11 @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el)); } +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn) +{ + gen_exception_insn_el(s, pc, excp, syn, default_exception_el(s)); +} + static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) { gen_set_condexec(s); @@ -1117,8 +1122,7 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) void unallocated_encoding(DisasContext *s) { /* Unallocated and reserved encodings are uncategorized */ - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized()); } /* Force a TB lookup after an instruction that changes the CPU state. */ @@ -2731,8 +2735,6 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, * an exception and return false. Otherwise it will return true, * and set *tgtmode and *regno appropriately. */ - int exc_target = default_exception_el(s); - /* These instructions are present only in ARMv8, or in ARMv7 with the * Virtualization Extensions. */ @@ -2869,8 +2871,7 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, undef: /* If we get here then some access check did not pass */ - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, - syn_uncategorized(), exc_target); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized()); return false; } @@ -8583,8 +8584,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a) tmp = load_cpu_field(v7m.ltpsize); tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc); tcg_temp_free_i32(tmp); - gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized()); gen_set_label(skipexc); } @@ -9054,8 +9054,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) * UsageFault exception. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized()); return; } @@ -9064,8 +9063,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, - syn_illegalstate(), default_exception_el(s)); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate()); return; } @@ -9634,8 +9632,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * Illegal execution state. This has priority over BTI * exceptions, but comes after instruction abort exceptions. */ - gen_exception_insn_el(dc, dc->pc_curr, EXCP_UDEF, - syn_illegalstate(), default_exception_el(dc)); + gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, syn_illegalstate()); return; } @@ -9708,8 +9705,8 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) */ tcg_remove_ops_after(dc->insn_eci_rewind); dc->condjmp = 0; - gen_exception_insn_el(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(), - default_exception_el(dc)); + gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, + syn_uncategorized()); } arm_post_translate_insn(dc); From patchwork Thu Jun 9 20:28:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580322 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1130966max; Thu, 9 Jun 2022 13:41:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyVdqazo8OTg2S6n+myZmG+pivfkeQRAd8vNIwcLT7eGCfQ4RLxMUEH0XAnEG1vgOejK7bT X-Received: by 2002:ac8:5915:0:b0:304:f2f8:f254 with SMTP id 21-20020ac85915000000b00304f2f8f254mr16319135qty.303.1654807289369; Thu, 09 Jun 2022 13:41:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654807289; cv=none; d=google.com; s=arc-20160816; b=OLCVNSUMBV0009JtlQ+VxXgkG4Ti+3eJ42wzeZq1oGvBtD8mY1XJCikM3iRtPjKd12 5nXaT1jllYTg651O/yqX1RhpTflNvP8oguh2X2zwLuYiVLzgZDVYHDIFE5JkLu5DEiNp QhnBs8x/tFMgQFxtO4nYI2fD1B+5K7dOnT7RKDUbcYMJ3AlRk/EYzM3/citgf8/kehI4 M1Q27fRgeR0ehRMksZTjdvdjRhHvT42Oyxq4zGeWycD+w96of3q6JTZjIpuqB/vPTD98 95Er/NxnF8UxTSBc3QRuDVs0FyY5uuf1LcxWFFFIj7IM9duPPIUZ95OKAzTVLmvpsHcK nBvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0+1B/GKcGEn9X9Wh/vHToPB3bf3Gcg47/xOcf+MkVK4=; b=HNHqCCDpata13cVf/jc962qAzq6VrTIIaw9dOpscbEX7tld7sftxV6EFHJI0AqwfiI fj42Jf06QzIZxJ/WMTZwLI/fjMidfF7OJm2/Cq/f8rZQxOjkRY1aJHf0MPbmRHg/Drd3 4l0amUF9BylQLp7rjvXfKFeS4XraKEMFScvfadQEY0qOs5k5Wi3L03HrxiWXjIeG4Ocn LHbzqWmbdOETD9K9OhX0Od2ZHrFNThEP86T8xmJRsxzoYWuPts8e0lwQL1EEbN71VbXP sprJDcY1ga1Rg9od1ZOjECmmHRwjYb4XQ3eHGU/nVzyRaC8sBkPAd3LhJ1qVJP/KjxPT HC9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=k+ly7rWs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e63-20020a378242000000b006a3ae33a2fbsi13341238qkd.622.2022.06.09.13.41.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 13:41:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=k+ly7rWs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51904 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzOy8-0007pI-Op for patch@linaro.org; Thu, 09 Jun 2022 16:41:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43392) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzOmO-0003zF-HA for qemu-devel@nongnu.org; Thu, 09 Jun 2022 16:29:20 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:56094) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzOmJ-0008Ux-Ad for qemu-devel@nongnu.org; Thu, 09 Jun 2022 16:29:20 -0400 Received: by mail-pj1-x1032.google.com with SMTP id e9so11776340pju.5 for ; Thu, 09 Jun 2022 13:29:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0+1B/GKcGEn9X9Wh/vHToPB3bf3Gcg47/xOcf+MkVK4=; b=k+ly7rWsmjvspi/PxfIQPbs7w5Q1elL8Dw0+KZmqiAZ1gnoUT4S/7BbUosoK8MPKB2 IjLtEGToeLRJ1Loc3G8eVnf5I/iqqe+Xr9PE+JxrKk/0B5V2vAW5i3G95GaSPv5Pf12H OdjxJ/QnxDMUfXDYOY3Gs1lTVRWeh5mSfHhFM1ERuQsfpEK2L8ssyFeLcXTVYQSl3Yec kerD0oxFp4iwikJ3+hOqjodq5WkRyyivqGnblXNXInHMGxFHjzJnxOmhHOvj2e629edp FZMXrFlgtOdkSO2sbJBE1zRHPLn3QZxVLoghxjo2rLkTEXZ8wzzmCTFGoeGMedDSPpdY QLTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0+1B/GKcGEn9X9Wh/vHToPB3bf3Gcg47/xOcf+MkVK4=; b=8I0/QBhrOsGSQ+4WRgc3kqZxKYpm1ZdMzY+fC3xYJNebMPXbgGgARUHA6Bn1Gzx8Dt 0gH8upHLG9xsORRK2o6oCD2k3Ol7X2W3nakyWfadF/5vpl/dqzeLLA7MX2ls2f4ouiaS 0XruLEJGtZ4uyuNPLpdke9YNFh2j4FZ4fmM/a6/kFB2L/TTitO/FI9b92WXSGXO1ke4g TvyoPxO0rlNfq5ZgPLmiYfppboaClk/FOtUwcYlweq5tB76szNRfOpTEKqV89E1ZL6o3 bw99uEE6ftu/xCmasgXIn1lw1h7LWZ/LoDSkuw0O0ysBpCkvGqqrjGKdgwG6Mr/KE7fL e3tQ== X-Gm-Message-State: AOAM530I7+Jjw8qOnftRsDhm57nI3yAcscITOv4Ol5LnstoojyN8a6Yw 1JJTq2zHAS9140UYbxh0lSkj/lGeUyel5w== X-Received: by 2002:a17:90b:2246:b0:1e8:5531:5e61 with SMTP id hk6-20020a17090b224600b001e855315e61mr5031073pjb.86.1654806553943; Thu, 09 Jun 2022 13:29:13 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 13/23] target/arm: Create helper_exception_swstep Date: Thu, 9 Jun 2022 13:28:51 -0700 Message-Id: <20220609202901.1177572-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the computation from gen_swstep_exception into a helper. This fixes a bug when: - MDSCR_EL1.KDE == 1 to enable debug exceptions within EL_D itself - we singlestep an ERET from EL_D to some lower EL Previously we were computing 'same el' based on the EL which executed the ERET instruction, whereas it ought to be computed based on the EL to which ERET returned. This happens naturally with the new helper, which runs after EL has been changed. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 1 + target/arm/translate.h | 12 +++--------- target/arm/debug_helper.c | 16 ++++++++++++++++ 3 files changed, 20 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 5a6802e3fa..db7447d233 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -47,6 +47,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, DEF_HELPER_2(exception_internal, noreturn, env, i32) DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) +DEF_HELPER_2(exception_swstep, noreturn, env, i32) DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) diff --git a/target/arm/translate.h b/target/arm/translate.h index 4575af6e1c..890e73194c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -341,15 +341,9 @@ static inline void gen_exception(int excp, uint32_t syndrome, /* Generate an architectural singlestep exception */ static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) { - bool same_el = (s->debug_target_el == s->current_el); - - /* - * If singlestep is targeting a lower EL than the current one, - * then s->ss_active must be false and we can never get here. - */ - assert(s->debug_target_el >= s->current_el); - - gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el); + /* Fill in the same_el field of the syndrome in the helper. */ + uint32_t syn = syn_swstep(false, isv, ex); + gen_helper_exception_swstep(cpu_env, tcg_constant_i32(syn)); } /* diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index a743061e89..a3a1b98de2 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -487,6 +487,22 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) raise_exception(env, EXCP_BKPT, syndrome, debug_el); } +void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome) +{ + int debug_el = arm_debug_target_el(env); + int cur_el = arm_current_el(env); + + /* + * If singlestep is targeting a lower EL than the current one, then + * DisasContext.ss_active must be false and we can never get here. + */ + assert(debug_el >= cur_el); + if (debug_el == cur_el) { + syndrome |= 1 << ARM_EL_EC_SHIFT; + } + raise_exception(env, EXCP_UDEF, syndrome, debug_el); +} + #if !defined(CONFIG_USER_ONLY) vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) From patchwork Thu Jun 9 20:28:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580328 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1140884max; Thu, 9 Jun 2022 13:57:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwH9cyqsECso5JrnLEvvj5xjfJvpktr8tSzz4XQkSoJU+AoKNa/nL/8biQ15yrT3UmmSUMJ X-Received: by 2002:ac8:4e51:0:b0:305:754:9f99 with SMTP id e17-20020ac84e51000000b0030507549f99mr7568859qtw.684.1654808236486; Thu, 09 Jun 2022 13:57:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654808236; cv=none; d=google.com; s=arc-20160816; b=TsoOlE4Yrn+LsCSSwlQtizBHdFoNgqgoIloulh8do9RS9EyB6Z4bU99vqxu8zgOM4Y a8LOYZE5szw7gxSkLN2/tC8nfx9Nw9D9Rlacq/PogE9/k+d/WlBPii1HNoioEigqb204 vexGvTvtdi7CJaA/apK7bJW1nkw9rcA0z2y51DaHIq4994K5MFvOJXAxgK/FhYI1J2Lx 5pehl6KE6mDbBmq86BQ7behLppjWsDtNIiVDVKZsX6qikm2fq7KEuMiipI6WHWIec5v5 M2bILj2jg0OWuIST8lx0On3t+dsX1VmOpuUHe6o100DqzNXo+6PGr82+pHdRLs9EgmhU A8rA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=X4QBEGoTbGLTN/ILF22bIhYsyh/MJrjgKuORCxmlFdc=; b=VlUolLVY1CErVOfH7nmjB5meJmnjebGCof2WJgWnDOBIW5Cmk/oPB8FrNgl8O02R1I xWGD7lPYpfyc9JaNmvSX9U/PwifoVVhy+ldBgdKi7X+J3yxNnxtKRuEngEOA8cZBDZP4 PckG1pPBAFH3oE/BRsPeYw5AsoSdFwTperehSo884Tt0hmMpPdzeSkIAbPKTBxM/wAuL Hy65ygACRLIqSOzcNhbV2n+a3GKXYofwZBWzm/04KWExxXpcryi6vwRda4NoOcup6Nml GUugPkGe4jUAOocsd/zhwiKwGbbkGMtmM4aUdRtJQdP4h9fj0uplWFUbsqqpS03mWhH2 0vag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WpcdIk92; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 14/23] target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_EL Date: Thu, 9 Jun 2022 13:28:52 -0700 Message-Id: <20220609202901.1177572-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We no longer need this value during translation, as it is now handled within the helpers. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 ++---- target/arm/translate.h | 2 -- target/arm/helper.c | 12 ++---------- target/arm/translate-a64.c | 1 - target/arm/translate.c | 1 - 5 files changed, 4 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 50b5a9c9fd..719613ad9e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3104,11 +3104,9 @@ FIELD(TBFLAG_ANY, BE_DATA, 3, 1) FIELD(TBFLAG_ANY, MMUIDX, 4, 4) /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) -/* For A-profile only, target EL for debug exceptions. */ -FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ -FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) -FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1) +FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) +FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) /* * Bit usage when in AArch32 state, both A- and M-profile. diff --git a/target/arm/translate.h b/target/arm/translate.h index 890e73194c..8685f55e80 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -59,8 +59,6 @@ typedef struct DisasContext { */ uint32_t svc_imm; int current_el; - /* Debug target exception level for single-step exceptions */ - int debug_target_el; GHashTable *cp_regs; uint64_t features; /* CPU features bits */ bool aarch64; diff --git a/target/arm/helper.c b/target/arm/helper.c index ac9942d750..2b2c1998fd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11102,18 +11102,10 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } -static CPUARMTBFlags rebuild_hflags_aprofile(CPUARMState *env) -{ - CPUARMTBFlags flags = {}; - - DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env)); - return flags; -} - static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { - CPUARMTBFlags flags = rebuild_hflags_aprofile(env); + CPUARMTBFlags flags = {}; int el = arm_current_el(env); if (arm_sctlr(env, el) & SCTLR_A) { @@ -11139,7 +11131,7 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { - CPUARMTBFlags flags = rebuild_hflags_aprofile(env); + CPUARMTBFlags flags = {}; ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint64_t sctlr; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0581118f56..4f6181a548 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14645,7 +14645,6 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->ss_active = EX_TBFLAG_ANY(tb_flags, SS_ACTIVE); dc->pstate_ss = EX_TBFLAG_ANY(tb_flags, PSTATE__SS); dc->is_ldex = false; - dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); /* Bound the number of insns to execute to those left on the page. */ bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; diff --git a/target/arm/translate.c b/target/arm/translate.c index c7d422b541..b8a8972bac 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9350,7 +9350,6 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT); dc->mve_no_pred = EX_TBFLAG_M32(tb_flags, MVE_NO_PRED); } else { - dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B); dc->hstr_active = EX_TBFLAG_A32(tb_flags, HSTR_ACTIVE); dc->ns = EX_TBFLAG_A32(tb_flags, NS); From patchwork Thu Jun 9 20:28:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580334 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1151570max; Thu, 9 Jun 2022 14:10:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzSEfd0Y/6bvjCeHI4706tmLCOy4kENk1pHqBUAEycZy6qFvuqmxA1ta2WwL7eeBkFdtyhN X-Received: by 2002:a05:620a:4101:b0:6a6:6c46:440 with SMTP id j1-20020a05620a410100b006a66c460440mr28672021qko.259.1654809030687; Thu, 09 Jun 2022 14:10:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654809030; cv=none; d=google.com; s=arc-20160816; b=nZlLY7UH/5XkSvejmisLSGJewPS4+T52H758Ptkqa+6Vj6/IDSFlukAlER4RKhvFtl rJ+JZB4qfLjoRgcyPwWaWN+pA0zRwS7gJWy9RQB/aZHZqxKnef1IBeBGLBDV7w9nN7qo NQ/ZRcSeXLS34EuRZkKYWLFaOIvC6Ochfcnpp5o/OfY4mBeEvFmP5RnLOy45pF6U6q7p JWhTgGHa6Ieq5TETV/UetU8ST7PBt+cF/7yEGVzttZYF57/m04vFRCV0o2ocESAW/qLV dazYLPAnU5MOygKG6wS08iYAyTafRJWFmNzHt2a18BlBGhUhICKDLZTjcYsBjjgWe8lf 0J6g== ARC-Message-Signature: i=1; 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 15/23] target/arm: Move gen_exception to translate.c Date: Thu, 9 Jun 2022 13:28:53 -0700 Message-Id: <20220609202901.1177572-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is not required by any other translation file. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.h | 8 -------- target/arm/translate.c | 7 +++++++ 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 8685f55e80..850bcdc155 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -328,14 +328,6 @@ static inline void gen_ss_advance(DisasContext *s) } } -static inline void gen_exception(int excp, uint32_t syndrome, - uint32_t target_el) -{ - gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), - tcg_constant_i32(syndrome), - tcg_constant_i32(target_el)); -} - /* Generate an architectural singlestep exception */ static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) { diff --git a/target/arm/translate.c b/target/arm/translate.c index b8a8972bac..fc5eafaeeb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1086,6 +1086,13 @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) s->base.is_jmp = DISAS_NORETURN; } +static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) +{ + gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), + tcg_constant_i32(syndrome), + tcg_constant_i32(target_el)); +} + static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, uint32_t syn, TCGv_i32 tcg_el) { From patchwork Thu Jun 9 20:28:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580337 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1157307max; Thu, 9 Jun 2022 14:18:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJytkEZ7XDTBWqbNwDi9mO4cIi7F3bZobQGp30ZQVxioJuym3270Kc13C34UzgU6FLnU7pAQ X-Received: by 2002:ae9:eb88:0:b0:6a6:b3e3:4c44 with SMTP id b130-20020ae9eb88000000b006a6b3e34c44mr17796332qkg.83.1654809533355; Thu, 09 Jun 2022 14:18:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654809533; cv=none; d=google.com; s=arc-20160816; b=YEbE4tBeBP7hxwdFsRqJ3KIDBJcknd6w/Nsz9xGwfEOzuLJaVKA9grJmmhyVo+yZOp 9vHrv7w/xgFYj/RypDqkoCXiE0ioDeCHTtPUG7knNHqAp42E782qn7/vZRwB0AmnvioG 1r4l4PaLDvXRn7X0GSXqLwzNCnYJh4yISP8qBttddVFK/cRKMaGG6ryNXKVkr0dk3whJ 800ObOoME+zgyJ18Q7FRkYPmleJALVTbIceGBLepYZ8pJcy6QKf3cIjDU8J7UbEKAyNs CxHfLzsBfndzs2YwR1v7Epx3UW+kaGt4AiRpU7NG2pQWAGepoliEbRRJEFzo0MXGBjDM hE2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=tkItDlBc/fej8rt3xUV6vGEsNdVvZUjvDsXBkPPMGQA=; b=wzGjARS7HHUGw/YhE3cXE3RjHz6Bn+w1mCw4ZwS8+7fNj4PCToYCVnTicXwgUp3laI sZrh9t1YEPm5o5LyMqdPCNJAi7ch4xA7irrOD2tA3jyIYjLLcvDOMnNt1efi7wiA2/5D tU8qEcSxzTmqHBqkuuXs45ExoQwKIX/XdXuoruLsgD+wk6pUiBWIwddnaOUUqDmi79jH DIO3mNbUIY9iTOwGH+MUfYqK80rCXiaiQI7aEo1IATEty84JCQjCvj2dCFsHNk1OftLt XrKHVuUXA1MMY0lp3xrr3FkCjT/FoJoVRQhd5maludEIGiDWQEeQ0lUYh+vBdvYyWXvs Uttg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I0CR6nhE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 16/23] target/arm: Rename gen_exception to gen_exception_el Date: Thu, 9 Jun 2022 13:28:54 -0700 Message-Id: <20220609202901.1177572-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index fc5eafaeeb..edb7d3f394 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1086,7 +1086,7 @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) s->base.is_jmp = DISAS_NORETURN; } -static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) +static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) { gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), tcg_constant_i32(syndrome), @@ -9758,16 +9758,16 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_SWI: gen_ss_advance(dc); - gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), - default_exception_el(dc)); + gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), + default_exception_el(dc)); break; case DISAS_HVC: gen_ss_advance(dc); - gen_exception(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); + gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); break; case DISAS_SMC: gen_ss_advance(dc); - gen_exception(EXCP_SMC, syn_aa32_smc(), 3); + gen_exception_el(EXCP_SMC, syn_aa32_smc(), 3); break; case DISAS_NEXT: case DISAS_TOO_MANY: @@ -9828,14 +9828,14 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_helper_yield(cpu_env); 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 17/23] target/arm: Introduce gen_exception Date: Thu, 9 Jun 2022 13:28:55 -0700 Message-Id: <20220609202901.1177572-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a new wrapper function that passes the default exception target to gen_exception_el. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index edb7d3f394..5a48937ede 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1093,6 +1093,11 @@ static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) tcg_constant_i32(target_el)); } +static void gen_exception(DisasContext *s, int excp, uint32_t syndrome) +{ + gen_exception_el(excp, syndrome, default_exception_el(s)); +} + static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, uint32_t syn, TCGv_i32 tcg_el) { @@ -9758,8 +9763,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_SWI: gen_ss_advance(dc); - gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), - default_exception_el(dc)); + gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); break; case DISAS_HVC: gen_ss_advance(dc); @@ -9828,8 +9832,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_helper_yield(cpu_env); break; case DISAS_SWI: - gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), - default_exception_el(dc)); + gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); break; case DISAS_HVC: gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); From patchwork Thu Jun 9 20:28:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580336 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1155407max; Thu, 9 Jun 2022 14:16:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyEJk2jPQ/rmCYAsHBXt24B8EiKhaurQLghF0d8qrRdDOBVVzi43xFelQXuJvPDOMQ+4L/X X-Received: by 2002:a05:622a:1ba0:b0:304:ef7a:ff6d with SMTP id bp32-20020a05622a1ba000b00304ef7aff6dmr17284710qtb.314.1654809363397; Thu, 09 Jun 2022 14:16:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654809363; cv=none; d=google.com; s=arc-20160816; b=H3WnaosPrSRolAi39IopLgV719NynXznYRw1JaMoao+6id50R0t9UCAht8ODK5WECd HZ1Cs138k5rvofeLTpzT/gRGBG2GL2VJaPQ17zmLyJNyGwrKuVUyDMU3+E9oqTFXHEg+ Rafcdh4pFAVVMYg+BP+wXioA1+Air3mpxgKEJCnDa8zkNWGPR+jUUMJZB0OGUNSVQWsl oaXy6dF7rEnPLKB0SxIe5dNz4gtwoNmCLCk0TPoE73WbJ6OVa8PT0izwKvkfxYdXi+91 jKnP5HR6XgDNryOhx0WHOS5252e+z1CgKqKpXK0FOs/Fwn0++QhU7P+QIB+NVSQtMDPA aVfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XrwBHtaJMwMweCtn22KfTI+wKyoZs8cSGLm5AgDVmqM=; b=gLL1XS/c8tWAMuCJuW264dmd8uR144t0HZrEQ8Y67bjOqcUxUk4E19t4unwCaF7uBl Fbv966jpN6VtocWTi84vX4hv2vOd2qq3AtYQrMHruW3a06pRZ2XoBQU0geGd8dkfV4n1 5qqM/yNFs1rpjJexUjoiOGAFaDRgjrpM4L5CD45yfoU69347zfEwWBQIoaZ3XIabkknj O4Mohs0ZB0F8n+OngzSw1C8I0hOn2bryiQ7zW25D8OYdhhspcxScy3Ye7XoAOWP0hC0B SRB17D3tpSvjAGhQiDbf88rfU0AoFutA/82xP1tjlmECCRVHMYn0QTvXs3PXIppJZWKK mpVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rG05RsYB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 18/23] target/arm: Introduce gen_exception_el_v Date: Thu, 9 Jun 2022 13:28:56 -0700 Message-Id: <20220609202901.1177572-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out a common helper function for gen_exception_el and gen_exception_insn_el_v. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5a48937ede..fcb6ee648b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1086,11 +1086,15 @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) s->base.is_jmp = DISAS_NORETURN; } -static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) +static void gen_exception_el_v(int excp, uint32_t syndrome, TCGv_i32 tcg_el) { gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), - tcg_constant_i32(syndrome), - tcg_constant_i32(target_el)); + tcg_constant_i32(syndrome), tcg_el); +} + +static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) +{ + gen_exception_el_v(excp, syndrome, tcg_constant_i32(target_el)); } static void gen_exception(DisasContext *s, int excp, uint32_t syndrome) @@ -1107,8 +1111,7 @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, gen_set_condexec(s); gen_set_pc_im(s, pc); } - gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), - tcg_constant_i32(syn), tcg_el); + gen_exception_el_v(excp, syn, tcg_el); s->base.is_jmp = DISAS_NORETURN; } From patchwork Thu Jun 9 20:28:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580331 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1146318max; Thu, 9 Jun 2022 14:03:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyDWEhH0JWorUs5hc6Ay9S1zJmexl5RTMW0Pxz0hH+3EEnUK+bnmxeAlSCkyiye5aJOhi/z X-Received: by 2002:a05:620a:2413:b0:6a6:c22d:97c8 with SMTP id d19-20020a05620a241300b006a6c22d97c8mr14708734qkn.610.1654808633589; Thu, 09 Jun 2022 14:03:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654808633; cv=none; d=google.com; s=arc-20160816; b=B2s8v+zdKXn9OptRw9xwUi0xR1TV9Kl36mGLiOvqzWzgNOg4kevCndwrxS4zhhW0bs G+0Oido5c/WASc6MMKNFXTjWWzN+CtJqjSrkRv9OZTP2fYmWOGL+OOGAGIMvH6SfhXUg EchowOrBs2p1PWGiOGsbOviFuEa8Va3zIRkaPpx+kEKjlEAb4EnZlEnivxJNseJFFdpM dGckTULh8d8ND+RfOgzXYEzRuIOQXywtNcknPvRLhzWkZ25KFJC1Ef8vN+m2iHXR9M6Z nilOkaQqN8vXXGhrdvxcMj9IGzR31SnvlSGMQvezUobSldS0HbIx/ZJGNefwJdMfzEBW YE/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DZfUsxzMa6ISMCnyMY5oUW8yvE0MgIXecjoPtJTXdCc=; b=HBbLHGSqsyG6Lmf8lGXMvEE/Lg0CG7kklN5ng+O6O+6GZ/pu6cuMauXDONvTLZESIq qBighNaO0IRP5kd31D5vjYFujx0R4dIHCx3knHHwS4tLzBrVurTmnFfe8+/9ebi6kgzF FlzddwlO273spGVdvREKOPPnZvFRhFwv5ERmwrgSly6skZT1fhHJyS1qv4Zvtml3olxy T8a2uQXHMCLIywdgqdiu911mHn2z9KeqAfY4e6K4vRD/u9x7WCVZhzyFfcy7eVt6/XqP 13KqHA+Ie2Lk8rCFr67KfX4301PaaDQpUHFmsNHOnkiqdFZYDZwoohnMC/aD4pquTCjR C3NQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="N/PtKLN+"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 19/23] target/arm: Introduce helper_exception_with_syndrome Date: Thu, 9 Jun 2022 13:28:57 -0700 Message-Id: <20220609202901.1177572-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With the helper we can use exception_target_el at runtime, instead of default_exception_el at translate time. While we're at it, remove the DisasContext parameter from gen_exception, as it is no longer used. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 1 + target/arm/op_helper.c | 10 ++++++++++ target/arm/translate.c | 18 +++++++++++++----- 3 files changed, 24 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index db7447d233..07d45faf49 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -45,6 +45,7 @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(exception_internal, noreturn, env, i32) +DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32) DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) DEF_HELPER_2(exception_swstep, noreturn, env, i32) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8a6a3b8551..c5bde1cfcc 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -399,6 +399,16 @@ void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp, raise_exception(env, excp, syndrome, target_el); } +/* + * Raise an exception with the specified syndrome register value + * to the default target el. + */ +void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, + uint32_t syndrome) +{ + raise_exception(env, excp, syndrome, exception_target_el(env)); +} + uint32_t HELPER(cpsr_read)(CPUARMState *env) { return cpsr_read(env) & ~CPSR_EXEC; diff --git a/target/arm/translate.c b/target/arm/translate.c index fcb6ee648b..81c27e7c70 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1097,9 +1097,10 @@ static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el) gen_exception_el_v(excp, syndrome, tcg_constant_i32(target_el)); } -static void gen_exception(DisasContext *s, int excp, uint32_t syndrome) +static void gen_exception(int excp, uint32_t syndrome) { - gen_exception_el(excp, syndrome, default_exception_el(s)); + gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp), + tcg_constant_i32(syndrome)); } static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp, @@ -1123,7 +1124,14 @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp, void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn) { - gen_exception_insn_el(s, pc, excp, syn, default_exception_el(s)); + if (s->aarch64) { + gen_a64_set_pc_im(pc); + } else { + gen_set_condexec(s); + gen_set_pc_im(s, pc); + } + gen_exception(excp, syn); + s->base.is_jmp = DISAS_NORETURN; } static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) @@ -9766,7 +9774,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_SWI: gen_ss_advance(dc); - gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); + gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); break; case DISAS_HVC: gen_ss_advance(dc); @@ -9835,7 +9843,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_helper_yield(cpu_env); break; case DISAS_SWI: - gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); + gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); break; case DISAS_HVC: gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2); From patchwork Thu Jun 9 20:28:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580333 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1149723max; 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 20/23] target/arm: Remove default_exception_el Date: Thu, 9 Jun 2022 13:28:58 -0700 Message-Id: <20220609202901.1177572-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is no longer used. At the same time, remove DisasContext.secure_routed_to_el3, as it in turn becomes unused. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.h | 16 ---------------- target/arm/translate-a64.c | 5 ----- target/arm/translate.c | 5 ----- 3 files changed, 26 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 850bcdc155..88dc18a034 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -43,8 +43,6 @@ typedef struct DisasContext { int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; /* SVE exception EL or 0 if enabled */ int vl; /* current vector length in bytes */ - /* Flag indicating that exceptions from secure mode are routed to EL3. */ - bool secure_routed_to_el3; bool vfp_enabled; /* FP enabled via FPSCR.EN */ int vec_len; int vec_stride; @@ -199,20 +197,6 @@ static inline int get_mem_index(DisasContext *s) return arm_to_core_mmu_idx(s->mmu_idx); } -/* Function used to determine the target exception EL when otherwise not known - * or default. - */ -static inline int default_exception_el(DisasContext *s) -{ - /* If we are coming from secure EL0 in a system with a 32-bit EL3, then - * there is no secure EL1, so we route exceptions to EL3. Otherwise, - * exceptions can only be routed to ELs above 1, so we target the higher of - * 1 or the current EL. - */ - return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3) - ? 3 : MAX(1, s->current_el); -} - static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) { /* We don't need to save all of the syndrome so we mask and shift diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4f6181a548..4c64546090 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14585,11 +14585,6 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->condjmp = 0; dc->aarch64 = true; - /* If we are coming from secure EL0 in a system with a 32-bit EL3, then - * there is no secure EL1, so we route exceptions to EL3. - */ - dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && - !arm_el_is_aa64(env, 3); dc->thumb = false; dc->sctlr_b = 0; dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; diff --git a/target/arm/translate.c b/target/arm/translate.c index 81c27e7c70..6617de775f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9319,11 +9319,6 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->condjmp = 0; dc->aarch64 = false; - /* If we are coming from secure EL0 in a system with a 32-bit EL3, then - * there is no secure EL1, so we route exceptions to EL3. - */ - dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && - !arm_el_is_aa64(env, 3); dc->thumb = EX_TBFLAG_AM32(tb_flags, THUMB); dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; condexec = EX_TBFLAG_AM32(tb_flags, CONDEXEC); From patchwork Thu Jun 9 20:28:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580335 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1154170max; Thu, 9 Jun 2022 14:14:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwgfGdZ4N6WtBfCDuc2wrvzjJpAloFVp9/++7YFYvUhQB3fNeD3VDlnA4fuRq1rUpKedrm4 X-Received: by 2002:ac8:5b44:0:b0:305:1aa7:1a96 with SMTP id n4-20020ac85b44000000b003051aa71a96mr578653qtw.608.1654809262602; Thu, 09 Jun 2022 14:14:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654809262; cv=none; d=google.com; s=arc-20160816; b=dRGvRhMLdA80W2g0LOQxaU9cc74tEEEeTtTmQ4CRKis5qDtcrUOZJ7zl4Az+fNkpCv qp0+c8VxXGzvc9zWgQ9tKIOW3U7EkhSieGm3on+WMiKkBVVpc96Zu+QHMU5KqoqIrsu+ P1OIJDPrYDkyRvDsTLlGJk9z2EN/cli4pUZnqGSfbGf07JT+QWsbnxDjCnf1YaOU3YS3 yNR6ott6Gr3ReQmB5K0CyKIhziumItq/zEdIarGvnR29jx0hL9Ylv3BLvekF6gp49hgh 0fDFFDhl5Oe9O6oICe7ld5Xt1NGobZg7zNYIUyE0b/b9hlvk6qC4UNqV7y5OWgwPBxYa U2QA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZvVhJ9luWKkwdZYjhq+lmyv/sw3Hp1aeF2mDU3UCb9I=; b=kv/XwZ9Apo3ErcDhgH5eK0kren3ZrZhjtoz0oQpTbF821YfRMGaQo5ae56c/CksduW KEOFOdMnQ31GEwZZl8O6Buzeau3P008rT9Txzt6KpnnxTk8/0cgMNElfkzkhjN7YAlUJ ql4VldN0iEJn//DM3iCnX+Vvb4GcbPiXfxNvE1uYiaP7NfqmWfGx8QITrUwzTULQEoJV lWVC+v/6zvSJ+xafgcY2/Xn1RmTUlQcVO1p49b0DfMhEW6foXVLAMTBOsvN2tS9jB+RN ggXyVAoIh5togN/ihhFx9g2DwMokR6jlyi9l17vDOeXZSrQQCJR0YmB3yqwapFbmmB3h s7Kw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DPulRIgo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 21/23] target/arm: Create raise_exception_debug Date: Thu, 9 Jun 2022 13:28:59 -0700 Message-Id: <20220609202901.1177572-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Handle the debug vs current el exception test in one place. Leave EXCP_BKPT alone, since that treats debug < current differently. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/debug_helper.c | 44 +++++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index a3a1b98de2..26004df99b 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -12,6 +12,26 @@ #include "exec/helper-proto.h" +/* + * Raise an exception to the debug target el. + * Modify syndrome to indicate when origin and target EL are the same. + */ +G_NORETURN static void +raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome) +{ + int debug_el = arm_debug_target_el(env); + int cur_el = arm_current_el(env); + + /* + * If singlestep is targeting a lower EL than the current one, then + * DisasContext.ss_active must be false and we can never get here. + * Similarly for watchpoint and breakpoint matches. + */ + assert(debug_el >= cur_el); + syndrome |= (debug_el == cur_el) << ARM_EL_EC_SHIFT; + raise_exception(env, excp, syndrome, debug_el); +} + /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ static bool aa64_generate_debug_exceptions(CPUARMState *env) { @@ -418,19 +438,16 @@ void arm_debug_excp_handler(CPUState *cs) if (wp_hit) { if (wp_hit->flags & BP_CPU) { bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0; - bool same_el = arm_debug_target_el(env) == arm_current_el(env); cs->watchpoint_hit = NULL; env->exception.fsr = arm_debug_exception_fsr(env); env->exception.vaddress = wp_hit->hitaddr; - raise_exception(env, EXCP_DATA_ABORT, - syn_watchpoint(same_el, 0, wnr), - arm_debug_target_el(env)); + raise_exception_debug(env, EXCP_DATA_ABORT, + syn_watchpoint(0, 0, wnr)); } } else { uint64_t pc = is_a64(env) ? env->pc : env->regs[15]; - bool same_el = (arm_debug_target_el(env) == arm_current_el(env)); /* * (1) GDB breakpoints should be handled first. @@ -450,9 +467,7 @@ void arm_debug_excp_handler(CPUState *cs) * exception/security level. */ env->exception.vaddress = 0; - raise_exception(env, EXCP_PREFETCH_ABORT, - syn_breakpoint(same_el), - arm_debug_target_el(env)); + raise_exception_debug(env, EXCP_PREFETCH_ABORT, syn_breakpoint(0)); } } @@ -489,18 +504,7 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome) { - int debug_el = arm_debug_target_el(env); - int cur_el = arm_current_el(env); - - /* - * If singlestep is targeting a lower EL than the current one, then - * DisasContext.ss_active must be false and we can never get here. - */ - assert(debug_el >= cur_el); - if (debug_el == cur_el) { - syndrome |= 1 << ARM_EL_EC_SHIFT; - } - raise_exception(env, EXCP_UDEF, syndrome, debug_el); + raise_exception_debug(env, EXCP_UDEF, syndrome); } #if !defined(CONFIG_USER_ONLY) From patchwork Thu Jun 9 20:29:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 580339 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp1160654max; Thu, 9 Jun 2022 14:24:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyi6+8ZFnyYHl8W2phS4oW/B/Ebt/piT6XgN2Tm76MzUkXZK4+ysQAdKbl8dQ37upf5vaoq X-Received: by 2002:a05:6214:2a8e:b0:464:5b2f:76bf with SMTP id jr14-20020a0562142a8e00b004645b2f76bfmr40523785qvb.60.1654809882674; Thu, 09 Jun 2022 14:24:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654809882; cv=none; d=google.com; s=arc-20160816; b=QH9sfoDQ5SaHKSTDuQtLAHekZOR6GFxYdnvvFag4/TjBeq/B4ZEWmzl/ynkJwfwbUY nWo6yYQm11NS+DtedhHyzdQRrAozeoW8vqcka3jrZssrzjnRpCeoZI1qoZR0qgWROb20 lUWLF94kdYthapNpoXqehePrPjl4tQTaJyTkUz7vtFPAIC4mp/yztpPgGo0LkGcdsWfH tJZUWt+Oj2aab3fSzFR2zZnHTc/CBbJW5KaEpp9QQiQqWsJv8mqh91Z2RQwySD7T3pX3 xcgPxqv44DkJDDbfwGV7cE3e0cyjHIwUhVzUENaC3CvD6pFRGhWh/T/teoOX3PvMrJqR DW3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rHr3GvWpnhlYyxP8wVfL31GtOWGiQW1hytUXYczR5lk=; b=0QSv59HOWUNcXSDjUgXDU2zVvMBxtakqjVF68ro2ycWa6WmWtTLVhgGt66YsH/PDeM ++Z9GI/2C6au1RdvV6+uR7tI62xiesYttFCdNAYPLVA1WxnVASVHuqMjHqJ6ALTqhO9I 9LU0SEO6lqabfdKWdk/o6JLo3jSTzQt2ck2lXu0ELGmDKf9FY+pntlDyRAC3a2SWu+vE 4JDCzi5k3HakE+XRGgoKjyX5LKa1NAhx2jxbz1U+DnYp3J4YUvPbbmxorpk27rQ9T7Jq YsKNGuYLj+0QZSyQSesk3C+U7Nsz3C83HaXmGrN4n5ozpDxn3aRo4/u8v7/re+pyx6TY GKhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FXddmIt9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 22/23] target/arm: Move arm_debug_target_el to debug_helper.c Date: Thu, 9 Jun 2022 13:29:00 -0700 Message-Id: <20220609202901.1177572-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is no longer used outside debug_helper.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 21 --------------------- target/arm/debug_helper.c | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 719613ad9e..161ac9fa2e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2986,27 +2986,6 @@ typedef enum ARMASIdx { ARMASIdx_TagS = 3, } ARMASIdx; -/* Return the Exception Level targeted by debug exceptions. */ -static inline int arm_debug_target_el(CPUARMState *env) -{ - bool secure = arm_is_secure(env); - bool route_to_el2 = false; - - if (arm_is_el2_enabled(env)) { - route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || - env->cp15.mdcr_el2 & MDCR_TDE; - } - - if (route_to_el2) { - return 2; - } else if (arm_feature(env, ARM_FEATURE_EL3) && - !arm_el_is_aa64(env, 3) && secure) { - return 3; - } else { - return 1; - } -} - static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) { /* If all the CLIDR.Ctypem bits are 0 there are no caches, and diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 26004df99b..b18a6bd3a2 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -12,6 +12,27 @@ #include "exec/helper-proto.h" +/* Return the Exception Level targeted by debug exceptions. */ +static int arm_debug_target_el(CPUARMState *env) +{ + bool secure = arm_is_secure(env); + bool route_to_el2 = false; + + if (arm_is_el2_enabled(env)) { + route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || + env->cp15.mdcr_el2 & MDCR_TDE; + } + + if (route_to_el2) { + return 2; + } else if (arm_feature(env, ARM_FEATURE_EL3) && + !arm_el_is_aa64(env, 3) && secure) { + return 3; + } else { + return 1; + } +} + /* * Raise an exception to the debug target el. * Modify syndrome to indicate when origin and target EL are the same. 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([2602:ae:1547:e101:839f:476f:678:38a]) by smtp.gmail.com with ESMTPSA id r20-20020a635d14000000b003fded88238esm7528139pgb.36.2022.06.09.13.29.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 13:29:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 23/23] target/arm: Fix Secure PL1 tests in fp_exception_el Date: Thu, 9 Jun 2022 13:29:01 -0700 Message-Id: <20220609202901.1177572-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609202901.1177572-1-richard.henderson@linaro.org> References: <20220609202901.1177572-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We were using arm_is_secure and is_a64, which are tests against the current EL, as opposed to arm_el_is_aa64 and arm_is_secure_below_el3, which can be applied to a different EL than current. Consolidate the two tests. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2b2c1998fd..b95aa53474 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10879,27 +10879,22 @@ int fp_exception_el(CPUARMState *env, int cur_el) int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN); switch (fpen) { + case 1: + if (cur_el != 0) { + break; + } + /* fall through */ case 0: case 2: - if (cur_el == 0 || cur_el == 1) { - /* Trap to PL1, which might be EL1 or EL3 */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { - return 3; - } - return 1; - } - if (cur_el == 3 && !is_a64(env)) { - /* Secure PL1 running at EL3 */ + /* Trap from Secure PL0 or PL1 to Secure PL1. */ + if (!arm_el_is_aa64(env, 3) + && (cur_el == 3 || arm_is_secure_below_el3(env))) { return 3; } - break; - case 1: - if (cur_el == 0) { + if (cur_el <= 1) { return 1; } break; - case 3: - break; } }