From patchwork Thu Jun 9 09:04:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580240 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp597299max; Thu, 9 Jun 2022 02:22:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwRPN89JcCjQyYy2qczhv76qQFqmTODrrDW9VsaME4ydrudeaDARd8Guw9+ya8pS1DFhKcs X-Received: by 2002:a05:622a:553:b0:305:a78:a1ed with SMTP id m19-20020a05622a055300b003050a78a1edmr3233068qtx.138.1654766561965; Thu, 09 Jun 2022 02:22:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654766561; cv=none; d=google.com; s=arc-20160816; b=n/PZ61MTwX2r3cpyDqjWt1eEfVP4vGDcE0rjqBW1u5bjWv6MziOwU+PkosmvRiBBb3 ZgKVODSZ3RedLnPLszVx56j89YN//B9WYzvtiXKY4m0wFmDQ0BIc6mlyLAGCx5mRuA70 bedZNqNAdk4afkdii2Ge5IuWBOsWSvZsfNDypW4e8mj9Lbp0lMlXSohfERhSKjFW4pXl Mn1HU8aoAx+lbNbGiigkPpzOpXMlN0F682H33hmdPDKiwt/WIf0KfF+sNTuH5CqgZVvl ZSSNmhOyXw4SkvAtYLmp0Crwu+8z/hn7KPocPkXXPsNTPSj0AesE2O2fptuyzUoIjf0Z h4vA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=n6D/t27wwLVN4prcAZRU1vm1AJNkQw3wnfuM1H0pUck=; b=DE81vIcwV0lM3FrjPioYhpprr9+wbcGPndYkjy0mUhr6y+QR97KGgPAkZuG/x3JJ4W xtJ9VEkMzdL26m17Qg9idTQQbPy5RkZDGiX9dUUMGmJ209Zv33FoM6FozRsfYdGyZbAf FN1py642jZbNM4Zln/KutO9ObbhPlp+jv1LMWe3N+MLXvDVfNgeGVCb0q3Oxp34Dnw19 vQn+oWUQjpvjqXGav88GJPmF8XK+M/jIm+iyI++80vqMkvmJ4Y60kg7hsJrE09sZFoMs qMOpYjzOEEJP6dvBlRgm4jtOQabKjCbFmsJSHYil7kt5SOhZoiiMnDUxkiDK0+FQjRqV 5SWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="h5Hwx/K2"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id bm3-20020a05620a198300b006a671d63e0csi234670qkb.209.2022.06.09.02.22.41 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:22:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="h5Hwx/K2"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:32962 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzENF-0008G4-Gq for patch@linaro.org; Thu, 09 Jun 2022 05:22:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39166) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE6t-0001OL-KI for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:48 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:46807) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE6q-0005v7-J9 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:47 -0400 Received: by mail-wr1-x429.google.com with SMTP id u8so27137454wrm.13 for ; Thu, 09 Jun 2022 02:05:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=n6D/t27wwLVN4prcAZRU1vm1AJNkQw3wnfuM1H0pUck=; b=h5Hwx/K2RSxhAEALBLGhe9sLO7nb48J383r2uyz/pSSfGhvp7FgZZnakzY+n7A7xEp U1x5Z/uuRLLBhDjZ5cbfP3P8Kmu2JlTx66BBe/Uy4R92F0tIK/SMms+15yrBnPe9dcBI PFV6B8lvXrMBjocMsh4KceBi06mCS86XLB8doY43a5Yt6dlyTQadknLB/2uQhHXMTQng O7v2LAwv4IIK3uALE/YpdXQW9JyV5050/PyrNPQgp1U2fCt6fyQcBcE79WSKAEsQw34Y vSyERkpyerYei2/mjJRFYpofejufXwfcSjOntAg9zsATD6shNrkkkTvSzhnoz9Ha7g1q cn7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n6D/t27wwLVN4prcAZRU1vm1AJNkQw3wnfuM1H0pUck=; b=JZh8kCIyPhSXCtVr4Jp36qBn2xIFUH3PPURa7zSbGgjU1tvxrdicZ7VL7nHJMZ+2fN gp/Dm8r3PwhVy/kicXNG/P1Ak085GZ21Hfes3s71L/UNP8TOtmj0nANoTM2aOGy7Lzo2 NxS7VemyL0kf+hTbnprflpz70mOVpOqqX6/Ydr+U90hmmEwEAo3dpeELhEdXSWM5vRIO dxl0ZWxyhB4IsBw6w9w6LdcpJNpKvb8zx6QU//70oAHiqQxYv8kWKyGLL5tJsDRww4lw JiMRvgQbhahJgOuU5XH68eIo+7mZYtIEIuRs25hVECq4POTZrWkQQltBUQ9aDNQLb0Rs rc4A== X-Gm-Message-State: AOAM533L4oTfDsV3BIS3jCkoj5Pi5J9bBycJMahcKJwbqSWmXmsynHFE uwhGz5qC4ZMDXj0Xqw5J9WihMfXI17F02Q== X-Received: by 2002:a5d:4290:0:b0:213:badd:abc5 with SMTP id k16-20020a5d4290000000b00213baddabc5mr32113648wrq.54.1654765541512; Thu, 09 Jun 2022 02:05:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/55] target/arm: Declare support for FEAT_RASv1p1 Date: Thu, 9 Jun 2022 10:04:43 +0100 Message-Id: <20220609090537.1971756-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The architectural feature RASv1p1 introduces the following new features: * new registers ERXPFGCDN_EL1, ERXPFGCTL_EL1 and ERXPFGF_EL1 * new bits in the fine-grained trap registers that control traps for these new registers * new trap bits HCR_EL2.FIEN and SCR_EL3.FIEN that control traps for ERXPFGCDN_EL1, ERXPFGCTL_EL1, ERXPFGP_EL1 * a larger number of the ERXMISC_EL1 registers * the format of ERRSTATUS registers changes The architecture permits that if ERRIDR_EL1.NUM is 0 (as it is for QEMU) then all these new registers may UNDEF, and the HCR_EL2.FIEN and SCR_EL3.FIEN bits may be RES0. We don't have any ERRSTATUS registers (again, because ERRIDR_EL1.NUM is 0). QEMU does not yet implement the fine-grained-trap extension. So there is nothing we need to implement to be compliant with the feature spec. Make the 'max' CPU report the feature in its ID registers, and document it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220531114258.855804-1-peter.maydell@linaro.org --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 49cc3e8340e..81467f02ce9 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -52,6 +52,7 @@ the following architecture extensions: - FEAT_PMUv3p1 (PMU Extensions v3.1) - FEAT_PMUv3p4 (PMU Extensions v3.4) - FEAT_RAS (Reliability, availability, and serviceability) +- FEAT_RASv1p1 (RAS Extension v1.1) - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) - FEAT_RNG (Random number generator) - FEAT_S2FWB (Stage 2 forced Write-Back) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3ff9219ca3b..bd1c62a3428 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -916,6 +916,7 @@ static void aarch64_max_initfn(Object *obj) * we do for EL2 with the virtualization=on property. */ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ + t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 1); /* FEAT_RASv1p1 */ t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 = t; From patchwork Thu Jun 9 09:04:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580238 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp592398max; Thu, 9 Jun 2022 02:14:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJykWOsphTfKkxUJbNyozIP+szW8bM5m3MUH2Z8OVOnR8KM3+nrvfDNHgTIxdsYANIlS7RCn X-Received: by 2002:a05:620a:1324:b0:6a6:bc8e:e3cb with SMTP id p4-20020a05620a132400b006a6bc8ee3cbmr14149389qkj.130.1654766081476; Thu, 09 Jun 2022 02:14:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654766081; cv=none; d=google.com; s=arc-20160816; b=cucn7OJajNWYPl63UES/Res+SdzIfQgUGBe59mOlDTyxwHUXEQJdnb6kkUpVij99Vt E0WHEEMtrVf+5DCRoS3eT4vgt4KyOrj6L395YKpqnPKfkK/F6fLfCi5C+krPPUHEQUhl NUVHO9mvfQmSiLYcQIntR8IevXgMDTZTht29QNFr/qXZeQFr+ZH8u4Mff1l05QbYhTpE 1uMu21NldUzO/q60DWQK4Qhn7Z1/VEakavdfAwFtfQSsiOii19RtfdZvbzKQPJHwn4Kh Rxb8AAlBynmx6cs/0z4grrMW/lLHm6/ag3P+ErQmRMKsVzvDk5yBT8fzVRlyulwzqF10 Jlmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tSthpF0IBNTJTlo30iWopYy1wniqooBbIAyfiEVSRlg=; b=yNwhrkv043qS8NyAaecTLQUovI+klxx6+hRufuZQmwHl4FcbP/zqixGH/jb4H5qpMM R6togALXyZtewUXCH4D49NVfg7zA9HO1vBkmP/ZXDiXAT6cUTb1gw7tuujjnryMgkP7Z vvW3KPWyTX4a1/LAxKxwbqLjb9LSk0jKqbe2BOVJie2JjjWeeAVlB5kCjDBB7ROgoLSF LyBvedAeY0ZabBy0yPB5Mr5q7rXdww6PfynwlQial/uBk1CS3qncqFwZpxmDf0aejrhY P5GT6gsqSmrTYPbSc/1iJLKdPjkgG8h/PKTi3mkCKlTQx8j51DrXfkcgDCHEMLUdENm+ K7zA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GOPr49eK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e9-20020a0562140d8900b004646783d13esi9006223qve.550.2022.06.09.02.14.41 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:14:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GOPr49eK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53500 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEFU-0002P8-Td for patch@linaro.org; Thu, 09 Jun 2022 05:14:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE6t-0001OM-Kr for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:48 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:38492) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE6q-0005vV-JI for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:47 -0400 Received: by mail-wr1-x430.google.com with SMTP id v14so5217169wra.5 for ; Thu, 09 Jun 2022 02:05:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=tSthpF0IBNTJTlo30iWopYy1wniqooBbIAyfiEVSRlg=; b=GOPr49eK9pq2k3gRjzuhfdVvDUrv10wE9LDEaYYk3C2Fz9a6ACIxfQLOLak4hv8P1M UBy+o6NwOXdG9U5FmGtt98QNsiICeDKCmxUshS2k7p1SbsQQJJqbytlkaVbIrEwNkocu UyMMHYpeHgduPlX9pSUMqSLaTO3htVxXEwIIOV8hhVNDhGljlbYq9jpeA9/bEmjw8DJP 77V8groWW5y1xzudbZfQU2Z4mYCaIjmjzK1MnaJvhmeIrXElGCacIv4RFXOKTQ9vB7XR Ia8g/YEbtgosWlYKVQLRxfB858kKf4oUtjzaC5UnGj4n7DSR32lPyqPYFrSCda3qhv4Y gM/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tSthpF0IBNTJTlo30iWopYy1wniqooBbIAyfiEVSRlg=; b=Vpy8ZA65fCG+dSCPJHuWD0qe0zr9iP/RQhKqDNuiDHd8sqwHbNpc9hNl8l/wGWqmgv nrIN5swu4qMBYejF+a5r2/ybcOC5xcPUOHweToebLXBCPNAuVNl7ggEGTfYHR6FjgBUh oS4RdAR4U8I+HlnQpIjxpu2dwB5LlWYnm7phMgHMHMhX8olyyrvcu4UUQxG1jvIbfwb6 Be8onCbhjSlzyqZAc+aGXfC2BTl0TM+8PNQ0lekfaGcTJeqVPecZhGF01tNv/p5AGplJ yJxiU9SbEz1+5q23/NrMRIc/K2ewVwx3AKRv1sj2183kPVgLCY0NzmczqaAa4gRoWzkK EyFw== X-Gm-Message-State: AOAM533qmS911VKetpDQzMMZaK9b1FhnJ/3vklxUMgDp2TXKHDr5/N2e zP35aGm6jqAOAzvP8A0xFrZ/OvapGEJfNw== X-Received: by 2002:a5d:67c2:0:b0:215:7a0f:71f9 with SMTP id n2-20020a5d67c2000000b002157a0f71f9mr30971485wrw.486.1654765542593; Thu, 09 Jun 2022 02:05:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/55] target/arm: Implement FEAT_DoubleFault Date: Thu, 9 Jun 2022 10:04:44 +0100 Message-Id: <20220609090537.1971756-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The FEAT_DoubleFault extension adds the following: * All external aborts on instruction fetches and translation table walks for instruction fetches must be synchronous. For QEMU this is already true. * SCR_EL3 has a new bit NMEA which disables the masking of SError interrupts by PSTATE.A when the SError interrupt is taken to EL3. For QEMU we only need to make the bit writable, because we have no sources of SError interrupts. * SCR_EL3 has a new bit EASE which causes synchronous external aborts taken to EL3 to be taken at the same entry point as SError. (Note that this does not mean that they are SErrors for purposes of PSTATE.A masking or that the syndrome register reports them as SErrors: it just means that the vector offset is different.) * The existing SCTLR_EL3.IESB has an effective value of 1 when SCR_EL3.NMEA is 1. For QEMU this is a no-op because we don't need different behaviour based on IESB (we don't need to do anything to ensure that error exceptions are synchronized). So for QEMU the things we need to change are: * Make SCR_EL3.{NMEA,EASE} writable * When taking a synchronous external abort at EL3, adjust the vector entry point if SCR_EL3.EASE is set * Advertise the feature in the ID registers Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220531151431.949322-1-peter.maydell@linaro.org --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 5 +++++ target/arm/cpu64.c | 4 ++-- target/arm/helper.c | 36 +++++++++++++++++++++++++++++++++++ 4 files changed, 44 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 81467f02ce9..83b44100659 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -23,6 +23,7 @@ the following architecture extensions: - FEAT_Debugv8p2 (Debug changes for v8.2) - FEAT_Debugv8p4 (Debug changes for v8.4) - FEAT_DotProd (Advanced SIMD dot product instructions) +- FEAT_DoubleFault (Double Fault Extension) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FHM (Floating-point half-precision multiplication instructions) - FEAT_FP16 (Half-precision floating-point data processing) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c1865ad5dad..0ee1705a4fa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3952,6 +3952,11 @@ static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; } +static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2; +} + static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index bd1c62a3428..cce68dd82a2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -899,7 +899,7 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64pfr0; t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ - t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */ + t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */ t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ @@ -916,7 +916,7 @@ static void aarch64_max_initfn(Object *obj) * we do for EL2 with the virtualization=on property. */ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ - t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 1); /* FEAT_RASv1p1 */ + t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */ t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 = t; diff --git a/target/arm/helper.c b/target/arm/helper.c index 40da63913c9..7f2c14bea94 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1776,6 +1776,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_scxtnum, cpu)) { valid_mask |= SCR_ENSCXT; } + if (cpu_isar_feature(aa64_doublefault, cpu)) { + valid_mask |= SCR_EASE | SCR_NMEA; + } } else { valid_mask &= ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -10113,6 +10116,31 @@ static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) return ret; } +static bool syndrome_is_sync_extabt(uint32_t syndrome) +{ + /* Return true if this syndrome value is a synchronous external abort */ + switch (syn_get_ec(syndrome)) { + case EC_INSNABORT: + case EC_INSNABORT_SAME_EL: + case EC_DATAABORT: + case EC_DATAABORT_SAME_EL: + /* Look at fault status code for all the synchronous ext abort cases */ + switch (syndrome & 0x3f) { + case 0x10: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + return true; + default: + return false; + } + default: + return false; + } +} + /* Handle exception entry to a target EL which is using AArch64 */ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) { @@ -10168,6 +10196,14 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) switch (cs->exception_index) { case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: + /* + * FEAT_DoubleFault allows synchronous external aborts taken to EL3 + * to be taken to the SError vector entrypoint. + */ + if (new_el == 3 && (env->cp15.scr_el3 & SCR_EASE) && + syndrome_is_sync_extabt(env->exception.syndrome)) { + addr += 0x180; + } env->cp15.far_el[new_el] = env->exception.vaddress; qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", env->cp15.far_el[new_el]); From patchwork Thu Jun 9 09:04:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580243 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp598253max; Thu, 9 Jun 2022 02:24:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwMIbbZ9/SPlKEYxIkKexFUJdfBmqZmT1458BmPf4zrzXUPhAaizTjE1QdkRFjsfc4OD1QS X-Received: by 2002:a05:620a:44c4:b0:6a5:a827:d86c with SMTP id y4-20020a05620a44c400b006a5a827d86cmr26037302qkp.624.1654766655935; Thu, 09 Jun 2022 02:24:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654766655; cv=none; d=google.com; s=arc-20160816; b=SUHwu7vzIzt3I9d7cENANGmFl7sQZqihan9iuiIL+Z9aaLu1MMJ2Bf3PYa3PekQvns WxyNNlw30dU11+IhEgExmVUTJyMX+uV80CLP/Ug0cWth9lSTnoewHc4FYAboYsq6msa6 reZA23qum0Tq8ZPiQFxBesTxIxCLYvM4MTgUhuiPeG9hKfaVNUs02eAWPTUMjtTTbMfq 8xJsunlAXd36vXbmvoX/czswoYBAE6MbHvCsMU/S3LNkEE4Cfwh4J/QrgcPUFs5qQ35N PnIcgtUAdDVe7Cs6DCn3C5YGm1gqKB6lxMzvw4vqBkZW9NRpoSiqjU5+n4t3IgSk22xk EUZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=a3NPxQEfQiPYIU+CS5LV4PTQGOjBrNVkuFvlYXBD2EU=; b=mtL4mlzCKS9Sx+mEBGx9vziiVZLRC7qArnX+wm0u1E8u0DsFpGyCB7uQjhkhU3YROp xZwhTPPdGAjK3nPTTkk+KFWrmJf2vMuGvz1L6L27oDVQS47+SeMTLpaxMj2DVWJgqkRM 5r54clxeTYCDWtaow6hlXioX1rHbEyU3BqJKGzXd+d+e6BjdFmhkK9Zti5IoxPwYsV2m BglEKYjC33ctDGyjGDBAIxiTAnzT2ppHh7m4bNc+Ekp8YIZXV93pYeVbBIZgXLEBj3q1 uRa9A/XKAUHz9Ny7jOn8Zv8Gz+JQ1zdLu0zK8XPZVdORuhTrmsHPMDYQmb/ObLqFPd+d 9Naw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oPESQEkJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d18-20020a05620a241200b006a5cf2c1191si14793106qkn.231.2022.06.09.02.24.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:24:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oPESQEkJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35990 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEOl-00024F-Ed for patch@linaro.org; Thu, 09 Jun 2022 05:24:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39228) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE6v-0001P1-WB for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:50 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:55142) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE6s-0005w5-7u for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:49 -0400 Received: by mail-wm1-x32e.google.com with SMTP id n185so12105923wmn.4 for ; Thu, 09 Jun 2022 02:05:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=a3NPxQEfQiPYIU+CS5LV4PTQGOjBrNVkuFvlYXBD2EU=; b=oPESQEkJiXqw96JYsCxfSoPpocP0aqx+3VH1r+Ynns3kKgdLEX9GLzSRWlk8RKWGbL vNveqnGaCaAP7wNrJe0wzSTUPukJS5cs8PFLjcMledJuL85BAYx++nkATSz5cDecWber G/ENPwecldYz7lw5V7rIN6Hcc9a9FmVfJ9ZOA23YPPc05CdHTka8hvLfpQUd2716FYFQ XdkJJHVuAdJpnudQ/F+aOhjEgrQXIl/Fmv74plC4hd0sLLM8R23Y/elqJQ8BqGZCngHI 7dskp9ME51CtUwGrH7Va6x/fBnBDkA+x2PPCxG4Cp/+xGiecbZ2e681QZSa2oCyR9JEG ad9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a3NPxQEfQiPYIU+CS5LV4PTQGOjBrNVkuFvlYXBD2EU=; b=WxTiHT3z4oVUswb7vXNB/87oiXauzFCBMhwkPQoJBZe11yjMYBzmR7zavQf/WH+FfL PbAb8E/P8pFVnly38cjA4d/dXXm9XShvK53Q42TfIV+1vuraBwlNsBIIBTSuqvkziin2 7Gj9Z4+NscQO+EjNSXPWCGWN0CpB0Ub+3vhVXWWwkO5pQDVLkJt6s5QTTbJgplz4GQsb t1tLmUDEh5vZvTYOQ95I3aKR3E7f5MVAqRqGgFygTGUK68ooUZAGiRwge4u2LrvUBj8w bJbY8xqaz7MQBkSDcBtmk5VrA6DaSeJwU0kYBF8nOi1CFYbLaLMRnqHc2vQMRe3F41vK gkSg== X-Gm-Message-State: AOAM5325Ow43y5OLThXK8bIAF2/9RF+xQ6zjRRXQd3yWx7U44P8BeR30 USGO2XdH+NwJrSTQzLRJaeMdR5AyJV0gxw== X-Received: by 2002:a1c:4682:0:b0:39c:4459:6a84 with SMTP id t124-20020a1c4682000000b0039c44596a84mr2209884wma.167.1654765543794; Thu, 09 Jun 2022 02:05:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/55] Fix 'writeable' typos Date: Thu, 9 Jun 2022 10:04:45 +0100 Message-Id: <20220609090537.1971756-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have about 30 instances of the typo/variant spelling 'writeable', and over 500 of the more common 'writable'. Standardize on the latter. Change produced with: sed -i -e 's/\([Ww][Rr][Ii][Tt]\)[Ee]\([Aa][Bb][Ll][Ee]\)/\1\2/g' $(git grep -il writeable) and then hand-undoing the instance in linux-headers/linux/kvm.h. Most of these changes are in comments or documentation; the exceptions are: * a local variable in accel/hvf/hvf-accel-ops.c * a local variable in accel/kvm/kvm-all.c * the PMCR_WRITABLE_MASK macro in target/arm/internals.h * the EPT_VIOLATION_GPA_WRITABLE macro in target/i386/hvf/vmcs.h (which is never used anywhere) * the AR_TYPE_WRITABLE_MASK macro in target/i386/hvf/vmx.h (which is never used anywhere) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Weil Message-id: 20220505095015.2714666-1-peter.maydell@linaro.org --- docs/interop/vhost-user.rst | 2 +- docs/specs/vmgenid.txt | 4 ++-- hw/scsi/mfi.h | 2 +- target/arm/internals.h | 4 ++-- target/i386/hvf/vmcs.h | 2 +- target/i386/hvf/vmx.h | 2 +- accel/hvf/hvf-accel-ops.c | 4 ++-- accel/kvm/kvm-all.c | 4 ++-- accel/tcg/user-exec.c | 6 +++--- hw/acpi/ghes.c | 2 +- hw/intc/arm_gicv3_cpuif.c | 2 +- hw/intc/arm_gicv3_dist.c | 2 +- hw/intc/arm_gicv3_redist.c | 4 ++-- hw/intc/riscv_aclint.c | 2 +- hw/intc/riscv_aplic.c | 2 +- hw/pci/shpc.c | 2 +- hw/sparc64/sun4u_iommu.c | 2 +- hw/timer/sse-timer.c | 2 +- target/arm/gdbstub.c | 2 +- target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 4 ++-- target/i386/cpu-sysemu.c | 2 +- target/s390x/ioinst.c | 2 +- python/qemu/machine/machine.py | 2 +- tests/tcg/x86_64/system/boot.S | 2 +- 25 files changed, 34 insertions(+), 34 deletions(-) diff --git a/docs/interop/vhost-user.rst b/docs/interop/vhost-user.rst index a99ba4433ce..d7cf904f7fe 100644 --- a/docs/interop/vhost-user.rst +++ b/docs/interop/vhost-user.rst @@ -222,7 +222,7 @@ Virtio device config space :size: a 32-bit configuration space access size in bytes :flags: a 32-bit value: - - 0: Vhost front-end messages used for writeable fields + - 0: Vhost front-end messages used for writable fields - 1: Vhost front-end messages used for live migration :payload: Size bytes array holding the contents of the virtio diff --git a/docs/specs/vmgenid.txt b/docs/specs/vmgenid.txt index aa9f5186767..80ff69f31cc 100644 --- a/docs/specs/vmgenid.txt +++ b/docs/specs/vmgenid.txt @@ -153,7 +153,7 @@ change the contents of the memory at runtime, specifically when starting a backed-up or snapshotted image. In order to do this, QEMU must know the address that has been allocated. -The mechanism chosen for this memory sharing is writeable fw_cfg blobs. +The mechanism chosen for this memory sharing is writable fw_cfg blobs. These are data object that are visible to both QEMU and guests, and are addressable as sequential files. @@ -164,7 +164,7 @@ Two fw_cfg blobs are used in this case: /etc/vmgenid_guid - contains the actual VM Generation ID GUID - read-only to the guest /etc/vmgenid_addr - contains the address of the downloaded vmgenid blob - - writeable by the guest + - writable by the guest QEMU sends the following commands to the guest at startup: diff --git a/hw/scsi/mfi.h b/hw/scsi/mfi.h index e67a5c0b477..0b4ee53dfc0 100644 --- a/hw/scsi/mfi.h +++ b/hw/scsi/mfi.h @@ -633,7 +633,7 @@ struct mfi_ctrl_props { * metadata and user data * 1=5%, 2=10%, 3=15% and so on */ - uint8_t viewSpace; /* snapshot writeable VIEWs + uint8_t viewSpace; /* snapshot writable VIEWs * capacity as a % of source LD * capacity. 0=READ only * 1=5%, 2=10%, 3=15% and so on diff --git a/target/arm/internals.h b/target/arm/internals.h index b654bee4682..1e4887b2dd3 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1280,10 +1280,10 @@ enum MVEECIState { #define PMCRP 0x2 #define PMCRE 0x1 /* - * Mask of PMCR bits writeable by guest (not including WO bits like C, P, + * Mask of PMCR bits writable by guest (not including WO bits like C, P, * which can be written as 1 to trigger behaviour but which stay RAZ). */ -#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) +#define PMCR_WRITABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) #define PMXEVTYPER_P 0x80000000 #define PMXEVTYPER_U 0x40000000 diff --git a/target/i386/hvf/vmcs.h b/target/i386/hvf/vmcs.h index 42de7ebc3af..b4692f63f65 100644 --- a/target/i386/hvf/vmcs.h +++ b/target/i386/hvf/vmcs.h @@ -330,7 +330,7 @@ #define EPT_VIOLATION_DATA_WRITE (1UL << 1) #define EPT_VIOLATION_INST_FETCH (1UL << 2) #define EPT_VIOLATION_GPA_READABLE (1UL << 3) -#define EPT_VIOLATION_GPA_WRITEABLE (1UL << 4) +#define EPT_VIOLATION_GPA_WRITABLE (1UL << 4) #define EPT_VIOLATION_GPA_EXECUTABLE (1UL << 5) #define EPT_VIOLATION_GLA_VALID (1UL << 7) #define EPT_VIOLATION_XLAT_VALID (1UL << 8) diff --git a/target/i386/hvf/vmx.h b/target/i386/hvf/vmx.h index 573ddc33c07..fcd9a95e5b5 100644 --- a/target/i386/hvf/vmx.h +++ b/target/i386/hvf/vmx.h @@ -80,7 +80,7 @@ static inline uint64_t cap2ctrl(uint64_t cap, uint64_t ctrl) #define AR_TYPE_ACCESSES_MASK 1 #define AR_TYPE_READABLE_MASK (1 << 1) -#define AR_TYPE_WRITEABLE_MASK (1 << 2) +#define AR_TYPE_WRITABLE_MASK (1 << 2) #define AR_TYPE_CODE_MASK (1 << 3) #define AR_TYPE_MASK 0x0f #define AR_TYPE_BUSY_64_TSS 11 diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index a70e2eb375d..24913ca9c49 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -120,12 +120,12 @@ static void hvf_set_phys_mem(MemoryRegionSection *section, bool add) { hvf_slot *mem; MemoryRegion *area = section->mr; - bool writeable = !area->readonly && !area->rom_device; + bool writable = !area->readonly && !area->rom_device; hv_memory_flags_t flags; uint64_t page_size = qemu_real_host_page_size(); if (!memory_region_is_ram(area)) { - if (writeable) { + if (writable) { return; } else if (!memory_region_is_romd(area)) { /* diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 32e177bd26b..a4c4863f532 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -1346,13 +1346,13 @@ static void kvm_set_phys_mem(KVMMemoryListener *kml, KVMSlot *mem; int err; MemoryRegion *mr = section->mr; - bool writeable = !mr->readonly && !mr->rom_device; + bool writable = !mr->readonly && !mr->rom_device; hwaddr start_addr, size, slot_size, mr_offset; ram_addr_t ram_start_offset; void *ram; if (!memory_region_is_ram(mr)) { - if (writeable || !kvm_readonly_mem_allowed) { + if (writable || !kvm_readonly_mem_allowed) { return; } else if (!mr->romd_mode) { /* If the memory device is not in romd_mode, then we actually want diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index ac57324d4f6..20ada5472b4 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -101,10 +101,10 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write) * Return true if the write fault has been handled, and should be re-tried. * * Note that it is important that we don't call page_unprotect() unless - * this is really a "write to nonwriteable page" fault, because + * this is really a "write to nonwritable page" fault, because * page_unprotect() assumes that if it is called for an access to - * a page that's writeable this means we had two threads racing and - * another thread got there first and already made the page writeable; + * a page that's writable this means we had two threads racing and + * another thread got there first and already made the page writable; * so we will retry the access. If we were to call page_unprotect() * for some other kind of fault that should really be passed to the * guest, we'd end up in an infinite loop of retrying the faulting access. diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index 45d9a809cc9..e9511d9b8f7 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -249,7 +249,7 @@ void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *linker) for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) { /* * Initialize the value of read_ack_register to 1, so GHES can be - * writeable after (re)boot. + * writable after (re)boot. * ACPI 6.2: 18.3.2.8 Generic Hardware Error Source version 2 * (GHESv2 - Type 10) */ diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 8867e2e496f..8ca630e5ad1 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2047,7 +2047,7 @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_CBPR; } - /* The only bit stored in icc_ctlr_el3 which is writeable is EOIMODE_EL3: */ + /* The only bit stored in icc_ctlr_el3 which is writable is EOIMODE_EL3: */ mask = ICC_CTLR_EL3_EOIMODE_EL3; cs->icc_ctlr_el3 &= ~mask; diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index b9ed955e36b..eea03681187 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -611,7 +611,7 @@ static bool gicd_writel(GICv3State *s, hwaddr offset, if (value & mask & GICD_CTLR_DS) { /* We just set DS, so the ARE_NS and EnG1S bits are now RES0. * Note that this is a one-way transition because if DS is set - * then it's not writeable, so it can only go back to 0 with a + * then it's not writable, so it can only go back to 0 with a * hardware reset. */ s->gicd_ctlr &= ~(GICD_CTLR_EN_GRP1S | GICD_CTLR_ARE_NS); diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index c3d4cdd66b7..f1ecb2502b1 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -257,7 +257,7 @@ static void gicr_write_vpendbaser(GICv3CPUState *cs, uint64_t newval) /* * The DIRTY bit is read-only and for us is always zero; - * other fields are writeable. + * other fields are writable. */ newval &= R_GICR_VPENDBASER_INNERCACHE_MASK | R_GICR_VPENDBASER_SHAREABILITY_MASK | @@ -491,7 +491,7 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset, /* RAZ/WI for our implementation */ return MEMTX_OK; case GICR_WAKER: - /* Only the ProcessorSleep bit is writeable. When the guest sets + /* Only the ProcessorSleep bit is writable. When the guest sets * it it requests that we transition the channel between the * redistributor and the cpu interface to quiescent, and that * we set the ChildrenAsleep bit once the inteface has reached the diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index e6bceceefdb..e7942c4e5a3 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -463,7 +463,7 @@ static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp) /* Claim software interrupt bits */ for (i = 0; i < swi->num_harts; i++) { RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i)); - /* We don't claim mip.SSIP because it is writeable by software */ + /* We don't claim mip.SSIP because it is writable by software */ if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) { error_report("MSIP already claimed"); exit(1); diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index e7809fb6b2c..cfd007e629c 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -646,7 +646,7 @@ static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value, } if (addr == APLIC_DOMAINCFG) { - /* Only IE bit writeable at the moment */ + /* Only IE bit writable at the moment */ value &= APLIC_DOMAINCFG_IE; aplic->domaincfg = value; } else if ((APLIC_SOURCECFG_BASE <= addr) && diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c index 28e62174c42..f822f18b980 100644 --- a/hw/pci/shpc.c +++ b/hw/pci/shpc.c @@ -456,7 +456,7 @@ static int shpc_cap_add_config(PCIDevice *d, Error **errp) pci_set_byte(config + SHPC_CAP_CxP, 0); pci_set_long(config + SHPC_CAP_DWORD_DATA, 0); d->shpc->cap = config_offset; - /* Make dword select and data writeable. */ + /* Make dword select and data writable. */ pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff); pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff); return 0; diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c index 9178277f824..1c1dca712e3 100644 --- a/hw/sparc64/sun4u_iommu.c +++ b/hw/sparc64/sun4u_iommu.c @@ -165,7 +165,7 @@ static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryRegion *iommu, } if (tte & IOMMU_TTE_DATA_W) { - /* Writeable */ + /* Writable */ ret.perm = IOMMU_RW; } else { ret.perm = IOMMU_RO; diff --git a/hw/timer/sse-timer.c b/hw/timer/sse-timer.c index f959cb9d603..e92e83747d2 100644 --- a/hw/timer/sse-timer.c +++ b/hw/timer/sse-timer.c @@ -324,7 +324,7 @@ static void sse_timer_write(void *opaque, hwaddr offset, uint64_t value, { uint32_t old_ctl = s->cntp_aival_ctl; - /* EN bit is writeable; CLR bit is write-0-to-clear, write-1-ignored */ + /* EN bit is writable; CLR bit is write-0-to-clear, write-1-ignored */ s->cntp_aival_ctl &= ~R_CNTP_AIVAL_CTL_EN_MASK; s->cntp_aival_ctl |= value & R_CNTP_AIVAL_CTL_EN_MASK; if (!(value & R_CNTP_AIVAL_CTL_CLR_MASK)) { diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index f5b35cd55f0..2f806512d0a 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -118,7 +118,7 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) /* * Don't allow writing to XPSR.Exception as it can cause * a transition into or out of handler mode (it's not - * writeable via the MSR insn so this is a reasonable + * writable via the MSR insn so this is a reasonable * restriction). Other fields are safe to update. */ xpsr_write(env, tmp, ~XPSR_EXCP); diff --git a/target/arm/helper.c b/target/arm/helper.c index 7f2c14bea94..5727ead5e4c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1411,8 +1411,8 @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, } } - env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK; - env->cp15.c9_pmcr |= (value & PMCR_WRITEABLE_MASK); + env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; + env->cp15.c9_pmcr |= (value & PMCR_WRITABLE_MASK); pmu_op_finish(env); } diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 1fdc5eef92b..060aa0ccf4b 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -978,8 +978,8 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) } } - env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK; - env->cp15.c9_pmcr |= (val & PMCR_WRITEABLE_MASK); + env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; + env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK); pmu_op_finish(env); break; diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c index e254d8ba10f..a6f47b7d114 100644 --- a/target/i386/cpu-sysemu.c +++ b/target/i386/cpu-sysemu.c @@ -103,7 +103,7 @@ static void x86_cpu_to_dict(X86CPU *cpu, QDict *props) /* Convert CPU model data from X86CPU object to a property dictionary * that can recreate exactly the same CPU model, including every - * writeable QOM property. + * writable QOM property. */ static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props) { diff --git a/target/s390x/ioinst.c b/target/s390x/ioinst.c index bdae5090bc8..b12f18d346f 100644 --- a/target/s390x/ioinst.c +++ b/target/s390x/ioinst.c @@ -284,7 +284,7 @@ void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb, g_assert(!s390_is_pv()); /* * As operand exceptions have a lower priority than access exceptions, - * we check whether the memory area is writeable (injecting the + * we check whether the memory area is writable (injecting the * access execption if it is not) first. */ if (!s390_cpu_virt_mem_check_write(cpu, addr, ar, sizeof(schib))) { diff --git a/python/qemu/machine/machine.py b/python/qemu/machine/machine.py index 07ac5a710be..37191f433b2 100644 --- a/python/qemu/machine/machine.py +++ b/python/qemu/machine/machine.py @@ -495,7 +495,7 @@ def _early_cleanup(self) -> None: """ # If we keep the console socket open, we may deadlock waiting # for QEMU to exit, while QEMU is waiting for the socket to - # become writeable. + # become writable. if self._console_socket is not None: self._console_socket.close() self._console_socket = None diff --git a/tests/tcg/x86_64/system/boot.S b/tests/tcg/x86_64/system/boot.S index f8a2fcc8395..ed0f638406b 100644 --- a/tests/tcg/x86_64/system/boot.S +++ b/tests/tcg/x86_64/system/boot.S @@ -56,7 +56,7 @@ * * - `ebx`: contains the physical memory address where the loader has placed * the boot start info structure. - * - `cr0`: bit 0 (PE) must be set. All the other writeable bits are cleared. + * - `cr0`: bit 0 (PE) must be set. All the other writable bits are cleared. * - `cr4`: all bits are cleared. * - `cs `: must be a 32-bit read/execute code segment with a base of ‘0’ * and a limit of ‘0xFFFFFFFF’. The selector value is unspecified. From patchwork Thu Jun 9 09:04:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580242 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp597672max; Thu, 9 Jun 2022 02:23:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzr+cGzloqSkR2F/IxyPKODsMI/3qDhK5IYOcz/MRqiKBqDOPgCab7tai4tmWQriTDReYlv X-Received: by 2002:a05:6214:20a1:b0:42d:6f51:46e2 with SMTP id 1-20020a05621420a100b0042d6f5146e2mr84320225qvd.67.1654766599756; Thu, 09 Jun 2022 02:23:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654766599; cv=none; d=google.com; s=arc-20160816; b=0HsDkIKN6g9VtGBQTyc4UW74sZl0EWOuRrkprC/1DS9uLB629XhrJ65ra08gePfDUm B2AsXePTxLOejitT8xKgCf72v4aMsDynWr9ISRyn6xhmhB/x+2DNXjxsR9pNQKpTp5N+ rWJDIxUrdlH8oAl/7RgXf22ZJGpTBTQrgf9fR1Y3XOLBrjIuGMx2qDp1O9ggKkXfba8S +wsiZhrBtH9gpzX2gi/azfcMXnD5LBoJmbUjy4WDqe8iOjRx2BxynuZW4kJU9MtDTumg iwi4hZfEDWnIhf40VpQA+VjkIiYMKHCQZ5r7+7cGjUTLaaT3SNI51vIDLdv4hR/wSy2Z 0FHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+dO1GyIhjcUyBFfxTAYsXe9nSJnuFJi4sDNVk2x8YQE=; b=cpQgVEckMl6k9RGzDB5KoA06BqLEmBy4EgJ/1Qxw6L0DXCTV8RT4A9Y6+/maAXUVP8 L0UYCVhBZzHlzM2RqwcPGb0FTL9Wnmj/tnnDSOJenkCpE1DQXLGyqJ9a1csdAKZW4KDf D850mqhW7NYZK0lJOrUMr+MsC1bzCjzRvm8sVA7krIFvS4jq2smHOVjAxMc8m5qrwqvt dSO/ckebMWAbzdvam5mgfZ8nAd7v6rrUFTYZfSbzzqlvDCDuQx5/NOyJfEnbQYDvI2F3 nVuPs6C9k13lie7ExWRxP9+u2kcAzXLHk5COBTGOtB2TAcA+VPDBFPjoUlXRmg0R0tpn kRbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Frz2q1B/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j12-20020ac85c4c000000b00304ebe47326si6809452qtj.256.2022.06.09.02.23.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:23:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Frz2q1B/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzENr-0000Ts-77 for patch@linaro.org; Thu, 09 Jun 2022 05:23:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39204) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE6u-0001Oi-Mg for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:49 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:40587) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE6s-0005wl-7s for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:48 -0400 Received: by mail-wr1-x436.google.com with SMTP id k16so31477811wrg.7 for ; Thu, 09 Jun 2022 02:05:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+dO1GyIhjcUyBFfxTAYsXe9nSJnuFJi4sDNVk2x8YQE=; b=Frz2q1B/v2Oee7pz8TnO3n+7PUIVXhv2dUiRVEAKnrP6jDCaSphne0ycihroILnOBu tnvYlitbRS9xJxyx8rxYJBz4BJt5tGFb+yLnyiwMM/2bMABOZXrNbgLOmOsevOgD5wh9 qN5Qy+NtWuZS7OZZoOHueYL3cG61PRBe+Pn2svo8hYEX5aIIZRLCt5NBBmnY2e2VrYpA yeceSNTugCXcSRKMkp82ABVb0tS27bDRIC5o0pyLzKgIAHiLuqeXV6OumCa8dFx0XJYa B/PTtD/Mm4LFMjjMz/GGNwS0G1R8aIFknZ2x50DwBCb1/Bw4i6cZ7rXHROirA2nvO58x UWYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+dO1GyIhjcUyBFfxTAYsXe9nSJnuFJi4sDNVk2x8YQE=; b=4LESYi/OmcNZbZRc6XbnRLy2jLYrmdxildHlEPCOq/7OK6Mvpjb146d4Zgl8Rx+27n yh1u1JnnbcYWsHv0PDSpZdMuCpayyxgP1U/PzZYAgBgjo/BCccq8f1qa/m4UuLj0+Fw/ H8vbVkNddDe/Asog2/PRFCudFj7ej7994Z3csc7FOjzCOdBmQOdtDdh4l9kBukJmV1hd tGl6n8rp2lrYNoOg13uez8Cg/IAgltca6RMfKSGfa9ZM0v3PrFZ8Eav/5hBIxWlhAqDK GOp7VXGvba2SP4ZzDJQc+s99gffkhPjqSI6lPeYzFeRuujdtcS/EPMZdrchcvMBF/iCW G4Fw== X-Gm-Message-State: AOAM5313WkFVeDY0/HF8oX+r3Yzw1tJuzPVw8FEWPGhRO43i/k3qo6/j fcnG+t6IfsGX7BUtMoh3c0HMF4MJ2OSmIQ== X-Received: by 2002:adf:f90f:0:b0:20e:5fd4:5d06 with SMTP id b15-20020adff90f000000b0020e5fd45d06mr37549172wrr.371.1654765544711; Thu, 09 Jun 2022 02:05:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/55] xlnx_dp: fix the wrong register size Date: Thu, 9 Jun 2022 10:04:46 +0100 Message-Id: <20220609090537.1971756-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Frederic Konrad The core and the vblend registers size are wrong, they should respectively be 0x3B0 and 0x1E0 according to: https://www.xilinx.com/htmldocs/registers/ug1087/ug1087-zynq-ultrascale-registers.html. Let's fix that and use macros when creating the mmio region. Fixes: 58ac482a66d ("introduce xlnx-dp") Signed-off-by: Frederic Konrad Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis Message-id: 20220601172353.3220232-2-fkonrad@xilinx.com Signed-off-by: Peter Maydell --- include/hw/display/xlnx_dp.h | 9 +++++++-- hw/display/xlnx_dp.c | 17 ++++++++++------- 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/include/hw/display/xlnx_dp.h b/include/hw/display/xlnx_dp.h index 8ab4733bb85..1ef5a89ee74 100644 --- a/include/hw/display/xlnx_dp.h +++ b/include/hw/display/xlnx_dp.h @@ -39,10 +39,15 @@ #define AUD_CHBUF_MAX_DEPTH (32 * KiB) #define MAX_QEMU_BUFFER_SIZE (4 * KiB) -#define DP_CORE_REG_ARRAY_SIZE (0x3AF >> 2) +#define DP_CORE_REG_OFFSET (0x0000) +#define DP_CORE_REG_ARRAY_SIZE (0x3B0 >> 2) +#define DP_AVBUF_REG_OFFSET (0xB000) #define DP_AVBUF_REG_ARRAY_SIZE (0x238 >> 2) -#define DP_VBLEND_REG_ARRAY_SIZE (0x1DF >> 2) +#define DP_VBLEND_REG_OFFSET (0xA000) +#define DP_VBLEND_REG_ARRAY_SIZE (0x1E0 >> 2) +#define DP_AUDIO_REG_OFFSET (0xC000) #define DP_AUDIO_REG_ARRAY_SIZE (0x50 >> 2) +#define DP_CONTAINER_SIZE (0xC050) struct PixmanPlane { pixman_format_code_t format; diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c index 9bb781e3125..0378570459d 100644 --- a/hw/display/xlnx_dp.c +++ b/hw/display/xlnx_dp.c @@ -1219,19 +1219,22 @@ static void xlnx_dp_init(Object *obj) SysBusDevice *sbd = SYS_BUS_DEVICE(obj); XlnxDPState *s = XLNX_DP(obj); - memory_region_init(&s->container, obj, TYPE_XLNX_DP, 0xC050); + memory_region_init(&s->container, obj, TYPE_XLNX_DP, DP_CONTAINER_SIZE); memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XLNX_DP - ".core", 0x3AF); - memory_region_add_subregion(&s->container, 0x0000, &s->core_iomem); + ".core", sizeof(s->core_registers)); + memory_region_add_subregion(&s->container, DP_CORE_REG_OFFSET, + &s->core_iomem); memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XLNX_DP - ".v_blend", 0x1DF); - memory_region_add_subregion(&s->container, 0xA000, &s->vblend_iomem); + ".v_blend", sizeof(s->vblend_registers)); + memory_region_add_subregion(&s->container, DP_VBLEND_REG_OFFSET, + &s->vblend_iomem); memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XLNX_DP - ".av_buffer_manager", 0x238); - memory_region_add_subregion(&s->container, 0xB000, &s->avbufm_iomem); + ".av_buffer_manager", sizeof(s->avbufm_registers)); + memory_region_add_subregion(&s->container, DP_AVBUF_REG_OFFSET, + &s->avbufm_iomem); memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XLNX_DP ".audio", sizeof(s->audio_registers)); From patchwork Thu Jun 9 09:04:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580239 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp593659max; Thu, 9 Jun 2022 02:16:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyl2KaNJQvqO/ksQ1s2lvuMMEx2bqvdL7qMNnLojjxwdEwy56qG1ta53qpLJiOtZp9mkEiT X-Received: by 2002:a05:622a:47:b0:305:1ab:e52d with SMTP id y7-20020a05622a004700b0030501abe52dmr5585007qtw.688.1654766193340; Thu, 09 Jun 2022 02:16:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654766193; cv=none; d=google.com; s=arc-20160816; b=G9ff8IB1DgcNX82xXebsWaYw9hMe58yJiWKFhWyDf42Zwq8apu6rlV8ERL/Mm1L4MD tdDbUgixCErMLF7kZvOgwSaC9Z+xymb38LLChD65Se1v2W94l42FmmIZHJNgU1EY1h4w Y/SvVh1GeyntoVLKI8qCZ1Lo8jlfIuMHhHPtTgph14aX2ZPDpb/i+37ePXjCMJ2pXnPH 8hILRrhzF0MiyF5ODwaZz5oYOtCxaeUyClLMOyFpL8EbvP98UxK8dMoeDqwqo+dWcW2y inCfMSVyJtHrEymtKyOjV13YQofGAcMSbVLottSyJ7ecjzGmlVeusvJkGepf8ZioU/CS INEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=815PqLyO6+Q2xJdxQZlA76V7TTOTcj2SZ6F7/EiLTo0=; b=WZuIT1godUURVI5S5qsSvLrpzSLJjlcQ4BiJJzg19pZopB9MELWr3D5k9x9N1bzyal 2OcSu0KzWbm1MVdF1p5hL9eF2lV4gqSrFvGQ9tpjZz2t1J1+u7UifEz61SLCg8B5ZPKg 9swhSkfP/xHhX2B2Suru1nEInxrxhEaeSOFcUdZu/oXf4R/6iXr2wxGdBHHm6f/WWsp5 GrWuwS2r0m1fBcJAiWfFMikEZ6QwTgRSBoz/XPJi23gf/zNJY6LC//ERvPWQ2bBnWyDC jjsMXs+o5URtQEcVumTp5Srik2mLp0IbTBjgUZgoxKkb2w74Q6cpleh9gIPmZZ6jFc18 Hf0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zhjXtb+T; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 188-20020a3703c5000000b006a6a8f5d123si8104461qkd.577.2022.06.09.02.16.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:16:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zhjXtb+T; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55556 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEHI-00046M-QV for patch@linaro.org; Thu, 09 Jun 2022 05:16:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39222) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE6v-0001Ov-5P for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:50 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:46819) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE6t-0005xd-8W for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:48 -0400 Received: by mail-wr1-x435.google.com with SMTP id u8so27137707wrm.13 for ; Thu, 09 Jun 2022 02:05:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=815PqLyO6+Q2xJdxQZlA76V7TTOTcj2SZ6F7/EiLTo0=; b=zhjXtb+TnQRYQTfulh//qntXvpj6PXAqQQ2mn31XIawjv9WtorBmvM5GQFk3d0HTFI lah41ldMiLnJBAf42J7toiOBxje0NiRGKvgWmCgaP0+vZnoiGOu0A1j3tCOaW1DZ6Zlu bAoK0VjfPCGiYtPyG35jWUrrs4kufWN2nBzZyTXwFi62k6MLWA69pU/cwORT8S18ArjC mY0Vk0Oj52hvsc0CaDioKutP+25wr1sqfcoKYjduZkIRuGS9qm5NOXLhQQ6PES3yWLbs 108P+8VwvAzjwyBFMmor0jy5B+a3Eeboq1oDTxGUmL2G/2yV5wCS3r3gB8MyZaetMn5S oX7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=815PqLyO6+Q2xJdxQZlA76V7TTOTcj2SZ6F7/EiLTo0=; b=duFyBLNzIogCoaaWnVoqVmhlgyhtBhy74CL/PfyH8bQVGACc7XSLx+tvgLkYb9HZFj 1+Cv4pyjIjaX6uOU5WM/pU1GvKhURRNc0iEZLDFXenlCbqWJvCfMOiwM3FIDfn4UpbOI Rqu7hViM5dOM2rRJG4cMqRsQAKG7hLrRFcQ9WQmy2C2sJfjkTF5eCuAbVRNHAve4AzTw QqopOlramslBz9f82/nvjduuLsyCthBw+JzVvzvCytZGQBcCHtVWykN/dgaIPZFBpl67 dvmQfhJceALBy2/WvBcqehcQqJKklcPrOBknNFqSAgTC81eshgJEjzxAA5udgaLXmsVE 6wOw== X-Gm-Message-State: AOAM532jd3KpjEcYQ8mLdijmlogrFfHVZrx6DZmltcAggYTQBDvK/HJC CHfR8yslN6/9tIHHY+rIvKbsAJrdJwibvA== X-Received: by 2002:a5d:59a6:0:b0:218:49ff:2712 with SMTP id p6-20020a5d59a6000000b0021849ff2712mr16631531wrr.106.1654765545792; Thu, 09 Jun 2022 02:05:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/55] xlnx_dp: Introduce a vblank signal Date: Thu, 9 Jun 2022 10:04:47 +0100 Message-Id: <20220609090537.1971756-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Sai Pavan Boddu Add a periodic timer which raises vblank at a frequency of 30Hz. Note that this is a migration compatibility break for the xlnx-zcu102 board type. Signed-off-by: Sai Pavan Boddu Signed-off-by: Edgar E. Iglesias Signed-off-by: Frederic Konrad Acked-by: Alistair Francis Message-id: 20220601172353.3220232-3-fkonrad@xilinx.com Changes by fkonrad: - Switched to transaction-based ptimer API. - Added the DP_INT_VBLNK_START macro. Signed-off-by: Frederic Konrad [PMM: bump vmstate version, add commit message note about compat break] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/display/xlnx_dp.h | 3 +++ hw/display/xlnx_dp.c | 30 ++++++++++++++++++++++++++---- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/include/hw/display/xlnx_dp.h b/include/hw/display/xlnx_dp.h index 1ef5a89ee74..e86a87f235e 100644 --- a/include/hw/display/xlnx_dp.h +++ b/include/hw/display/xlnx_dp.h @@ -35,6 +35,7 @@ #include "hw/dma/xlnx_dpdma.h" #include "audio/audio.h" #include "qom/object.h" +#include "hw/ptimer.h" #define AUD_CHBUF_MAX_DEPTH (32 * KiB) #define MAX_QEMU_BUFFER_SIZE (4 * KiB) @@ -107,6 +108,8 @@ struct XlnxDPState { */ DPCDState *dpcd; I2CDDCState *edid; + + ptimer_state *vblank; }; #define TYPE_XLNX_DP "xlnx.v-dp" diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c index 0378570459d..ed856b596da 100644 --- a/hw/display/xlnx_dp.c +++ b/hw/display/xlnx_dp.c @@ -114,6 +114,7 @@ #define DP_TX_N_AUD (0x032C >> 2) #define DP_TX_AUDIO_EXT_DATA(n) ((0x0330 + 4 * n) >> 2) #define DP_INT_STATUS (0x03A0 >> 2) +#define DP_INT_VBLNK_START (1 << 13) #define DP_INT_MASK (0x03A4 >> 2) #define DP_INT_EN (0x03A8 >> 2) #define DP_INT_DS (0x03AC >> 2) @@ -260,7 +261,7 @@ typedef enum DPVideoFmt DPVideoFmt; static const VMStateDescription vmstate_dp = { .name = TYPE_XLNX_DP, - .version_id = 1, + .version_id = 2, .fields = (VMStateField[]){ VMSTATE_UINT32_ARRAY(core_registers, XlnxDPState, DP_CORE_REG_ARRAY_SIZE), @@ -270,10 +271,15 @@ static const VMStateDescription vmstate_dp = { DP_VBLEND_REG_ARRAY_SIZE), VMSTATE_UINT32_ARRAY(audio_registers, XlnxDPState, DP_AUDIO_REG_ARRAY_SIZE), + VMSTATE_PTIMER(vblank, XlnxDPState), VMSTATE_END_OF_LIST() } }; +#define DP_VBLANK_PTIMER_POLICY (PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | \ + PTIMER_POLICY_CONTINUOUS_TRIGGER | \ + PTIMER_POLICY_NO_IMMEDIATE_TRIGGER) + static void xlnx_dp_update_irq(XlnxDPState *s); static uint64_t xlnx_dp_audio_read(void *opaque, hwaddr offset, unsigned size) @@ -773,6 +779,13 @@ static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value, break; case DP_TRANSMITTER_ENABLE: s->core_registers[offset] = value & 0x01; + ptimer_transaction_begin(s->vblank); + if (value & 0x1) { + ptimer_run(s->vblank, 0); + } else { + ptimer_stop(s->vblank); + } + ptimer_transaction_commit(s->vblank); break; case DP_FORCE_SCRAMBLER_RESET: /* @@ -1177,9 +1190,6 @@ static void xlnx_dp_update_display(void *opaque) return; } - s->core_registers[DP_INT_STATUS] |= (1 << 13); - xlnx_dp_update_irq(s); - xlnx_dpdma_trigger_vsync_irq(s->dpdma); /* @@ -1275,6 +1285,14 @@ static void xlnx_dp_finalize(Object *obj) fifo8_destroy(&s->rx_fifo); } +static void vblank_hit(void *opaque) +{ + XlnxDPState *s = XLNX_DP(opaque); + + s->core_registers[DP_INT_STATUS] |= DP_INT_VBLNK_START; + xlnx_dp_update_irq(s); +} + static void xlnx_dp_realize(DeviceState *dev, Error **errp) { XlnxDPState *s = XLNX_DP(dev); @@ -1309,6 +1327,10 @@ static void xlnx_dp_realize(DeviceState *dev, Error **errp) &as); AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255); xlnx_dp_audio_activate(s); + s->vblank = ptimer_init(vblank_hit, s, DP_VBLANK_PTIMER_POLICY); + ptimer_transaction_begin(s->vblank); + ptimer_set_freq(s->vblank, 30); + ptimer_transaction_commit(s->vblank); } static void xlnx_dp_reset(DeviceState *dev) From patchwork Thu Jun 9 09:04:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580246 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp600595max; Thu, 9 Jun 2022 02:28:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzNKy9Q3oChkmP860x+o4jl3F8lxeiicjYkAvyiU/2uTw0Cr+Ee37EdZIsztTBLnguImdtG X-Received: by 2002:a05:6214:21c7:b0:464:4a7b:31e3 with SMTP id d7-20020a05621421c700b004644a7b31e3mr43262853qvh.44.1654766899862; Thu, 09 Jun 2022 02:28:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654766899; cv=none; d=google.com; s=arc-20160816; b=R+AgLQR+swLktAWTAiflNfGX5Xh/D9/ryqUewCfd5jJnVtFaG72RQ113XdMdrg9lua DfG6nsivwvnbJxYny1HUD9hBPZzZTAMBCYUhroXPLXg9Yr0LOJwW4JVX10cEINvBGyBD LSqXQSUieFo0r/U13qshpFpgu+DHDi+5Cy4PteIDgw7K8/yWv+Sk3vH012nFPsCm/few 377bmgEHTdxMu5/VHRYgi+hx+SwvJ4MDzVnBcjtsrGZ8liOfZAqFZ26lTt1XK5eF/MOo VTevbGOSTi3NvEN6b+7AWdV1+jA4IzJHXcJMpEGt1nhkhlYb6W5jMAZE+nLT7mm9C5ga QO8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=v6Qr9bE25ltpawAcQgSfkzrSpXI1MycLCG8XufyC2js=; b=QPEAIPlXDsgFSveaOBsUgksM6ic7PhjBDXmRbERGGWta9O4Uor1wOow+UmP/HlqPNh lPz9OEyqyMwB3b7Nkgs5psiBekmch7KRm9EsNCtAWCZfY4nLIffeU3BtelT7QWiGT0yI xLVpWUir5IBWfZriOunt5x0nds1LevRIwIM/AtU90vdqnvAhO4+mjimtE8aFzq3DHRTY 1QSIZPuEGMP8QkrOXQF5AAk57VNtGC0yn4rKd/BHxk3VU8lcwiwWVL2Dc/aUp2lQaUWw hxAzIZV4A1/GDvUsMFk3R9pkRVObaLTwzC9htgoCgCHyjzdv6AzTcBurOJU3GtZUxsWE +fRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bKA17z9Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e7-20020ac85dc7000000b00304fbd0186esi3271294qtx.467.2022.06.09.02.28.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:28:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bKA17z9Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42530 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzESh-0006eC-CO for patch@linaro.org; Thu, 09 Jun 2022 05:28:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39230) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE6w-0001P2-17 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:50 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:35634) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE6u-0005y0-1E for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:49 -0400 Received: by mail-wr1-x435.google.com with SMTP id a15so22952820wrh.2 for ; Thu, 09 Jun 2022 02:05:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=v6Qr9bE25ltpawAcQgSfkzrSpXI1MycLCG8XufyC2js=; b=bKA17z9ZQuuNoWzip2SlJ844IpZsf7Gb7WyDu2G8duXJxRa39m9YZpaDdkXr88xfpq atdfYK9AUTa1HRrK2IUb8jHK5yb/9+lu2XL9rNsRJshwdvyjiC/CzQzjwiKpqFR2nPFa bo/ngXemLA17moqfZ4GaJTcRK1aXA6qzE0IdHbJmfHKb/iB71sbeLjPLuPPiAyW9Gt8i OSgVRZxkTWCKSzqrh7qOrLWDjoh46Qn2Jdvopi5k38ceNrdNt81b3b56p2G5PGy5QUKl QxPTM72k1phA8vw+seTTC5AV772uMQZjeWDXlK6f+yehzOEuETcMT0vDH9FoQEF7DHQH ZpOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v6Qr9bE25ltpawAcQgSfkzrSpXI1MycLCG8XufyC2js=; b=DTc0/uVEiZQRyaVmMk4diVgpo5cdmXUFLhWJrMf5AEXdTOSKqLoTUnzal+rViSSpxK GuTQu20UfoJ40a6qDRmbppRXSxR9buLN81A7Gw2Yln5KTXdngLVFAgjzymRbhiB5AlXh /rfDtpka3L01kWA3J7xfbJlzcknsoWNxescNk1+Y8UEEjULxmhZQNzXf5NJON4jNE066 p+TYgO0lbzaRfec5Wov5oFIS7Xf5am9zpVUHNTvty9PIreWCwFYZiRGtYNG+g/YBAAq5 uqqE98Tqy6i8KrT6INARLRJgaVpHaFMylNAulBWizZDZ1cbsRuw1TM6z5Yyv8/GPtAbT PTHg== X-Gm-Message-State: AOAM531NuW3LmLFnP11IYLInNVHwvC3XLyfssjJuTpeVSzSxKcnhhjMF N5/HB9gel2kO6GebHf3R/29CASQ6wtQDBg== X-Received: by 2002:a05:6000:152:b0:216:160:2e60 with SMTP id r18-20020a056000015200b0021601602e60mr27313060wrx.663.1654765546692; Thu, 09 Jun 2022 02:05:46 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/55] xlnx_dp: Fix the interrupt disable logic Date: Thu, 9 Jun 2022 10:04:48 +0100 Message-Id: <20220609090537.1971756-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Sai Pavan Boddu Fix interrupt disable logic. Mask value 1 indicates that interrupts are disabled. Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias Signed-off-by: Frederic Konrad Acked-by: Alistair Francis Message-id: 20220601172353.3220232-4-fkonrad@xilinx.com Signed-off-by: Peter Maydell --- hw/display/xlnx_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c index ed856b596da..a071c818833 100644 --- a/hw/display/xlnx_dp.c +++ b/hw/display/xlnx_dp.c @@ -889,7 +889,7 @@ static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value, xlnx_dp_update_irq(s); break; case DP_INT_DS: - s->core_registers[DP_INT_MASK] |= ~value; + s->core_registers[DP_INT_MASK] |= value; xlnx_dp_update_irq(s); break; default: From patchwork Thu Jun 9 09:04:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580254 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp614085max; Thu, 9 Jun 2022 02:49:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzBt3updB0X7HkrfLq3cwdZyLIpKGXPWIMN1tJA0k1ZFfJ1/bDQv1VU0BhJDBHtd6TVPJVc X-Received: by 2002:a37:581:0:b0:6a6:c190:deb5 with SMTP id 123-20020a370581000000b006a6c190deb5mr12817357qkf.358.1654768178061; Thu, 09 Jun 2022 02:49:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654768178; cv=none; d=google.com; s=arc-20160816; b=t77IGLNL1SUXTTBzn934+ww9ogGr1z7pshml2r9Z+SwdOh8/jyRg5OVhXGXHDbj3aL fLgDAd+b0ybiU90wL9gm9WFsGBITha9bp6yS/wPPg0N4n3zrVbIvfOG3k7IpyKnv4q7U C2CFOHgw4chHGwVDPF6gDo+smGSAANmD88k8v07Sn/1V68r0sm/MS2kfFLxj/CVyCYvC LgGG4apcsYWh7FCiAW5GO2ct2W6hFa+2F/fBGLTDe+mEmSgIh5BBPB7KrDMLUEKMwjEs oGBJVtEuhgz2dwq5fJ1ZD4fF0ag6iGFFfpROD0iLte9Scrv703Au0ao6s2WNFSrAiAJy b4qQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PJOPhcXmy6choxCt00mzWvMSiOwf3GdqrbZyGZMGfOM=; b=INgU+CZUYywb2Wt0+HsHk5Qk3VPI3kmBXmQmvoAmJJnBVOUSKquDhX0fYgD2dsdJ3+ tUeoJ7tq0hoAiMq35H5MBahJKfdpuRWCbMaMnTCdkwo2VN4vXm1GLRxjOv8bd69bTA8C 0Xe8Ph+521KcVgbJDy2ue68NhUHvepaB4TN3+TradOJpTHusYLmMhz9ExMC891CcnHkH KWZw2mUdnUgW/j0OjAKY5iEXC8WZMfarN4CX8gbeKWnHbxayLB9NciCCEmlMGP/3YvPM z9d7eY0MqdddfFn+jhjyrFgp8OY6CQNXgK/84m+0tA0hGCE9iFH/MaWeYqWZc10ruJ/X h1jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BNaNygxB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 5-20020a05621420a500b0046b8e864d34si6691873qvd.318.2022.06.09.02.49.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:49:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BNaNygxB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59920 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEnJ-0002ZS-Hy for patch@linaro.org; Thu, 09 Jun 2022 05:49:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39270) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE6z-0001Rn-Je for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:54 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:38492) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE6u-0005vV-D4 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:53 -0400 Received: by mail-wr1-x430.google.com with SMTP id v14so5217169wra.5 for ; Thu, 09 Jun 2022 02:05:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PJOPhcXmy6choxCt00mzWvMSiOwf3GdqrbZyGZMGfOM=; b=BNaNygxBqSsuoPvknhhIgp6zcO0xaKmmL202ENURdiYY/5o9X497A5P6VE2VN7phsg TWu63cfcVsP0OoEWXy9obQOtwwsQmxub+wjeoeaykhNsSf599VZc7cUETPcmV15Cr7Um BgN3LpFGLCKTJJjjf2LdLrOQu0lyvB0XwymiI1i2RKNdCZIw34hfI+pW/KIMG2K3w3xR AE1PgurOVj/S1a9TnUZJOehC6+7HjPu8Cswln9htodD1AteF6dZbAVwF7mwsaxk2+90s hu9jZLSXA7jg4vg/vy3zsN6KG/qjz7KNRbXC14kJxv9V0u4qPqTmiAcskkllPhhAgHuR NZGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PJOPhcXmy6choxCt00mzWvMSiOwf3GdqrbZyGZMGfOM=; b=O7YAh9oD3h1JmjpdKMIme+gtmVRGPQItZNuhMmLuU9OXh5+DVzjxaRvwdrJoNTvL/g PUcZQdk4bDw/JAUW++d03H07QM5BNQGA1YS+nptYjxXNMrf27CDWy1deS4Ec8TDCdHrO +QALoSfSqvQtQeiYoGLuIQloQhH/urMXjGo1XiIOcwSPVneAtpM+0bePw7ZKu0hQE+Ij xIK1q1eYqPAQZRKh2croKPYR8XTEX1oXgrebl74MiQRfz0vUERKifVOFgjuQ5ocS+Xpm lHeWE0hMh2w//6OeCnCywUJpLYIANkHl8xf/TQsYr6zcruLmffJvQ0LtilabxyKsEix8 iScg== X-Gm-Message-State: AOAM533d4/ntD6n0clBy1bYYqkmElCI+JcVw1Y7V/X3Rx+f1yyxjcaDZ m8F0Os+R3dAeTR5957bkiTrx8WJGdRG3Mw== X-Received: by 2002:adf:ed82:0:b0:213:1315:1dbb with SMTP id c2-20020adfed82000000b0021313151dbbmr35315784wro.484.1654765547694; Thu, 09 Jun 2022 02:05:47 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/55] xlnx-zynqmp: fix the irq mapping for the display port and its dma Date: Thu, 9 Jun 2022 10:04:49 +0100 Message-Id: <20220609090537.1971756-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Frederic Konrad When the display port has been initially implemented the device driver wasn't using interrupts. Now that the display port driver waits for vblank interrupt it has been noticed that the irq mapping is wrong. So use the value from the linux device tree and the ultrascale+ reference manual. Signed-off-by: Frederic Konrad Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis Message-id: 20220601172353.3220232-5-fkonrad@xilinx.com [PMM: refold lines in commit message] Signed-off-by: Peter Maydell --- hw/arm/xlnx-zynqmp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 375309e68eb..383e177a001 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -60,10 +60,10 @@ #define SERDES_SIZE 0x20000 #define DP_ADDR 0xfd4a0000 -#define DP_IRQ 113 +#define DP_IRQ 0x77 #define DPDMA_ADDR 0xfd4c0000 -#define DPDMA_IRQ 116 +#define DPDMA_IRQ 0x7a #define APU_ADDR 0xfd5c0000 #define APU_IRQ 153 From patchwork Thu Jun 9 09:04:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580250 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp606714max; Thu, 9 Jun 2022 02:37:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzqZWE0TKLkto/E7k4gU/tVy4IEziKrIBekO8c6NA0z+qRpLh+abA2TbKxp+BSMEWYSJKX8 X-Received: by 2002:a05:622a:216:b0:304:b3e7:5a7e with SMTP id b22-20020a05622a021600b00304b3e75a7emr31276657qtx.270.1654767456519; Thu, 09 Jun 2022 02:37:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654767456; cv=none; d=google.com; s=arc-20160816; b=FzRGT2kfphfqXBXGCvEpCY280SU+RJe1kwhFFImcA8aWrb2l7cSaXSmPZwKMg1wHSQ FRfOt+A/kPJ0+tz7hKvF9FOCmidkf7x+dugG86A5fEIsv3a1TUkEukUY6Wf88DPyB1fH HmwLxbrrZiKv/agk6mTaFWxP9kR3HPXS2M45wNjwpfBDtEqtYQo3cBMl+9Dyju5AFUlR pExW1Jor7+6cGTt6C6C1AzlQYL4rHiIOHCJ9zczSFjf8EvUid/gKmmBwfYyPdIbTke6G j9o+kdMKUyJewnNYwSahvWIDj+Uep7snh7SMfnTQKNxZiC9KFPIpKtsFb51XDOTIqf+G DNvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9eBXb6ngArhkEwA5Ae/7R9RnXAQ3z1Rjo8kM5NbQegY=; b=aow9ASYfCtydoCL0tm9SBpQFoQjjy9i1GOP0UER8bWX6MkbZJ8gi3zFiT8lvXW36rb jauAV9IMZEOkUg+21Kc0/ND1KKVd3FSQFrZFXvZPEoESMVbiTwfN1CkJJRuZ1Nnc0kYI 8xR2dZAFi/HsAi8ZQdQQUoVT/S0YXnSL41vu9RsT/Q5350qhjByQuzh0cq1zjPYP53qA imHTqdbsR9HQwmq/dN+DVas9GdZf6scSAjNEbrfgPj8quOjwWxDc6v3Cmw+hLiQozCYW o87lpJB8boUn5CWpaaRFeXEYhyZSmCXT30qTBH2hIeq3xo4VLleJp+QPOk+5zAiAgop6 9Z4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H9lQwEXw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k21-20020a05620a415500b006a042cb4ce7si8497060qko.8.2022.06.09.02.37.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:37:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H9lQwEXw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51080 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEbf-0004L0-VX for patch@linaro.org; Thu, 09 Jun 2022 05:37:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39262) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE6y-0001QL-2U for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:53 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:34742) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE6w-0005zr-0x for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:51 -0400 Received: by mail-wr1-x42b.google.com with SMTP id q26so21096176wra.1 for ; Thu, 09 Jun 2022 02:05:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9eBXb6ngArhkEwA5Ae/7R9RnXAQ3z1Rjo8kM5NbQegY=; b=H9lQwEXwCP30cwktaIsUzRorw2Il2qxYXPUFGwblgwdk3dj+PSElrU8nCdlgKx23u+ Os9SQ7N5bDfzMldoJvFeSQBg8MolOg/Ny6pbCado5/9+X1D/TZbSUJMgn9KmtKJbX1x7 w0L6itWjyf2Ghwy+ATluvPas7KgpvVaKFMevEQlIy5CCjq1IaMrAMSNMyedMOhn1GpgF 35Lx72No5uoKGCiPAN0Rw29lIThS199FbGL6G4TydYLB/SLy3B8UCQr/dt14MuFPcUN6 eSmErW4O1AdNN67B3yzn8GOtp4+JVx76pYXSJEw3ve90HA66t/mcSelm0swX6nDZuTCc 6N2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9eBXb6ngArhkEwA5Ae/7R9RnXAQ3z1Rjo8kM5NbQegY=; b=lLWtyfs0/7cOAbBgbdhk6vqYJf2X7bT25pbMXrJju01c8kjQjIa7tUMSzSKOC1kEFx 2rQuNLlm2sGVJBNqDDFS/+Bw1dBiMfOg6kZVv1eF/wLQv5Z1+NTOQ2OarBk/0lpT7FJO Z0z+RKIphAo4jbk6GC9AlnOv4Hoqn1E/OA24sH6jAGxvzmxTt69vZYdP0Ewh+fgkfv4E f82rnbKWGGF4yhLFlJLZzACg6Zw20d5oLIW5CR2bXTp7rRS812Ziqs81Hd2Whdt8DlXc OAIm0cSkyrG2Dig/K545huveAtdwidm32jm4hucAxjyOe+8SzyKwC8C6PVH1X+Q3sgZi O++A== X-Gm-Message-State: AOAM531sCOoYeMFfvJTHGYJmHv1O0xe6KK0z6SRpHnak4WpUXrueqm/t 4k4T52Ndf3Q7Tg/6uVLKBgdhbC1ObXuKvw== X-Received: by 2002:a5d:67c2:0:b0:215:7a0f:71f9 with SMTP id n2-20020a5d67c2000000b002157a0f71f9mr30971956wrw.486.1654765548590; Thu, 09 Jun 2022 02:05:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/55] target/arm: Move stage_1_mmu_idx decl to internals.h Date: Thu, 9 Jun 2022 10:04:50 +0100 Message-Id: <20220609090537.1971756-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Move the decl from ptw.h to internals.h. Provide an inline version for user-only, just as we do for arm_stage1_mmu_idx. Move an endif down to make the definition in helper.c be system only. Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/internals.h | 5 +++++ target/arm/helper.c | 5 ++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1e4887b2dd3..049edce946c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -979,11 +979,16 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env); * Return the ARMMMUIdx for the stage1 traversal for the current regime. */ #ifdef CONFIG_USER_ONLY +static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) +{ + return ARMMMUIdx_Stage1_E0; +} static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) { return ARMMMUIdx_Stage1_E0; } #else +ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx); ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 5727ead5e4c..829b660db92 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10517,12 +10517,10 @@ static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, } } -#endif /* !CONFIG_USER_ONLY */ - /* Convert a possible stage1+2 MMU index into the appropriate * stage 1 MMU index */ -static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) +ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_SE10_0: @@ -10541,6 +10539,7 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) return mmu_idx; } } +#endif /* !CONFIG_USER_ONLY */ /* Return true if the translation regime is using LPAE format page tables */ static inline bool regime_using_lpae_format(CPUARMState *env, From patchwork Thu Jun 9 09:04:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580258 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp619371max; Thu, 9 Jun 2022 02:57:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwRPU94ntNrhrMitIhcwkKLvg482dHhXRuVFyA0LznXlOIqhSttW8Oc6Hqom/jNedyHWgaA X-Received: by 2002:a05:620a:2847:b0:67d:2bad:422f with SMTP id h7-20020a05620a284700b0067d2bad422fmr25883530qkp.559.1654768654284; Thu, 09 Jun 2022 02:57:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654768654; cv=none; d=google.com; s=arc-20160816; b=sL7/OQjrkRmXZ8olSKPRbiPDWi8Tv+a4ngkrnTO7GvoGDDN9nJHJqjhdZJpP9Zk0zQ WrYDnysSrJJVnUrq69iZdrChOdS90yi6TlMLl4zB8r5tF2qqhO+CCnMgnNdwzgaz6At3 vM68eEJnoyhp0L67RiZNv+khgc9fs5NZctCZ+bm8StwzMd449SrOGcUeK9bf+HpQSirv 67lReP1MhmC+QCUkIShW2FPXq9UM/JlwV/84V6OpC5tiJd6QH/SRzNLpspkdoX9Ni3xa 7WEoxMIzytNDiQpqnEPdVZ7KAezp7BZlj3E2QBA2MsDfXf3H/+/m7UoikIbAd3FIQOz3 2fBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hc5zkvCsi6gg6RtC6i+txFH2JRDjXFdVtwnnnFfRk5Y=; b=Ui8u9D315m6BVzTo6g4lqoCEdMcQunVxZraqhdGnXmiUHxKQrcHlv/LOHpoKOyEY5J iv5u/Zdo4lgsBrHlWdKVHXVLu4QedolyeukiV25u27SghT0cIUmZ1Hg6GyYCrg5UsbAl QLH9aBsILCAZD6YgTxjqATXtJA+UL89Rz/PVq9Pixe/0nS+i5aYoVz/4X+8C2vMjD9HY jGG5mYgLcLyTVvJp6dpCarHUgcwicxPBOu1LlYOVzuLMnUO7Yh8e0zDb/EPoagIAkvk3 mPcHlcvYHS2g4sW097LuPSw1X4aci0q6puEvqCIKSHf4W6UaIzsMec+sh280s8qUjk2k +Jcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=baAdG3yc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j19-20020a05620a289300b006a37a7632cesi1239432qkp.549.2022.06.09.02.57.34 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:57:34 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=baAdG3yc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEuz-0000m8-Nj for patch@linaro.org; Thu, 09 Jun 2022 05:57:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39302) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE71-0001TV-AJ for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:55 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:40587) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE6x-0005wl-R3 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:55 -0400 Received: by mail-wr1-x436.google.com with SMTP id k16so31477811wrg.7 for ; Thu, 09 Jun 2022 02:05:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hc5zkvCsi6gg6RtC6i+txFH2JRDjXFdVtwnnnFfRk5Y=; b=baAdG3ycirS9ozBNAcguePoPK+4apMDZ9WHZkHthEKipv9a73/Z3BWfsJHFh07Bvo/ rBFcvaKn5x0vOXIZ+F8O5yFkNV1EboizS3PHIm4AdJj1YOlgfga9/K31YFiuapxiGIrK rOMKM4jm/xRTiKFqdVbWev4Jb9Zel5yoQV/8YPfWAIm066L6TvU03dFTauIjjIZC3Jy5 gRGYGWFcng84FuWUG9M2ntTd5NOkqYLgMmnDVoBpgNV0QUKOK5JxZv2gB9LRvRUxZDjg HNADpRNRItqqN1XObU0wXMyetK3jIJ3nJ9YlhW3CLbO6z99AzPcGX1sbIBBqf79F+q1Z nGsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hc5zkvCsi6gg6RtC6i+txFH2JRDjXFdVtwnnnFfRk5Y=; b=qd6lmkx/83I/01CklAQ7yVgoXXDXY8gnYOPI66AshmqQukba+r0rY37YmGrsvI0HJS 4QHMBd5CWmr9+P7WNW126mxcaIqdjxtMbqdg8itCmOQ1Os4NjXVGGUhHSFvXnvW2F8c+ 7uHqBzwkOA275tjP3eYbLy/bDQJ3nhj6j1+Dv2T/sz9eXF6Qfcx7XQnsYLrgaXmRmjse mWoGx94vSocU2DVpOxf9wgTsa1QbRdF7cWYRzQIobc9x1ayMxG5/gka51wOx2H2Fj35L JGYAYtSLTQEqoxhkyca2a46F30nY+FLFYzc/8tUd+GLYEXxjGV2M2nlICNxtUlCOvyGt T/Xg== X-Gm-Message-State: AOAM531imTqL5+dbtAkvh+jx6YAoDtlky5+ytPTXA7irDNLXOySYU20J 5lKtAnk6leITyL7406s6KMHiOGfbVCrDGg== X-Received: by 2002:adf:f90f:0:b0:20e:5fd4:5d06 with SMTP id b15-20020adff90f000000b0020e5fd45d06mr37549597wrr.371.1654765549972; Thu, 09 Jun 2022 02:05:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/55] target/arm: Move get_phys_addr to ptw.c Date: Thu, 9 Jun 2022 10:04:51 +0100 Message-Id: <20220609090537.1971756-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Begin moving all of the page table walking functions out of helper.c, starting with get_phys_addr(). Create a temporary header file, "ptw.h", in which to share declarations between the two C files while we are moving functions. Move a few declarations to "internals.h", which will remain used by multiple C files. Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/internals.h | 18 ++- target/arm/ptw.h | 51 ++++++ target/arm/helper.c | 344 +++++------------------------------------ target/arm/ptw.c | 267 ++++++++++++++++++++++++++++++++ target/arm/meson.build | 1 + 5 files changed, 372 insertions(+), 309 deletions(-) create mode 100644 target/arm/ptw.h create mode 100644 target/arm/ptw.c diff --git a/target/arm/internals.h b/target/arm/internals.h index 049edce946c..1d83146d565 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -613,8 +613,13 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); -/* Return true if the stage 1 translation regime is using LPAE format page - * tables */ +/* Return true if the translation regime is using LPAE format page tables */ +bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); + +/* + * Return true if the stage 1 translation regime is using LPAE + * format page tables + */ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); /* Raise a data fault alignment exception for the specified virtual address */ @@ -777,6 +782,12 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) } } +/* Return the SCTLR value which controls this address translation regime */ +static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; +} + /* Return the TCR controlling this translation regime */ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { @@ -1095,6 +1106,9 @@ typedef struct ARMVAParameters { ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); +int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); +int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx); + static inline int exception_target_el(CPUARMState *env) { int target_el = MAX(1, arm_current_el(env)); diff --git a/target/arm/ptw.h b/target/arm/ptw.h new file mode 100644 index 00000000000..e2023ae7508 --- /dev/null +++ b/target/arm/ptw.h @@ -0,0 +1,51 @@ +/* + * ARM page table walking. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TARGET_ARM_PTW_H +#define TARGET_ARM_PTW_H + +#ifndef CONFIG_USER_ONLY + +bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx); +bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx); +ARMCacheAttrs combine_cacheattrs(CPUARMState *env, + ARMCacheAttrs s1, ARMCacheAttrs s2); + +bool get_phys_addr_v5(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi); +bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, int *prot, + ARMMMUFaultInfo *fi); +bool get_phys_addr_v6(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, ARMMMUFaultInfo *fi); +bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi); +bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *txattrs, + int *prot, target_ulong *page_size, + ARMMMUFaultInfo *fi); +bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + bool s1_is_el0, + hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, + target_ulong *page_size_ptr, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) + __attribute__((nonnull)); + +#endif /* !CONFIG_USER_ONLY */ +#endif /* TARGET_ARM_PTW_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 829b660db92..3ffd122178d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -37,22 +37,11 @@ #include "semihosting/common-semi.h" #endif #include "cpregs.h" +#include "ptw.h" #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ -#ifndef CONFIG_USER_ONLY - -static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool s1_is_el0, - hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, - target_ulong *page_size_ptr, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) - __attribute__((nonnull)); -#endif - static void switch_mode(CPUARMState *env, int mode); -static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -10440,17 +10429,10 @@ uint64_t arm_sctlr(CPUARMState *env, int el) return env->cp15.sctlr_el[el]; } -/* Return the SCTLR value which controls this address translation regime */ -static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; -} - #ifndef CONFIG_USER_ONLY /* Return true if the specified stage of address translation is disabled */ -static inline bool regime_translation_disabled(CPUARMState *env, - ARMMMUIdx mmu_idx) +bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) { uint64_t hcr_el2; @@ -10542,8 +10524,7 @@ ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) #endif /* !CONFIG_USER_ONLY */ /* Return true if the translation regime is using LPAE format page tables */ -static inline bool regime_using_lpae_format(CPUARMState *env, - ARMMMUIdx mmu_idx) +bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) { int el = regime_el(env, mmu_idx); if (el == 2 || arm_el_is_aa64(env, el)) { @@ -10567,7 +10548,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) } #ifndef CONFIG_USER_ONLY -static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) +bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_SE10_0: @@ -10959,11 +10940,11 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, return 0; } -static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi) +bool get_phys_addr_v5(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); int level = 1; @@ -11081,10 +11062,10 @@ do_fault: return true; } -static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, ARMMMUFaultInfo *fi) +bool get_phys_addr_v6(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); ARMCPU *cpu = env_archcpu(env); @@ -11360,7 +11341,7 @@ unsigned int arm_pamax(ARMCPU *cpu) return pamax_map[parange]; } -static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) +int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) { if (regime_has_2_ranges(mmu_idx)) { return extract64(tcr, 37, 2); @@ -11372,7 +11353,7 @@ static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) } } -static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) +int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) { if (regime_has_2_ranges(mmu_idx)) { return extract64(tcr, 51, 2); @@ -11602,12 +11583,12 @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, * @fi: set to fault info if the translation fails * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes */ -static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool s1_is_el0, - hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, - target_ulong *page_size_ptr, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) +bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + bool s1_is_el0, + hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, + target_ulong *page_size_ptr, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { ARMCPU *cpu = env_archcpu(env); CPUState *cs = CPU(cpu); @@ -12055,11 +12036,11 @@ static inline bool m_is_system_region(CPUARMState *env, uint32_t address) return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; } -static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi) +bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); int n; @@ -12501,11 +12482,11 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, } -static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, target_ulong *page_size, - ARMMMUFaultInfo *fi) +bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *txattrs, + int *prot, target_ulong *page_size, + ARMMMUFaultInfo *fi) { uint32_t secure = regime_is_secure(env, mmu_idx); V8M_SAttributes sattrs = {}; @@ -12575,10 +12556,10 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, return ret; } -static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - ARMMMUFaultInfo *fi) +bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, int *prot, + ARMMMUFaultInfo *fi) { int n; uint32_t mask; @@ -12795,8 +12776,8 @@ static uint8_t combined_attrs_fwb(CPUARMState *env, * @s1: Attributes from stage 1 walk * @s2: Attributes from stage 2 walk */ -static ARMCacheAttrs combine_cacheattrs(CPUARMState *env, - ARMCacheAttrs s1, ARMCacheAttrs s2) +ARMCacheAttrs combine_cacheattrs(CPUARMState *env, + ARMCacheAttrs s1, ARMCacheAttrs s2) { ARMCacheAttrs ret; bool tagged = false; @@ -12848,256 +12829,6 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env, return ret; } - -/* get_phys_addr - get the physical address for this virtual address - * - * Find the physical address corresponding to the given virtual address, - * by doing a translation table walk on MMU based systems or using the - * MPU state on MPU based systems. - * - * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, - * prot and page_size may not be filled in, and the populated fsr value provides - * information on why the translation aborted, in the format of a - * DFSR/IFSR fault register, with the following caveats: - * * we honour the short vs long DFSR format differences. - * * the WnR bit is never set (the caller must do this). - * * for PSMAv5 based systems we don't bother to return a full FSR format - * value. - * - * @env: CPUARMState - * @address: virtual address to get physical address for - * @access_type: 0 for read, 1 for write, 2 for execute - * @mmu_idx: MMU index indicating required translation regime - * @phys_ptr: set to the physical address corresponding to the virtual address - * @attrs: set to the memory transaction attributes to use - * @prot: set to the permissions for the page containing phys_ptr - * @page_size: set to the size of the page containing phys_ptr - * @fi: set to fault info if the translation fails - * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes - */ -bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) -{ - ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); - - if (mmu_idx != s1_mmu_idx) { - /* Call ourselves recursively to do the stage 1 and then stage 2 - * translations if mmu_idx is a two-stage regime. - */ - if (arm_feature(env, ARM_FEATURE_EL2)) { - hwaddr ipa; - int s2_prot; - int ret; - bool ipa_secure; - ARMCacheAttrs cacheattrs2 = {}; - ARMMMUIdx s2_mmu_idx; - bool is_el0; - - ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa, - attrs, prot, page_size, fi, cacheattrs); - - /* If S1 fails or S2 is disabled, return early. */ - if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) { - *phys_ptr = ipa; - return ret; - } - - ipa_secure = attrs->secure; - if (arm_is_secure_below_el3(env)) { - if (ipa_secure) { - attrs->secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); - } else { - attrs->secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); - } - } else { - assert(!ipa_secure); - } - - s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; - is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0; - - /* S1 is done. Now do S2 translation. */ - ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0, - phys_ptr, attrs, &s2_prot, - page_size, fi, &cacheattrs2); - fi->s2addr = ipa; - /* Combine the S1 and S2 perms. */ - *prot &= s2_prot; - - /* If S2 fails, return early. */ - if (ret) { - return ret; - } - - /* Combine the S1 and S2 cache attributes. */ - if (arm_hcr_el2_eff(env) & HCR_DC) { - /* - * HCR.DC forces the first stage attributes to - * Normal Non-Shareable, - * Inner Write-Back Read-Allocate Write-Allocate, - * Outer Write-Back Read-Allocate Write-Allocate. - * Do not overwrite Tagged within attrs. - */ - if (cacheattrs->attrs != 0xf0) { - cacheattrs->attrs = 0xff; - } - cacheattrs->shareability = 0; - } - *cacheattrs = combine_cacheattrs(env, *cacheattrs, cacheattrs2); - - /* Check if IPA translates to secure or non-secure PA space. */ - if (arm_is_secure_below_el3(env)) { - if (ipa_secure) { - attrs->secure = - !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW)); - } else { - attrs->secure = - !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_NSW)) - || (env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW))); - } - } - return 0; - } else { - /* - * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. - */ - mmu_idx = stage_1_mmu_idx(mmu_idx); - } - } - - /* The page table entries may downgrade secure to non-secure, but - * cannot upgrade an non-secure translation regime's attributes - * to secure. - */ - attrs->secure = regime_is_secure(env, mmu_idx); - attrs->user = regime_is_user(env, mmu_idx); - - /* Fast Context Switch Extension. This doesn't exist at all in v8. - * In v7 and earlier it affects all stage 1 translations. - */ - if (address < 0x02000000 && mmu_idx != ARMMMUIdx_Stage2 - && !arm_feature(env, ARM_FEATURE_V8)) { - if (regime_el(env, mmu_idx) == 3) { - address += env->cp15.fcseidr_s; - } else { - address += env->cp15.fcseidr_ns; - } - } - - if (arm_feature(env, ARM_FEATURE_PMSA)) { - bool ret; - *page_size = TARGET_PAGE_SIZE; - - if (arm_feature(env, ARM_FEATURE_V8)) { - /* PMSAv8 */ - ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, - phys_ptr, attrs, prot, page_size, fi); - } else if (arm_feature(env, ARM_FEATURE_V7)) { - /* PMSAv7 */ - ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, - phys_ptr, prot, page_size, fi); - } else { - /* Pre-v7 MPU */ - ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, - phys_ptr, prot, fi); - } - qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 - " mmu_idx %u -> %s (prot %c%c%c)\n", - access_type == MMU_DATA_LOAD ? "reading" : - (access_type == MMU_DATA_STORE ? "writing" : "execute"), - (uint32_t)address, mmu_idx, - ret ? "Miss" : "Hit", - *prot & PAGE_READ ? 'r' : '-', - *prot & PAGE_WRITE ? 'w' : '-', - *prot & PAGE_EXEC ? 'x' : '-'); - - return ret; - } - - /* Definitely a real MMU, not an MPU */ - - if (regime_translation_disabled(env, mmu_idx)) { - uint64_t hcr; - uint8_t memattr; - - /* - * MMU disabled. S1 addresses within aa64 translation regimes are - * still checked for bounds -- see AArch64.TranslateAddressS1Off. - */ - if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) { - int r_el = regime_el(env, mmu_idx); - if (arm_el_is_aa64(env, r_el)) { - int pamax = arm_pamax(env_archcpu(env)); - uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; - int addrtop, tbi; - - tbi = aa64_va_parameter_tbi(tcr, mmu_idx); - if (access_type == MMU_INST_FETCH) { - tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); - } - tbi = (tbi >> extract64(address, 55, 1)) & 1; - addrtop = (tbi ? 55 : 63); - - if (extract64(address, pamax, addrtop - pamax + 1) != 0) { - fi->type = ARMFault_AddressSize; - fi->level = 0; - fi->stage2 = false; - return 1; - } - - /* - * When TBI is disabled, we've just validated that all of the - * bits above PAMax are zero, so logically we only need to - * clear the top byte for TBI. But it's clearer to follow - * the pseudocode set of addrdesc.paddress. - */ - address = extract64(address, 0, 52); - } - } - *phys_ptr = address; - *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - *page_size = TARGET_PAGE_SIZE; - - /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr = arm_hcr_el2_eff(env); - cacheattrs->shareability = 0; - cacheattrs->is_s2_format = false; - if (hcr & HCR_DC) { - if (hcr & HCR_DCT) { - memattr = 0xf0; /* Tagged, Normal, WB, RWA */ - } else { - memattr = 0xff; /* Normal, WB, RWA */ - } - } else if (access_type == MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr = 0xee; /* Normal, WT, RA, NT */ - } else { - memattr = 0x44; /* Normal, NC, No */ - } - cacheattrs->shareability = 2; /* outer sharable */ - } else { - memattr = 0x00; /* Device, nGnRnE */ - } - cacheattrs->attrs = memattr; - return 0; - } - - if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, address, access_type, mmu_idx, false, - phys_ptr, attrs, prot, page_size, - fi, cacheattrs); - } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { - return get_phys_addr_v6(env, address, access_type, mmu_idx, - phys_ptr, attrs, prot, page_size, fi); - } else { - return get_phys_addr_v5(env, address, access_type, mmu_idx, - phys_ptr, prot, page_size, fi); - } -} - hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { @@ -13121,7 +12852,6 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, } return phys_addr; } - #endif /* Note that signed overflow is undefined in C. The following routines are diff --git a/target/arm/ptw.c b/target/arm/ptw.c new file mode 100644 index 00000000000..318000f6d94 --- /dev/null +++ b/target/arm/ptw.c @@ -0,0 +1,267 @@ +/* + * ARM page table walking. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "cpu.h" +#include "internals.h" +#include "ptw.h" + + +/** + * get_phys_addr - get the physical address for this virtual address + * + * Find the physical address corresponding to the given virtual address, + * by doing a translation table walk on MMU based systems or using the + * MPU state on MPU based systems. + * + * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, + * prot and page_size may not be filled in, and the populated fsr value provides + * information on why the translation aborted, in the format of a + * DFSR/IFSR fault register, with the following caveats: + * * we honour the short vs long DFSR format differences. + * * the WnR bit is never set (the caller must do this). + * * for PSMAv5 based systems we don't bother to return a full FSR format + * value. + * + * @env: CPUARMState + * @address: virtual address to get physical address for + * @access_type: 0 for read, 1 for write, 2 for execute + * @mmu_idx: MMU index indicating required translation regime + * @phys_ptr: set to the physical address corresponding to the virtual address + * @attrs: set to the memory transaction attributes to use + * @prot: set to the permissions for the page containing phys_ptr + * @page_size: set to the size of the page containing phys_ptr + * @fi: set to fault info if the translation fails + * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes + */ +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) +{ + ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); + + if (mmu_idx != s1_mmu_idx) { + /* + * Call ourselves recursively to do the stage 1 and then stage 2 + * translations if mmu_idx is a two-stage regime. + */ + if (arm_feature(env, ARM_FEATURE_EL2)) { + hwaddr ipa; + int s2_prot; + int ret; + bool ipa_secure; + ARMCacheAttrs cacheattrs2 = {}; + ARMMMUIdx s2_mmu_idx; + bool is_el0; + + ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa, + attrs, prot, page_size, fi, cacheattrs); + + /* If S1 fails or S2 is disabled, return early. */ + if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) { + *phys_ptr = ipa; + return ret; + } + + ipa_secure = attrs->secure; + if (arm_is_secure_below_el3(env)) { + if (ipa_secure) { + attrs->secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); + } else { + attrs->secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + } + } else { + assert(!ipa_secure); + } + + s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; + is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0; + + /* S1 is done. Now do S2 translation. */ + ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0, + phys_ptr, attrs, &s2_prot, + page_size, fi, &cacheattrs2); + fi->s2addr = ipa; + /* Combine the S1 and S2 perms. */ + *prot &= s2_prot; + + /* If S2 fails, return early. */ + if (ret) { + return ret; + } + + /* Combine the S1 and S2 cache attributes. */ + if (arm_hcr_el2_eff(env) & HCR_DC) { + /* + * HCR.DC forces the first stage attributes to + * Normal Non-Shareable, + * Inner Write-Back Read-Allocate Write-Allocate, + * Outer Write-Back Read-Allocate Write-Allocate. + * Do not overwrite Tagged within attrs. + */ + if (cacheattrs->attrs != 0xf0) { + cacheattrs->attrs = 0xff; + } + cacheattrs->shareability = 0; + } + *cacheattrs = combine_cacheattrs(env, *cacheattrs, cacheattrs2); + + /* Check if IPA translates to secure or non-secure PA space. */ + if (arm_is_secure_below_el3(env)) { + if (ipa_secure) { + attrs->secure = + !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW)); + } else { + attrs->secure = + !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_NSW)) + || (env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW))); + } + } + return 0; + } else { + /* + * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. + */ + mmu_idx = stage_1_mmu_idx(mmu_idx); + } + } + + /* + * The page table entries may downgrade secure to non-secure, but + * cannot upgrade an non-secure translation regime's attributes + * to secure. + */ + attrs->secure = regime_is_secure(env, mmu_idx); + attrs->user = regime_is_user(env, mmu_idx); + + /* + * Fast Context Switch Extension. This doesn't exist at all in v8. + * In v7 and earlier it affects all stage 1 translations. + */ + if (address < 0x02000000 && mmu_idx != ARMMMUIdx_Stage2 + && !arm_feature(env, ARM_FEATURE_V8)) { + if (regime_el(env, mmu_idx) == 3) { + address += env->cp15.fcseidr_s; + } else { + address += env->cp15.fcseidr_ns; + } + } + + if (arm_feature(env, ARM_FEATURE_PMSA)) { + bool ret; + *page_size = TARGET_PAGE_SIZE; + + if (arm_feature(env, ARM_FEATURE_V8)) { + /* PMSAv8 */ + ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, + phys_ptr, attrs, prot, page_size, fi); + } else if (arm_feature(env, ARM_FEATURE_V7)) { + /* PMSAv7 */ + ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, + phys_ptr, prot, page_size, fi); + } else { + /* Pre-v7 MPU */ + ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, + phys_ptr, prot, fi); + } + qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 + " mmu_idx %u -> %s (prot %c%c%c)\n", + access_type == MMU_DATA_LOAD ? "reading" : + (access_type == MMU_DATA_STORE ? "writing" : "execute"), + (uint32_t)address, mmu_idx, + ret ? "Miss" : "Hit", + *prot & PAGE_READ ? 'r' : '-', + *prot & PAGE_WRITE ? 'w' : '-', + *prot & PAGE_EXEC ? 'x' : '-'); + + return ret; + } + + /* Definitely a real MMU, not an MPU */ + + if (regime_translation_disabled(env, mmu_idx)) { + uint64_t hcr; + uint8_t memattr; + + /* + * MMU disabled. S1 addresses within aa64 translation regimes are + * still checked for bounds -- see AArch64.TranslateAddressS1Off. + */ + if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) { + int r_el = regime_el(env, mmu_idx); + if (arm_el_is_aa64(env, r_el)) { + int pamax = arm_pamax(env_archcpu(env)); + uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; + int addrtop, tbi; + + tbi = aa64_va_parameter_tbi(tcr, mmu_idx); + if (access_type == MMU_INST_FETCH) { + tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi = (tbi >> extract64(address, 55, 1)) & 1; + addrtop = (tbi ? 55 : 63); + + if (extract64(address, pamax, addrtop - pamax + 1) != 0) { + fi->type = ARMFault_AddressSize; + fi->level = 0; + fi->stage2 = false; + return 1; + } + + /* + * When TBI is disabled, we've just validated that all of the + * bits above PAMax are zero, so logically we only need to + * clear the top byte for TBI. But it's clearer to follow + * the pseudocode set of addrdesc.paddress. + */ + address = extract64(address, 0, 52); + } + } + *phys_ptr = address; + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + *page_size = TARGET_PAGE_SIZE; + + /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ + hcr = arm_hcr_el2_eff(env); + cacheattrs->shareability = 0; + cacheattrs->is_s2_format = false; + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr = 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr = 0xff; /* Normal, WB, RWA */ + } + } else if (access_type == MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr = 0xee; /* Normal, WT, RA, NT */ + } else { + memattr = 0x44; /* Normal, NC, No */ + } + cacheattrs->shareability = 2; /* outer sharable */ + } else { + memattr = 0x00; /* Device, nGnRnE */ + } + cacheattrs->attrs = memattr; + return 0; + } + + if (regime_using_lpae_format(env, mmu_idx)) { + return get_phys_addr_lpae(env, address, access_type, mmu_idx, false, + phys_ptr, attrs, prot, page_size, + fi, cacheattrs); + } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { + return get_phys_addr_v6(env, address, access_type, mmu_idx, + phys_ptr, attrs, prot, page_size, fi); + } else { + return get_phys_addr_v5(env, address, access_type, mmu_idx, + phys_ptr, prot, page_size, fi); + } +} diff --git a/target/arm/meson.build b/target/arm/meson.build index 50f152214af..ac571fc45db 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -58,6 +58,7 @@ arm_softmmu_ss.add(files( 'machine.c', 'monitor.c', 'psci.c', + 'ptw.c', )) subdir('hvf') From patchwork Thu Jun 9 09:04:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580244 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp600231max; Thu, 9 Jun 2022 02:27:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyVEzsXR+b/CP2W8pgVL2Ivhp72fqZMx1SwFK1jPmYCjycEG7fmxdsBafiD+XFRLA/Ebsoe X-Received: by 2002:a37:a1c4:0:b0:6a6:ac4f:1d3f with SMTP id k187-20020a37a1c4000000b006a6ac4f1d3fmr17782324qke.666.1654766862177; Thu, 09 Jun 2022 02:27:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654766862; cv=none; d=google.com; s=arc-20160816; b=tm87/RavuViuVMxjkopxmTuX5yofrMb7Vr069Jmf/mo/ETNGq19LM3PLYhmZKGTalX tMk1pM9AwtD1t42JWS5OBx6sq5sha7A592RXhJDHC32yYsZbioTytbLyJNbmQjkKL0ke gkDGB593fzuV+OjjFNFljoglJeQe1nsLugB7u/pvOBGFu2OuKvQT4KTVuL9i3BpVGwpj knu86p2L2DN4r8fHsFrBXGoNJx81mipjkS4RqzBRvk+7TlTGhKXBGSqkjgQMQyMp9C+w ZNgzAazjyqujy8HUvTfb2xobR1xOlBzWpzRbEK8z4y0X1pBSi5q9N6SLKV6Ec/IuZMFt Im5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VG4un4lC8exaz+aSq1lh+oEDzRxMaXaOxXswh3zyYxQ=; b=YlXE4O6/J1qAEbsW9HDDBuU/57kQ/EWwpiWis+h+9AToFQpWjtIF8kmEj/osjSkCrq IPzSSefctj421Kpb7MhvdqIXMGP9LGYFWLxN7SAJEDSMZRiMWZbynK57EmL3QEcZ5yTe Jng6MuHS6I/79kiVXx+bj/cdEOSaF7VwWRCO6nmIan0Dqo74QXrZ7sRpEJC19m8ATcEH OKa8nQPwVduqREd5+V7jmbPoUhlvQx3CF9yLyjmHxzggoffWXcCYX/lI3qVBKP5Zvk1k lE/N0Kc2lz257VoAbSyLrm1wPj4XAFR4sfAAjitDnDNwPsmV20ssMtVjuMCAZanSjRP2 t/Uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="RNFip/6F"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w2-20020ac87e82000000b0030503a8977fsi1930953qtj.674.2022.06.09.02.27.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:27:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="RNFip/6F"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzES4-0005r4-Uy for patch@linaro.org; Thu, 09 Jun 2022 05:27:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39294) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE70-0001Si-Vj for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:55 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:44816) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE6y-00060e-Nh for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:54 -0400 Received: by mail-wr1-x433.google.com with SMTP id q15so23422931wrc.11 for ; Thu, 09 Jun 2022 02:05:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VG4un4lC8exaz+aSq1lh+oEDzRxMaXaOxXswh3zyYxQ=; b=RNFip/6FQJ0qiatRXnuFSwr2NKZi/wJ4POxtXwUSNPccIJDNi+9LIRwKQL5d1L9KAR x9BNLllr8/EJOWN7f2Eu3AHuGm1bMN+kmHfMOhTfjwtc8ATMygZrhOyd0kgybk4c2fuJ VqrrIo2kJE6l5SQbS4OI/bXMJ1V4kSLQeE7QjyzXWYvkLfc2gk0acJcjPpzMQ18rpOT9 kq4TDC+Cdvrbs34UFdvexWrwh/za0WJTZjIpd8LfOOvekl+bISw/EbpDG845eKVU7ME5 x1mXIBk0MUfImKqtaW0XcTIbhcv7RMHn20vgKbmNqzdCbMcaubMxgjfPia3EkPPTZwP2 T9Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VG4un4lC8exaz+aSq1lh+oEDzRxMaXaOxXswh3zyYxQ=; b=2MFgUC6g6iPq+I3u1DU+/eBMlaG/ivGHCtEjHv6QWk9PJpE/JZoKAiyR90jIgfzRrP 8/FKPdmKhKegxo9ijvMx6FUcd1GYeLmdDskFXQg/+0kWegBJ3RvhwCXjNgy2lMswIuPS HYtnrOxD4P7I7bSss9BaEzixWMu2yOPZmakxJgborcEfOxPrKNYyJYjgSBqk2InHDPu4 /7Ji7/cOef88BB80eSdetr7EYXq5sSdjutOolCW0U3bE4Sz8h6eFP4akwDNirFsRwiog /b3RqLCvTAyvJBlG/ME2mSEzZCvoJ6d9iwmwRnkoE1eD6r18GWXBL3bRqr6fk3N6NQa9 8T+Q== X-Gm-Message-State: AOAM531aZgBVwAIuhQua8xCvrSpeQ8NGz6tP58UGLnMt7IOCgcy1e9iw sKEoy13DTmHpOgHkJ9obcotMkvnl3CL+Mg== X-Received: by 2002:a5d:58ed:0:b0:217:dd5:7508 with SMTP id f13-20020a5d58ed000000b002170dd57508mr24328263wrd.606.1654765551221; Thu, 09 Jun 2022 02:05:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/55] target/arm: Move get_phys_addr_v5 to ptw.c Date: Thu, 9 Jun 2022 10:04:52 +0100 Message-Id: <20220609090537.1971756-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 15 +++-- target/arm/helper.c | 137 +++----------------------------------------- target/arm/ptw.c | 123 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 140 insertions(+), 135 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index e2023ae7508..2dbd97b8cbf 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -11,16 +11,21 @@ #ifndef CONFIG_USER_ONLY +uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, + ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi); +uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, + ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi); + bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx); bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx); ARMCacheAttrs combine_cacheattrs(CPUARMState *env, ARMCacheAttrs s1, ARMCacheAttrs s2); -bool get_phys_addr_v5(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi); +bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, + uint32_t *table, uint32_t address); +int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, + int ap, int domain_prot); + bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, diff --git a/target/arm/helper.c b/target/arm/helper.c index 3ffd122178d..321716914b1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10578,8 +10578,7 @@ bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) * @ap: The 3-bit access permissions (AP[2:0]) * @domain_prot: The 2-bit domain access permissions */ -static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, - int ap, int domain_prot) +int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap, int domain_prot) { bool is_user = regime_is_user(env, mmu_idx); @@ -10782,8 +10781,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, return prot_rw | PAGE_EXEC; } -static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, - uint32_t *table, uint32_t address) +bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, + uint32_t *table, uint32_t address) { /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ TCR *tcr = regime_tcr(env, mmu_idx); @@ -10882,8 +10881,8 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, } /* All loads done in the course of a page table walk go through here. */ -static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) +uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, + ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; @@ -10911,8 +10910,8 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, return 0; } -static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) +uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, + ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; @@ -10940,128 +10939,6 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, return 0; } -bool get_phys_addr_v5(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi) -{ - CPUState *cs = env_cpu(env); - int level = 1; - uint32_t table; - uint32_t desc; - int type; - int ap; - int domain = 0; - int domain_prot; - hwaddr phys_addr; - uint32_t dacr; - - /* Pagetable walk. */ - /* Lookup l1 descriptor. */ - if (!get_level1_table_address(env, mmu_idx, &table, address)) { - /* Section translation fault if page walk is disabled by PD0 or PD1 */ - fi->type = ARMFault_Translation; - goto do_fault; - } - desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); - if (fi->type != ARMFault_None) { - goto do_fault; - } - type = (desc & 3); - domain = (desc >> 5) & 0x0f; - if (regime_el(env, mmu_idx) == 1) { - dacr = env->cp15.dacr_ns; - } else { - dacr = env->cp15.dacr_s; - } - domain_prot = (dacr >> (domain * 2)) & 3; - if (type == 0) { - /* Section translation fault. */ - fi->type = ARMFault_Translation; - goto do_fault; - } - if (type != 2) { - level = 2; - } - if (domain_prot == 0 || domain_prot == 2) { - fi->type = ARMFault_Domain; - goto do_fault; - } - if (type == 2) { - /* 1Mb section. */ - phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); - ap = (desc >> 10) & 3; - *page_size = 1024 * 1024; - } else { - /* Lookup l2 entry. */ - if (type == 1) { - /* Coarse pagetable. */ - table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - } else { - /* Fine pagetable. */ - table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); - } - desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); - if (fi->type != ARMFault_None) { - goto do_fault; - } - switch (desc & 3) { - case 0: /* Page translation fault. */ - fi->type = ARMFault_Translation; - goto do_fault; - case 1: /* 64k page. */ - phys_addr = (desc & 0xffff0000) | (address & 0xffff); - ap = (desc >> (4 + ((address >> 13) & 6))) & 3; - *page_size = 0x10000; - break; - case 2: /* 4k page. */ - phys_addr = (desc & 0xfffff000) | (address & 0xfff); - ap = (desc >> (4 + ((address >> 9) & 6))) & 3; - *page_size = 0x1000; - break; - case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ - if (type == 1) { - /* ARMv6/XScale extended small page format */ - if (arm_feature(env, ARM_FEATURE_XSCALE) - || arm_feature(env, ARM_FEATURE_V6)) { - phys_addr = (desc & 0xfffff000) | (address & 0xfff); - *page_size = 0x1000; - } else { - /* UNPREDICTABLE in ARMv5; we choose to take a - * page translation fault. - */ - fi->type = ARMFault_Translation; - goto do_fault; - } - } else { - phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); - *page_size = 0x400; - } - ap = (desc >> 4) & 3; - break; - default: - /* Never happens, but compiler isn't smart enough to tell. */ - g_assert_not_reached(); - } - } - *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); - *prot |= *prot ? PAGE_EXEC : 0; - if (!(*prot & (1 << access_type))) { - /* Access permission fault. */ - fi->type = ARMFault_Permission; - goto do_fault; - } - *phys_ptr = phys_addr; - return false; -do_fault: - fi->domain = domain; - fi->level = level; - return true; -} - bool get_phys_addr_v6(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 318000f6d94..09c44726287 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -13,6 +13,129 @@ #include "ptw.h" +static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi) +{ + CPUState *cs = env_cpu(env); + int level = 1; + uint32_t table; + uint32_t desc; + int type; + int ap; + int domain = 0; + int domain_prot; + hwaddr phys_addr; + uint32_t dacr; + + /* Pagetable walk. */ + /* Lookup l1 descriptor. */ + if (!get_level1_table_address(env, mmu_idx, &table, address)) { + /* Section translation fault if page walk is disabled by PD0 or PD1 */ + fi->type = ARMFault_Translation; + goto do_fault; + } + desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fi); + if (fi->type != ARMFault_None) { + goto do_fault; + } + type = (desc & 3); + domain = (desc >> 5) & 0x0f; + if (regime_el(env, mmu_idx) == 1) { + dacr = env->cp15.dacr_ns; + } else { + dacr = env->cp15.dacr_s; + } + domain_prot = (dacr >> (domain * 2)) & 3; + if (type == 0) { + /* Section translation fault. */ + fi->type = ARMFault_Translation; + goto do_fault; + } + if (type != 2) { + level = 2; + } + if (domain_prot == 0 || domain_prot == 2) { + fi->type = ARMFault_Domain; + goto do_fault; + } + if (type == 2) { + /* 1Mb section. */ + phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); + ap = (desc >> 10) & 3; + *page_size = 1024 * 1024; + } else { + /* Lookup l2 entry. */ + if (type == 1) { + /* Coarse pagetable. */ + table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); + } else { + /* Fine pagetable. */ + table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); + } + desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fi); + if (fi->type != ARMFault_None) { + goto do_fault; + } + switch (desc & 3) { + case 0: /* Page translation fault. */ + fi->type = ARMFault_Translation; + goto do_fault; + case 1: /* 64k page. */ + phys_addr = (desc & 0xffff0000) | (address & 0xffff); + ap = (desc >> (4 + ((address >> 13) & 6))) & 3; + *page_size = 0x10000; + break; + case 2: /* 4k page. */ + phys_addr = (desc & 0xfffff000) | (address & 0xfff); + ap = (desc >> (4 + ((address >> 9) & 6))) & 3; + *page_size = 0x1000; + break; + case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ + if (type == 1) { + /* ARMv6/XScale extended small page format */ + if (arm_feature(env, ARM_FEATURE_XSCALE) + || arm_feature(env, ARM_FEATURE_V6)) { + phys_addr = (desc & 0xfffff000) | (address & 0xfff); + *page_size = 0x1000; + } else { + /* + * UNPREDICTABLE in ARMv5; we choose to take a + * page translation fault. + */ + fi->type = ARMFault_Translation; + goto do_fault; + } + } else { + phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); + *page_size = 0x400; + } + ap = (desc >> 4) & 3; + break; + default: + /* Never happens, but compiler isn't smart enough to tell. */ + g_assert_not_reached(); + } + } + *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + *prot |= *prot ? PAGE_EXEC : 0; + if (!(*prot & (1 << access_type))) { + /* Access permission fault. */ + fi->type = ARMFault_Permission; + goto do_fault; + } + *phys_ptr = phys_addr; + return false; +do_fault: + fi->domain = domain; + fi->level = level; + return true; +} + /** * get_phys_addr - get the physical address for this virtual address * From patchwork Thu Jun 9 09:04:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580241 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp597375max; Thu, 9 Jun 2022 02:22:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzChQT7+sabYl6eNWPgdtGJk2KX5fuokt/fhtOu2VwlTDmiUr5CaGS3rAUxPIuwQcM2SV8E X-Received: by 2002:a05:622a:180e:b0:305:8aa:a24a with SMTP id t14-20020a05622a180e00b0030508aaa24amr4286459qtc.429.1654766570103; Thu, 09 Jun 2022 02:22:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654766570; cv=none; d=google.com; s=arc-20160816; b=lFjZNPdTgpodHXDDnnT42JZCk3W/3yAHQY/hGmhbT29edX64sF2oA8TugsuvzHhDLn iGeHt0sO3q7vxee9PBfd8VvUl1WNY8G2MkRuvLmxqewX3IJlHBDnO9nP9ZSkVys0FTAU OTj/fzjYUpezv6GUZbJpMq7QkNp4/AuICvZjMBsO037ITrROjNIh/qc/bX2sA9dqNTXv pFkqO9xUCcg/r0I42e9WbwW1dK9Z8oGKVVY7mNLZzu7iJ3AIZxCcvxNsZpCTl5ox4T36 NozeUx+n/yJiHG4QWTt7OMxxhDjKVGtQYU/ufdOYELG0WWB7+eMbULDS+pJjJjIG6xo6 uuMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XtUVBNi8Hf8p1qU71YRb6ABVBGS+B/b2TUi9wKuJp40=; b=h/+G9kBfDkv83XwaxtxocX3ELSnGYrXERCksJv/qzkNN4HjQvvxHhSjkXBUBSpzkb1 jzqr+4SzK9zfy80gZ886+gGNGdDRbrQ09yAWaySMefj04o8BPea06YflZek6oCF8VQ28 FWa6HPR608C7l4oB3lRQ/M7qsRRTPEm6kMjDEKPkW+60johwSEV+7vxu3gJQQWTfRLP2 zFLL10ElN5oF3xllLANJRIJIZE6WvR117bSPcAS8Qzup/mL2FPn3zrRUZWEA3PB6ZHpS ZdnM37OScpuZewLDgvxUeMQDRuV8z9rwd2KKbA4p9OfYjZzqi7eLd5DImQUuRFYv6J/r h48Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yMpIlZ96; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id gw10-20020a0562140f0a00b00461da2b24edsi13381951qvb.294.2022.06.09.02.22.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:22:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yMpIlZ96; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33120 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzENN-0008ML-Kp for patch@linaro.org; Thu, 09 Jun 2022 05:22:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39334) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE72-0001U6-JW for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:56 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:42899) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE70-00060y-CF for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:56 -0400 Received: by mail-wr1-x432.google.com with SMTP id s1so8358409wra.9 for ; Thu, 09 Jun 2022 02:05:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XtUVBNi8Hf8p1qU71YRb6ABVBGS+B/b2TUi9wKuJp40=; b=yMpIlZ96Z0LOVZ7k1utzjc/cAFyrCn9mxGwsiOlzYo2jb7AiftK7CcKKnXh3XKC3tt WtLtGQHBEtKtYUO6SDa4VeAaiJzUKVtcsG2ghGCDQg0U+0KOBbiZntZRAYXDDviBKP7G qoK82OJ/32nOckI1sh7/Qp5/lG72LyVl/gL0EDN9wpGBWu+TsQFJ1g9BUkjBo7wnih5E axqElVgegtiXHlsVUaB0Hgvtploa85p8BCfYLrjiHztltsm2LohkhKFNqeGip42yX2+I LmFYHc6rgLJqxlGdSdy/4ZGUDb+8IDAyFn9i/LkYdcLqKTUup4mm7x0zoH2CthlQiYEf fD1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XtUVBNi8Hf8p1qU71YRb6ABVBGS+B/b2TUi9wKuJp40=; b=2O0pZRw44D2B4GG8peeTb2Ss/VQPZLt9qe7mA6MmkS7AsSBoMbe4hVR9KlXoTfimgS anZOLTim/K62CZKq1k/PAsAncj5dTCOt5i1P/gKMVp6+FDAWut1afF+5kU/hIikR+zzP BUrVR/ksv3MDBtvdgV/uVbVmeV47vaiEBEZyri/dtYGZlLZ4aa6hXXVIiwQjr1Wq5f9q l0l+kaL2NGdywzVLCOEoF0lXYa+bc2P+23M3OnblxNkMfqySnAILQzxClT34llWNVzZ4 yaEfRae1HT2pMNK2VQAUb4B11Gnku84mg7H4KJaiuXvVrH5DfNMwJkGJ64K3mw7a4gE9 z4gA== X-Gm-Message-State: AOAM531PKq04ytrCttB2kAraZ8MfLLlzUN2u80JHAxTECzzF5g6n9jhB gElyoCeX+9xxn8GI35ihey4SyLnHlLPnXw== X-Received: by 2002:a05:6000:152:b0:216:160:2e60 with SMTP id r18-20020a056000015200b0021601602e60mr27313517wrx.663.1654765552585; Thu, 09 Jun 2022 02:05:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/55] target/arm: Move get_phys_addr_v6 to ptw.c Date: Thu, 9 Jun 2022 10:04:53 +0100 Message-Id: <20220609090537.1971756-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 11 +-- target/arm/helper.c | 161 +------------------------------------------- target/arm/ptw.c | 153 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 161 insertions(+), 164 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index 2dbd97b8cbf..349b842d3ce 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -25,15 +25,18 @@ bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, uint32_t *table, uint32_t address); int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap, int domain_prot); +int simple_ap_to_rw_prot_is_user(int ap, bool is_user); + +static inline int +simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) +{ + return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); +} bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, ARMMMUFaultInfo *fi); -bool get_phys_addr_v6(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, ARMMMUFaultInfo *fi); bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, diff --git a/target/arm/helper.c b/target/arm/helper.c index 321716914b1..4a588220250 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10631,7 +10631,7 @@ int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap, int domain_prot) * @ap: The 2-bit simple AP (AP[2:1]) * @is_user: TRUE if accessing from PL0 */ -static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) +int simple_ap_to_rw_prot_is_user(int ap, bool is_user) { switch (ap) { case 0: @@ -10647,12 +10647,6 @@ static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) } } -static inline int -simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) -{ - return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); -} - /* Translate S2 section/page access permissions to protection flags * * @env: CPUARMState @@ -10939,159 +10933,6 @@ uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, return 0; } -bool get_phys_addr_v6(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, ARMMMUFaultInfo *fi) -{ - CPUState *cs = env_cpu(env); - ARMCPU *cpu = env_archcpu(env); - int level = 1; - uint32_t table; - uint32_t desc; - uint32_t xn; - uint32_t pxn = 0; - int type; - int ap; - int domain = 0; - int domain_prot; - hwaddr phys_addr; - uint32_t dacr; - bool ns; - - /* Pagetable walk. */ - /* Lookup l1 descriptor. */ - if (!get_level1_table_address(env, mmu_idx, &table, address)) { - /* Section translation fault if page walk is disabled by PD0 or PD1 */ - fi->type = ARMFault_Translation; - goto do_fault; - } - desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); - if (fi->type != ARMFault_None) { - goto do_fault; - } - type = (desc & 3); - if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) { - /* Section translation fault, or attempt to use the encoding - * which is Reserved on implementations without PXN. - */ - fi->type = ARMFault_Translation; - goto do_fault; - } - if ((type == 1) || !(desc & (1 << 18))) { - /* Page or Section. */ - domain = (desc >> 5) & 0x0f; - } - if (regime_el(env, mmu_idx) == 1) { - dacr = env->cp15.dacr_ns; - } else { - dacr = env->cp15.dacr_s; - } - if (type == 1) { - level = 2; - } - domain_prot = (dacr >> (domain * 2)) & 3; - if (domain_prot == 0 || domain_prot == 2) { - /* Section or Page domain fault */ - fi->type = ARMFault_Domain; - goto do_fault; - } - if (type != 1) { - if (desc & (1 << 18)) { - /* Supersection. */ - phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); - phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; - phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; - *page_size = 0x1000000; - } else { - /* Section. */ - phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); - *page_size = 0x100000; - } - ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); - xn = desc & (1 << 4); - pxn = desc & 1; - ns = extract32(desc, 19, 1); - } else { - if (cpu_isar_feature(aa32_pxn, cpu)) { - pxn = (desc >> 2) & 1; - } - ns = extract32(desc, 3, 1); - /* Lookup l2 entry. */ - table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); - if (fi->type != ARMFault_None) { - goto do_fault; - } - ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); - switch (desc & 3) { - case 0: /* Page translation fault. */ - fi->type = ARMFault_Translation; - goto do_fault; - case 1: /* 64k page. */ - phys_addr = (desc & 0xffff0000) | (address & 0xffff); - xn = desc & (1 << 15); - *page_size = 0x10000; - break; - case 2: case 3: /* 4k page. */ - phys_addr = (desc & 0xfffff000) | (address & 0xfff); - xn = desc & 1; - *page_size = 0x1000; - break; - default: - /* Never happens, but compiler isn't smart enough to tell. */ - g_assert_not_reached(); - } - } - if (domain_prot == 3) { - *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - } else { - if (pxn && !regime_is_user(env, mmu_idx)) { - xn = 1; - } - if (xn && access_type == MMU_INST_FETCH) { - fi->type = ARMFault_Permission; - goto do_fault; - } - - if (arm_feature(env, ARM_FEATURE_V6K) && - (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { - /* The simplified model uses AP[0] as an access control bit. */ - if ((ap & 1) == 0) { - /* Access flag fault. */ - fi->type = ARMFault_AccessFlag; - goto do_fault; - } - *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); - } else { - *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); - } - if (*prot && !xn) { - *prot |= PAGE_EXEC; - } - if (!(*prot & (1 << access_type))) { - /* Access permission fault. */ - fi->type = ARMFault_Permission; - goto do_fault; - } - } - if (ns) { - /* The NS bit will (as required by the architecture) have no effect if - * the CPU doesn't support TZ or this is a non-secure translation - * regime, because the attribute will already be non-secure. - */ - attrs->secure = false; - } - *phys_ptr = phys_addr; - return false; -do_fault: - fi->domain = domain; - fi->level = level; - return true; -} - /* * check_s2_mmu_setup * @cpu: ARMCPU diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 09c44726287..6a1f4b549d8 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -136,6 +136,159 @@ do_fault: return true; } +static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, ARMMMUFaultInfo *fi) +{ + CPUState *cs = env_cpu(env); + ARMCPU *cpu = env_archcpu(env); + int level = 1; + uint32_t table; + uint32_t desc; + uint32_t xn; + uint32_t pxn = 0; + int type; + int ap; + int domain = 0; + int domain_prot; + hwaddr phys_addr; + uint32_t dacr; + bool ns; + + /* Pagetable walk. */ + /* Lookup l1 descriptor. */ + if (!get_level1_table_address(env, mmu_idx, &table, address)) { + /* Section translation fault if page walk is disabled by PD0 or PD1 */ + fi->type = ARMFault_Translation; + goto do_fault; + } + desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fi); + if (fi->type != ARMFault_None) { + goto do_fault; + } + type = (desc & 3); + if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) { + /* Section translation fault, or attempt to use the encoding + * which is Reserved on implementations without PXN. + */ + fi->type = ARMFault_Translation; + goto do_fault; + } + if ((type == 1) || !(desc & (1 << 18))) { + /* Page or Section. */ + domain = (desc >> 5) & 0x0f; + } + if (regime_el(env, mmu_idx) == 1) { + dacr = env->cp15.dacr_ns; + } else { + dacr = env->cp15.dacr_s; + } + if (type == 1) { + level = 2; + } + domain_prot = (dacr >> (domain * 2)) & 3; + if (domain_prot == 0 || domain_prot == 2) { + /* Section or Page domain fault */ + fi->type = ARMFault_Domain; + goto do_fault; + } + if (type != 1) { + if (desc & (1 << 18)) { + /* Supersection. */ + phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); + phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; + phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; + *page_size = 0x1000000; + } else { + /* Section. */ + phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); + *page_size = 0x100000; + } + ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); + xn = desc & (1 << 4); + pxn = desc & 1; + ns = extract32(desc, 19, 1); + } else { + if (cpu_isar_feature(aa32_pxn, cpu)) { + pxn = (desc >> 2) & 1; + } + ns = extract32(desc, 3, 1); + /* Lookup l2 entry. */ + table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); + desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fi); + if (fi->type != ARMFault_None) { + goto do_fault; + } + ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); + switch (desc & 3) { + case 0: /* Page translation fault. */ + fi->type = ARMFault_Translation; + goto do_fault; + case 1: /* 64k page. */ + phys_addr = (desc & 0xffff0000) | (address & 0xffff); + xn = desc & (1 << 15); + *page_size = 0x10000; + break; + case 2: case 3: /* 4k page. */ + phys_addr = (desc & 0xfffff000) | (address & 0xfff); + xn = desc & 1; + *page_size = 0x1000; + break; + default: + /* Never happens, but compiler isn't smart enough to tell. */ + g_assert_not_reached(); + } + } + if (domain_prot == 3) { + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + } else { + if (pxn && !regime_is_user(env, mmu_idx)) { + xn = 1; + } + if (xn && access_type == MMU_INST_FETCH) { + fi->type = ARMFault_Permission; + goto do_fault; + } + + if (arm_feature(env, ARM_FEATURE_V6K) && + (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { + /* The simplified model uses AP[0] as an access control bit. */ + if ((ap & 1) == 0) { + /* Access flag fault. */ + fi->type = ARMFault_AccessFlag; + goto do_fault; + } + *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); + } else { + *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + } + if (*prot && !xn) { + *prot |= PAGE_EXEC; + } + if (!(*prot & (1 << access_type))) { + /* Access permission fault. */ + fi->type = ARMFault_Permission; + goto do_fault; + } + } + if (ns) { + /* The NS bit will (as required by the architecture) have no effect if + * the CPU doesn't support TZ or this is a non-secure translation + * regime, because the attribute will already be non-secure. + */ + attrs->secure = false; + } + *phys_ptr = phys_addr; + return false; +do_fault: + fi->domain = domain; + fi->level = level; + return true; +} + /** * get_phys_addr - get the physical address for this virtual address * From patchwork Thu Jun 9 09:04:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580247 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp601367max; Thu, 9 Jun 2022 02:29:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwTkF7eK3Zs+2aDdsDVZEDcpW0DnXPskAIgm695b19e4hBpBJJq2gIwiT5xMc2Nx32uGgGh X-Received: by 2002:a05:620a:2046:b0:6a6:b8d1:7ddf with SMTP id d6-20020a05620a204600b006a6b8d17ddfmr14075531qka.380.1654766969474; Thu, 09 Jun 2022 02:29:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654766969; cv=none; d=google.com; s=arc-20160816; b=iJp81QWfLwQVIB7ipGyD44lv4nNeVOTJj/f3/ZMKQ8DbC2Emy+GFCb/7CnTU/05NPY GM1EzQHSBE9ienHMgcqFMmM1tQC9dFyQYt5FKc6dEfrUCc0Z1xJ4bnMM0CZUfJ03FeZJ GX7RMY/bkGeVHE0YbzYOTAsLXRrd4X8xAyaDsFspdKOBr6guj8tsPhTcIrlsklOCDeXB 12qyy+KfX4iwC4gWri4PbR3ENwBaRN4lwtGMAnALzHXL/1UhdAmP7x04j9F3rQCeYIdc jFm+M2LyheCHRNm9dXSOFOXtreBkwSKT7bKM12sdm3baZ920i4EWq6ExChgULdwThoMp hQTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3/ajaWjvxs0DjIe4wzlTwAQI78+yJDb5luhxxky7riw=; b=HQB1/wUCKtBWxVLF7GEPwLqhhepAGtGRX9lx0VuWVQMsAXYXzkwgY/f7nLqM10XXXD XlOMP7l1pe4XF7tamjYnvpeiNw00xEcCdRIGYNFO+0S4D/PaqW2r4shnsZei9pF5WP3r u0SrJUzwB0TAKh8tuVphEcsvpV5oYlvmkvD7zaXnrgngMTeMPk1KDiu6cFa14v2PAaYQ TrwJKWEjee1AoKDaSYeoGnzupqsN0ux6Q2FL5KMF9gYUUUJPEA+7UjRxAwf0eX23TU3R y9YbG1qB+qgyXvxJR9VCehpThfmHZayb+DkptReScpbF4q75zfinx+Bjou+iAMwHVVh+ PBeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NHUiQjtU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y16-20020a05620a0e1000b006a72eeb58d5si413276qkm.63.2022.06.09.02.29.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:29:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NHUiQjtU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzETp-0008AM-12 for patch@linaro.org; Thu, 09 Jun 2022 05:29:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39336) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE72-0001U8-R4 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:57 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:47100) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE70-00061B-Vt for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:56 -0400 Received: by mail-wm1-x32e.google.com with SMTP id r123-20020a1c2b81000000b0039c1439c33cso12264463wmr.5 for ; Thu, 09 Jun 2022 02:05:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=3/ajaWjvxs0DjIe4wzlTwAQI78+yJDb5luhxxky7riw=; b=NHUiQjtUMYG/VXcQjkFsEMfzlssyJz6ZTLF8bZjheJXP4T/njF18PFDS08qnXbd9JG np0UyhmKifFdIznxG5JP5unZ4jR1F+aOcL4kELB7gXlrPSdiq4GkQgAubRMlndIHUJC/ dBlU4T7aAJ91YGWxf3j6cvvZjRmHP+rxoIB7K9eONNuUjAqheI6XsDy5jTCG226tJjK8 xeiZdvkURQZ8BdPxfgKfj2kIqmuIjOBA+fSPbs8Pi4o4s/ZD86usbqPp8dWMbEuqckZR uQKKh6+kUo6wVLAFlV/0ItgnNG4uZQ+Dy7UJNlX3Pz3u0N3S1M4XgeS1dYEVi+OsISVn 4r2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3/ajaWjvxs0DjIe4wzlTwAQI78+yJDb5luhxxky7riw=; b=uzRZ29l8jMkr1ZFYH5LR3frdS8fUjB3Gdow/GdSTi3jSEVRZ2Dnm7UWu2qtbMXdKt+ QNv7UMA1TGZorwkMzYuY7JvP3k4PJBi7trCssN0QeSTahQgsTilpm3jlhIVEHhDhMLWA 90iyS5JGTK2K7CuAoj4uFE82E2Kk37kTa29Zr+ST5Qk/XuiYU0uHuyuTY5LaK4gsl6ME WINQkN6ODzkfpv1SRozcdb/kK0HDUTBr1mNXwDAa5FLsUVVhvKI0kHuVB9oHdKwlNCJj VKulO0TwUdZe0BnrNdOvrLWoGSS2whMI8GtyJphcUq0SVUnHueWtqd4cfImrZfGbieSr rmFQ== X-Gm-Message-State: AOAM531ot1xQG1PX3ZwC46OxzWjZdzqQd10xjrMEbQgO4xeyO0WPsncO IWfD5GgN/DOfPJQu0g9S2OKLY5ilqzNQLw== X-Received: by 2002:a05:600c:2c46:b0:39c:55a0:9533 with SMTP id r6-20020a05600c2c4600b0039c55a09533mr2278909wmg.104.1654765553651; Thu, 09 Jun 2022 02:05:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/55] target/arm: Move get_phys_addr_pmsav5 to ptw.c Date: Thu, 9 Jun 2022 10:04:54 +0100 Message-Id: <20220609090537.1971756-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 4 --- target/arm/helper.c | 85 --------------------------------------------- target/arm/ptw.c | 85 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+), 89 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index 349b842d3ce..324a9dde140 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -33,10 +33,6 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); } -bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - ARMMMUFaultInfo *fi); bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, diff --git a/target/arm/helper.c b/target/arm/helper.c index 4a588220250..5d010190108 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12274,91 +12274,6 @@ bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, return ret; } -bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - ARMMMUFaultInfo *fi) -{ - int n; - uint32_t mask; - uint32_t base; - bool is_user = regime_is_user(env, mmu_idx); - - if (regime_translation_disabled(env, mmu_idx)) { - /* MPU disabled. */ - *phys_ptr = address; - *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return false; - } - - *phys_ptr = address; - for (n = 7; n >= 0; n--) { - base = env->cp15.c6_region[n]; - if ((base & 1) == 0) { - continue; - } - mask = 1 << ((base >> 1) & 0x1f); - /* Keep this shift separate from the above to avoid an - (undefined) << 32. */ - mask = (mask << 1) - 1; - if (((base ^ address) & ~mask) == 0) { - break; - } - } - if (n < 0) { - fi->type = ARMFault_Background; - return true; - } - - if (access_type == MMU_INST_FETCH) { - mask = env->cp15.pmsav5_insn_ap; - } else { - mask = env->cp15.pmsav5_data_ap; - } - mask = (mask >> (n * 4)) & 0xf; - switch (mask) { - case 0: - fi->type = ARMFault_Permission; - fi->level = 1; - return true; - case 1: - if (is_user) { - fi->type = ARMFault_Permission; - fi->level = 1; - return true; - } - *prot = PAGE_READ | PAGE_WRITE; - break; - case 2: - *prot = PAGE_READ; - if (!is_user) { - *prot |= PAGE_WRITE; - } - break; - case 3: - *prot = PAGE_READ | PAGE_WRITE; - break; - case 5: - if (is_user) { - fi->type = ARMFault_Permission; - fi->level = 1; - return true; - } - *prot = PAGE_READ; - break; - case 6: - *prot = PAGE_READ; - break; - default: - /* Bad permission. */ - fi->type = ARMFault_Permission; - fi->level = 1; - return true; - } - *prot |= PAGE_EXEC; - return false; -} - /* Combine either inner or outer cacheability attributes for normal * memory, according to table D4-42 and pseudocode procedure * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6a1f4b549d8..5c32648a16a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -289,6 +289,91 @@ do_fault: return true; } +static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, int *prot, + ARMMMUFaultInfo *fi) +{ + int n; + uint32_t mask; + uint32_t base; + bool is_user = regime_is_user(env, mmu_idx); + + if (regime_translation_disabled(env, mmu_idx)) { + /* MPU disabled. */ + *phys_ptr = address; + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return false; + } + + *phys_ptr = address; + for (n = 7; n >= 0; n--) { + base = env->cp15.c6_region[n]; + if ((base & 1) == 0) { + continue; + } + mask = 1 << ((base >> 1) & 0x1f); + /* Keep this shift separate from the above to avoid an + (undefined) << 32. */ + mask = (mask << 1) - 1; + if (((base ^ address) & ~mask) == 0) { + break; + } + } + if (n < 0) { + fi->type = ARMFault_Background; + return true; + } + + if (access_type == MMU_INST_FETCH) { + mask = env->cp15.pmsav5_insn_ap; + } else { + mask = env->cp15.pmsav5_data_ap; + } + mask = (mask >> (n * 4)) & 0xf; + switch (mask) { + case 0: + fi->type = ARMFault_Permission; + fi->level = 1; + return true; + case 1: + if (is_user) { + fi->type = ARMFault_Permission; + fi->level = 1; + return true; + } + *prot = PAGE_READ | PAGE_WRITE; + break; + case 2: + *prot = PAGE_READ; + if (!is_user) { + *prot |= PAGE_WRITE; + } + break; + case 3: + *prot = PAGE_READ | PAGE_WRITE; + break; + case 5: + if (is_user) { + fi->type = ARMFault_Permission; + fi->level = 1; + return true; + } + *prot = PAGE_READ; + break; + case 6: + *prot = PAGE_READ; + break; + default: + /* Bad permission. */ + fi->type = ARMFault_Permission; + fi->level = 1; + return true; + } + *prot |= PAGE_EXEC; + return false; +} + /** * get_phys_addr - get the physical address for this virtual address * From patchwork Thu Jun 9 09:04:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580251 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp608231max; Thu, 9 Jun 2022 02:40:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxaGkCDuppaj02H7HtYZNhAl5HXP2luFklHkTMoVrOby1pnj3KVRwFEQbQOR8BI6pLl3sE2 X-Received: by 2002:a37:a808:0:b0:6a6:b3fb:4219 with SMTP id r8-20020a37a808000000b006a6b3fb4219mr15306264qke.557.1654767615175; Thu, 09 Jun 2022 02:40:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654767615; cv=none; d=google.com; s=arc-20160816; b=O3UYboOd9d+lTSgupwCtCgtj2zA/dBddMIYA+iedGYpjzfn/TjMQU81RVqr9m5UlWT LToQ8pFEpvLqCi5VQGNd6yHMzYyA4Lvc2u7ILvjXlSDM17XXHfrCLBtsUU3zzCLK/J9T ef9UBZY2olpKEd7ht1A/8TlhC1kqEEC9oIYFYQsNKs6Jk8ove20zgeikA3xj2CYxkXbO zMHUIXIfAbTARCxDP0AW/JF7zAV9tzOuTzyFefk+0CSMj4SAOnBVaEAfwATWfZZilmDL wk9pzeuCI/SaPjYb7C3LbaY0Vbagauaw2IKOnuZ3Jjs4R8cVXfp1yjdn6gHF0ZfG5iqX qIwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=llQtcWwNeSrJSmpF2SS5+s+znVWOvXUe+nYV4DkHFB4=; b=QCj+4yJcFAQ5Sie4Kmk/TzLxtwOhpY9mq1LXD3LY13NJvTZVbsRDFLkMxaMxT36y+C Vslh/Zzn54MZDz2n8S1F5luql/7fi6sM7C42XzqdYmyfnXiEKxpVM9gFL03WS4iLyred J1EwBJD/Ia+7FaNPPsyPgWTYdytCa1hd4NSit1/BafU3fwZWiVTPYW5l4ambDY9XgnkK p2AKAyJolGEmW8pvLvIrEW4uhuSSgHiNhM9KKxmRDyEvfd5pnbjBNKOem6jZZIV5jz20 nA+UhR8tVeo9XuKlzl+wAgQxYIxKDdPujvV/DYzRJLU0+Dd7syx3YXQmHUsg1jyUDuz1 T8og== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tBALSHNW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o15-20020ac87c4f000000b002f3efb90971si10431856qtv.145.2022.06.09.02.40.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:40:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tBALSHNW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEeD-00064w-V4 for patch@linaro.org; Thu, 09 Jun 2022 05:40:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39344) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE73-0001UF-4s for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:57 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:44816) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE71-00060e-Fu for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:05:56 -0400 Received: by mail-wr1-x433.google.com with SMTP id q15so23422931wrc.11 for ; Thu, 09 Jun 2022 02:05:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=llQtcWwNeSrJSmpF2SS5+s+znVWOvXUe+nYV4DkHFB4=; b=tBALSHNWAyN9UYpJHD52j7m83ptiodFB7YAUi+majjleYBx3mPloAHpiukNoXNZPJb spNWz7uajzeqcgJYdEfTOgIJe5WLsact9HM/liGCOiiHo6PDviZGc46J5hpoUzUzT2/h uCCvpwdKia4VN0f8tROT0570M12xTMRfFZkpguB9oQ1WUX0pQ5yQzBJksLXafaT+NqlD IrydJyLhuxRIPPT2sww2LP2WVqN4JwXAtW1CdLFUzK6ZAVEMAjJEI3SbJH3HHmvkcTCp klhe23xK0WUHQcwaIYhfhjrZd+LjRnRunmMZUwKblR7IypuETdhcUJPczPxEeD1NYsLI gtbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=llQtcWwNeSrJSmpF2SS5+s+znVWOvXUe+nYV4DkHFB4=; b=Zfh+1oFesjhyhsgvNQg8K2zgHKVDOynKUdoKbKRgGXFscQijb5lJy6/zdxWK5eHBT5 tfIDuDLicUUg6asFEqT74jOQu6qotxtxzAKvKcP3LAQ1yByDBPcWcMMayyJbmvaWTCm0 3pz0Zpdyt2pFWs0rdy2D11aMehq69DmFvMKOKjXtedqaxUG4pPBjT0G4t2jqgcLSi8L4 55qDwT4PvX7k6iqbZe8yk3l2ubqSD6/y1Zp38iecIubEOmulfzpXnoruA8w4URnK4xdU qOU1OCG+Biu7/6t/waHWfZrRYgiQyLHvlnc4eA3x4QesSQS95WChhb30AsBm6CrtuG+T eMxQ== X-Gm-Message-State: AOAM5303z5aUc0D/bUCal6Tc2V4AnFWmVOfow7ZZcAacU5AtN7ypEgXu qx0Tfcxt1t0QrfACMv3cfIthSLVolQ8BJQ== X-Received: by 2002:a5d:64c7:0:b0:218:4a82:ffa4 with SMTP id f7-20020a5d64c7000000b002184a82ffa4mr15854122wri.592.1654765554687; Thu, 09 Jun 2022 02:05:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/55] target/arm: Move get_phys_addr_pmsav7_default to ptw.c Date: Thu, 9 Jun 2022 10:04:55 +0100 Message-Id: <20220609090537.1971756-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-7-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 3 +++ target/arm/helper.c | 41 ----------------------------------------- target/arm/ptw.c | 41 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 41 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index 324a9dde140..d6e3fee1523 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -33,6 +33,9 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); } +void get_phys_addr_pmsav7_default(CPUARMState *env, + ARMMMUIdx mmu_idx, + int32_t address, int *prot); bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, diff --git a/target/arm/helper.c b/target/arm/helper.c index 5d010190108..d4f7c05625c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11678,47 +11678,6 @@ do_fault: return true; } -static inline void get_phys_addr_pmsav7_default(CPUARMState *env, - ARMMMUIdx mmu_idx, - int32_t address, int *prot) -{ - if (!arm_feature(env, ARM_FEATURE_M)) { - *prot = PAGE_READ | PAGE_WRITE; - switch (address) { - case 0xF0000000 ... 0xFFFFFFFF: - if (regime_sctlr(env, mmu_idx) & SCTLR_V) { - /* hivecs execing is ok */ - *prot |= PAGE_EXEC; - } - break; - case 0x00000000 ... 0x7FFFFFFF: - *prot |= PAGE_EXEC; - break; - } - } else { - /* Default system address map for M profile cores. - * The architecture specifies which regions are execute-never; - * at the MPU level no other checks are defined. - */ - switch (address) { - case 0x00000000 ... 0x1fffffff: /* ROM */ - case 0x20000000 ... 0x3fffffff: /* SRAM */ - case 0x60000000 ... 0x7fffffff: /* RAM */ - case 0x80000000 ... 0x9fffffff: /* RAM */ - *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - break; - case 0x40000000 ... 0x5fffffff: /* Peripheral */ - case 0xa0000000 ... 0xbfffffff: /* Device */ - case 0xc0000000 ... 0xdfffffff: /* Device */ - case 0xe0000000 ... 0xffffffff: /* System */ - *prot = PAGE_READ | PAGE_WRITE; - break; - default: - g_assert_not_reached(); - } - } -} - static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool is_user) { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5c32648a16a..74650c6c525 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -374,6 +374,47 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, return false; } +void get_phys_addr_pmsav7_default(CPUARMState *env, + ARMMMUIdx mmu_idx, + int32_t address, int *prot) +{ + if (!arm_feature(env, ARM_FEATURE_M)) { + *prot = PAGE_READ | PAGE_WRITE; + switch (address) { + case 0xF0000000 ... 0xFFFFFFFF: + if (regime_sctlr(env, mmu_idx) & SCTLR_V) { + /* hivecs execing is ok */ + *prot |= PAGE_EXEC; + } + break; + case 0x00000000 ... 0x7FFFFFFF: + *prot |= PAGE_EXEC; + break; + } + } else { + /* Default system address map for M profile cores. + * The architecture specifies which regions are execute-never; + * at the MPU level no other checks are defined. + */ + switch (address) { + case 0x00000000 ... 0x1fffffff: /* ROM */ + case 0x20000000 ... 0x3fffffff: /* SRAM */ + case 0x60000000 ... 0x7fffffff: /* RAM */ + case 0x80000000 ... 0x9fffffff: /* RAM */ + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + break; + case 0x40000000 ... 0x5fffffff: /* Peripheral */ + case 0xa0000000 ... 0xbfffffff: /* Device */ + case 0xc0000000 ... 0xdfffffff: /* Device */ + case 0xe0000000 ... 0xffffffff: /* System */ + *prot = PAGE_READ | PAGE_WRITE; + break; + default: + g_assert_not_reached(); + } + } +} + /** * get_phys_addr - get the physical address for this virtual address * From patchwork Thu Jun 9 09:04:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580270 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp637255max; Thu, 9 Jun 2022 03:21:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyEzcQ61UCaRW2XHCPCmijw0MFa9YL/1kfic13jeTPTXCd/k0nRVMiLOffBQr6QlQFdf0yh X-Received: by 2002:a05:620a:4150:b0:6a3:7c90:ee20 with SMTP id k16-20020a05620a415000b006a37c90ee20mr26419753qko.351.1654770109752; Thu, 09 Jun 2022 03:21:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654770109; cv=none; d=google.com; s=arc-20160816; b=rnV333kylT4u524K0Jtcs+4U8gMwnuLREuTexVJvweHGYIFKDPtZCJhdOBjXqHce1W OqjUcvYlaJCo6u+xGbaI5C4XpKrihoZp/YoTshSYbL8yyrTkIZK5Y90aEGYji1vIL3iC mCiSCE2+UNqsuQLshdOtzsXnZKdh5lBAcjj5KFEpsOv5MddeToUbRwSCeHjo5aDXAZLe cWEjkLj1mbvNhdMNH4YiEXHovaAumRp5ZmwClEvY1IVlIMAmf39h2mcXKoM3JFLVPWYV JWuefuZbXiR2ypgOzQ14c6bSh5TopHLzpVHi+0ARnQ33Ul0KbZ7oyxyiDs1PawfxqzGz 1MfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0Ac7KbUehUrhXzsuRCDQnaYGhbdKNCku5Way9XfeMZo=; b=vaN2urwlKxuE2gyB6fl73MI/4Jp6rCnbbIHxlJlugHqnMv5/jvhQHBQ20j8eYok+8y Uz9OIc36ghrqgV4I9JLSH97D8ylMYSiUb7YAVRgbLgBzUfhZxrgvBP+yKqlQMHUBAA2x GeKFmgEFWp5Dv8dI3dDkS7tuFCPT02JZehf8GOhtFc0mx7bEpnr09HgvfvYObf5ODog0 9ECH+fX7csKiPo/kmzDeEUCMH+AAZ+yIn/Q6zgj7LuGI23MeqVdiedUFNYoHx6ZtG8ry 4gfNI94L2YyAS/tjMeMV5Y5aBxam68J4/K0zHb3VomYEFGNOa7LfwyoeOro/XrbG8xPR Lffg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R7KO9PzZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b3-20020ac85bc3000000b00304b6c8bcc7si12782720qtb.209.2022.06.09.03.21.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:21:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R7KO9PzZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38938 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFIT-0003g7-1N for patch@linaro.org; Thu, 09 Jun 2022 06:21:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE79-0001Xq-5M for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:08 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:43532) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE72-0005uZ-QU for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:02 -0400 Received: by mail-wm1-x333.google.com with SMTP id 67-20020a1c1946000000b00397382b44f4so12289092wmz.2 for ; Thu, 09 Jun 2022 02:05:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0Ac7KbUehUrhXzsuRCDQnaYGhbdKNCku5Way9XfeMZo=; b=R7KO9PzZ/pB0nd8inZoLEQw0ERb5LxGezHzFfZC361K6hTCLflUmg4fD5FVfWn5oQn Rlv5MXYBbC19BRz77vAefjOmI2fPAikzp97igxl79mxolXePWfiTZEZOdyHf4AWeQxI0 7YvXGOmoGSMID+qEXOEsiNdS0vZq3pvNj5fgl+8rvf/YIYcItSqhR+NS8t76VY2SbfK4 VwGw19Cp3R7VhAh3FLJf5hxEmQPkEizbsHeNSCFtpc6D8uuAM191XOhgGZvNZV5OjXyL RZRuYhRCyr8FAcdD8f8hBhKiO+rjDT9E2kQUMC0+h4wlGSqKi2Sgp16eATPb8lTx/kSX DMcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Ac7KbUehUrhXzsuRCDQnaYGhbdKNCku5Way9XfeMZo=; b=XNWhLrXZTE7YlTCk6/bd0b27lDNDCLy6wz3QM3R/EIZtEB6r53B63Slh0b8ZuZrSOZ rF4/OGsrdn7Q0cXil5cpG5A8SCoxc0ltN+vv7MK7OuzRKDyu3SRqChO8DHkd++tHKDmg t0O0e/C9QnMivsmewIfztG0y9ei6I5wijDi7tDVCp4W2GbPvpxO8c++HHqQLrRxYPLLk LoGifJsCIBDVqdiQlGLmBbQg2sXYSAplaIQTdaZ3gsEZrJ7p2a59pbKswP9fvLg8UIvk rRJg3hnxkQcZ+IIUr+BcOpJ3s8/pM6lFHuC/+iBBapeE2zqTGc5qAZ20fAUcxJctRo0v 3jvw== X-Gm-Message-State: AOAM531P+3pvPzLxxzadFs8zZGuUXxO9JByQPfCJG3NSB30jUpvoMEWp xDNrjHmSUYRm3zfhjIesMOn97R4IV1lbFw== X-Received: by 2002:a05:600c:3d1b:b0:39b:1743:4d84 with SMTP id bh27-20020a05600c3d1b00b0039b17434d84mr2231723wmb.118.1654765555993; Thu, 09 Jun 2022 02:05:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/55] target/arm: Move get_phys_addr_pmsav7 to ptw.c Date: Thu, 9 Jun 2022 10:04:56 +0100 Message-Id: <20220609090537.1971756-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 10 +-- target/arm/helper.c | 194 +------------------------------------------- target/arm/ptw.c | 190 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 198 insertions(+), 196 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index d6e3fee1523..d24b7c263a8 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -33,14 +33,14 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); } +bool m_is_ppb_region(CPUARMState *env, uint32_t address); +bool m_is_system_region(CPUARMState *env, uint32_t address); + void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_idx, int32_t address, int *prot); -bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi); +bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool is_user); + bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, diff --git a/target/arm/helper.c b/target/arm/helper.c index d4f7c05625c..2ebaf694075 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11678,8 +11678,7 @@ do_fault: return true; } -static bool pmsav7_use_background_region(ARMCPU *cpu, - ARMMMUIdx mmu_idx, bool is_user) +bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool is_user) { /* Return true if we should use the default memory map as a * "background" region if there are no hits against any MPU regions. @@ -11698,14 +11697,14 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, } } -static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) +bool m_is_ppb_region(CPUARMState *env, uint32_t address) { /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */ return arm_feature(env, ARM_FEATURE_M) && extract32(address, 20, 12) == 0xe00; } -static inline bool m_is_system_region(CPUARMState *env, uint32_t address) +bool m_is_system_region(CPUARMState *env, uint32_t address) { /* True if address is in the M profile system region * 0xe0000000 - 0xffffffff @@ -11713,193 +11712,6 @@ static inline bool m_is_system_region(CPUARMState *env, uint32_t address) return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; } -bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi) -{ - ARMCPU *cpu = env_archcpu(env); - int n; - bool is_user = regime_is_user(env, mmu_idx); - - *phys_ptr = address; - *page_size = TARGET_PAGE_SIZE; - *prot = 0; - - if (regime_translation_disabled(env, mmu_idx) || - m_is_ppb_region(env, address)) { - /* MPU disabled or M profile PPB access: use default memory map. - * The other case which uses the default memory map in the - * v7M ARM ARM pseudocode is exception vector reads from the vector - * table. In QEMU those accesses are done in arm_v7m_load_vector(), - * which always does a direct read using address_space_ldl(), rather - * than going via this function, so we don't need to check that here. - */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); - } else { /* MPU enabled */ - for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { - /* region search */ - uint32_t base = env->pmsav7.drbar[n]; - uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); - uint32_t rmask; - bool srdis = false; - - if (!(env->pmsav7.drsr[n] & 0x1)) { - continue; - } - - if (!rsize) { - qemu_log_mask(LOG_GUEST_ERROR, - "DRSR[%d]: Rsize field cannot be 0\n", n); - continue; - } - rsize++; - rmask = (1ull << rsize) - 1; - - if (base & rmask) { - qemu_log_mask(LOG_GUEST_ERROR, - "DRBAR[%d]: 0x%" PRIx32 " misaligned " - "to DRSR region size, mask = 0x%" PRIx32 "\n", - n, base, rmask); - continue; - } - - if (address < base || address > base + rmask) { - /* - * Address not in this region. We must check whether the - * region covers addresses in the same page as our address. - * In that case we must not report a size that covers the - * whole page for a subsequent hit against a different MPU - * region or the background region, because it would result in - * incorrect TLB hits for subsequent accesses to addresses that - * are in this MPU region. - */ - if (ranges_overlap(base, rmask, - address & TARGET_PAGE_MASK, - TARGET_PAGE_SIZE)) { - *page_size = 1; - } - continue; - } - - /* Region matched */ - - if (rsize >= 8) { /* no subregions for regions < 256 bytes */ - int i, snd; - uint32_t srdis_mask; - - rsize -= 3; /* sub region size (power of 2) */ - snd = ((address - base) >> rsize) & 0x7; - srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); - - srdis_mask = srdis ? 0x3 : 0x0; - for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { - /* This will check in groups of 2, 4 and then 8, whether - * the subregion bits are consistent. rsize is incremented - * back up to give the region size, considering consistent - * adjacent subregions as one region. Stop testing if rsize - * is already big enough for an entire QEMU page. - */ - int snd_rounded = snd & ~(i - 1); - uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], - snd_rounded + 8, i); - if (srdis_mask ^ srdis_multi) { - break; - } - srdis_mask = (srdis_mask << i) | srdis_mask; - rsize++; - } - } - if (srdis) { - continue; - } - if (rsize < TARGET_PAGE_BITS) { - *page_size = 1 << rsize; - } - break; - } - - if (n == -1) { /* no hits */ - if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { - /* background fault */ - fi->type = ARMFault_Background; - return true; - } - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); - } else { /* a MPU hit! */ - uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); - uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1); - - if (m_is_system_region(env, address)) { - /* System space is always execute never */ - xn = 1; - } - - if (is_user) { /* User mode AP bit decoding */ - switch (ap) { - case 0: - case 1: - case 5: - break; /* no access */ - case 3: - *prot |= PAGE_WRITE; - /* fall through */ - case 2: - case 6: - *prot |= PAGE_READ | PAGE_EXEC; - break; - case 7: - /* for v7M, same as 6; for R profile a reserved value */ - if (arm_feature(env, ARM_FEATURE_M)) { - *prot |= PAGE_READ | PAGE_EXEC; - break; - } - /* fall through */ - default: - qemu_log_mask(LOG_GUEST_ERROR, - "DRACR[%d]: Bad value for AP bits: 0x%" - PRIx32 "\n", n, ap); - } - } else { /* Priv. mode AP bits decoding */ - switch (ap) { - case 0: - break; /* no access */ - case 1: - case 2: - case 3: - *prot |= PAGE_WRITE; - /* fall through */ - case 5: - case 6: - *prot |= PAGE_READ | PAGE_EXEC; - break; - case 7: - /* for v7M, same as 6; for R profile a reserved value */ - if (arm_feature(env, ARM_FEATURE_M)) { - *prot |= PAGE_READ | PAGE_EXEC; - break; - } - /* fall through */ - default: - qemu_log_mask(LOG_GUEST_ERROR, - "DRACR[%d]: Bad value for AP bits: 0x%" - PRIx32 "\n", n, ap); - } - } - - /* execute never */ - if (xn) { - *prot &= ~PAGE_EXEC; - } - } - } - - fi->type = ARMFault_Permission; - fi->level = 1; - return !(*prot & (1 << access_type)); -} - static bool v8m_is_sau_exempt(CPUARMState *env, uint32_t address, MMUAccessType access_type) { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 74650c6c525..27715dbfa8c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -8,6 +8,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/range.h" #include "cpu.h" #include "internals.h" #include "ptw.h" @@ -415,6 +416,195 @@ void get_phys_addr_pmsav7_default(CPUARMState *env, } } +static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi) +{ + ARMCPU *cpu = env_archcpu(env); + int n; + bool is_user = regime_is_user(env, mmu_idx); + + *phys_ptr = address; + *page_size = TARGET_PAGE_SIZE; + *prot = 0; + + if (regime_translation_disabled(env, mmu_idx) || + m_is_ppb_region(env, address)) { + /* + * MPU disabled or M profile PPB access: use default memory map. + * The other case which uses the default memory map in the + * v7M ARM ARM pseudocode is exception vector reads from the vector + * table. In QEMU those accesses are done in arm_v7m_load_vector(), + * which always does a direct read using address_space_ldl(), rather + * than going via this function, so we don't need to check that here. + */ + get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + } else { /* MPU enabled */ + for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { + /* region search */ + uint32_t base = env->pmsav7.drbar[n]; + uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); + uint32_t rmask; + bool srdis = false; + + if (!(env->pmsav7.drsr[n] & 0x1)) { + continue; + } + + if (!rsize) { + qemu_log_mask(LOG_GUEST_ERROR, + "DRSR[%d]: Rsize field cannot be 0\n", n); + continue; + } + rsize++; + rmask = (1ull << rsize) - 1; + + if (base & rmask) { + qemu_log_mask(LOG_GUEST_ERROR, + "DRBAR[%d]: 0x%" PRIx32 " misaligned " + "to DRSR region size, mask = 0x%" PRIx32 "\n", + n, base, rmask); + continue; + } + + if (address < base || address > base + rmask) { + /* + * Address not in this region. We must check whether the + * region covers addresses in the same page as our address. + * In that case we must not report a size that covers the + * whole page for a subsequent hit against a different MPU + * region or the background region, because it would result in + * incorrect TLB hits for subsequent accesses to addresses that + * are in this MPU region. + */ + if (ranges_overlap(base, rmask, + address & TARGET_PAGE_MASK, + TARGET_PAGE_SIZE)) { + *page_size = 1; + } + continue; + } + + /* Region matched */ + + if (rsize >= 8) { /* no subregions for regions < 256 bytes */ + int i, snd; + uint32_t srdis_mask; + + rsize -= 3; /* sub region size (power of 2) */ + snd = ((address - base) >> rsize) & 0x7; + srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); + + srdis_mask = srdis ? 0x3 : 0x0; + for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { + /* + * This will check in groups of 2, 4 and then 8, whether + * the subregion bits are consistent. rsize is incremented + * back up to give the region size, considering consistent + * adjacent subregions as one region. Stop testing if rsize + * is already big enough for an entire QEMU page. + */ + int snd_rounded = snd & ~(i - 1); + uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], + snd_rounded + 8, i); + if (srdis_mask ^ srdis_multi) { + break; + } + srdis_mask = (srdis_mask << i) | srdis_mask; + rsize++; + } + } + if (srdis) { + continue; + } + if (rsize < TARGET_PAGE_BITS) { + *page_size = 1 << rsize; + } + break; + } + + if (n == -1) { /* no hits */ + if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { + /* background fault */ + fi->type = ARMFault_Background; + return true; + } + get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + } else { /* a MPU hit! */ + uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); + uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1); + + if (m_is_system_region(env, address)) { + /* System space is always execute never */ + xn = 1; + } + + if (is_user) { /* User mode AP bit decoding */ + switch (ap) { + case 0: + case 1: + case 5: + break; /* no access */ + case 3: + *prot |= PAGE_WRITE; + /* fall through */ + case 2: + case 6: + *prot |= PAGE_READ | PAGE_EXEC; + break; + case 7: + /* for v7M, same as 6; for R profile a reserved value */ + if (arm_feature(env, ARM_FEATURE_M)) { + *prot |= PAGE_READ | PAGE_EXEC; + break; + } + /* fall through */ + default: + qemu_log_mask(LOG_GUEST_ERROR, + "DRACR[%d]: Bad value for AP bits: 0x%" + PRIx32 "\n", n, ap); + } + } else { /* Priv. mode AP bits decoding */ + switch (ap) { + case 0: + break; /* no access */ + case 1: + case 2: + case 3: + *prot |= PAGE_WRITE; + /* fall through */ + case 5: + case 6: + *prot |= PAGE_READ | PAGE_EXEC; + break; + case 7: + /* for v7M, same as 6; for R profile a reserved value */ + if (arm_feature(env, ARM_FEATURE_M)) { + *prot |= PAGE_READ | PAGE_EXEC; + break; + } + /* fall through */ + default: + qemu_log_mask(LOG_GUEST_ERROR, + "DRACR[%d]: Bad value for AP bits: 0x%" + PRIx32 "\n", n, ap); + } + } + + /* execute never */ + if (xn) { + *prot &= ~PAGE_EXEC; + } + } + } + + fi->type = ARMFault_Permission; + fi->level = 1; + return !(*prot & (1 << access_type)); +} + /** * get_phys_addr - get the physical address for this virtual address * From patchwork Thu Jun 9 09:04:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580248 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp605949max; Thu, 9 Jun 2022 02:36:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwLYMS2cxGbqKCMg8RSGeKDTLqXsob7pxZv2ia5jMsLSAs5nui80lITx4Qx3xc0vczPuf6m X-Received: by 2002:a37:2714:0:b0:6a6:b527:a472 with SMTP id n20-20020a372714000000b006a6b527a472mr15317038qkn.722.1654767375528; Thu, 09 Jun 2022 02:36:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654767375; cv=none; d=google.com; s=arc-20160816; b=h7TkeKl8WWg0QzYgqO9YNPONUbD6vc0IGKK+SoFW81ag3qQm5HOEieLpZ0Fc6gMoly RgwyTplrXjWi3PUoOVQCfeEOGSKkDAMJ7qCunJnW2id5YmpOsWOFsueG7DnaU77qvtvV kJduHwaviutCDgJ77D5bl7ssIDl1pG2RUjhuGrbvFte4v7nfu5cQtDecQ+UMbwiDwteo 06P+Nly8IOEyrpQeuqxQ2FO+PG+p2mxIBXkldaD+UVWLwD0985YciC5r00dwkzazk3cM DtI7/O41ubtWUjm9PUZNx/vSZRHq6CmiCTuWvzjfmNklxEiLhYqD2gDfZpYNE2w0jWkO +dUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0CrroLgAVXvSasQsUTUPnEeQd/AepQTm/OwhtRxFesc=; b=sZGVCoolg1M+DHtQhsZG/KIq97jPp/JMrqz2zZ0ZbnH+5015dhK6OK9ZfCKUhjn1VT LyNjXRYnRLNx+64E44KR9Cdy0Ucf/5EcAsD/XSBon2QC+EiGQZ7BnZ3ZJQZeJIEiQ3gS cKwxi3aN+/fHJByfyql5LBRGdWC9+qIS8MiUPWXG4EeyiFMhntXaE91/zwknB/Q6IeTN Qv9+hxCBYO9Kk7gAR37WA9w7R7tCqfcjwkHnm1fJYOim6mt8JJXGh3YseWJdKPvsNhMs jgJUer6fxclClkzLZz6otEPc/szEX7F0qeoYpFZKsk1TTvkssXXxQErz12HiH4CjG6ae QFFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oS8y6H0w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k13-20020a05622a03cd00b00304f3e3e96dsi4747462qtx.400.2022.06.09.02.36.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:36:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oS8y6H0w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEaN-0003cm-34 for patch@linaro.org; Thu, 09 Jun 2022 05:36:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39388) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE77-0001X7-3o for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:01 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:33250) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE75-000620-2C for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:00 -0400 Received: by mail-wm1-x335.google.com with SMTP id i17-20020a7bc951000000b0039c4760ec3fso594191wml.0 for ; Thu, 09 Jun 2022 02:05:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0CrroLgAVXvSasQsUTUPnEeQd/AepQTm/OwhtRxFesc=; b=oS8y6H0wz3miCZrehSvpsKh3E4CCBENGX9eKT4jV7y9XYRXYC1sFicKCHV6dDEirAL ZJGnUABEGeEkp+qysASvYMPtU7xR9w1lubLNvIuyUPO87abBD/NWxFrT+cCj2P6C6utE Z3edGgRmyDGfnOVoB+sEBfmlTpyHJCNCAt+A9MjPUQ3OL6lns1UTCUJu34FgvVlYiF+o WslEjfFr3k5YNcQvpHH2730M0E1Cey4r0k09Vn+VkuqBE93MTF9YogMlZsA7OZ4gkw9k c+BtND+LWBc2bJENbkJ+vyVKYm8kUtkqtpmNQU02fTqGMKit00vr+qkIgbXo4D9uAvud zbgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0CrroLgAVXvSasQsUTUPnEeQd/AepQTm/OwhtRxFesc=; b=YYiurH1qabR7SnBlRqTy/eMYJPaofvaAPFDwws1ezD/LA1e/YsVO7ALL08pjXc3T45 vrD0pEMZATsZ5sk3dthkuRnPVxKf7U0h/yuiIBLjxwKZcQK8sLSz3n5J3xvah1Jbzyi+ VumRqYEYhJKo4k2SeRkAdn5oLhMejsnDs0JTnZU8PvO2gszTU0j4AZi2FVbGVsQRh4Eb U4GCjPVSNBfJcwcKWFO7ENI8UoT+Kh3DpEx7TSHZREEy8tkZ/EIKxRGWed9e457u7Dts Lj/XbMOjQrNaatzX1Mz816MuVFisOe7+NWc8mclicqULB9Z8XGam6qfN+c7Nevz0eEku 3sew== X-Gm-Message-State: AOAM531xN9gfJ4iy9rV9Dt68JjcYVQccfDsQSwupfceI7RcMd7310fi1 DtdhpCsvamXsjKFOuIVTM9nuJWbqWZ6pUg== X-Received: by 2002:a7b:c04b:0:b0:39c:511e:2dd4 with SMTP id u11-20020a7bc04b000000b0039c511e2dd4mr2366777wmc.58.1654765557402; Thu, 09 Jun 2022 02:05:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/55] target/arm: Move get_phys_addr_pmsav8 to ptw.c Date: Thu, 9 Jun 2022 10:04:57 +0100 Message-Id: <20220609090537.1971756-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-9-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 5 --- target/arm/helper.c | 75 ------------------------------------------- target/arm/ptw.c | 77 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 77 insertions(+), 80 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index d24b7c263a8..d569507951f 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -41,11 +41,6 @@ void get_phys_addr_pmsav7_default(CPUARMState *env, int32_t address, int *prot); bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool is_user); -bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, target_ulong *page_size, - ARMMMUFaultInfo *fi); bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, bool s1_is_el0, diff --git a/target/arm/helper.c b/target/arm/helper.c index 2ebaf694075..44997fd179d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11970,81 +11970,6 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, return !(*prot & (1 << access_type)); } - -bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, target_ulong *page_size, - ARMMMUFaultInfo *fi) -{ - uint32_t secure = regime_is_secure(env, mmu_idx); - V8M_SAttributes sattrs = {}; - bool ret; - bool mpu_is_subpage; - - if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); - if (access_type == MMU_INST_FETCH) { - /* Instruction fetches always use the MMU bank and the - * transaction attribute determined by the fetch address, - * regardless of CPU state. This is painful for QEMU - * to handle, because it would mean we need to encode - * into the mmu_idx not just the (user, negpri) information - * for the current security state but also that for the - * other security state, which would balloon the number - * of mmu_idx values needed alarmingly. - * Fortunately we can avoid this because it's not actually - * possible to arbitrarily execute code from memory with - * the wrong security attribute: it will always generate - * an exception of some kind or another, apart from the - * special case of an NS CPU executing an SG instruction - * in S&NSC memory. So we always just fail the translation - * here and sort things out in the exception handler - * (including possibly emulating an SG instruction). - */ - if (sattrs.ns != !secure) { - if (sattrs.nsc) { - fi->type = ARMFault_QEMU_NSCExec; - } else { - fi->type = ARMFault_QEMU_SFault; - } - *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; - *phys_ptr = address; - *prot = 0; - return true; - } - } else { - /* For data accesses we always use the MMU bank indicated - * by the current CPU state, but the security attributes - * might downgrade a secure access to nonsecure. - */ - if (sattrs.ns) { - txattrs->secure = false; - } else if (!secure) { - /* NS access to S memory must fault. - * Architecturally we should first check whether the - * MPU information for this address indicates that we - * are doing an unaligned access to Device memory, which - * should generate a UsageFault instead. QEMU does not - * currently check for that kind of unaligned access though. - * If we added it we would need to do so as a special case - * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). - */ - fi->type = ARMFault_QEMU_SFault; - *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; - *phys_ptr = address; - *prot = 0; - return true; - } - } - } - - ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, - txattrs, prot, &mpu_is_subpage, fi, NULL); - *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; - return ret; -} - /* Combine either inner or outer cacheability attributes for normal * memory, according to table D4-42 and pseudocode procedure * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 27715dbfa8c..28caa7a7ae0 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -605,6 +605,83 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, return !(*prot & (1 << access_type)); } +static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *txattrs, + int *prot, target_ulong *page_size, + ARMMMUFaultInfo *fi) +{ + uint32_t secure = regime_is_secure(env, mmu_idx); + V8M_SAttributes sattrs = {}; + bool ret; + bool mpu_is_subpage; + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); + if (access_type == MMU_INST_FETCH) { + /* + * Instruction fetches always use the MMU bank and the + * transaction attribute determined by the fetch address, + * regardless of CPU state. This is painful for QEMU + * to handle, because it would mean we need to encode + * into the mmu_idx not just the (user, negpri) information + * for the current security state but also that for the + * other security state, which would balloon the number + * of mmu_idx values needed alarmingly. + * Fortunately we can avoid this because it's not actually + * possible to arbitrarily execute code from memory with + * the wrong security attribute: it will always generate + * an exception of some kind or another, apart from the + * special case of an NS CPU executing an SG instruction + * in S&NSC memory. So we always just fail the translation + * here and sort things out in the exception handler + * (including possibly emulating an SG instruction). + */ + if (sattrs.ns != !secure) { + if (sattrs.nsc) { + fi->type = ARMFault_QEMU_NSCExec; + } else { + fi->type = ARMFault_QEMU_SFault; + } + *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; + *phys_ptr = address; + *prot = 0; + return true; + } + } else { + /* + * For data accesses we always use the MMU bank indicated + * by the current CPU state, but the security attributes + * might downgrade a secure access to nonsecure. + */ + if (sattrs.ns) { + txattrs->secure = false; + } else if (!secure) { + /* + * NS access to S memory must fault. + * Architecturally we should first check whether the + * MPU information for this address indicates that we + * are doing an unaligned access to Device memory, which + * should generate a UsageFault instead. QEMU does not + * currently check for that kind of unaligned access though. + * If we added it we would need to do so as a special case + * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). + */ + fi->type = ARMFault_QEMU_SFault; + *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; + *phys_ptr = address; + *prot = 0; + return true; + } + } + } + + ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, + txattrs, prot, &mpu_is_subpage, fi, NULL); + *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; + return ret; +} + /** * get_phys_addr - get the physical address for this virtual address * From patchwork Thu Jun 9 09:04:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580262 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp624415max; Thu, 9 Jun 2022 03:04:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzo3tKT4b6/2qF6kiTvS7KOJOmaaan7zkQYQXS5NgE48ibp5kiztQgxWAPpPl4jaSYgTvio X-Received: by 2002:a05:620a:248f:b0:6a6:ee8e:712e with SMTP id i15-20020a05620a248f00b006a6ee8e712emr7850832qkn.690.1654769049379; Thu, 09 Jun 2022 03:04:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654769049; cv=none; d=google.com; s=arc-20160816; b=SgcNj0neTLH5Y4a7GX0wrqti+PfjXO/DizZSf9+jLJjF7gkAtq8gaIxDvjEHiIXHfg 9urEblU51U2SB+8NJ6gkMv4QLTYU+mnjS1u+gHA5yuIXv7dnOuscM2fn+WpOF+D62fP2 ZH3VnXglawYtUiEWqTbuBooJ3EwaUwGqYiWJjlh9VouIBGCrU90xrFaq5chXI8PIfmug 5LX2mGIzcNWx2MYUgNFgFL1n8AFPIztWmQjrl8tOw7gtMfsy8gZ4F2k89Fi7RM5njAbO peOld5fZclRtZUWbZC+Jm087oGBd6PB85mGQn2b0QOdATd4v7cdZWE0muJWOYPJo8IuV N2Vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7p331RrRhxlmCYz1Fu61IkjHxiG1EXhXcEiGzFLN0kw=; b=ZstxSbHGkvXbv9ZIa1Uz2tSpcK8iSB+PM8GhfTmbHVEgVq5hsj+gD16DqSUXZvm0t0 ZAhGDS6AGg8gGkEbV4gCfebUNrIlBphwWBFMhJbbONFxRsI7VkRPrmRBqJf7cBRkVqe4 1tBI7pWoqB98XzRmZsTfq+km8xpk9XgkIafoh9tqGs3bx8IaYd+vlnq1ldYFBrDiFVA1 Qupvw6DbLUvoH4GRFABYdXm5U95ojoNkOH+uNCfH349ZhzoKqhHkZGV0Wy0L9ML6dQ8F QvGqiycSX2sh0pWMZBFFNi/8hdSPjjiAV01EZCVm3jn+UoO21RGI3QhvzcjAaHeaklRn PmXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Nzac9gLV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p11-20020ad45f4b000000b0046370bf7ceasi12219526qvg.459.2022.06.09.03.04.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:04:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Nzac9gLV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50144 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzF1M-0007NF-TR for patch@linaro.org; Thu, 09 Jun 2022 06:04:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39396) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE77-0001XE-Ko for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:01 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:34742) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE75-0005zr-Fk for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:01 -0400 Received: by mail-wr1-x42b.google.com with SMTP id q26so21096176wra.1 for ; Thu, 09 Jun 2022 02:05:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7p331RrRhxlmCYz1Fu61IkjHxiG1EXhXcEiGzFLN0kw=; b=Nzac9gLVaxxc32tKrtQRJAZuVDIlh9ntgDd7nqzjeEZGkyB3+ttOeAzGG0C0KS8Fku uZHHp35VMOXdSQpOzFmKThuy7hip9G2q+91v29aIF5WY+1CNviyEMy43+O8lGcihvi+Z DRQwJLFknxYYjC/LmP4t6P5Fa3r27PPNXZ6k2S+EmAdFKRcAHMeqcTmjmfYCr+HuuUqp BsSuu6aInbx8xqVdQl4sMCoCRLmCYYWSHgI1Xnt2c/BFZ1Ce/driy9R1DbRzjehma6L8 n08XOq9DGzM6s6MB5F4SfQMDT9YsyeTnxslgrDHms4d0OH9Z/DVNTjS1c95fhxZvehxz naew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7p331RrRhxlmCYz1Fu61IkjHxiG1EXhXcEiGzFLN0kw=; b=r+Dnfm/BX7Diqz9uDfpoKLglXnpO4Odh/5MkgcV1sW8k394fQ6lKJt4MVOiHWL0enV 2DHH/TLmR+9PeWTEZZUPXMPukiOvECrQgwpBjC92GbRcRiTNRC0TMsN3fgle5ksXzE4Q GihwMMav+iXnKzOL17ke9SlfoNX0i9tYBe8aYUH97PBcrY7SV0DsHo/FOadUabBaTlHb c71eqB5BfYDhLqEIScrJBnMPx2I3E0nD1UBPhHZOEMkuQwIw/T/Gd4dTMeLzOqqSo4VF QioSYYbrdqDIqmMYBFvX1qrWU39TJuiDwZW6z4jLIZBVTsVumuT5rkSGBvzUwZfYja5n ihBw== X-Gm-Message-State: AOAM531F66Yceor/PpQSmUrNPlIq+dASWxUbGw5kf+COxQKP6oBs6nNK H/ZSZFK02ZcP2rmrd8l7OF5tK6mslnMg/w== X-Received: by 2002:a5d:67c2:0:b0:215:7a0f:71f9 with SMTP id n2-20020a5d67c2000000b002157a0f71f9mr30972761wrw.486.1654765558598; Thu, 09 Jun 2022 02:05:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/55] target/arm: Move pmsav8_mpu_lookup to ptw.c Date: Thu, 9 Jun 2022 10:04:58 +0100 Message-Id: <20220609090537.1971756-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This is the final user of get_phys_addr_pmsav7_default within helper.c, so make it static within ptw.c. Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-10-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 3 - target/arm/helper.c | 136 ----------------------------------------- target/arm/ptw.c | 146 +++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 143 insertions(+), 142 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index d569507951f..8d2e2397147 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -36,9 +36,6 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) bool m_is_ppb_region(CPUARMState *env, uint32_t address); bool m_is_system_region(CPUARMState *env, uint32_t address); -void get_phys_addr_pmsav7_default(CPUARMState *env, - ARMMMUIdx mmu_idx, - int32_t address, int *prot); bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool is_user); bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, diff --git a/target/arm/helper.c b/target/arm/helper.c index 44997fd179d..cb23413d8e5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11834,142 +11834,6 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address, } } -bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion) -{ - /* Perform a PMSAv8 MPU lookup (without also doing the SAU check - * that a full phys-to-virt translation does). - * mregion is (if not NULL) set to the region number which matched, - * or -1 if no region number is returned (MPU off, address did not - * hit a region, address hit in multiple regions). - * We set is_subpage to true if the region hit doesn't cover the - * entire TARGET_PAGE the address is within. - */ - ARMCPU *cpu = env_archcpu(env); - bool is_user = regime_is_user(env, mmu_idx); - uint32_t secure = regime_is_secure(env, mmu_idx); - int n; - int matchregion = -1; - bool hit = false; - uint32_t addr_page_base = address & TARGET_PAGE_MASK; - uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); - - *is_subpage = false; - *phys_ptr = address; - *prot = 0; - if (mregion) { - *mregion = -1; - } - - /* Unlike the ARM ARM pseudocode, we don't need to check whether this - * was an exception vector read from the vector table (which is always - * done using the default system address map), because those accesses - * are done in arm_v7m_load_vector(), which always does a direct - * read using address_space_ldl(), rather than going via this function. - */ - if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ - hit = true; - } else if (m_is_ppb_region(env, address)) { - hit = true; - } else { - if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { - hit = true; - } - - for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { - /* region search */ - /* Note that the base address is bits [31:5] from the register - * with bits [4:0] all zeroes, but the limit address is bits - * [31:5] from the register with bits [4:0] all ones. - */ - uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f; - uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f; - - if (!(env->pmsav8.rlar[secure][n] & 0x1)) { - /* Region disabled */ - continue; - } - - if (address < base || address > limit) { - /* - * Address not in this region. We must check whether the - * region covers addresses in the same page as our address. - * In that case we must not report a size that covers the - * whole page for a subsequent hit against a different MPU - * region or the background region, because it would result in - * incorrect TLB hits for subsequent accesses to addresses that - * are in this MPU region. - */ - if (limit >= base && - ranges_overlap(base, limit - base + 1, - addr_page_base, - TARGET_PAGE_SIZE)) { - *is_subpage = true; - } - continue; - } - - if (base > addr_page_base || limit < addr_page_limit) { - *is_subpage = true; - } - - if (matchregion != -1) { - /* Multiple regions match -- always a failure (unlike - * PMSAv7 where highest-numbered-region wins) - */ - fi->type = ARMFault_Permission; - fi->level = 1; - return true; - } - - matchregion = n; - hit = true; - } - } - - if (!hit) { - /* background fault */ - fi->type = ARMFault_Background; - return true; - } - - if (matchregion == -1) { - /* hit using the background region */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); - } else { - uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); - uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); - bool pxn = false; - - if (arm_feature(env, ARM_FEATURE_V8_1M)) { - pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); - } - - if (m_is_system_region(env, address)) { - /* System space is always execute never */ - xn = 1; - } - - *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); - if (*prot && !xn && !(pxn && !is_user)) { - *prot |= PAGE_EXEC; - } - /* We don't need to look the attribute up in the MAIR0/MAIR1 - * registers because that only tells us about cacheability. - */ - if (mregion) { - *mregion = matchregion; - } - } - - fi->type = ARMFault_Permission; - fi->level = 1; - return !(*prot & (1 << access_type)); -} - /* Combine either inner or outer cacheability attributes for normal * memory, according to table D4-42 and pseudocode procedure * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 28caa7a7ae0..989e783cce9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -375,9 +375,8 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, return false; } -void get_phys_addr_pmsav7_default(CPUARMState *env, - ARMMMUIdx mmu_idx, - int32_t address, int *prot) +static void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_idx, + int32_t address, int *prot) { if (!arm_feature(env, ARM_FEATURE_M)) { *prot = PAGE_READ | PAGE_WRITE; @@ -605,6 +604,147 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, return !(*prot & (1 << access_type)); } +bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *txattrs, + int *prot, bool *is_subpage, + ARMMMUFaultInfo *fi, uint32_t *mregion) +{ + /* + * Perform a PMSAv8 MPU lookup (without also doing the SAU check + * that a full phys-to-virt translation does). + * mregion is (if not NULL) set to the region number which matched, + * or -1 if no region number is returned (MPU off, address did not + * hit a region, address hit in multiple regions). + * We set is_subpage to true if the region hit doesn't cover the + * entire TARGET_PAGE the address is within. + */ + ARMCPU *cpu = env_archcpu(env); + bool is_user = regime_is_user(env, mmu_idx); + uint32_t secure = regime_is_secure(env, mmu_idx); + int n; + int matchregion = -1; + bool hit = false; + uint32_t addr_page_base = address & TARGET_PAGE_MASK; + uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); + + *is_subpage = false; + *phys_ptr = address; + *prot = 0; + if (mregion) { + *mregion = -1; + } + + /* + * Unlike the ARM ARM pseudocode, we don't need to check whether this + * was an exception vector read from the vector table (which is always + * done using the default system address map), because those accesses + * are done in arm_v7m_load_vector(), which always does a direct + * read using address_space_ldl(), rather than going via this function. + */ + if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ + hit = true; + } else if (m_is_ppb_region(env, address)) { + hit = true; + } else { + if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { + hit = true; + } + + for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { + /* region search */ + /* + * Note that the base address is bits [31:5] from the register + * with bits [4:0] all zeroes, but the limit address is bits + * [31:5] from the register with bits [4:0] all ones. + */ + uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f; + uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f; + + if (!(env->pmsav8.rlar[secure][n] & 0x1)) { + /* Region disabled */ + continue; + } + + if (address < base || address > limit) { + /* + * Address not in this region. We must check whether the + * region covers addresses in the same page as our address. + * In that case we must not report a size that covers the + * whole page for a subsequent hit against a different MPU + * region or the background region, because it would result in + * incorrect TLB hits for subsequent accesses to addresses that + * are in this MPU region. + */ + if (limit >= base && + ranges_overlap(base, limit - base + 1, + addr_page_base, + TARGET_PAGE_SIZE)) { + *is_subpage = true; + } + continue; + } + + if (base > addr_page_base || limit < addr_page_limit) { + *is_subpage = true; + } + + if (matchregion != -1) { + /* + * Multiple regions match -- always a failure (unlike + * PMSAv7 where highest-numbered-region wins) + */ + fi->type = ARMFault_Permission; + fi->level = 1; + return true; + } + + matchregion = n; + hit = true; + } + } + + if (!hit) { + /* background fault */ + fi->type = ARMFault_Background; + return true; + } + + if (matchregion == -1) { + /* hit using the background region */ + get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + } else { + uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); + uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); + bool pxn = false; + + if (arm_feature(env, ARM_FEATURE_V8_1M)) { + pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); + } + + if (m_is_system_region(env, address)) { + /* System space is always execute never */ + xn = 1; + } + + *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); + if (*prot && !xn && !(pxn && !is_user)) { + *prot |= PAGE_EXEC; + } + /* + * We don't need to look the attribute up in the MAIR0/MAIR1 + * registers because that only tells us about cacheability. + */ + if (mregion) { + *mregion = matchregion; + } + } + + fi->type = ARMFault_Permission; + fi->level = 1; + return !(*prot & (1 << access_type)); +} + static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, From patchwork Thu Jun 9 09:04:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580266 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp631107max; Thu, 9 Jun 2022 03:12:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy5zJ/Mt4PLtUNuh6SNv1ZQQoA+ywQVWtcw/YKQpKvBUZsAbQmEgVWO4I4j6t1y7E1QI+kS X-Received: by 2002:ac8:7d88:0:b0:304:ec4a:91b5 with SMTP id c8-20020ac87d88000000b00304ec4a91b5mr16750846qtd.500.1654769570905; Thu, 09 Jun 2022 03:12:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654769570; cv=none; d=google.com; s=arc-20160816; b=oMOlQ1pr5ZStKYfSX0Yx/RpAcTxZ0u1tlC3tavsElZ7D6c7lWQFXjDmWslZTiBDvd2 9r1gyNjt0Kc6vjqjZCGcGlUYUV65tqkrCDufe59MhalTkB8CN8m+R4tlFWEBbdwsCAQz IGJzFVGWqBMfIOefhvnMQ05OqudvyKmoIGHbDTpUzoYmXK2+o/ztKQWoNjcjSUelgYVT 35vd5B0E2ZM9100zQfH9ZzavKh8Rgkkt3iOGE5DnLAV3JRabKtbpjmskgdHvKH7Bi0ow JELopi/7P8m04LvmJEVVnaV1tYogfvELWNX+yeRqrjLqjK8Wy9Tl3QRKFtj3WnXm2vdy sp2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EUZ/tNvP5WO5oV5qgdTYHUfZb+lkPxFhWBi0KRDzQ54=; b=hlp6bVsL94q5n8VfSesjG/BiquAzuO8GBsASWG3fP2A+ZWSsc177f80WmbgMagLbkI t+Gx4IaRgIxnddioQf1kXb18FctZAbFajeRpDfbP/RdwxRSiUBZHBxRhf0viDxD577p6 hopuHbzsK4ShXE9VPwCTq2G4e8IDfWvQ+bVhRrFoGuruWNhtRGdoQyJhEMF1NOkbUVWh 2WHbLy+DXX1tBNob5MIQN0xqYvnf7L+YKXgBFT+LB1tTotiqOzfGyF/+FsEVjig+Zkmm Lds/W9tFsVxsikRZHL7jt6VKq09olZ0YqnXkJPjd0rvH0+9HCSyj+FwjT9Mbiherd+T1 fKrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OpoQr7bA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ib13-20020a0562141c8d00b004646640422csi12639679qvb.593.2022.06.09.03.12.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:12:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OpoQr7bA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzF9m-00061a-F5 for patch@linaro.org; Thu, 09 Jun 2022 06:12:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39406) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE78-0001Xj-DK for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:06 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:46807) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE76-0005v7-GQ for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:02 -0400 Received: by mail-wr1-x429.google.com with SMTP id u8so27137454wrm.13 for ; Thu, 09 Jun 2022 02:05:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=EUZ/tNvP5WO5oV5qgdTYHUfZb+lkPxFhWBi0KRDzQ54=; b=OpoQr7bAeWcoudBuNJFoIyB0bBeEnTOXTh5O2Oo/GSnqeByeknfak96HCpU5qNLrVa mCNy+IMhwcj5NUs5vs2VD/bBNlIEM7k197t+JGt2fd9jEoqbDYhYlTV7hOoq6B83WuAt 26NCs/NVhF7VW2un4XXQT2A53kyhtXtmDxV0//YhxpEPYDNw/9f+ca3WUrzp49jyufLX EhYgNP/4ScZlFjVd8KD7pViHdwyh8YNQuPvH0k3+lf6U6GViuiKpn+Kb+9iivTfXbIZE DUZQEvqnJ7GbHUkJGppHZfynaeNRsUB+1L9PoBFJUXgSQ2QQ4ivF/R9FtMdQ6yS5KWIW /0gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EUZ/tNvP5WO5oV5qgdTYHUfZb+lkPxFhWBi0KRDzQ54=; b=ZLAp3AJX/4h3k0bb1ToU+9rOeT20QUyXFKg0/aurqQ5HV4fj38PJFYy7ZwnxzoPnQX nCBVQMJS52spn+gamLBvnU7GiGSfi8grZVm62YGbV2j7Scfc7bGNuk9qgoueuTfzNdx6 MtEyN+ZTGfz5WfeH+uFTRLutltVhbcIcN0t3DzhCmZ72CT98/N24up7UlE44GhM4IOWQ Sag6HgrnQ+CfIwUO+uOysnK8CpTgPBrQFOvFe6mdAz4Dz8X3JJ2sKKig2JHB7dh4969z 01IehT9T4Kh6ysnFtExhTSRtyJMoiqzqRFrJcnhyAltqBQ97IWNwH3dl2jlBpz/TPOWK fCBQ== X-Gm-Message-State: AOAM530U5h4xuGZMQPMOqgfbD86kegzVkdQwrW+A+3GX+V2rBebkhzy4 4sIBtJBelf+j4ZeI/Y0et2EvtdCLhjY3ng== X-Received: by 2002:a5d:620b:0:b0:210:11d9:770 with SMTP id y11-20020a5d620b000000b0021011d90770mr37269450wru.11.1654765559590; Thu, 09 Jun 2022 02:05:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:05:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/55] target/arm: Move pmsav7_use_background_region to ptw.c Date: Thu, 9 Jun 2022 10:04:59 +0100 Message-Id: <20220609090537.1971756-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-11-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 2 -- target/arm/helper.c | 19 ------------------- target/arm/ptw.c | 21 +++++++++++++++++++++ 3 files changed, 21 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index 8d2e2397147..d2d27119082 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -36,8 +36,6 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) bool m_is_ppb_region(CPUARMState *env, uint32_t address); bool m_is_system_region(CPUARMState *env, uint32_t address); -bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool is_user); - bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, bool s1_is_el0, diff --git a/target/arm/helper.c b/target/arm/helper.c index cb23413d8e5..62e48f0925c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11678,25 +11678,6 @@ do_fault: return true; } -bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool is_user) -{ - /* Return true if we should use the default memory map as a - * "background" region if there are no hits against any MPU regions. - */ - CPUARMState *env = &cpu->env; - - if (is_user) { - return false; - } - - if (arm_feature(env, ARM_FEATURE_M)) { - return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] - & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; - } else { - return regime_sctlr(env, mmu_idx) & SCTLR_BR; - } -} - bool m_is_ppb_region(CPUARMState *env, uint32_t address) { /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 989e783cce9..b82638b5a06 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -415,6 +415,27 @@ static void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_idx, } } +static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, + bool is_user) +{ + /* + * Return true if we should use the default memory map as a + * "background" region if there are no hits against any MPU regions. + */ + CPUARMState *env = &cpu->env; + + if (is_user) { + return false; + } + + if (arm_feature(env, ARM_FEATURE_M)) { + return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] + & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; + } else { + return regime_sctlr(env, mmu_idx) & SCTLR_BR; + } +} + static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, From patchwork Thu Jun 9 09:05:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580237 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp591888max; Thu, 9 Jun 2022 02:13:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJza/SqMIYajuy0w+yzbUWlx8shnyS9i68xj3TYoXaK8tdSAzepvAXvcemE2IS99yjS3DT2H X-Received: by 2002:a05:620a:444b:b0:6a6:d37d:4e55 with SMTP id w11-20020a05620a444b00b006a6d37d4e55mr10313926qkp.138.1654766028306; Thu, 09 Jun 2022 02:13:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654766028; cv=none; d=google.com; s=arc-20160816; b=EA3QD9Hd6MGy2P5MqrzfzZtSmsElt+S3rZHGnw9s7/cdNbapeC+eAXbmloEdmahFAE 7WjK4jQCiQ/8iZyI9NT40nuPe1xIlvyNJQBW/o5/41cdyRqsZRxc6ljMGYsw3BrS1C/C ZJITB31UuFpNVYu4kQ3MEKyr4zi0obQOUaIr/dbNF7EB0omDEuIGzE/ROCGBqPPD5R0z mh4ZxjWSLafbWpBE+bX1nuNLKuo4YrdV1a404TQcmmmqfsIDINDLTKwBcL7s5YlPwWyk rOfy5UAR7vDc37Ds4Mi8qN4g43vDGeFUGdYmiumaWcweVXNFxfgJmKVbPOUyfJbCs0l/ HhwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PQxd2r1Hvfyyf27MTzwwWzDTkgYpufX1zJ4GE3JaSv0=; b=eNm9Y6m0xsoKgyDQiuk4Ru6DQ8ze8uxqIVvkSISbO785sxAlCweZ3d+SI9N3UPbTxd 1PSGdGUqBacNymI5grbW5lPKbeGv/auu1D+KVX8E7vRDLoGQThpx40dhzl65o2HzwOYI 9GW1+bFyec7aCdnNPTXHm5bRGMWSNNfm1qagf4BKwZwO/biAEiu0Uw8qjqiQRUqtkLib i8csfu++2m75kMIG1zabwDXa/FGFIRzbGG4WpxrTMPPWxtdFs/S3ikcoshoLfVH/W8nI +k38IuHEhnmM9lxpEEnhVaEozdYTXnUcKwjAsmNlwOZPgsACeAZK/fQ7f4lOipAPqG6t 1mcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dIKXG3Or; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w22-20020ac857d6000000b0030514468474si50501qta.512.2022.06.09.02.13.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:13:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dIKXG3Or; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52660 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEEc-0001ed-5S for patch@linaro.org; Thu, 09 Jun 2022 05:13:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39428) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE79-0001Xr-LQ for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:08 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:42899) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE77-00060y-Js for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:03 -0400 Received: by mail-wr1-x432.google.com with SMTP id s1so8358409wra.9 for ; Thu, 09 Jun 2022 02:06:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PQxd2r1Hvfyyf27MTzwwWzDTkgYpufX1zJ4GE3JaSv0=; b=dIKXG3OrPBWVrRHvaF6E0lPpMDMtut+AS/r6i2ObQqKYW9GfYvKY9l05PE9qvlyc3I RdznEX0cokNLSJ0s8ApqzczHhyfjfTc9//ASO5/tQI/H8sP7t+7eBCEUPc65E2KTS+1n VQoors/20iEudqdgTxeMY4PhB9ShKb9u5saTCqwStuRXYKFiyjh9susS3KNpI1E7v2fK Q4/KHMs9fPHbSb0YQhe2OvMFM0Wt6Hv91W6OTVtlns32p2Q56TSCLwy5WcCU+Gu0/amw 1z5SkDK+TYUQlD+ys7uExbApmGgZBoVh3DnfBLp9moC0XbpjfiPYaGxd8+40WjVNYwVm zpjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PQxd2r1Hvfyyf27MTzwwWzDTkgYpufX1zJ4GE3JaSv0=; b=IN+R0SUZ4IFxVjCLW7qF1Il+YWY+IJd6LMxYqKtI/pzLBwG3/rbDnTqFYuBl4JUiev NGlpMSKOytvYzxJePwW21HP++yr7uZRsk7qeebvAt5RIJP63qmsfPWlfOrpHJkyWul63 RPGYyeAx3ILhSR9Q+aWISkyZ/bzZYBR44cxOqAKd0fnQqLo8no0fonj2de8dwLYJjhCk tJaL8cF3ui014ZyapJd83rRZPOAg6Rxv0DdadUbN+0oeOZ/MPQjjhxBQxGcoPrNKdSAZ I0fUufDpE9jlm2giyUasUz762lRbEE3B0hLDN6eRPhC/jiXgfeIqLHLNKdYVffG6PCEA B+Aw== X-Gm-Message-State: AOAM530wcQZWFhxtw3ZC3cQfhvSTAZC9/J75L+TJajyC4OQM/BRIiL+w AvfgJnv3HRdiju8msnLnslp4TDws5fsYyA== X-Received: by 2002:a5d:5281:0:b0:20c:d5be:331c with SMTP id c1-20020a5d5281000000b0020cd5be331cmr37224786wrv.9.1654765560628; Thu, 09 Jun 2022 02:06:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.05.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/55] target/arm: Move v8m_security_lookup to ptw.c Date: Thu, 9 Jun 2022 10:05:00 +0100 Message-Id: <20220609090537.1971756-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This function has one private helper, v8m_is_sau_exempt, so move that at the same time. Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-12-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 123 ------------------------------------------ target/arm/ptw.c | 126 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 126 insertions(+), 123 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 62e48f0925c..d6a749ad0ed 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9,7 +9,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qemu/log.h" -#include "target/arm/idau.h" #include "trace.h" #include "cpu.h" #include "internals.h" @@ -11693,128 +11692,6 @@ bool m_is_system_region(CPUARMState *env, uint32_t address) return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; } -static bool v8m_is_sau_exempt(CPUARMState *env, - uint32_t address, MMUAccessType access_type) -{ - /* The architecture specifies that certain address ranges are - * exempt from v8M SAU/IDAU checks. - */ - return - (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) || - (address >= 0xe0000000 && address <= 0xe0002fff) || - (address >= 0xe000e000 && address <= 0xe000efff) || - (address >= 0xe002e000 && address <= 0xe002efff) || - (address >= 0xe0040000 && address <= 0xe0041fff) || - (address >= 0xe00ff000 && address <= 0xe00fffff); -} - -void v8m_security_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - V8M_SAttributes *sattrs) -{ - /* Look up the security attributes for this address. Compare the - * pseudocode SecurityCheck() function. - * We assume the caller has zero-initialized *sattrs. - */ - ARMCPU *cpu = env_archcpu(env); - int r; - bool idau_exempt = false, idau_ns = true, idau_nsc = true; - int idau_region = IREGION_NOTVALID; - uint32_t addr_page_base = address & TARGET_PAGE_MASK; - uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); - - if (cpu->idau) { - IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau); - IDAUInterface *ii = IDAU_INTERFACE(cpu->idau); - - iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, - &idau_nsc); - } - - if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { - /* 0xf0000000..0xffffffff is always S for insn fetches */ - return; - } - - if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { - sattrs->ns = !regime_is_secure(env, mmu_idx); - return; - } - - if (idau_region != IREGION_NOTVALID) { - sattrs->irvalid = true; - sattrs->iregion = idau_region; - } - - switch (env->sau.ctrl & 3) { - case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */ - break; - case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */ - sattrs->ns = true; - break; - default: /* SAU.ENABLE == 1 */ - for (r = 0; r < cpu->sau_sregion; r++) { - if (env->sau.rlar[r] & 1) { - uint32_t base = env->sau.rbar[r] & ~0x1f; - uint32_t limit = env->sau.rlar[r] | 0x1f; - - if (base <= address && limit >= address) { - if (base > addr_page_base || limit < addr_page_limit) { - sattrs->subpage = true; - } - if (sattrs->srvalid) { - /* If we hit in more than one region then we must report - * as Secure, not NS-Callable, with no valid region - * number info. - */ - sattrs->ns = false; - sattrs->nsc = false; - sattrs->sregion = 0; - sattrs->srvalid = false; - break; - } else { - if (env->sau.rlar[r] & 2) { - sattrs->nsc = true; - } else { - sattrs->ns = true; - } - sattrs->srvalid = true; - sattrs->sregion = r; - } - } else { - /* - * Address not in this region. We must check whether the - * region covers addresses in the same page as our address. - * In that case we must not report a size that covers the - * whole page for a subsequent hit against a different MPU - * region or the background region, because it would result - * in incorrect TLB hits for subsequent accesses to - * addresses that are in this MPU region. - */ - if (limit >= base && - ranges_overlap(base, limit - base + 1, - addr_page_base, - TARGET_PAGE_SIZE)) { - sattrs->subpage = true; - } - } - } - } - break; - } - - /* - * The IDAU will override the SAU lookup results if it specifies - * higher security than the SAU does. - */ - if (!idau_ns) { - if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { - sattrs->ns = false; - sattrs->nsc = idau_nsc; - } - } -} - /* Combine either inner or outer cacheability attributes for normal * memory, according to table D4-42 and pseudocode procedure * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b82638b5a06..c15fba43c31 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -11,6 +11,7 @@ #include "qemu/range.h" #include "cpu.h" #include "internals.h" +#include "idau.h" #include "ptw.h" @@ -766,6 +767,131 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, return !(*prot & (1 << access_type)); } +static bool v8m_is_sau_exempt(CPUARMState *env, + uint32_t address, MMUAccessType access_type) +{ + /* + * The architecture specifies that certain address ranges are + * exempt from v8M SAU/IDAU checks. + */ + return + (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) || + (address >= 0xe0000000 && address <= 0xe0002fff) || + (address >= 0xe000e000 && address <= 0xe000efff) || + (address >= 0xe002e000 && address <= 0xe002efff) || + (address >= 0xe0040000 && address <= 0xe0041fff) || + (address >= 0xe00ff000 && address <= 0xe00fffff); +} + +void v8m_security_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + V8M_SAttributes *sattrs) +{ + /* + * Look up the security attributes for this address. Compare the + * pseudocode SecurityCheck() function. + * We assume the caller has zero-initialized *sattrs. + */ + ARMCPU *cpu = env_archcpu(env); + int r; + bool idau_exempt = false, idau_ns = true, idau_nsc = true; + int idau_region = IREGION_NOTVALID; + uint32_t addr_page_base = address & TARGET_PAGE_MASK; + uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); + + if (cpu->idau) { + IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau); + IDAUInterface *ii = IDAU_INTERFACE(cpu->idau); + + iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, + &idau_nsc); + } + + if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { + /* 0xf0000000..0xffffffff is always S for insn fetches */ + return; + } + + if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { + sattrs->ns = !regime_is_secure(env, mmu_idx); + return; + } + + if (idau_region != IREGION_NOTVALID) { + sattrs->irvalid = true; + sattrs->iregion = idau_region; + } + + switch (env->sau.ctrl & 3) { + case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */ + break; + case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */ + sattrs->ns = true; + break; + default: /* SAU.ENABLE == 1 */ + for (r = 0; r < cpu->sau_sregion; r++) { + if (env->sau.rlar[r] & 1) { + uint32_t base = env->sau.rbar[r] & ~0x1f; + uint32_t limit = env->sau.rlar[r] | 0x1f; + + if (base <= address && limit >= address) { + if (base > addr_page_base || limit < addr_page_limit) { + sattrs->subpage = true; + } + if (sattrs->srvalid) { + /* + * If we hit in more than one region then we must report + * as Secure, not NS-Callable, with no valid region + * number info. + */ + sattrs->ns = false; + sattrs->nsc = false; + sattrs->sregion = 0; + sattrs->srvalid = false; + break; + } else { + if (env->sau.rlar[r] & 2) { + sattrs->nsc = true; + } else { + sattrs->ns = true; + } + sattrs->srvalid = true; + sattrs->sregion = r; + } + } else { + /* + * Address not in this region. We must check whether the + * region covers addresses in the same page as our address. + * In that case we must not report a size that covers the + * whole page for a subsequent hit against a different MPU + * region or the background region, because it would result + * in incorrect TLB hits for subsequent accesses to + * addresses that are in this MPU region. + */ + if (limit >= base && + ranges_overlap(base, limit - base + 1, + addr_page_base, + TARGET_PAGE_SIZE)) { + sattrs->subpage = true; + } + } + } + } + break; + } + + /* + * The IDAU will override the SAU lookup results if it specifies + * higher security than the SAU does. + */ + if (!idau_ns) { + if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { + sattrs->ns = false; + sattrs->nsc = idau_nsc; + } + } +} + static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, From patchwork Thu Jun 9 09:05:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580252 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp613566max; Thu, 9 Jun 2022 02:48:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzPrcH7D89D1FfZuXWPNGAmiO+vUlAFoTtz1IIhugzPtZYqpiSBFDddhwtIAX47yFayAOlK X-Received: by 2002:a05:6214:d4c:b0:46a:43f5:9bbd with SMTP id 12-20020a0562140d4c00b0046a43f59bbdmr21599348qvr.56.1654768126631; Thu, 09 Jun 2022 02:48:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654768126; cv=none; d=google.com; s=arc-20160816; b=r3qLTS8jE/kbug2zMSetpkl3lwSmx/XYmMaQZ/b25BM6D5gUVXfJSKexblFDLyKn/8 1/ebZ1zy/32Hv8S3zhb2dHdCizk6SclxAVydFtqhcOzFDTsoyoYMFmlg18Y1KPbn78Wm bhhTk2JMpSr9zw+7z5aSpLz5Sz61RfmmxvhYWmYwqVLx7XUURQIM6IqC4GF967Rsnxmd a9z/fX1OxtBtzI9xe5jTLy7s0PkJqTddBdprRgsVoxL/HNHQIRgbGihN6H2Y3/9eaR44 Eq+kQPQgU638dia/R6yaMLiiQwEg714hSSM+l23ALry0fujhIoP8xaEP3rHApolMJnyf NJnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=O5ejk88Q4maSJEwIoy6uu9RtbcDZwf0hyA9JefrZq5A=; b=twFXPJOUUUwTXkZF5I4LjqJ1Sszm1+NZswMEwNfMcNFFSS4gpH5yxgUbul3XLEXfRA qK3y9wV8aP/8c/nxZaVINnkyn2me5botj9PO93CD88t/qgdppayvebb6Waxz05CprbNv 7vTUzfzWQDtdt7bYgf6rpVcNwC1oXX62J+pPWByB9aHDP7i4noMid/jnfsOFJlFcGc24 WeD+7QcuEgEMgvAW8zNCU5z8v9XSaEy8xGx0BAptcrjAE3hnMYvVDakFKX9/QQ0+Doah Lxhm0LB85Rbs4Vb5JwJtnT3ghpQjBcep2b5jnOl0Efs6jO3XC4ftPdsNH8MTjqWc50gB /ajg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P5T+JMDE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x19-20020a05622a001300b00304fdcdb9ddsi3423041qtw.734.2022.06.09.02.48.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:48:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P5T+JMDE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58776 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEmU-0001gW-5Q for patch@linaro.org; Thu, 09 Jun 2022 05:48:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39478) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7H-0001YQ-Mc for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:15 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:35634) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE78-0005y0-UB for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:08 -0400 Received: by mail-wr1-x435.google.com with SMTP id a15so22952820wrh.2 for ; Thu, 09 Jun 2022 02:06:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=O5ejk88Q4maSJEwIoy6uu9RtbcDZwf0hyA9JefrZq5A=; b=P5T+JMDEt812vzh29gjMGZgKP5V6fbpIGzbDbJ3CGwk2h2aag7FJtFQBVJhIDOoSPs kX/ovRFgvMndp/XMIf9msmRtL11sQhXv3EKD+HqWrwxXrE9WlSZaRig9uxDfDWnfjaUY f3RCWg0Y3ri8BFUUINucz9Ejtr7NKugxAEn6vFiOiB1wp0yY6impFIAIq9h+/vOEjY4R AizkBkhG8GoWVTw2H+u603/cUMWgFL8qwUgZzQc3wIaVmY1HDHrzZx5LJt+lx/Gp7bN6 oiulz4Ak6/JhzHj05fuXfCEW4Bm6XMQrD3ClX9tQyM6TdTtKs4hr0Vxn4Gm0DB2HTjHG ukbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O5ejk88Q4maSJEwIoy6uu9RtbcDZwf0hyA9JefrZq5A=; b=RVbKphj8mJPPNaWRz/KSuktFO7Va/cQ4++Z9gYNUvMYFJDa5OF33qfJzO253Rl4Sn5 Ea0lYn43dJr9LiwJkDoOT9+etXVTOAZtYtxYTFC0xEZ2REuEBjDa5S/5wp7O03IV5DPp lTVUws3c/KtrZ8xWh0vRcyiOW9p1ADrg7z5dQxb+IrGz8zh5DgwHyvvPgBQsikXZA942 cAbLYIgxG0zWCxJjJSqJK53mG5GXnR0xtSEToDsO4JuawGIniC1ZURnmKhCq5ZCJowmk +MTdWX1itaSt7P20r6GR+yQDdF/Pner/cWLP+oocMS1T4IuqEhXV6OBYDW6OPeO0047I Vq0g== X-Gm-Message-State: AOAM533xDDnev0VQk4MYEF4RYTs4pJK/R1KagOcYG0dhnkr3J2m5JWJq uBYDEw7bCTSTQ0KDCOIWt6NfzAL956UIjQ== X-Received: by 2002:a5d:58ed:0:b0:217:dd5:7508 with SMTP id f13-20020a5d58ed000000b002170dd57508mr24329097wrd.606.1654765561753; Thu, 09 Jun 2022 02:06:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/55] target/arm: Move m_is_{ppb,system}_region to ptw.c Date: Thu, 9 Jun 2022 10:05:01 +0100 Message-Id: <20220609090537.1971756-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-13-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 3 --- target/arm/helper.c | 15 --------------- target/arm/ptw.c | 16 ++++++++++++++++ 3 files changed, 16 insertions(+), 18 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index d2d27119082..6c47a575991 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -33,9 +33,6 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); } -bool m_is_ppb_region(CPUARMState *env, uint32_t address); -bool m_is_system_region(CPUARMState *env, uint32_t address); - bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, bool s1_is_el0, diff --git a/target/arm/helper.c b/target/arm/helper.c index d6a749ad0ed..d2ef12346b6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11677,21 +11677,6 @@ do_fault: return true; } -bool m_is_ppb_region(CPUARMState *env, uint32_t address) -{ - /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */ - return arm_feature(env, ARM_FEATURE_M) && - extract32(address, 20, 12) == 0xe00; -} - -bool m_is_system_region(CPUARMState *env, uint32_t address) -{ - /* True if address is in the M profile system region - * 0xe0000000 - 0xffffffff - */ - return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; -} - /* Combine either inner or outer cacheability attributes for normal * memory, according to table D4-42 and pseudocode procedure * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c15fba43c31..32ba2e5e8bf 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -416,6 +416,22 @@ static void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_idx, } } +static bool m_is_ppb_region(CPUARMState *env, uint32_t address) +{ + /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */ + return arm_feature(env, ARM_FEATURE_M) && + extract32(address, 20, 12) == 0xe00; +} + +static bool m_is_system_region(CPUARMState *env, uint32_t address) +{ + /* + * True if address is in the M profile system region + * 0xe0000000 - 0xffffffff + */ + return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; +} + static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool is_user) { From patchwork Thu Jun 9 09:05:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580274 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp647463max; Thu, 9 Jun 2022 03:37:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwzszcwRCOcxbkuxS4jDSgNQ74IPPuYBMGPViUORqGZ/5/ihd/i+3yL0qX1T6fuFFHkWdVi X-Received: by 2002:a05:622a:487:b0:304:fbfc:9933 with SMTP id p7-20020a05622a048700b00304fbfc9933mr10051168qtx.682.1654771034684; Thu, 09 Jun 2022 03:37:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654771034; cv=none; d=google.com; s=arc-20160816; b=CxsGrO4OBCdzUSe0URiyjrURBHI/sZ5b1peKxkX54827YqAmQqfiRcEM77zzdRdwKu 8um/aHyw4gNmyATiLsPCLvD0dkHwtKT3a8ge5Uk3+sapYlswhV6cLdCunOH7D7vnvB0a pFwfiszd+jalxNtRIyctmgg0gg3Ud3VlZWJVtzMPC8Hcb+CFAaNA+qBumeguzkaW6XjL szQM7wxtSxs5eGZd6j51MMIRWVlYh8VprneJawVcSxXjhn4TrA09j4L5z9u62Da8aZPq uCiOMXQ+tYs6v6STqaz3Mn89r83IG+FjREIVUkjbQGFP87Til1iVeiLvVKKGYw75hjAR MX4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=TD1PLdCagSw5QrlgIXtULFKaHs2aOf+o891C3P6EsSQ=; b=FJ+uqtnVVCKeuO79UwBSN63JWYKAx9zq1kC5m5eBar+zQPLloqtpvuMJjmSRjS47f3 5pgcf4dIwYrcSURnrSi6JZXjZbd8ThKeddyxmDF+UIRstKmmBJatbJ0VezdcZ4AvMlMz 0RofjVBE/RjZZ5dPCz4bpspcNtXRBFvYwZpnanv4xbMrvzQPmpXe5pf3lt3zynS6O9a4 sfnXQbDUfC36RcFtxV01insURWMkSdkx3WYBPZU0K+EzM6Jh1ba/Jw5PEWRlQkPrCHi3 df4YYsxfckRr7txKqPPBpCH19tNNae4I7Gpu/qa/ofglZ9kNGgfwsC9v5QJGBivHOGNs vPEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j0TKzAGA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z12-20020ac87f8c000000b00305105719dfsi424009qtj.274.2022.06.09.03.37.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:37:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j0TKzAGA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47646 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFXO-0002N8-5v for patch@linaro.org; Thu, 09 Jun 2022 06:37:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39514) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7J-0001Yd-9E for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:18 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:36485) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7B-00062j-TP for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:13 -0400 Received: by mail-wr1-x431.google.com with SMTP id o8so3625311wro.3 for ; Thu, 09 Jun 2022 02:06:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TD1PLdCagSw5QrlgIXtULFKaHs2aOf+o891C3P6EsSQ=; b=j0TKzAGApZF0gBczopLtY9dfGeA9G24MSE6bd8q5WZ9INxwNEVAHb5ZlHlb2uZSqHj xW1dEkkQxA+Pjpn70kE4930ySQsmj784eZdX+9zKcXbkdX/J+oCGP9yJh0Jb+45U5TTd WdhYRBxT3V4ciMpAf6zssDYCn7jV/+D9RgMISVu/oEMzucugWVu5h/Ky5/0WneE2jTrW W/cuOa38nylOvpZomInaEHjnRMisNcMmEnj8K/uaOavJjm+n8y2neZesFlE5owAEICKM LBEXaSGXb1MDMxfHiTT0ljY951MvQ5suLAYj2wdHM72wWc64YfjbpRy6Ti+xu3To5MUG uiww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TD1PLdCagSw5QrlgIXtULFKaHs2aOf+o891C3P6EsSQ=; b=jpTvf9PzjDHsdzThD/XiMOZpdDeiulno3TZE1H4C6MRG+NQizpEY+4eL3FGwefpK+g Rxij+Btq+NKaD4UcSjDwATUjZbvgwT+EPfCeVvUqQeEeDAJ62AvYL8PLh7JbrnG1noGe PRaEs6JWBtQId042Dpq35AjM4Z2OFg46cTH5rKMqM7VN6wWAy1kIh5UshSNRCVk+Bd+H q81MD0DIwBK7BkEv5LtA0BxUdGDrDZGn+HSTCMj/P31tEI7KfBZgJrdH+MON+tQmM0L1 OGuuXm+hRRpCQ4l+wfBtaeufAAwNT9LAkw8jvlWwp1/ZGr2LBU31N8QVr1tmS4eNL8rX 4E3w== X-Gm-Message-State: AOAM530srhmuhIoHuvzbt5NCdmqvyIbeQ+XJhW277+KOubwL7wjBSitY y9TxyUhnUWD+UPLOPpwuNK/7TEE8hUR5yA== X-Received: by 2002:a05:6000:184f:b0:218:555e:6b69 with SMTP id c15-20020a056000184f00b00218555e6b69mr11528701wri.562.1654765562794; Thu, 09 Jun 2022 02:06:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/55] target/arm: Move get_level1_table_address to ptw.c Date: Thu, 9 Jun 2022 10:05:02 +0100 Message-Id: <20220609090537.1971756-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-14-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 4 ++-- target/arm/helper.c | 26 +------------------------- target/arm/ptw.c | 23 +++++++++++++++++++++++ 3 files changed, 26 insertions(+), 27 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index 6c47a575991..dd6fb93f336 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -18,11 +18,11 @@ uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx); bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx); +uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn); + ARMCacheAttrs combine_cacheattrs(CPUARMState *env, ARMCacheAttrs s1, ARMCacheAttrs s2); -bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, - uint32_t *table, uint32_t address); int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap, int domain_prot); int simple_ap_to_rw_prot_is_user(int ap, bool is_user); diff --git a/target/arm/helper.c b/target/arm/helper.c index d2ef12346b6..a144cb26413 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10482,8 +10482,7 @@ static inline bool regime_translation_big_endian(CPUARMState *env, } /* Return the TTBR associated with this translation regime */ -static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, - int ttbrn) +uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) { if (mmu_idx == ARMMMUIdx_Stage2) { return env->cp15.vttbr_el2; @@ -10774,29 +10773,6 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, return prot_rw | PAGE_EXEC; } -bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, - uint32_t *table, uint32_t address) -{ - /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ - TCR *tcr = regime_tcr(env, mmu_idx); - - if (address & tcr->mask) { - if (tcr->raw_tcr & TTBCR_PD1) { - /* Translation table walk disabled for TTBR1 */ - return false; - } - *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; - } else { - if (tcr->raw_tcr & TTBCR_PD0) { - /* Translation table walk disabled for TTBR0 */ - return false; - } - *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; - } - *table |= (address >> 18) & 0x3ffc; - return true; -} - static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs) { /* diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 32ba2e5e8bf..5737a3976b8 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -15,6 +15,29 @@ #include "ptw.h" +static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, + uint32_t *table, uint32_t address) +{ + /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ + TCR *tcr = regime_tcr(env, mmu_idx); + + if (address & tcr->mask) { + if (tcr->raw_tcr & TTBCR_PD1) { + /* Translation table walk disabled for TTBR1 */ + return false; + } + *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; + } else { + if (tcr->raw_tcr & TTBCR_PD0) { + /* Translation table walk disabled for TTBR0 */ + return false; + } + *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; + } + *table |= (address >> 18) & 0x3ffc; + return true; +} + static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, From patchwork Thu Jun 9 09:05:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580255 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp616221max; Thu, 9 Jun 2022 02:52:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyBMYmGVr7e5Ipzb26octOyihweh2Ybxmmzu32N2Bw2xm/okWqm+RZbaQKR2gvsbFLy9yKM X-Received: by 2002:a05:6214:5195:b0:464:507d:8eea with SMTP id kl21-20020a056214519500b00464507d8eeamr28665810qvb.91.1654768377598; Thu, 09 Jun 2022 02:52:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654768377; cv=none; d=google.com; s=arc-20160816; b=ON+tmivERl1Bv6E5qWDnrSFss4BvNaFRsIKglslSpm1Dh+LzJKMQAuwiN8F89sRSYx MINqK+X06AOTAsqxBl23JKvQg7x7zohhILgq57+jYDlz3og6JeZ/y4ex+S+gOF3BpvEV 3ue2MBs57E6RpySiHKNTPwUWZWyzN9b+GNPqwps+eakxtj7vK8Qjrbr02N/4DBGCfrT0 Zzk9+erbpDl3kZoQiZEtlENYr96BVsL53+NwUO15Cu17kcuzUBzwSWKwlAmh66sT1Blr 3bawMlZmWALfoPIm9mcL5KvP7Tu8jMpPIYfVkE/lncDBXsHTT9yKP6tzybAhQVm2RdWb cZug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WD/V0E1GSbC8kw/VTqqWFOO+IaFp5Vx0rfDhyIWhFDU=; b=VE7l6N4XH1yIVnK0uatv3MPH81SYt4hbkAqDP6KXx366F07E0yrF5e7B+PWfDP7Lxp SDOtjH/kATY1tBUBCg1NWkV81axSyDGNJ54kPWh1XJFxxSZm6E0YdSinIH3yzqd2w5qi xj7+96ERj0bAYM93gLogOCYeLLgdGOqNaOkyL/+GfuF39Qff9rbGcE4XdVcmWHK9VpwO Ztt4NAsb2c0i3eeoFIuvhB/2prfVh3Y0Wpt5y/OOYM+ihDXco+4kmlXN/AKUjToal+zV 6V59yO36IVJhde0HlNt7FpO/Zdx2UG2nct6/US7SQnz6GHI5tRjEMEtrE8ek+p3tSX08 BdJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AEa7Rqui; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z7-20020a05622a060700b00304e37a41f8si9516497qta.250.2022.06.09.02.52.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:52:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AEa7Rqui; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33796 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEqV-0004Ij-47 for patch@linaro.org; Thu, 09 Jun 2022 05:52:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39502) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7I-0001Yb-W1 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:18 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:43557) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7E-00062u-Kx for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:12 -0400 Received: by mail-wr1-x42e.google.com with SMTP id d14so22478158wra.10 for ; Thu, 09 Jun 2022 02:06:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WD/V0E1GSbC8kw/VTqqWFOO+IaFp5Vx0rfDhyIWhFDU=; b=AEa7RquiRN8Zm/M2WAO56Kis0lEpu8H6AzF7P3XXGVxgdAHEr6p51Kw0FxcnX4IHyU UP0DxsUyg8VN7jWt1BZb/5YPab9cDALHw23DA6yYqC8R4aQT7DbkC2F+BzQQsRhDhIro 6UH2wsOmx2czkgQZk9qHsUbIIT00/rlkCSOqkeQoWiglFnZdkwzc45QqYUvFQzY4IgSa KO8ibbZmjwZ5tkRJ9XBSbPHZxifZhOEJscU88nh/vFp9jT8y1b+d4i11L1CvSYE2OSJJ BsdN64Bi80ikkxYHnrrXLo27P3RHoWdZ+JaYNd5cVlnnB0/RzP9lH6hZO1wIzRTg5iZi 3n1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WD/V0E1GSbC8kw/VTqqWFOO+IaFp5Vx0rfDhyIWhFDU=; b=LKIA1s9Hi4BqnQ86Uh1UPFRq/Hs/rAf+a7ImOZYlOmEXABauo4qu2KD509hyRKF+qt LC/MoMZEc4FDqt935/m0ELUEk6TkiCw7i3BXzawHG1nfOHImvDabmQvdcyHf4Vfm4xTJ C6FBbpEeMW4jBgEzs2p0RaRKD4d06+yvcIIngVqBWnZCw5lPA2/CqI5VKbZa6D6at87l 4BFnfBdZbsOFwPnQrGsmjtjGJ7Klau4UvGChrXaq/iA8sotX1vNeKYjA3GYWNz1crVRI k4l8X63VBP6Psa934t3CxThjE3poAp0HFL65LVZFcf+Rfc7D2sh4EbKlXLmOdMHmXjtS Iwog== X-Gm-Message-State: AOAM533ZdcV4v6GjwBQI3MqSbsmxEN84vcRAZJtwpOwm++6lYpCp4wZL WTvxSFdqYIGMYVDYjZHHAcCN+u1tI2WPag== X-Received: by 2002:a5d:4344:0:b0:20c:cad4:9e9b with SMTP id u4-20020a5d4344000000b0020ccad49e9bmr36841605wrr.187.1654765563996; Thu, 09 Jun 2022 02:06:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/55] target/arm: Move combine_cacheattrs and subroutines to ptw.c Date: Thu, 9 Jun 2022 10:05:03 +0100 Message-Id: <20220609090537.1971756-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson There are a handful of helpers for combine_cacheattrs that we can move at the same time as the main entry point. Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-15-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 3 - target/arm/helper.c | 218 ------------------------------------------- target/arm/ptw.c | 221 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 221 insertions(+), 221 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index dd6fb93f336..b2dfe489bbe 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -20,9 +20,6 @@ bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx); bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx); uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn); -ARMCacheAttrs combine_cacheattrs(CPUARMState *env, - ARMCacheAttrs s1, ARMCacheAttrs s2); - int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap, int domain_prot); int simple_ap_to_rw_prot_is_user(int ap, bool is_user); diff --git a/target/arm/helper.c b/target/arm/helper.c index a144cb26413..dab485e64ae 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10977,36 +10977,6 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, } return true; } - -/* Translate from the 4-bit stage 2 representation of - * memory attributes (without cache-allocation hints) to - * the 8-bit representation of the stage 1 MAIR registers - * (which includes allocation hints). - * - * ref: shared/translation/attrs/S2AttrDecode() - * .../S2ConvertAttrsHints() - */ -static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) -{ - uint8_t hiattr = extract32(s2attrs, 2, 2); - uint8_t loattr = extract32(s2attrs, 0, 2); - uint8_t hihint = 0, lohint = 0; - - if (hiattr != 0) { /* normal memory */ - if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */ - hiattr = loattr = 1; /* non-cacheable */ - } else { - if (hiattr != 1) { /* Write-through or write-back */ - hihint = 3; /* RW allocate */ - } - if (loattr != 1) { /* Write-through or write-back */ - lohint = 3; /* RW allocate */ - } - } - } - - return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; -} #endif /* !CONFIG_USER_ONLY */ /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ @@ -11653,194 +11623,6 @@ do_fault: return true; } -/* Combine either inner or outer cacheability attributes for normal - * memory, according to table D4-42 and pseudocode procedure - * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). - * - * NB: only stage 1 includes allocation hints (RW bits), leading to - * some asymmetry. - */ -static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) -{ - if (s1 == 4 || s2 == 4) { - /* non-cacheable has precedence */ - return 4; - } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) { - /* stage 1 write-through takes precedence */ - return s1; - } else if (extract32(s2, 2, 2) == 2) { - /* stage 2 write-through takes precedence, but the allocation hint - * is still taken from stage 1 - */ - return (2 << 2) | extract32(s1, 0, 2); - } else { /* write-back */ - return s1; - } -} - -/* - * Combine the memory type and cacheability attributes of - * s1 and s2 for the HCR_EL2.FWB == 0 case, returning the - * combined attributes in MAIR_EL1 format. - */ -static uint8_t combined_attrs_nofwb(CPUARMState *env, - ARMCacheAttrs s1, ARMCacheAttrs s2) -{ - uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs; - - s2_mair_attrs = convert_stage2_attrs(env, s2.attrs); - - s1lo = extract32(s1.attrs, 0, 4); - s2lo = extract32(s2_mair_attrs, 0, 4); - s1hi = extract32(s1.attrs, 4, 4); - s2hi = extract32(s2_mair_attrs, 4, 4); - - /* Combine memory type and cacheability attributes */ - if (s1hi == 0 || s2hi == 0) { - /* Device has precedence over normal */ - if (s1lo == 0 || s2lo == 0) { - /* nGnRnE has precedence over anything */ - ret_attrs = 0; - } else if (s1lo == 4 || s2lo == 4) { - /* non-Reordering has precedence over Reordering */ - ret_attrs = 4; /* nGnRE */ - } else if (s1lo == 8 || s2lo == 8) { - /* non-Gathering has precedence over Gathering */ - ret_attrs = 8; /* nGRE */ - } else { - ret_attrs = 0xc; /* GRE */ - } - } else { /* Normal memory */ - /* Outer/inner cacheability combine independently */ - ret_attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4 - | combine_cacheattr_nibble(s1lo, s2lo); - } - return ret_attrs; -} - -static uint8_t force_cacheattr_nibble_wb(uint8_t attr) -{ - /* - * Given the 4 bits specifying the outer or inner cacheability - * in MAIR format, return a value specifying Normal Write-Back, - * with the allocation and transient hints taken from the input - * if the input specified some kind of cacheable attribute. - */ - if (attr == 0 || attr == 4) { - /* - * 0 == an UNPREDICTABLE encoding - * 4 == Non-cacheable - * Either way, force Write-Back RW allocate non-transient - */ - return 0xf; - } - /* Change WriteThrough to WriteBack, keep allocation and transient hints */ - return attr | 4; -} - -/* - * Combine the memory type and cacheability attributes of - * s1 and s2 for the HCR_EL2.FWB == 1 case, returning the - * combined attributes in MAIR_EL1 format. - */ -static uint8_t combined_attrs_fwb(CPUARMState *env, - ARMCacheAttrs s1, ARMCacheAttrs s2) -{ - switch (s2.attrs) { - case 7: - /* Use stage 1 attributes */ - return s1.attrs; - case 6: - /* - * Force Normal Write-Back. Note that if S1 is Normal cacheable - * then we take the allocation hints from it; otherwise it is - * RW allocate, non-transient. - */ - if ((s1.attrs & 0xf0) == 0) { - /* S1 is Device */ - return 0xff; - } - /* Need to check the Inner and Outer nibbles separately */ - return force_cacheattr_nibble_wb(s1.attrs & 0xf) | - force_cacheattr_nibble_wb(s1.attrs >> 4) << 4; - case 5: - /* If S1 attrs are Device, use them; otherwise Normal Non-cacheable */ - if ((s1.attrs & 0xf0) == 0) { - return s1.attrs; - } - return 0x44; - case 0 ... 3: - /* Force Device, of subtype specified by S2 */ - return s2.attrs << 2; - default: - /* - * RESERVED values (including RES0 descriptor bit [5] being nonzero); - * arbitrarily force Device. - */ - return 0; - } -} - -/* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 - * and CombineS1S2Desc() - * - * @env: CPUARMState - * @s1: Attributes from stage 1 walk - * @s2: Attributes from stage 2 walk - */ -ARMCacheAttrs combine_cacheattrs(CPUARMState *env, - ARMCacheAttrs s1, ARMCacheAttrs s2) -{ - ARMCacheAttrs ret; - bool tagged = false; - - assert(s2.is_s2_format && !s1.is_s2_format); - ret.is_s2_format = false; - - if (s1.attrs == 0xf0) { - tagged = true; - s1.attrs = 0xff; - } - - /* Combine shareability attributes (table D4-43) */ - if (s1.shareability == 2 || s2.shareability == 2) { - /* if either are outer-shareable, the result is outer-shareable */ - ret.shareability = 2; - } else if (s1.shareability == 3 || s2.shareability == 3) { - /* if either are inner-shareable, the result is inner-shareable */ - ret.shareability = 3; - } else { - /* both non-shareable */ - ret.shareability = 0; - } - - /* Combine memory type and cacheability attributes */ - if (arm_hcr_el2_eff(env) & HCR_FWB) { - ret.attrs = combined_attrs_fwb(env, s1, s2); - } else { - ret.attrs = combined_attrs_nofwb(env, s1, s2); - } - - /* - * Any location for which the resultant memory type is any - * type of Device memory is always treated as Outer Shareable. - * Any location for which the resultant memory type is Normal - * Inner Non-cacheable, Outer Non-cacheable is always treated - * as Outer Shareable. - * TODO: FEAT_XS adds another value (0x40) also meaning iNCoNC - */ - if ((ret.attrs & 0xf0) == 0 || ret.attrs == 0x44) { - ret.shareability = 2; - } - - /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */ - if (tagged && ret.attrs == 0xff) { - ret.attrs = 0xf0; - } - - return ret; -} - hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5737a3976b8..f2ca2bb8fe1 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1008,6 +1008,227 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, return ret; } +/* + * Translate from the 4-bit stage 2 representation of + * memory attributes (without cache-allocation hints) to + * the 8-bit representation of the stage 1 MAIR registers + * (which includes allocation hints). + * + * ref: shared/translation/attrs/S2AttrDecode() + * .../S2ConvertAttrsHints() + */ +static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) +{ + uint8_t hiattr = extract32(s2attrs, 2, 2); + uint8_t loattr = extract32(s2attrs, 0, 2); + uint8_t hihint = 0, lohint = 0; + + if (hiattr != 0) { /* normal memory */ + if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */ + hiattr = loattr = 1; /* non-cacheable */ + } else { + if (hiattr != 1) { /* Write-through or write-back */ + hihint = 3; /* RW allocate */ + } + if (loattr != 1) { /* Write-through or write-back */ + lohint = 3; /* RW allocate */ + } + } + } + + return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; +} + +/* + * Combine either inner or outer cacheability attributes for normal + * memory, according to table D4-42 and pseudocode procedure + * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). + * + * NB: only stage 1 includes allocation hints (RW bits), leading to + * some asymmetry. + */ +static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) +{ + if (s1 == 4 || s2 == 4) { + /* non-cacheable has precedence */ + return 4; + } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) { + /* stage 1 write-through takes precedence */ + return s1; + } else if (extract32(s2, 2, 2) == 2) { + /* stage 2 write-through takes precedence, but the allocation hint + * is still taken from stage 1 + */ + return (2 << 2) | extract32(s1, 0, 2); + } else { /* write-back */ + return s1; + } +} + +/* + * Combine the memory type and cacheability attributes of + * s1 and s2 for the HCR_EL2.FWB == 0 case, returning the + * combined attributes in MAIR_EL1 format. + */ +static uint8_t combined_attrs_nofwb(CPUARMState *env, + ARMCacheAttrs s1, ARMCacheAttrs s2) +{ + uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs; + + s2_mair_attrs = convert_stage2_attrs(env, s2.attrs); + + s1lo = extract32(s1.attrs, 0, 4); + s2lo = extract32(s2_mair_attrs, 0, 4); + s1hi = extract32(s1.attrs, 4, 4); + s2hi = extract32(s2_mair_attrs, 4, 4); + + /* Combine memory type and cacheability attributes */ + if (s1hi == 0 || s2hi == 0) { + /* Device has precedence over normal */ + if (s1lo == 0 || s2lo == 0) { + /* nGnRnE has precedence over anything */ + ret_attrs = 0; + } else if (s1lo == 4 || s2lo == 4) { + /* non-Reordering has precedence over Reordering */ + ret_attrs = 4; /* nGnRE */ + } else if (s1lo == 8 || s2lo == 8) { + /* non-Gathering has precedence over Gathering */ + ret_attrs = 8; /* nGRE */ + } else { + ret_attrs = 0xc; /* GRE */ + } + } else { /* Normal memory */ + /* Outer/inner cacheability combine independently */ + ret_attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4 + | combine_cacheattr_nibble(s1lo, s2lo); + } + return ret_attrs; +} + +static uint8_t force_cacheattr_nibble_wb(uint8_t attr) +{ + /* + * Given the 4 bits specifying the outer or inner cacheability + * in MAIR format, return a value specifying Normal Write-Back, + * with the allocation and transient hints taken from the input + * if the input specified some kind of cacheable attribute. + */ + if (attr == 0 || attr == 4) { + /* + * 0 == an UNPREDICTABLE encoding + * 4 == Non-cacheable + * Either way, force Write-Back RW allocate non-transient + */ + return 0xf; + } + /* Change WriteThrough to WriteBack, keep allocation and transient hints */ + return attr | 4; +} + +/* + * Combine the memory type and cacheability attributes of + * s1 and s2 for the HCR_EL2.FWB == 1 case, returning the + * combined attributes in MAIR_EL1 format. + */ +static uint8_t combined_attrs_fwb(CPUARMState *env, + ARMCacheAttrs s1, ARMCacheAttrs s2) +{ + switch (s2.attrs) { + case 7: + /* Use stage 1 attributes */ + return s1.attrs; + case 6: + /* + * Force Normal Write-Back. Note that if S1 is Normal cacheable + * then we take the allocation hints from it; otherwise it is + * RW allocate, non-transient. + */ + if ((s1.attrs & 0xf0) == 0) { + /* S1 is Device */ + return 0xff; + } + /* Need to check the Inner and Outer nibbles separately */ + return force_cacheattr_nibble_wb(s1.attrs & 0xf) | + force_cacheattr_nibble_wb(s1.attrs >> 4) << 4; + case 5: + /* If S1 attrs are Device, use them; otherwise Normal Non-cacheable */ + if ((s1.attrs & 0xf0) == 0) { + return s1.attrs; + } + return 0x44; + case 0 ... 3: + /* Force Device, of subtype specified by S2 */ + return s2.attrs << 2; + default: + /* + * RESERVED values (including RES0 descriptor bit [5] being nonzero); + * arbitrarily force Device. + */ + return 0; + } +} + +/* + * Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 + * and CombineS1S2Desc() + * + * @env: CPUARMState + * @s1: Attributes from stage 1 walk + * @s2: Attributes from stage 2 walk + */ +static ARMCacheAttrs combine_cacheattrs(CPUARMState *env, + ARMCacheAttrs s1, ARMCacheAttrs s2) +{ + ARMCacheAttrs ret; + bool tagged = false; + + assert(s2.is_s2_format && !s1.is_s2_format); + ret.is_s2_format = false; + + if (s1.attrs == 0xf0) { + tagged = true; + s1.attrs = 0xff; + } + + /* Combine shareability attributes (table D4-43) */ + if (s1.shareability == 2 || s2.shareability == 2) { + /* if either are outer-shareable, the result is outer-shareable */ + ret.shareability = 2; + } else if (s1.shareability == 3 || s2.shareability == 3) { + /* if either are inner-shareable, the result is inner-shareable */ + ret.shareability = 3; + } else { + /* both non-shareable */ + ret.shareability = 0; + } + + /* Combine memory type and cacheability attributes */ + if (arm_hcr_el2_eff(env) & HCR_FWB) { + ret.attrs = combined_attrs_fwb(env, s1, s2); + } else { + ret.attrs = combined_attrs_nofwb(env, s1, s2); + } + + /* + * Any location for which the resultant memory type is any + * type of Device memory is always treated as Outer Shareable. + * Any location for which the resultant memory type is Normal + * Inner Non-cacheable, Outer Non-cacheable is always treated + * as Outer Shareable. + * TODO: FEAT_XS adds another value (0x40) also meaning iNCoNC + */ + if ((ret.attrs & 0xf0) == 0 || ret.attrs == 0x44) { + ret.shareability = 2; + } + + /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */ + if (tagged && ret.attrs == 0xff) { + ret.attrs = 0xf0; + } + + return ret; +} + /** * get_phys_addr - get the physical address for this virtual address * From patchwork Thu Jun 9 09:05:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580256 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp619011max; Thu, 9 Jun 2022 02:56:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzsRzwuyguHrnKLR8P8+T464n1B5il6RCk/LLlfGmuH6IfHb+5A39rxuZaJdGQBe4dWQHN+ X-Received: by 2002:a05:620a:460d:b0:6a0:47a3:4da1 with SMTP id br13-20020a05620a460d00b006a047a34da1mr25180531qkb.359.1654768617894; Thu, 09 Jun 2022 02:56:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654768617; cv=none; d=google.com; s=arc-20160816; b=OUboeweaAmzgJjMPDWhh3inCQetotxAktSz4voIkIIiS60Aa6CkmnRWvFlBWH7T9pM NQ3Xi/KX6AAS+4QPlvngLh+6lTsfAsw3oWPJfegvNa1S6rW0S/WmXi0qXffEg2b95Je2 QG515D6pJ6hmi7zr0eFsmvM62c5H+V5YWi7H3STux6dRS9Xvqs6/3E+CEWC0jECPns8B URb3txkK49yKx1zCyb//M8CkoeUnnOkAgdM8PwAbBU0t7ZBX6gnF2UjrjG2Utzfc1rAP vSSFYfaX6OOtIz+us5R+ulEQ78jBveqZo7xdBsTc21zByj0wNuONgaYiA3MMwf2bXHPU Skkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IkbtgPvv7dCQdgswPKDWhOCh/FDmgZL+ieXHCGa70Nc=; b=yRXXdBtlv2UyP3IOkSt3wbf+xsUJF8REAkMsAvcJ5nkzz7MoGHQoLWbfwKKW9q0yme cMWbQylLJn9aC0VPbderZiPU8Nh6gkvMPzhAyCapf66vdOKYw3pAdfFPcxenTIa+3elI E+H4cGKHveV3P1ckEb92satz2WBCUSgNt9bK1SPiAMInI/FdidI4O2jMoJDo/yxXu8Lv 2QUMfQRqgbFM/SwLY4pvsmtjYlMF/fqIXRBtdTcV3PzLO+63sDShiazRqgQDB0NL3Tmt O4mVnFsoKGBGAFWYkTh+PT4k3wYDGNoVvYDNQJpKOvWCdPU3kSDYREvby6m6yBGCuZYS Mh2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uexGmZ7w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s191-20020a37a9c8000000b006a6a3e2587csi9214261qke.146.2022.06.09.02.56.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:56:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uexGmZ7w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEuP-0008Lq-7Z for patch@linaro.org; Thu, 09 Jun 2022 05:56:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39576) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7L-0001Yr-Ok for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:18 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:47100) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7G-00061B-H8 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:15 -0400 Received: by mail-wm1-x32e.google.com with SMTP id r123-20020a1c2b81000000b0039c1439c33cso12264463wmr.5 for ; Thu, 09 Jun 2022 02:06:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=IkbtgPvv7dCQdgswPKDWhOCh/FDmgZL+ieXHCGa70Nc=; b=uexGmZ7w53heQKOcqy9uLQQPEFllbg7yoEshVBByqDqi19iQ6HnagqXP1fQOrJBpc1 2IHmV/90X6zqfg0H1aAm+H1+ksAqy7qD/iDjVY1oiJ8GBfPYDk8wkYfT0MN943CAgRpd PINdbyGFtWLCNzQSILGbEMa/6UmjVqB3nQJiYwprIco+/TRslz7fuKe16Fb6LT6RQz+x fGxzI84cmPFa9hFsTiuBaDxBo6AyZzs+gw5eBzlq75tTnYbVSv7oBhbtMa/QeDkzMO3k 8su8vGpLLkYviwAfD5rxueLRYgAeoosoR3TQtDI8tgvuO908BSoZ9T0INn4mqtB4U8Vp c/qQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IkbtgPvv7dCQdgswPKDWhOCh/FDmgZL+ieXHCGa70Nc=; b=hAY410lb1OAuXxdJ8FB5VBQY8QtKmq8iD0VUM6WCtgiK65Vyp+LuXNstLKZbABrTju M6tEpIqhqUyhRTP1FdDKjqCrbWMi/ZwhFMxjj/60zp9CTHTJJoqBP8Y18qwgjOaYWP+w aSmtuqPAJgtoeWH8cs/EhusoejsPXJeyhauBNfcYYhgsv3bb5EC+OG3yW4Bqcm2KZLyN LcIGmcGa27tcPblBlfBjVxx76xT0am9k+CejDMk9KgfEbmvVsfqHeE/ZVdsrCP/YZI/A R50g/q8kyHJHx5pdwp/yhkkSUkSybgnhqCjUOuBlk2qVXlRXI1cz1/UT7VndceDTOZKM np9A== X-Gm-Message-State: AOAM530fdAdUAO48syIHhvhXr/LojzI46t7s/mAa/r+4pt+Uw7bjA8mb G5s9au/aF0epLViJDjpKal6HgyrMLBmtFQ== X-Received: by 2002:a05:600c:2e14:b0:39c:58c4:c6ed with SMTP id o20-20020a05600c2e1400b0039c58c4c6edmr2306223wmf.156.1654765565602; Thu, 09 Jun 2022 02:06:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/55] target/arm: Move get_phys_addr_lpae to ptw.c Date: Thu, 9 Jun 2022 10:05:04 +0100 Message-Id: <20220609090537.1971756-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-16-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 10 ++ target/arm/helper.c | 416 +------------------------------------------- target/arm/ptw.c | 411 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 429 insertions(+), 408 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index b2dfe489bbe..31744df6646 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -11,6 +11,8 @@ #ifndef CONFIG_USER_ONLY +extern const uint8_t pamax_map[7]; + uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi); uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, @@ -30,6 +32,14 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); } +ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, + ARMMMUIdx mmu_idx); +bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, + int inputsize, int stride, int outputsize); +int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0); +int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, + int ap, int ns, int xn, int pxn); + bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, bool s1_is_el0, diff --git a/target/arm/helper.c b/target/arm/helper.c index dab485e64ae..7de815fe986 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10652,7 +10652,7 @@ int simple_ap_to_rw_prot_is_user(int ap, bool is_user) * @xn: XN (execute-never) bits * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 */ -static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) +int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) { int prot = 0; @@ -10703,8 +10703,8 @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) * @xn: XN (execute-never) bit * @pxn: PXN (privileged execute-never) bit */ -static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, - int ap, int ns, int xn, int pxn) +int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, + int ap, int ns, int xn, int pxn) { bool is_user = regime_is_user(env, mmu_idx); int prot_rw, user_rw; @@ -10919,8 +10919,8 @@ uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, * Returns true if the suggested S2 translation parameters are OK and * false otherwise. */ -static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, - int inputsize, int stride, int outputsize) +bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, + int inputsize, int stride, int outputsize) { const int grainsize = stride + 3; int startsizecheck; @@ -10980,7 +10980,7 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, #endif /* !CONFIG_USER_ONLY */ /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ -static const uint8_t pamax_map[] = { +const uint8_t pamax_map[] = { [0] = 32, [1] = 36, [2] = 40, @@ -11159,8 +11159,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, } #ifndef CONFIG_USER_ONLY -static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, - ARMMMUIdx mmu_idx) +ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, + ARMMMUIdx mmu_idx) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el = regime_el(env, mmu_idx); @@ -11223,406 +11223,6 @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, }; } -/** - * get_phys_addr_lpae: perform one stage of page table walk, LPAE format - * - * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, - * prot and page_size may not be filled in, and the populated fsr value provides - * information on why the translation aborted, in the format of a long-format - * DFSR/IFSR fault register, with the following caveats: - * * the WnR bit is never set (the caller must do this). - * - * @env: CPUARMState - * @address: virtual address to get physical address for - * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH - * @mmu_idx: MMU index indicating required translation regime - * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table - * walk), must be true if this is stage 2 of a stage 1+2 walk for an - * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored. - * @phys_ptr: set to the physical address corresponding to the virtual address - * @attrs: set to the memory transaction attributes to use - * @prot: set to the permissions for the page containing phys_ptr - * @page_size_ptr: set to the size of the page containing phys_ptr - * @fi: set to fault info if the translation fails - * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes - */ -bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool s1_is_el0, - hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, - target_ulong *page_size_ptr, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) -{ - ARMCPU *cpu = env_archcpu(env); - CPUState *cs = CPU(cpu); - /* Read an LPAE long-descriptor translation table. */ - ARMFaultType fault_type = ARMFault_Translation; - uint32_t level; - ARMVAParameters param; - uint64_t ttbr; - hwaddr descaddr, indexmask, indexmask_grainsize; - uint32_t tableattrs; - target_ulong page_size; - uint32_t attrs; - int32_t stride; - int addrsize, inputsize, outputsize; - TCR *tcr = regime_tcr(env, mmu_idx); - int ap, ns, xn, pxn; - uint32_t el = regime_el(env, mmu_idx); - uint64_t descaddrmask; - bool aarch64 = arm_el_is_aa64(env, el); - bool guarded = false; - - /* TODO: This code does not support shareability levels. */ - if (aarch64) { - int ps; - - param = aa64_va_parameters(env, address, mmu_idx, - access_type != MMU_INST_FETCH); - level = 0; - - /* - * If TxSZ is programmed to a value larger than the maximum, - * or smaller than the effective minimum, it is IMPLEMENTATION - * DEFINED whether we behave as if the field were programmed - * within bounds, or if a level 0 Translation fault is generated. - * - * With FEAT_LVA, fault on less than minimum becomes required, - * so our choice is to always raise the fault. - */ - if (param.tsz_oob) { - fault_type = ARMFault_Translation; - goto do_fault; - } - - addrsize = 64 - 8 * param.tbi; - inputsize = 64 - param.tsz; - - /* - * Bound PS by PARANGE to find the effective output address size. - * ID_AA64MMFR0 is a read-only register so values outside of the - * supported mappings can be considered an implementation error. - */ - ps = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); - ps = MIN(ps, param.ps); - assert(ps < ARRAY_SIZE(pamax_map)); - outputsize = pamax_map[ps]; - } else { - param = aa32_va_parameters(env, address, mmu_idx); - level = 1; - addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32); - inputsize = addrsize - param.tsz; - outputsize = 40; - } - - /* - * We determined the region when collecting the parameters, but we - * have not yet validated that the address is valid for the region. - * Extract the top bits and verify that they all match select. - * - * For aa32, if inputsize == addrsize, then we have selected the - * region by exclusion in aa32_va_parameters and there is no more - * validation to do here. - */ - if (inputsize < addrsize) { - target_ulong top_bits = sextract64(address, inputsize, - addrsize - inputsize); - if (-top_bits != param.select) { - /* The gap between the two regions is a Translation fault */ - fault_type = ARMFault_Translation; - goto do_fault; - } - } - - if (param.using64k) { - stride = 13; - } else if (param.using16k) { - stride = 11; - } else { - stride = 9; - } - - /* Note that QEMU ignores shareability and cacheability attributes, - * so we don't need to do anything with the SH, ORGN, IRGN fields - * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the - * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently - * implement any ASID-like capability so we can ignore it (instead - * we will always flush the TLB any time the ASID is changed). - */ - ttbr = regime_ttbr(env, mmu_idx, param.select); - - /* Here we should have set up all the parameters for the translation: - * inputsize, ttbr, epd, stride, tbi - */ - - if (param.epd) { - /* Translation table walk disabled => Translation fault on TLB miss - * Note: This is always 0 on 64-bit EL2 and EL3. - */ - goto do_fault; - } - - if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) { - /* The starting level depends on the virtual address size (which can - * be up to 48 bits) and the translation granule size. It indicates - * the number of strides (stride bits at a time) needed to - * consume the bits of the input address. In the pseudocode this is: - * level = 4 - RoundUp((inputsize - grainsize) / stride) - * where their 'inputsize' is our 'inputsize', 'grainsize' is - * our 'stride + 3' and 'stride' is our 'stride'. - * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: - * = 4 - (inputsize - stride - 3 + stride - 1) / stride - * = 4 - (inputsize - 4) / stride; - */ - level = 4 - (inputsize - 4) / stride; - } else { - /* For stage 2 translations the starting level is specified by the - * VTCR_EL2.SL0 field (whose interpretation depends on the page size) - */ - uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); - uint32_t sl2 = extract64(tcr->raw_tcr, 33, 1); - uint32_t startlevel; - bool ok; - - /* SL2 is RES0 unless DS=1 & 4kb granule. */ - if (param.ds && stride == 9 && sl2) { - if (sl0 != 0) { - level = 0; - fault_type = ARMFault_Translation; - goto do_fault; - } - startlevel = -1; - } else if (!aarch64 || stride == 9) { - /* AArch32 or 4KB pages */ - startlevel = 2 - sl0; - - if (cpu_isar_feature(aa64_st, cpu)) { - startlevel &= 3; - } - } else { - /* 16KB or 64KB pages */ - startlevel = 3 - sl0; - } - - /* Check that the starting level is valid. */ - ok = check_s2_mmu_setup(cpu, aarch64, startlevel, - inputsize, stride, outputsize); - if (!ok) { - fault_type = ARMFault_Translation; - goto do_fault; - } - level = startlevel; - } - - indexmask_grainsize = MAKE_64BIT_MASK(0, stride + 3); - indexmask = MAKE_64BIT_MASK(0, inputsize - (stride * (4 - level))); - - /* Now we can extract the actual base address from the TTBR */ - descaddr = extract64(ttbr, 0, 48); - - /* - * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR. - * - * Otherwise, if the base address is out of range, raise AddressSizeFault. - * In the pseudocode, this is !IsZero(baseregister<47:outputsize>), - * but we've just cleared the bits above 47, so simplify the test. - */ - if (outputsize > 48) { - descaddr |= extract64(ttbr, 2, 4) << 48; - } else if (descaddr >> outputsize) { - level = 0; - fault_type = ARMFault_AddressSize; - goto do_fault; - } - - /* - * We rely on this masking to clear the RES0 bits at the bottom of the TTBR - * and also to mask out CnP (bit 0) which could validly be non-zero. - */ - descaddr &= ~indexmask; - - /* - * For AArch32, the address field in the descriptor goes up to bit 39 - * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0 - * or an AddressSize fault is raised. So for v8 we extract those SBZ - * bits as part of the address, which will be checked via outputsize. - * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2; - * the highest bits of a 52-bit output are placed elsewhere. - */ - if (param.ds) { - descaddrmask = MAKE_64BIT_MASK(0, 50); - } else if (arm_feature(env, ARM_FEATURE_V8)) { - descaddrmask = MAKE_64BIT_MASK(0, 48); - } else { - descaddrmask = MAKE_64BIT_MASK(0, 40); - } - descaddrmask &= ~indexmask_grainsize; - - /* Secure accesses start with the page table in secure memory and - * can be downgraded to non-secure at any step. Non-secure accesses - * remain non-secure. We implement this by just ORing in the NSTable/NS - * bits at each step. - */ - tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); - for (;;) { - uint64_t descriptor; - bool nstable; - - descaddr |= (address >> (stride * (4 - level))) & indexmask; - descaddr &= ~7ULL; - nstable = extract32(tableattrs, 4, 1); - descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi); - if (fi->type != ARMFault_None) { - goto do_fault; - } - - if (!(descriptor & 1) || - (!(descriptor & 2) && (level == 3))) { - /* Invalid, or the Reserved level 3 encoding */ - goto do_fault; - } - - descaddr = descriptor & descaddrmask; - - /* - * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12] - * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of - * descaddr are in [9:8]. Otherwise, if descaddr is out of range, - * raise AddressSizeFault. - */ - if (outputsize > 48) { - if (param.ds) { - descaddr |= extract64(descriptor, 8, 2) << 50; - } else { - descaddr |= extract64(descriptor, 12, 4) << 48; - } - } else if (descaddr >> outputsize) { - fault_type = ARMFault_AddressSize; - goto do_fault; - } - - if ((descriptor & 2) && (level < 3)) { - /* Table entry. The top five bits are attributes which may - * propagate down through lower levels of the table (and - * which are all arranged so that 0 means "no effect", so - * we can gather them up by ORing in the bits at each level). - */ - tableattrs |= extract64(descriptor, 59, 5); - level++; - indexmask = indexmask_grainsize; - continue; - } - /* - * Block entry at level 1 or 2, or page entry at level 3. - * These are basically the same thing, although the number - * of bits we pull in from the vaddr varies. Note that although - * descaddrmask masks enough of the low bits of the descriptor - * to give a correct page or table address, the address field - * in a block descriptor is smaller; so we need to explicitly - * clear the lower bits here before ORing in the low vaddr bits. - */ - page_size = (1ULL << ((stride * (4 - level)) + 3)); - descaddr &= ~(page_size - 1); - descaddr |= (address & (page_size - 1)); - /* Extract attributes from the descriptor */ - attrs = extract64(descriptor, 2, 10) - | (extract64(descriptor, 52, 12) << 10); - - if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { - /* Stage 2 table descriptors do not include any attribute fields */ - break; - } - /* Merge in attributes from table descriptors */ - attrs |= nstable << 3; /* NS */ - guarded = extract64(descriptor, 50, 1); /* GP */ - if (param.hpd) { - /* HPD disables all the table attributes except NSTable. */ - break; - } - attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ - /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 - * means "force PL1 access only", which means forcing AP[1] to 0. - */ - attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */ - attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */ - break; - } - /* Here descaddr is the final physical address, and attributes - * are all in attrs. - */ - fault_type = ARMFault_AccessFlag; - if ((attrs & (1 << 8)) == 0) { - /* Access flag */ - goto do_fault; - } - - ap = extract32(attrs, 4, 2); - - if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { - ns = mmu_idx == ARMMMUIdx_Stage2; - xn = extract32(attrs, 11, 2); - *prot = get_S2prot(env, ap, xn, s1_is_el0); - } else { - ns = extract32(attrs, 3, 1); - xn = extract32(attrs, 12, 1); - pxn = extract32(attrs, 11, 1); - *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); - } - - fault_type = ARMFault_Permission; - if (!(*prot & (1 << access_type))) { - goto do_fault; - } - - if (ns) { - /* The NS bit will (as required by the architecture) have no effect if - * the CPU doesn't support TZ or this is a non-secure translation - * regime, because the attribute will already be non-secure. - */ - txattrs->secure = false; - } - /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ - if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { - arm_tlb_bti_gp(txattrs) = true; - } - - if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { - cacheattrs->is_s2_format = true; - cacheattrs->attrs = extract32(attrs, 0, 4); - } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx = extract32(attrs, 0, 3); - uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <= 7); - cacheattrs->is_s2_format = false; - cacheattrs->attrs = extract64(mair, attrindx * 8, 8); - } - - /* - * For FEAT_LPA2 and effective DS, the SH field in the attributes - * was re-purposed for output address bits. The SH attribute in - * that case comes from TCR_ELx, which we extracted earlier. - */ - if (param.ds) { - cacheattrs->shareability = param.sh; - } else { - cacheattrs->shareability = extract32(attrs, 6, 2); - } - - *phys_ptr = descaddr; - *page_size_ptr = page_size; - return false; - -do_fault: - fi->type = fault_type; - fi->level = level; - /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ - fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2 || - mmu_idx == ARMMMUIdx_Stage2_S); - fi->s1ns = mmu_idx == ARMMMUIdx_Stage2; - return true; -} - hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index f2ca2bb8fe1..cbccf91b132 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -314,6 +314,417 @@ do_fault: return true; } +/** + * get_phys_addr_lpae: perform one stage of page table walk, LPAE format + * + * Returns false if the translation was successful. Otherwise, phys_ptr, + * attrs, prot and page_size may not be filled in, and the populated fsr + * value provides information on why the translation aborted, in the format + * of a long-format DFSR/IFSR fault register, with the following caveat: + * the WnR bit is never set (the caller must do this). + * + * @env: CPUARMState + * @address: virtual address to get physical address for + * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH + * @mmu_idx: MMU index indicating required translation regime + * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page + * table walk), must be true if this is stage 2 of a stage 1+2 + * walk for an EL0 access. If @mmu_idx is anything else, + * @s1_is_el0 is ignored. + * @phys_ptr: set to the physical address corresponding to the virtual address + * @attrs: set to the memory transaction attributes to use + * @prot: set to the permissions for the page containing phys_ptr + * @page_size_ptr: set to the size of the page containing phys_ptr + * @fi: set to fault info if the translation fails + * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes + */ +bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + bool s1_is_el0, + hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, + target_ulong *page_size_ptr, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) +{ + ARMCPU *cpu = env_archcpu(env); + CPUState *cs = CPU(cpu); + /* Read an LPAE long-descriptor translation table. */ + ARMFaultType fault_type = ARMFault_Translation; + uint32_t level; + ARMVAParameters param; + uint64_t ttbr; + hwaddr descaddr, indexmask, indexmask_grainsize; + uint32_t tableattrs; + target_ulong page_size; + uint32_t attrs; + int32_t stride; + int addrsize, inputsize, outputsize; + TCR *tcr = regime_tcr(env, mmu_idx); + int ap, ns, xn, pxn; + uint32_t el = regime_el(env, mmu_idx); + uint64_t descaddrmask; + bool aarch64 = arm_el_is_aa64(env, el); + bool guarded = false; + + /* TODO: This code does not support shareability levels. */ + if (aarch64) { + int ps; + + param = aa64_va_parameters(env, address, mmu_idx, + access_type != MMU_INST_FETCH); + level = 0; + + /* + * If TxSZ is programmed to a value larger than the maximum, + * or smaller than the effective minimum, it is IMPLEMENTATION + * DEFINED whether we behave as if the field were programmed + * within bounds, or if a level 0 Translation fault is generated. + * + * With FEAT_LVA, fault on less than minimum becomes required, + * so our choice is to always raise the fault. + */ + if (param.tsz_oob) { + fault_type = ARMFault_Translation; + goto do_fault; + } + + addrsize = 64 - 8 * param.tbi; + inputsize = 64 - param.tsz; + + /* + * Bound PS by PARANGE to find the effective output address size. + * ID_AA64MMFR0 is a read-only register so values outside of the + * supported mappings can be considered an implementation error. + */ + ps = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + ps = MIN(ps, param.ps); + assert(ps < ARRAY_SIZE(pamax_map)); + outputsize = pamax_map[ps]; + } else { + param = aa32_va_parameters(env, address, mmu_idx); + level = 1; + addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32); + inputsize = addrsize - param.tsz; + outputsize = 40; + } + + /* + * We determined the region when collecting the parameters, but we + * have not yet validated that the address is valid for the region. + * Extract the top bits and verify that they all match select. + * + * For aa32, if inputsize == addrsize, then we have selected the + * region by exclusion in aa32_va_parameters and there is no more + * validation to do here. + */ + if (inputsize < addrsize) { + target_ulong top_bits = sextract64(address, inputsize, + addrsize - inputsize); + if (-top_bits != param.select) { + /* The gap between the two regions is a Translation fault */ + fault_type = ARMFault_Translation; + goto do_fault; + } + } + + if (param.using64k) { + stride = 13; + } else if (param.using16k) { + stride = 11; + } else { + stride = 9; + } + + /* + * Note that QEMU ignores shareability and cacheability attributes, + * so we don't need to do anything with the SH, ORGN, IRGN fields + * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the + * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently + * implement any ASID-like capability so we can ignore it (instead + * we will always flush the TLB any time the ASID is changed). + */ + ttbr = regime_ttbr(env, mmu_idx, param.select); + + /* + * Here we should have set up all the parameters for the translation: + * inputsize, ttbr, epd, stride, tbi + */ + + if (param.epd) { + /* + * Translation table walk disabled => Translation fault on TLB miss + * Note: This is always 0 on 64-bit EL2 and EL3. + */ + goto do_fault; + } + + if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) { + /* + * The starting level depends on the virtual address size (which can + * be up to 48 bits) and the translation granule size. It indicates + * the number of strides (stride bits at a time) needed to + * consume the bits of the input address. In the pseudocode this is: + * level = 4 - RoundUp((inputsize - grainsize) / stride) + * where their 'inputsize' is our 'inputsize', 'grainsize' is + * our 'stride + 3' and 'stride' is our 'stride'. + * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: + * = 4 - (inputsize - stride - 3 + stride - 1) / stride + * = 4 - (inputsize - 4) / stride; + */ + level = 4 - (inputsize - 4) / stride; + } else { + /* + * For stage 2 translations the starting level is specified by the + * VTCR_EL2.SL0 field (whose interpretation depends on the page size) + */ + uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); + uint32_t sl2 = extract64(tcr->raw_tcr, 33, 1); + uint32_t startlevel; + bool ok; + + /* SL2 is RES0 unless DS=1 & 4kb granule. */ + if (param.ds && stride == 9 && sl2) { + if (sl0 != 0) { + level = 0; + fault_type = ARMFault_Translation; + goto do_fault; + } + startlevel = -1; + } else if (!aarch64 || stride == 9) { + /* AArch32 or 4KB pages */ + startlevel = 2 - sl0; + + if (cpu_isar_feature(aa64_st, cpu)) { + startlevel &= 3; + } + } else { + /* 16KB or 64KB pages */ + startlevel = 3 - sl0; + } + + /* Check that the starting level is valid. */ + ok = check_s2_mmu_setup(cpu, aarch64, startlevel, + inputsize, stride, outputsize); + if (!ok) { + fault_type = ARMFault_Translation; + goto do_fault; + } + level = startlevel; + } + + indexmask_grainsize = MAKE_64BIT_MASK(0, stride + 3); + indexmask = MAKE_64BIT_MASK(0, inputsize - (stride * (4 - level))); + + /* Now we can extract the actual base address from the TTBR */ + descaddr = extract64(ttbr, 0, 48); + + /* + * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR. + * + * Otherwise, if the base address is out of range, raise AddressSizeFault. + * In the pseudocode, this is !IsZero(baseregister<47:outputsize>), + * but we've just cleared the bits above 47, so simplify the test. + */ + if (outputsize > 48) { + descaddr |= extract64(ttbr, 2, 4) << 48; + } else if (descaddr >> outputsize) { + level = 0; + fault_type = ARMFault_AddressSize; + goto do_fault; + } + + /* + * We rely on this masking to clear the RES0 bits at the bottom of the TTBR + * and also to mask out CnP (bit 0) which could validly be non-zero. + */ + descaddr &= ~indexmask; + + /* + * For AArch32, the address field in the descriptor goes up to bit 39 + * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0 + * or an AddressSize fault is raised. So for v8 we extract those SBZ + * bits as part of the address, which will be checked via outputsize. + * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2; + * the highest bits of a 52-bit output are placed elsewhere. + */ + if (param.ds) { + descaddrmask = MAKE_64BIT_MASK(0, 50); + } else if (arm_feature(env, ARM_FEATURE_V8)) { + descaddrmask = MAKE_64BIT_MASK(0, 48); + } else { + descaddrmask = MAKE_64BIT_MASK(0, 40); + } + descaddrmask &= ~indexmask_grainsize; + + /* + * Secure accesses start with the page table in secure memory and + * can be downgraded to non-secure at any step. Non-secure accesses + * remain non-secure. We implement this by just ORing in the NSTable/NS + * bits at each step. + */ + tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); + for (;;) { + uint64_t descriptor; + bool nstable; + + descaddr |= (address >> (stride * (4 - level))) & indexmask; + descaddr &= ~7ULL; + nstable = extract32(tableattrs, 4, 1); + descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi); + if (fi->type != ARMFault_None) { + goto do_fault; + } + + if (!(descriptor & 1) || + (!(descriptor & 2) && (level == 3))) { + /* Invalid, or the Reserved level 3 encoding */ + goto do_fault; + } + + descaddr = descriptor & descaddrmask; + + /* + * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12] + * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of + * descaddr are in [9:8]. Otherwise, if descaddr is out of range, + * raise AddressSizeFault. + */ + if (outputsize > 48) { + if (param.ds) { + descaddr |= extract64(descriptor, 8, 2) << 50; + } else { + descaddr |= extract64(descriptor, 12, 4) << 48; + } + } else if (descaddr >> outputsize) { + fault_type = ARMFault_AddressSize; + goto do_fault; + } + + if ((descriptor & 2) && (level < 3)) { + /* + * Table entry. The top five bits are attributes which may + * propagate down through lower levels of the table (and + * which are all arranged so that 0 means "no effect", so + * we can gather them up by ORing in the bits at each level). + */ + tableattrs |= extract64(descriptor, 59, 5); + level++; + indexmask = indexmask_grainsize; + continue; + } + /* + * Block entry at level 1 or 2, or page entry at level 3. + * These are basically the same thing, although the number + * of bits we pull in from the vaddr varies. Note that although + * descaddrmask masks enough of the low bits of the descriptor + * to give a correct page or table address, the address field + * in a block descriptor is smaller; so we need to explicitly + * clear the lower bits here before ORing in the low vaddr bits. + */ + page_size = (1ULL << ((stride * (4 - level)) + 3)); + descaddr &= ~(page_size - 1); + descaddr |= (address & (page_size - 1)); + /* Extract attributes from the descriptor */ + attrs = extract64(descriptor, 2, 10) + | (extract64(descriptor, 52, 12) << 10); + + if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { + /* Stage 2 table descriptors do not include any attribute fields */ + break; + } + /* Merge in attributes from table descriptors */ + attrs |= nstable << 3; /* NS */ + guarded = extract64(descriptor, 50, 1); /* GP */ + if (param.hpd) { + /* HPD disables all the table attributes except NSTable. */ + break; + } + attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ + /* + * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 + * means "force PL1 access only", which means forcing AP[1] to 0. + */ + attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */ + attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */ + break; + } + /* + * Here descaddr is the final physical address, and attributes + * are all in attrs. + */ + fault_type = ARMFault_AccessFlag; + if ((attrs & (1 << 8)) == 0) { + /* Access flag */ + goto do_fault; + } + + ap = extract32(attrs, 4, 2); + + if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { + ns = mmu_idx == ARMMMUIdx_Stage2; + xn = extract32(attrs, 11, 2); + *prot = get_S2prot(env, ap, xn, s1_is_el0); + } else { + ns = extract32(attrs, 3, 1); + xn = extract32(attrs, 12, 1); + pxn = extract32(attrs, 11, 1); + *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); + } + + fault_type = ARMFault_Permission; + if (!(*prot & (1 << access_type))) { + goto do_fault; + } + + if (ns) { + /* + * The NS bit will (as required by the architecture) have no effect if + * the CPU doesn't support TZ or this is a non-secure translation + * regime, because the attribute will already be non-secure. + */ + txattrs->secure = false; + } + /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ + if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { + arm_tlb_bti_gp(txattrs) = true; + } + + if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { + cacheattrs->is_s2_format = true; + cacheattrs->attrs = extract32(attrs, 0, 4); + } else { + /* Index into MAIR registers for cache attributes */ + uint8_t attrindx = extract32(attrs, 0, 3); + uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; + assert(attrindx <= 7); + cacheattrs->is_s2_format = false; + cacheattrs->attrs = extract64(mair, attrindx * 8, 8); + } + + /* + * For FEAT_LPA2 and effective DS, the SH field in the attributes + * was re-purposed for output address bits. The SH attribute in + * that case comes from TCR_ELx, which we extracted earlier. + */ + if (param.ds) { + cacheattrs->shareability = param.sh; + } else { + cacheattrs->shareability = extract32(attrs, 6, 2); + } + + *phys_ptr = descaddr; + *page_size_ptr = page_size; + return false; + +do_fault: + fi->type = fault_type; + fi->level = level; + /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ + fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2 || + mmu_idx == ARMMMUIdx_Stage2_S); + fi->s1ns = mmu_idx == ARMMMUIdx_Stage2; + return true; +} + static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, From patchwork Thu Jun 9 09:05:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580276 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp650976max; Thu, 9 Jun 2022 03:42:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwoHHVn2x4m4HIm9oodAUJt03A4Odd4ynhqSH7c94BsJ70gCB0G2ofqJcbpFlZOPqh54tyw X-Received: by 2002:a05:6214:518f:b0:464:5788:fe55 with SMTP id kl15-20020a056214518f00b004645788fe55mr40542166qvb.4.1654771369709; Thu, 09 Jun 2022 03:42:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654771369; cv=none; d=google.com; s=arc-20160816; b=XJ8pLrg0rwNII/Qn0Qf2gxoDO3kVJLdJYg9QwaaHlNCr+Cr2m0H19inm8F3xdrGzH7 mGxNlhtAlgqX6tJO65Pk3BAYrPpgwsvVu3YQpCkluN6ecX+7hyVl7jJVO0QPEbs+CQLN cRVVD1ZsSy+aCGpbghI/7HGQ1RPBP8ASVBB2nrghwwQWW8PPR0ipuDSceEqMHj+S73BC w1Aye7nxqLrP0bFmU74kPLP3EuCZ7UaQEiEmojR1siqpA57QVQnNvTd8Diq0pWf4f3eL tFOLuBXP28Oh6HuxMRsJpZLbZMZ5LTm9AeOpPg2EnfJYoxh8sC0kGp0L792dDDFzZ2Hd YwDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DsW3nbtPSrSfTu9Rena6hSRG4ePZWb5I260ZDnqhOaQ=; b=ZHbRgRka/NHSO8U/B5sTDAJOVqm1nA9eHD2FyYJ5Q+nwZg37vlpaxJ48f1ClZlTQXM TRZdFlmYgamf57PYPGL+ht0TiKL/URqKmHw3Tgn3+/E8Or/W77zET73j5tDKSvgpUE+c tEOtATeTlQQUH7aHPlWsE3j+PbsCH6n5+vkhg4a6kHM8zZTYeq44tqnUuDmTVO53zsyP 8ROZU4hgZD9dt9C3X5yyTElILlFEmJZMCT8CydSW3pQoNdcUEHaxaIYEEn94JIn2n8Nx F0zndOUrYqyH+6NtjOMRTP7hMi3V6w4rxK+clcFkcnPZMQi/osub3in3XQxFg4KegREs OuhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZZjTHK2s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ay32-20020a05620a17a000b006a6ae2b9d61si9341345qkb.725.2022.06.09.03.42.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:42:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZZjTHK2s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56302 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFcn-0008UO-4j for patch@linaro.org; Thu, 09 Jun 2022 06:42:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39548) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7K-0001Yq-H2 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:18 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:40576) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7F-000633-2Y for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:14 -0400 Received: by mail-wm1-x336.google.com with SMTP id j5-20020a05600c1c0500b0039c5dbbfa48so3048438wms.5 for ; Thu, 09 Jun 2022 02:06:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DsW3nbtPSrSfTu9Rena6hSRG4ePZWb5I260ZDnqhOaQ=; b=ZZjTHK2siwm0u69fTlk3CnlYIS06ODUXpXqs7PuwMYQkNILJofl0DleClJfx1XF4G4 BB9FhVDlNJWE98Q2x2vwZwa+qd3j1yHd5gKx1WA9bCFMR5OZGtfv27lau2MuDLtQxj0w WDRS+7X6X7EGeoY7sYtyT/TuoDyGjrKD5RDULq5gQVoP1pv5Uqg5VBK6e4vqwXkjXzeC FPwu8mJsuulorgRE+pvNYrkul6MjmEDnmXrOcip5BBsLzIevPn4hNdwrakldQhrx1561 BnDLN35bHB3J2O2frxFc1GolMWvvGujG2tXmXkByYInUv5rW1cnxwh9fMX3cYUxy9vye UsRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DsW3nbtPSrSfTu9Rena6hSRG4ePZWb5I260ZDnqhOaQ=; b=1fPPgN/x3u4JJsswXg64idTvGGsYlp3X31fty/FLZ+a1hRmRLlseXlxImL0dMNs2m0 Ry5pdn/kBgmT/l6Aym9TWUn8FCoCgGEivYHc1f6CMkd5pgxbffUqb3af81+FvCxYVA4l YB8P/XLm9pP5WyO3OXIyoCQiIXPzkPP+zXBznzhXpK6gu08MqBQUYvegQr17+TQPVKiZ 6wWfzA68ERANjXtERmxh8jt1FG1t+U0wYY0M4apGDOTQyB+ZI0IzlagAN5zw5/KMrzni WBpRfdrkhBDQLRlvNjbTJ0DKOkSzW1lqa0+3/POoR+tQOEQozRnFX2Sqv3xwoC28d7jl R0oQ== X-Gm-Message-State: AOAM530geySCj0DwIaz+Rmzy2FtSAB6s+Ou9OVU9D8ezlU5Nz4t2xOo3 Iy5ZbOds32WbTXs5mBtWsVksLtJ77iMxLQ== X-Received: by 2002:a05:600c:3792:b0:39c:6667:202 with SMTP id o18-20020a05600c379200b0039c66670202mr2254531wmr.104.1654765566707; Thu, 09 Jun 2022 02:06:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/55] target/arm: Move arm_{ldl,ldq}_ptw to ptw.c Date: Thu, 9 Jun 2022 10:05:05 +0100 Message-Id: <20220609090537.1971756-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Move the ptw load functions, plus 3 common subroutines: S1_ptw_translate, ptw_attrs_are_device, and regime_translation_big_endian. This also allows get_phys_addr_lpae to become static again. Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-17-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 13 ---- target/arm/helper.c | 141 -------------------------------------- target/arm/ptw.c | 160 ++++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 154 insertions(+), 160 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index 31744df6646..28b8cb9fb89 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -13,11 +13,6 @@ extern const uint8_t pamax_map[7]; -uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi); -uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi); - bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx); bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx); uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn); @@ -40,13 +35,5 @@ int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0); int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, int ap, int ns, int xn, int pxn); -bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool s1_is_el0, - hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, - target_ulong *page_size_ptr, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) - __attribute__((nonnull)); - #endif /* !CONFIG_USER_ONLY */ #endif /* TARGET_ARM_PTW_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 7de815fe986..398bcd62ab9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10475,12 +10475,6 @@ bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; } -static inline bool regime_translation_big_endian(CPUARMState *env, - ARMMMUIdx mmu_idx) -{ - return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; -} - /* Return the TTBR associated with this translation regime */ uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) { @@ -10773,141 +10767,6 @@ int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, return prot_rw | PAGE_EXEC; } -static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs) -{ - /* - * For an S1 page table walk, the stage 1 attributes are always - * some form of "this is Normal memory". The combined S1+S2 - * attributes are therefore only Device if stage 2 specifies Device. - * With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00, - * ie when cacheattrs.attrs bits [3:2] are 0b00. - * With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie - * when cacheattrs.attrs bit [2] is 0. - */ - assert(cacheattrs.is_s2_format); - if (arm_hcr_el2_eff(env) & HCR_FWB) { - return (cacheattrs.attrs & 0x4) == 0; - } else { - return (cacheattrs.attrs & 0xc) == 0; - } -} - -/* Translate a S1 pagetable walk through S2 if needed. */ -static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, - hwaddr addr, bool *is_secure, - ARMMMUFaultInfo *fi) -{ - if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { - target_ulong s2size; - hwaddr s2pa; - int s2prot; - int ret; - ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S - : ARMMMUIdx_Stage2; - ARMCacheAttrs cacheattrs = {}; - MemTxAttrs txattrs = {}; - - ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false, - &s2pa, &txattrs, &s2prot, &s2size, fi, - &cacheattrs); - if (ret) { - assert(fi->type != ARMFault_None); - fi->s2addr = addr; - fi->stage2 = true; - fi->s1ptw = true; - fi->s1ns = !*is_secure; - return ~0; - } - if ((arm_hcr_el2_eff(env) & HCR_PTW) && - ptw_attrs_are_device(env, cacheattrs)) { - /* - * PTW set and S1 walk touched S2 Device memory: - * generate Permission fault. - */ - fi->type = ARMFault_Permission; - fi->s2addr = addr; - fi->stage2 = true; - fi->s1ptw = true; - fi->s1ns = !*is_secure; - return ~0; - } - - if (arm_is_secure_below_el3(env)) { - /* Check if page table walk is to secure or non-secure PA space. */ - if (*is_secure) { - *is_secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); - } else { - *is_secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); - } - } else { - assert(!*is_secure); - } - - addr = s2pa; - } - return addr; -} - -/* All loads done in the course of a page table walk go through here. */ -uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) -{ - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - MemTxAttrs attrs = {}; - MemTxResult result = MEMTX_OK; - AddressSpace *as; - uint32_t data; - - addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); - attrs.secure = is_secure; - as = arm_addressspace(cs, attrs); - if (fi->s1ptw) { - return 0; - } - if (regime_translation_big_endian(env, mmu_idx)) { - data = address_space_ldl_be(as, addr, attrs, &result); - } else { - data = address_space_ldl_le(as, addr, attrs, &result); - } - if (result == MEMTX_OK) { - return data; - } - fi->type = ARMFault_SyncExternalOnWalk; - fi->ea = arm_extabort_type(result); - return 0; -} - -uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) -{ - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - MemTxAttrs attrs = {}; - MemTxResult result = MEMTX_OK; - AddressSpace *as; - uint64_t data; - - addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); - attrs.secure = is_secure; - as = arm_addressspace(cs, attrs); - if (fi->s1ptw) { - return 0; - } - if (regime_translation_big_endian(env, mmu_idx)) { - data = address_space_ldq_be(as, addr, attrs, &result); - } else { - data = address_space_ldq_le(as, addr, attrs, &result); - } - if (result == MEMTX_OK) { - return data; - } - fi->type = ARMFault_SyncExternalOnWalk; - fi->ea = arm_extabort_type(result); - return 0; -} - /* * check_s2_mmu_setup * @cpu: ARMCPU diff --git a/target/arm/ptw.c b/target/arm/ptw.c index cbccf91b132..e4b860d2aee 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -15,6 +15,154 @@ #include "ptw.h" +static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + bool s1_is_el0, hwaddr *phys_ptr, + MemTxAttrs *txattrs, int *prot, + target_ulong *page_size_ptr, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) + __attribute__((nonnull)); + +static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; +} + +static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs) +{ + /* + * For an S1 page table walk, the stage 1 attributes are always + * some form of "this is Normal memory". The combined S1+S2 + * attributes are therefore only Device if stage 2 specifies Device. + * With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00, + * ie when cacheattrs.attrs bits [3:2] are 0b00. + * With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie + * when cacheattrs.attrs bit [2] is 0. + */ + assert(cacheattrs.is_s2_format); + if (arm_hcr_el2_eff(env) & HCR_FWB) { + return (cacheattrs.attrs & 0x4) == 0; + } else { + return (cacheattrs.attrs & 0xc) == 0; + } +} + +/* Translate a S1 pagetable walk through S2 if needed. */ +static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, + hwaddr addr, bool *is_secure, + ARMMMUFaultInfo *fi) +{ + if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && + !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { + target_ulong s2size; + hwaddr s2pa; + int s2prot; + int ret; + ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S + : ARMMMUIdx_Stage2; + ARMCacheAttrs cacheattrs = {}; + MemTxAttrs txattrs = {}; + + ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false, + &s2pa, &txattrs, &s2prot, &s2size, fi, + &cacheattrs); + if (ret) { + assert(fi->type != ARMFault_None); + fi->s2addr = addr; + fi->stage2 = true; + fi->s1ptw = true; + fi->s1ns = !*is_secure; + return ~0; + } + if ((arm_hcr_el2_eff(env) & HCR_PTW) && + ptw_attrs_are_device(env, cacheattrs)) { + /* + * PTW set and S1 walk touched S2 Device memory: + * generate Permission fault. + */ + fi->type = ARMFault_Permission; + fi->s2addr = addr; + fi->stage2 = true; + fi->s1ptw = true; + fi->s1ns = !*is_secure; + return ~0; + } + + if (arm_is_secure_below_el3(env)) { + /* Check if page table walk is to secure or non-secure PA space. */ + if (*is_secure) { + *is_secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); + } else { + *is_secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + } + } else { + assert(!*is_secure); + } + + addr = s2pa; + } + return addr; +} + +/* All loads done in the course of a page table walk go through here. */ +static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, + ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + MemTxAttrs attrs = {}; + MemTxResult result = MEMTX_OK; + AddressSpace *as; + uint32_t data; + + addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); + attrs.secure = is_secure; + as = arm_addressspace(cs, attrs); + if (fi->s1ptw) { + return 0; + } + if (regime_translation_big_endian(env, mmu_idx)) { + data = address_space_ldl_be(as, addr, attrs, &result); + } else { + data = address_space_ldl_le(as, addr, attrs, &result); + } + if (result == MEMTX_OK) { + return data; + } + fi->type = ARMFault_SyncExternalOnWalk; + fi->ea = arm_extabort_type(result); + return 0; +} + +static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, + ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + MemTxAttrs attrs = {}; + MemTxResult result = MEMTX_OK; + AddressSpace *as; + uint64_t data; + + addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); + attrs.secure = is_secure; + as = arm_addressspace(cs, attrs); + if (fi->s1ptw) { + return 0; + } + if (regime_translation_big_endian(env, mmu_idx)) { + data = address_space_ldq_be(as, addr, attrs, &result); + } else { + data = address_space_ldq_le(as, addr, attrs, &result); + } + if (result == MEMTX_OK) { + return data; + } + fi->type = ARMFault_SyncExternalOnWalk; + fi->ea = arm_extabort_type(result); + return 0; +} + static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, uint32_t *table, uint32_t address) { @@ -338,12 +486,12 @@ do_fault: * @fi: set to fault info if the translation fails * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes */ -bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool s1_is_el0, - hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, - target_ulong *page_size_ptr, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) +static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + bool s1_is_el0, hwaddr *phys_ptr, + MemTxAttrs *txattrs, int *prot, + target_ulong *page_size_ptr, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { ARMCPU *cpu = env_archcpu(env); CPUState *cs = CPU(cpu); From patchwork Thu Jun 9 09:05:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580285 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp671316max; Thu, 9 Jun 2022 04:11:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzjHcifQErvM4R7UjDWu8JRAePEnZusz9RA5LYWcHPhHAD6a4hStCuui+pt9b2AvaVdfVbn X-Received: by 2002:ac8:57c6:0:b0:304:f163:bc5c with SMTP id w6-20020ac857c6000000b00304f163bc5cmr13976677qta.274.1654773069551; Thu, 09 Jun 2022 04:11:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654773069; cv=none; d=google.com; s=arc-20160816; b=bROGvfciKUgtIsHj3ajZEhoNJ8FSWuSlTlUnNQHrVVnRxfz+5TRqZ+/U+nmeakiS6J u+q4BepS0X+ftCxiNql9SxIgnf5ncnrcBBzymZ5bXyZ2XIJ0JodDBq038dYgbj4jsLSU lzNrZuaF35Z2QyW4TagLU/h8k/LTmTbO17tP4JVWeOZXfBl81/ldkBHizHFhlovnYdh1 gRSclvii7k+s1zSiW0xX1XxDpLSEVC/g8W8VQR0hYSBZO5gcXL8cLRzZNqHSpC9exVd9 rwExk/70kk6eWraHFu+/+pAOk3HUrSUKT4o3lQX1h96yeghN1brPhA0045sbvW/893/f 2+8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LQAbBz4sWCtAO2yu2KsDdB0OcUgNeqq9QInZEXr67f8=; b=0fl7Yke9wfiylXoLCH6Rfh/Iq5VcZHbv/5286m0WHnc99tRysSDr6mgRCvEB5AYVac oq305l/N2vapUHwPi6SxrTtrdZg/T0aoQDY0xZb/6wAcKbXwcyxl0iEfdI4Ttho0AGsB loXPH1DFGvfhNQkxySzPH7nYE0qwoYFcStAS7WC+x7BR4gOfIgzypYleHg5oXkkLPYNF vt044S0jvobWjrm9YR5vs3f5Jw/FLAgWOjJ42Z1pq8LAnUzwedBQnwtjMo7mHBo0HNeE eMCjHepnlPz6m/R6gg79DzRmJ8bnJO66pBc0qzLJ5yq5/mOM8UmqJooyBlBhURqtkScz fYJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uv2vHh+r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ef7-20020a05620a808700b006a6c193124fsi5406793qkb.110.2022.06.09.04.11.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 04:11:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uv2vHh+r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34472 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzG4D-0000zb-4s for patch@linaro.org; Thu, 09 Jun 2022 07:11:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39718) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7Q-0001ZE-JP for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:22 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:51890) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7H-000638-G6 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:19 -0400 Received: by mail-wm1-x331.google.com with SMTP id z17so7275188wmi.1 for ; Thu, 09 Jun 2022 02:06:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LQAbBz4sWCtAO2yu2KsDdB0OcUgNeqq9QInZEXr67f8=; b=uv2vHh+riZszdtFm3LFhhQ7v4NIhkOmxQbzVRPNGbcRLEMthArUO/YkdBK9RmAGGLx O5o7zGdZMSlq9CDf+t1porKCQqSAk1rtPs5BYKolvCoUIlXBLoiG2BoTqRc7XcN91NNu lkH5cgO0x5oTEHdgg/dNNF2Yu0XtBKW3gzdHTvqQWq13JPdqK6CHxhKH19EYGuRPUqB5 554cntq1TYAas6rBJ5Xv8WFSfBcFekr2rGAHT3PRubRq39KkM+JU38M2BzRFvX+Lwvep n/cBHbDPqjjop3CfwVsRoXiQOdaqPBPSSbRQzkdd6JpYSst5UZ52bWx/Hu3itj7kkJfi xomQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LQAbBz4sWCtAO2yu2KsDdB0OcUgNeqq9QInZEXr67f8=; b=Iw06qqy5GHMXeSEmmqmk4CuqP4O5mnN+5lbWQy9pT5mqR4E+iXpdlmkwmLinCFxTKO 4A7NPyaR4o/1CswYxpDUkw8ZgtpFe4coERV13+sWuGpdSGSAY8OjRAa84n9qP1HBlRNa VOWrKwU3qQWme2MxOb0qNOAKwWiOd40rNcNQIHuJcNYOIcmm4EYWDmPMsMdYF7Hl2WYK 7WQvZTXBWIy2lH5vjyUMILnNOjRqjLsQJrUnTkabE1elONmZhAJMrCBXJVkyHBnaMVl4 qJCtbFOw1XXz5b8LGmAK7/jTlYnZVMKpaTB8z1f60bRP045zJQAdhLfefIdREPrtHEhx 1uHw== X-Gm-Message-State: AOAM531QYqYzvRjzPvQRYO3vGzsqC4+mMnGEscMO/CW52BspRs6vbMUd Ef8B0q583+ljJBkyomDOt7xMYEQjJRKnuw== X-Received: by 2002:a05:600c:2244:b0:39c:4060:1ec9 with SMTP id a4-20020a05600c224400b0039c40601ec9mr2186915wmm.147.1654765567686; Thu, 09 Jun 2022 02:06:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/55] target/arm: Move {arm_s1_, }regime_using_lpae_format to tlb_helper.c Date: Thu, 9 Jun 2022 10:05:06 +0100 Message-Id: <20220609090537.1971756-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson These functions are used for both page table walking and for deciding what format in which to deliver exception results. Since ptw.c is only present for system mode, put the functions into tlb_helper.c. Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-18-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 24 ------------------------ target/arm/tlb_helper.c | 26 ++++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 24 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 398bcd62ab9..d2b196ff3e5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10515,30 +10515,6 @@ ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) } #endif /* !CONFIG_USER_ONLY */ -/* Return true if the translation regime is using LPAE format page tables */ -bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - int el = regime_el(env, mmu_idx); - if (el == 2 || arm_el_is_aa64(env, el)) { - return true; - } - if (arm_feature(env, ARM_FEATURE_LPAE) - && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { - return true; - } - return false; -} - -/* Returns true if the stage 1 translation regime is using LPAE format page - * tables. Used when raising alignment exceptions, whose FSR changes depending - * on whether the long or short descriptor format is in use. */ -bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - mmu_idx = stage_1_mmu_idx(mmu_idx); - - return regime_using_lpae_format(env, mmu_idx); -} - #ifndef CONFIG_USER_ONLY bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 6421e16202e..7d8a86b3c45 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -11,6 +11,32 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" + +/* Return true if the translation regime is using LPAE format page tables */ +bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + int el = regime_el(env, mmu_idx); + if (el == 2 || arm_el_is_aa64(env, el)) { + return true; + } + if (arm_feature(env, ARM_FEATURE_LPAE) + && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { + return true; + } + return false; +} + +/* + * Returns true if the stage 1 translation regime is using LPAE format page + * tables. Used when raising alignment exceptions, whose FSR changes depending + * on whether the long or short descriptor format is in use. + */ +bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + mmu_idx = stage_1_mmu_idx(mmu_idx); + return regime_using_lpae_format(env, mmu_idx); +} + static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, bool same_el, bool ea, From patchwork Thu Jun 9 09:05:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580260 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp623042max; Thu, 9 Jun 2022 03:02:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwtSJeYaHD1kusMJAPGgMUib0nuE/WgJzVaHuujo2IYt7lN/d/NWWNWR+kRKoVo3WO8PlKu X-Received: by 2002:a05:6214:2b07:b0:432:f7e6:e443 with SMTP id jx7-20020a0562142b0700b00432f7e6e443mr82586654qvb.125.1654768950262; Thu, 09 Jun 2022 03:02:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654768950; cv=none; d=google.com; s=arc-20160816; b=BpTR5fJCXJEbxQSs1Mu5RmMKA4QEGMtUQxk2PX2WjWdW2sxlpidNi9HLbJ0QOdod7E 3ISJl6zm/cH4rpK717mwHjQpESnAIyU9voX5pOfTr34az1AuH49lnq7cHFXEHxV+zlCc hvmYQW+8t8H0ug4M0/WxbHwTB99z9RY/WAUpk2wdJvnvTFgQW0T8HSHYAKLzxM6VuR8q 6hVxb6nF+PREUqEqirPkt21L/wc+kV8CWx0HxStsXE2tNDSKrzBrKlJd8Bm/3p9dpN+V BVfcNBcGL8IB9beT8T6kxXiUMFWLHLPZiTYU+8WyDvTVyNqVDmdXzbBsANru79nwtMxI kbBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vIokLa9eFuxFiVW77KIrOZU1hdMYpdkzIffZFBXlcuc=; b=GwmbUjWg1nrLyulQntf8EaieeT0PxtdG2kjeVrQXwGYp6TCqkqDOYLQAYjf8D8VO18 sA+5f+BJ6dxHWBaDbBoQdcVezoP1JDRavNK/+KmDZlgyJcIeuuusr0RNFzD+AmTPXo2x fIgqIUujuBn9mIZARTGpkCJY04+1X2bukhRabVobLcMjJ9zzMJjg8DiUkc0KXfszlkjX gqRUG0BTCxDFkplQG+ZpdPwhNS/kVtoxxnokSStuzM9mnbp/pdoSQ+vsZiqwP6XvKcGK amzJiWZ9iyNj8LSnrpd6VJkThO0qCxZ4ozRwUONyA0sC4+jhKilWAhfE0PNsWcFNisy1 3Igw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CQqjOu4D; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id gs3-20020a056214226300b004643305f0cfsi3103781qvb.130.2022.06.09.03.02.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:02:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CQqjOu4D; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEzl-0006Q7-L5 for patch@linaro.org; Thu, 09 Jun 2022 06:02:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7K-0001Yp-Gw for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:18 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:43563) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7H-00063C-GG for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:14 -0400 Received: by mail-wr1-x433.google.com with SMTP id d14so22478436wra.10 for ; Thu, 09 Jun 2022 02:06:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vIokLa9eFuxFiVW77KIrOZU1hdMYpdkzIffZFBXlcuc=; b=CQqjOu4DBavLPFvIx3KuaWUMdGxL+Q8upq+K2k83UjjqO8avt4fANTtmgyGvENzIlq bG0OrlgLufrp6AgPdkr3t7qpHgZT3zuQ0D439n6RukPJIZ5SNUbNuii8qTdWPz4QrjOc AVyfC+7kAnk1V2x0ArAjV/RvAQPp5LZDf7QDUl5OU0xmxWSu8YuI5eQ7vQPoLJSchP90 6T7Y0mBlOzlufl6Zmeo9GhOjGs7ZMvTSMn38YuuxleiRWjt4KOzE7Jq5mHjsB9mtMCQl VCtBi165GQz4C2P5vrROmlxyzPwcVyWR7OCnoRXhzMeWWd9DlAvr8x0e35IlhqfvVckp W2jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vIokLa9eFuxFiVW77KIrOZU1hdMYpdkzIffZFBXlcuc=; b=AMvyxtzxW2876YLWuIHObXdEjBtc7hwn5QzNckJIttp7OlY0vPPPSOUzvjS1ZmL3fI s85nNvdOv/7KiupUK4A+D9vzi4lN0l3ifLGERxUEOPhka3EppeHq0I5HoCU2Lh1GW998 XB/dcHK+epaHZuy+LVnepQxp8kfeQqEuEa6E8389O/BAFY5abinnaRn5kLpFFeteEkTY FwXBENKQZOQurpgAMFgaqR8eHw+cfW2f0TjueKloLnkdfC+c9vMGU4M7ATFgvL90fr4c z52WShNCUwqnNe8Abm2gO7WwegFdYLEt5p0q8cHdBqMNOz1kbDGTThZzXV/j4kMZKRkA zM8w== X-Gm-Message-State: AOAM533veghIVQEDxBJFw+6d+RlP5E2dd31Zhcb9iHQSCF+TC65jmsnR lFAmSQsCKE5WxSazzfX4yt9ryLBLVpCshQ== X-Received: by 2002:a05:6000:1acc:b0:20f:f12a:a535 with SMTP id i12-20020a0560001acc00b0020ff12aa535mr39078137wry.375.1654765568513; Thu, 09 Jun 2022 02:06:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/55] target/arm: Move arm_pamax, pamax_map into ptw.c Date: Thu, 9 Jun 2022 10:05:07 +0100 Message-Id: <20220609090537.1971756-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-19-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 2 -- target/arm/helper.c | 25 ------------------------- target/arm/ptw.c | 25 +++++++++++++++++++++++++ 3 files changed, 25 insertions(+), 27 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index 28b8cb9fb89..fba650d01ca 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -11,8 +11,6 @@ #ifndef CONFIG_USER_ONLY -extern const uint8_t pamax_map[7]; - bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx); bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx); uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn); diff --git a/target/arm/helper.c b/target/arm/helper.c index d2b196ff3e5..563e34ecded 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10814,31 +10814,6 @@ bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, } #endif /* !CONFIG_USER_ONLY */ -/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ -const uint8_t pamax_map[] = { - [0] = 32, - [1] = 36, - [2] = 40, - [3] = 42, - [4] = 44, - [5] = 48, - [6] = 52, -}; - -/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ -unsigned int arm_pamax(ARMCPU *cpu) -{ - unsigned int parange = - FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); - - /* - * id_aa64mmfr0 is a read-only register so values outside of the - * supported mappings can be considered an implementation error. - */ - assert(parange < ARRAY_SIZE(pamax_map)); - return pamax_map[parange]; -} - int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) { if (regime_has_2_ranges(mmu_idx)) { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e4b860d2aee..d754273fa16 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -23,6 +23,31 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) __attribute__((nonnull)); +/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ +static const uint8_t pamax_map[] = { + [0] = 32, + [1] = 36, + [2] = 40, + [3] = 42, + [4] = 44, + [5] = 48, + [6] = 52, +}; + +/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ +unsigned int arm_pamax(ARMCPU *cpu) +{ + unsigned int parange = + FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + + /* + * id_aa64mmfr0 is a read-only register so values outside of the + * supported mappings can be considered an implementation error. + */ + assert(parange < ARRAY_SIZE(pamax_map)); + return pamax_map[parange]; +} + static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx) { return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; From patchwork Thu Jun 9 09:05:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580257 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp619178max; Thu, 9 Jun 2022 02:57:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJygeZYK5WmpjHpVz6JenAFFXPwoA/dMCmDss6GW63JNbc0wVoma+OjTQQK8PLOTCKrbuQ7E X-Received: by 2002:a05:620a:1914:b0:6a6:b473:b217 with SMTP id bj20-20020a05620a191400b006a6b473b217mr15158255qkb.65.1654768632602; Thu, 09 Jun 2022 02:57:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654768632; cv=none; d=google.com; s=arc-20160816; b=NFMZnPKjL7Ht0YTALHZ5d9eXUijXwtFkg1NYVmPWqQW6a+TR5seEvyNeZTsTx0KZUI Ez0WpMyf7kk6xRcccRctsf1UZS2ASKZMVlq8Mxi1yitHNr11Ij0pZk+W+WSJ4/TEvvMW xIqz/4m6z/7/Rku+LALSgbUbBBJNf+awxC6RggpMKTnt9OcjJpnJ/+c2jmpUIYc6D6Xp TaJa5TaskeK1hL7VJ3DMq0I5zwpL+FbDtX0ZIPWtoTef0TBZd0vpu+7RmPfe9WLHTfPj 05i/IbSxI8GgOX/g5zLTgd9psdRXI9sj7W/8uqvwx5O8qsdWnXbgAAgb5/xTgMNHAkL3 PUfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NZ83DvVjSP5f3cqPypoQ1LPQjwV9cfTRg8x9u5U5b3g=; b=m9+iEJ2jtl7QCEX3MhMcE63qOwfFWc7DPeE0wzQWsjuuNts9BIpG8Y3EgIoqArrsXc mQ6rJhMUsm0wEpueiVAVcQjIXE5t8Iw2omrALMGXw27zcr0KKWo3Y8wK2AYiWMj2xu2t N8YH3EomupH+pVd+/YsZYw4DBRT8jbkcPpSD6yIi1oJEb/rfERi0IlsHbfRo/Vaq7hLC C2lch2sSxdeaXXz6RHgSiM2hgcdPednnNhWju7y+RDHRecz2rgWBZ2BOB/YS5zAjxd7O ft6L6FVx04FpL0/Q4lwObM5oMInLyN/UH+piofct0BPl/k0SmtE9rBY99rGDFiQGeGaj SbNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fZa6bg6q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o21-20020ac87c55000000b0030511cdf49fsi188613qtv.55.2022.06.09.02.57.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:57:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fZa6bg6q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40056 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEue-0000Iq-3Q for patch@linaro.org; Thu, 09 Jun 2022 05:57:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39862) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7W-0001ci-Pq for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:28 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:38492) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7G-0005vV-Hm for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:26 -0400 Received: by mail-wr1-x430.google.com with SMTP id v14so5217169wra.5 for ; Thu, 09 Jun 2022 02:06:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NZ83DvVjSP5f3cqPypoQ1LPQjwV9cfTRg8x9u5U5b3g=; b=fZa6bg6qSNkmXf57PyJdhOmHbZVgPgo9omqBX1ryW+WwjPjDi4aIn8AU9k9NFiBpFq pErvXrBSbSSRMWExtYBG7c/5veva9BgeP08Rx68+TU2s4nM1kalUNhbdngddleEhOyIG TGqzqznfGO3valMdZqn9/7iliaI7XKI7zy0NCstvLf8z1xzuGNb0odFnTWw+OHvJUyXA EPAnhhbLr9iA+pvmiwtjqkf9DKAFKjeyOAFS6/2u+2rjOPdbGonG0uj26mLhVIMZ7U6k Vfiy4du8asrK6tvvGjmKGX1RiurywbKrFMzgFZgtxWLzkOLdhYffqUG0nrFT0gIFjIrR f8BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NZ83DvVjSP5f3cqPypoQ1LPQjwV9cfTRg8x9u5U5b3g=; b=eQGHIi5n9DHXdZRi23F8NbcLS3/HUvXak0HYYRUhkl+IMsPVNgqDfm/t+BmlvFOgSj XvnwRcP4X1LvErqp75XBMmjapOnou1UkQJfskeV7VbZC88Dx8hWmlUl3mwUAypRqMCDy YhQEHbHwElIrxHaggcXWtKAHKmD+mG4NtlruKUhkt39z28sxMh0WtsrffQp+jow6xDVI DVBW7hei/wM2aXS5k4Zig1rUGZTR29tcVVUDvpChN9vppozgHHIX7tijoDwjjbq9pjj5 IH2/J7B6YgxqVcTRo7FENkPiFAFR5hyGwzdcdnGzNBz+dutdeIHlX4lmri/PeTwJHZhh fosw== X-Gm-Message-State: AOAM532ccOxflbNYf3+fIC/1KaWf2cNzVCcrGuBFNMQuHp9HeOx6vAYg scsXXZrA33U0hCCpdcdrcpMBKQk77VYflA== X-Received: by 2002:a5d:67c2:0:b0:215:7a0f:71f9 with SMTP id n2-20020a5d67c2000000b002157a0f71f9mr30973731wrw.486.1654765569593; Thu, 09 Jun 2022 02:06:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/55] target/arm: Move get_S1prot, get_S2prot to ptw.c Date: Thu, 9 Jun 2022 10:05:08 +0100 Message-Id: <20220609090537.1971756-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-20-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 3 -- target/arm/helper.c | 128 -------------------------------------------- target/arm/ptw.c | 128 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 128 insertions(+), 131 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index fba650d01ca..93147e0b065 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -29,9 +29,6 @@ ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx); bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, int inputsize, int stride, int outputsize); -int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0); -int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, - int ap, int ns, int xn, int pxn); #endif /* !CONFIG_USER_ONLY */ #endif /* TARGET_ARM_PTW_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 563e34ecded..148eb28ba8c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10615,134 +10615,6 @@ int simple_ap_to_rw_prot_is_user(int ap, bool is_user) } } -/* Translate S2 section/page access permissions to protection flags - * - * @env: CPUARMState - * @s2ap: The 2-bit stage2 access permissions (S2AP) - * @xn: XN (execute-never) bits - * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 - */ -int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) -{ - int prot = 0; - - if (s2ap & 1) { - prot |= PAGE_READ; - } - if (s2ap & 2) { - prot |= PAGE_WRITE; - } - - if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { - switch (xn) { - case 0: - prot |= PAGE_EXEC; - break; - case 1: - if (s1_is_el0) { - prot |= PAGE_EXEC; - } - break; - case 2: - break; - case 3: - if (!s1_is_el0) { - prot |= PAGE_EXEC; - } - break; - default: - g_assert_not_reached(); - } - } else { - if (!extract32(xn, 1, 1)) { - if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { - prot |= PAGE_EXEC; - } - } - } - return prot; -} - -/* Translate section/page access permissions to protection flags - * - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * @is_aa64: TRUE if AArch64 - * @ap: The 2-bit simple AP (AP[2:1]) - * @ns: NS (non-secure) bit - * @xn: XN (execute-never) bit - * @pxn: PXN (privileged execute-never) bit - */ -int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, - int ap, int ns, int xn, int pxn) -{ - bool is_user = regime_is_user(env, mmu_idx); - int prot_rw, user_rw; - bool have_wxn; - int wxn = 0; - - assert(mmu_idx != ARMMMUIdx_Stage2); - assert(mmu_idx != ARMMMUIdx_Stage2_S); - - user_rw = simple_ap_to_rw_prot_is_user(ap, true); - if (is_user) { - prot_rw = user_rw; - } else { - if (user_rw && regime_is_pan(env, mmu_idx)) { - /* PAN forbids data accesses but doesn't affect insn fetch */ - prot_rw = 0; - } else { - prot_rw = simple_ap_to_rw_prot_is_user(ap, false); - } - } - - if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { - return prot_rw; - } - - /* TODO have_wxn should be replaced with - * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) - * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE - * compatible processors have EL2, which is required for [U]WXN. - */ - have_wxn = arm_feature(env, ARM_FEATURE_LPAE); - - if (have_wxn) { - wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; - } - - if (is_aa64) { - if (regime_has_2_ranges(mmu_idx) && !is_user) { - xn = pxn || (user_rw & PAGE_WRITE); - } - } else if (arm_feature(env, ARM_FEATURE_V7)) { - switch (regime_el(env, mmu_idx)) { - case 1: - case 3: - if (is_user) { - xn = xn || !(user_rw & PAGE_READ); - } else { - int uwxn = 0; - if (have_wxn) { - uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; - } - xn = xn || !(prot_rw & PAGE_READ) || pxn || - (uwxn && (user_rw & PAGE_WRITE)); - } - break; - case 2: - break; - } - } else { - xn = wxn = 0; - } - - if (xn || (wxn && (prot_rw & PAGE_WRITE))) { - return prot_rw; - } - return prot_rw | PAGE_EXEC; -} - /* * check_s2_mmu_setup * @cpu: ARMCPU diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d754273fa16..af9ad420288 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -487,6 +487,134 @@ do_fault: return true; } +/* + * Translate S2 section/page access permissions to protection flags + * @env: CPUARMState + * @s2ap: The 2-bit stage2 access permissions (S2AP) + * @xn: XN (execute-never) bits + * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 + */ +static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) +{ + int prot = 0; + + if (s2ap & 1) { + prot |= PAGE_READ; + } + if (s2ap & 2) { + prot |= PAGE_WRITE; + } + + if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { + switch (xn) { + case 0: + prot |= PAGE_EXEC; + break; + case 1: + if (s1_is_el0) { + prot |= PAGE_EXEC; + } + break; + case 2: + break; + case 3: + if (!s1_is_el0) { + prot |= PAGE_EXEC; + } + break; + default: + g_assert_not_reached(); + } + } else { + if (!extract32(xn, 1, 1)) { + if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { + prot |= PAGE_EXEC; + } + } + } + return prot; +} + +/* + * Translate section/page access permissions to protection flags + * @env: CPUARMState + * @mmu_idx: MMU index indicating required translation regime + * @is_aa64: TRUE if AArch64 + * @ap: The 2-bit simple AP (AP[2:1]) + * @ns: NS (non-secure) bit + * @xn: XN (execute-never) bit + * @pxn: PXN (privileged execute-never) bit + */ +static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, + int ap, int ns, int xn, int pxn) +{ + bool is_user = regime_is_user(env, mmu_idx); + int prot_rw, user_rw; + bool have_wxn; + int wxn = 0; + + assert(mmu_idx != ARMMMUIdx_Stage2); + assert(mmu_idx != ARMMMUIdx_Stage2_S); + + user_rw = simple_ap_to_rw_prot_is_user(ap, true); + if (is_user) { + prot_rw = user_rw; + } else { + if (user_rw && regime_is_pan(env, mmu_idx)) { + /* PAN forbids data accesses but doesn't affect insn fetch */ + prot_rw = 0; + } else { + prot_rw = simple_ap_to_rw_prot_is_user(ap, false); + } + } + + if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { + return prot_rw; + } + + /* TODO have_wxn should be replaced with + * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) + * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE + * compatible processors have EL2, which is required for [U]WXN. + */ + have_wxn = arm_feature(env, ARM_FEATURE_LPAE); + + if (have_wxn) { + wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; + } + + if (is_aa64) { + if (regime_has_2_ranges(mmu_idx) && !is_user) { + xn = pxn || (user_rw & PAGE_WRITE); + } + } else if (arm_feature(env, ARM_FEATURE_V7)) { + switch (regime_el(env, mmu_idx)) { + case 1: + case 3: + if (is_user) { + xn = xn || !(user_rw & PAGE_READ); + } else { + int uwxn = 0; + if (have_wxn) { + uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; + } + xn = xn || !(prot_rw & PAGE_READ) || pxn || + (uwxn && (user_rw & PAGE_WRITE)); + } + break; + case 2: + break; + } + } else { + xn = wxn = 0; + } + + if (xn || (wxn && (prot_rw & PAGE_WRITE))) { + return prot_rw; + } + return prot_rw | PAGE_EXEC; +} + /** * get_phys_addr_lpae: perform one stage of page table walk, LPAE format * From patchwork Thu Jun 9 09:05:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580264 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp630132max; Thu, 9 Jun 2022 03:11:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyK3ULdqxbVGaO/5VjO8gvMGennvug/nww4cIj7U9iACAFe8VVz0tlgDkSx1hxbtJnhTVTK X-Received: by 2002:ac8:5a53:0:b0:305:12:fc8f with SMTP id o19-20020ac85a53000000b003050012fc8fmr7235689qta.446.1654769503883; Thu, 09 Jun 2022 03:11:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654769503; cv=none; d=google.com; s=arc-20160816; b=uhsEq7/zrsl+GzB9stxUchupyPCeyavwM5mDoBCrcrs9FUmX84dUcxQHp4mcBzftr8 fm+dh5z3d2y2L9v/vSFoaER0Tp3UBSiJWjiklHfduTlRhNRXLgyo3ZC4Wp+GeTbcdMZv IaY8Jq2zrrSLjfgsU1PrPT3kdlLeQK3IGASUgUHVpxC3IB0FVSst6rM8ruyEw53aWvE5 a7O6QKDYgFORIH/YfvoUVDf06RcOA5ZWwhQ5vXSczP6vlLpvg08S1UkC0tR90XImB9b7 1lKVSsH05BaH7y2eqZ5NVbcPcdl9UEniIgHO5XLBkV1EYQpIryl7gEVf72mXqlfUs8+T SdLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7iWAmr8aLaBxhjnqmS0IabAjJ74tn9UJA1n63C3136o=; b=0oFpmN2aoWEV9M4cJkVau1WYW+S8Y+CO8QHFzBTVvbwtu9XGW/i4exifM1Jvco/XRW 1NLmilw19S6jkXkCpUe4mQQ6KrvzP0V5cDcuXfJ7k8LvKWBaSZhCJL2ZnlYJ+fIngH+0 x2YjydEIGBhhgAEXnMxYiaRe8HU6UFUz7qjhquHlvunuRiCc8F1DnHyb2pCTJFNeCg6H ImquEcbgavqknP9JdOMjEo8HvMRgkHvRtRzq+WFTcW4NZ3dqRtOtvCEkQ0u389yHlejP 29y7db4eZixHBTrVQV5ZbXnM/5J0to6Sl5cf6yR2HnfyKd8tDFnUOyQlLVC+OyFCygRc 8Rcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HNL4ROPL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b23-20020a05620a119700b006a6ab2932f3si7978518qkk.642.2022.06.09.03.11.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:11:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HNL4ROPL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57416 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzF8h-00055p-3j for patch@linaro.org; Thu, 09 Jun 2022 06:11:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39580) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7L-0001Ys-U6 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:18 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:46819) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7H-0005xd-GH for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:15 -0400 Received: by mail-wr1-x435.google.com with SMTP id u8so27137707wrm.13 for ; Thu, 09 Jun 2022 02:06:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7iWAmr8aLaBxhjnqmS0IabAjJ74tn9UJA1n63C3136o=; b=HNL4ROPLJvjh4JaPHTWCeUuweTRQ81y7PyFIBHd8wx4uAjAR7e8JuBTNbKpZ5Y4sM1 B/4dZpBRuvmT8LhC8EsqHjb/ebNsHqM3pvSfiswEk0PaQHHt9vYFIhumMcRglNlkFwCS 80rzdEVa0xIG1NacQAeV2TK+8IWK0trkcpEt7QwYFxBrauGgeY2L9I5fxcaDGnuL7OwV STS0II2jv8amtgt6r48vq9Y0AGK3NPpRGCUVDWESqJToqwQckfKKT4L8hOefQmQHU5w8 lYR9AFPAT/2FbqkqTOPj6hydajpOWmBsNgj4y3609MxIQOn7HNg3X0gXIa49CCx/fsBa m7hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7iWAmr8aLaBxhjnqmS0IabAjJ74tn9UJA1n63C3136o=; b=Pd8yJRLdVAcReDENDMQzyyC0is3nJERN49fAi1Z330x1xJEu68npVkpJuZ4A0CHlt7 +fLf+5CJBOoNxnS408bOd/qPDCaG4c0/Tq8Uqpp1cRu4pMqhZeq5zV5SnJ7nyIsPOIqz +KjJkupABarHsSjXJeMsOPJTLzep5iWq4QPu8WI5cj9AJg3w/Ft/3f4FsTqMcG5glr/+ 1pErzJajFtI9nA/82/3ueR+6w7WsTxbciTkP/2gDYakKjnyWhotI4BM51r9GVI6GaxCa W3/9MOeTFyza4Q9Vbo/DviLJeum2rBLeMyTF3Zvjb4zirfTbjEYuWXKBYLlyskPZTqff bu+A== X-Gm-Message-State: AOAM533CKrpbzijRKLfq209oKLvAuUu6wEKeelbyiT1mTqFD6mqbPTnl zOO0FiwOVCQgwWd5nvqWvJ/ZBg3Q9cNEUw== X-Received: by 2002:a5d:620b:0:b0:210:11d9:770 with SMTP id y11-20020a5d620b000000b0021011d90770mr37270326wru.11.1654765570493; Thu, 09 Jun 2022 02:06:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/55] target/arm: Move check_s2_mmu_setup to ptw.c Date: Thu, 9 Jun 2022 10:05:09 +0100 Message-Id: <20220609090537.1971756-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-21-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 2 -- target/arm/helper.c | 70 --------------------------------------------- target/arm/ptw.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+), 72 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index 93147e0b065..a71161b01bd 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -27,8 +27,6 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx); -bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, - int inputsize, int stride, int outputsize); #endif /* !CONFIG_USER_ONLY */ #endif /* TARGET_ARM_PTW_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 148eb28ba8c..2526f4c6c4a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10614,76 +10614,6 @@ int simple_ap_to_rw_prot_is_user(int ap, bool is_user) g_assert_not_reached(); } } - -/* - * check_s2_mmu_setup - * @cpu: ARMCPU - * @is_aa64: True if the translation regime is in AArch64 state - * @startlevel: Suggested starting level - * @inputsize: Bitsize of IPAs - * @stride: Page-table stride (See the ARM ARM) - * - * Returns true if the suggested S2 translation parameters are OK and - * false otherwise. - */ -bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, - int inputsize, int stride, int outputsize) -{ - const int grainsize = stride + 3; - int startsizecheck; - - /* - * Negative levels are usually not allowed... - * Except for FEAT_LPA2, 4k page table, 52-bit address space, which - * begins with level -1. Note that previous feature tests will have - * eliminated this combination if it is not enabled. - */ - if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) { - return false; - } - - startsizecheck = inputsize - ((3 - level) * stride + grainsize); - if (startsizecheck < 1 || startsizecheck > stride + 4) { - return false; - } - - if (is_aa64) { - switch (stride) { - case 13: /* 64KB Pages. */ - if (level == 0 || (level == 1 && outputsize <= 42)) { - return false; - } - break; - case 11: /* 16KB Pages. */ - if (level == 0 || (level == 1 && outputsize <= 40)) { - return false; - } - break; - case 9: /* 4KB Pages. */ - if (level == 0 && outputsize <= 42) { - return false; - } - break; - default: - g_assert_not_reached(); - } - - /* Inputsize checks. */ - if (inputsize > outputsize && - (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) { - /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ - return false; - } - } else { - /* AArch32 only supports 4KB pages. Assert on that. */ - assert(stride == 9); - - if (level == 0) { - return false; - } - } - return true; -} #endif /* !CONFIG_USER_ONLY */ int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index af9ad420288..525272e99af 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -615,6 +615,76 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, return prot_rw | PAGE_EXEC; } +/* + * check_s2_mmu_setup + * @cpu: ARMCPU + * @is_aa64: True if the translation regime is in AArch64 state + * @startlevel: Suggested starting level + * @inputsize: Bitsize of IPAs + * @stride: Page-table stride (See the ARM ARM) + * + * Returns true if the suggested S2 translation parameters are OK and + * false otherwise. + */ +static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, + int inputsize, int stride, int outputsize) +{ + const int grainsize = stride + 3; + int startsizecheck; + + /* + * Negative levels are usually not allowed... + * Except for FEAT_LPA2, 4k page table, 52-bit address space, which + * begins with level -1. Note that previous feature tests will have + * eliminated this combination if it is not enabled. + */ + if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) { + return false; + } + + startsizecheck = inputsize - ((3 - level) * stride + grainsize); + if (startsizecheck < 1 || startsizecheck > stride + 4) { + return false; + } + + if (is_aa64) { + switch (stride) { + case 13: /* 64KB Pages. */ + if (level == 0 || (level == 1 && outputsize <= 42)) { + return false; + } + break; + case 11: /* 16KB Pages. */ + if (level == 0 || (level == 1 && outputsize <= 40)) { + return false; + } + break; + case 9: /* 4KB Pages. */ + if (level == 0 && outputsize <= 42) { + return false; + } + break; + default: + g_assert_not_reached(); + } + + /* Inputsize checks. */ + if (inputsize > outputsize && + (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) { + /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ + return false; + } + } else { + /* AArch32 only supports 4KB pages. Assert on that. */ + assert(stride == 9); + + if (level == 0) { + return false; + } + } + return true; +} + /** * get_phys_addr_lpae: perform one stage of page table walk, LPAE format * From patchwork Thu Jun 9 09:05:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580245 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp600500max; Thu, 9 Jun 2022 02:28:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwXzqKAn60iXXkeTsjjNRTKnEb3KGT3TXME0We9i4MtRXQtd9MssVH7s5MZlZyzVFv2Fk6k X-Received: by 2002:a05:6214:62f:b0:468:1689:a1d8 with SMTP id a15-20020a056214062f00b004681689a1d8mr23305341qvx.0.1654766891028; Thu, 09 Jun 2022 02:28:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654766891; cv=none; d=google.com; s=arc-20160816; b=OJUJTbYmn2E7pcomSxfozDNYoDW6rBPUTIYyCwnlW2l+nqW11WH+L1i6tkK76YgUTN i1up5f5uBUKAAJzmJ4faImSBJHxU/1NOhbRACtDvNfqFT1ExRSRu/Oo2Rmb9KFeqh+Z7 ssQqW9Gx1TuTr6PKC5G/BnX5XtAqVGFozOxGT39QLjaeMRjjFkvQMW5dEQLiwguBgGWK xScTmiL3RVfIlEznOV9aGazKUyYzTqZDnew5Md7McR9RRSwW5IAli4Re9bK1L3K4vnrZ OJsVyeXthmba5Ag5WxEq10rbgVzJ+fY/8kkq+DjYJ7p2m0pa2oLTxdSfIp/osc79O9Qc Eepg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NDy5L1j1NFeCwxkRreoifiteCmt9uSlmxDgPX55fTNU=; b=W/TLhT+ZhB3NKhq26OWl2AXmN1OPvlvsKPKxAHwpRYoiFv8ZVCPo9qRFfLNURGYz2P 1qj8sWoUb/K/C4nRjjCSj7AR7pcpEv7UPJGMwQnOJGpAmblRnN0WDKJtXFE76UkUN5wN VUngfWlPtdmrem5KwxxrbvWXSgh+c8j6W/RPKbrdir3NiBD5mTd47ob1ILbWNhp/Ck1C 4rAPt7wLeys5TrJDnwc2LO5Jg3GDki4AjKN4s//c/LzOpQdM1iagaXU8cMxIxBuT3h6J ljG1ojXuLMM5gVyPi0Y9svL+rOwXdxHRNczI3lmw59ULbAe7ECoimnoBWGiOPMk3kxqj 5N/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rn1tLAMC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j2-20020ae9c202000000b006a57b09338asi7525713qkg.726.2022.06.09.02.28.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:28:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rn1tLAMC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41924 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzESW-00068f-HN for patch@linaro.org; Thu, 09 Jun 2022 05:28:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39648) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7O-0001Z0-C6 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:21 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:33709) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7J-00063a-3z for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:16 -0400 Received: by mail-wr1-x433.google.com with SMTP id h5so31518410wrb.0 for ; Thu, 09 Jun 2022 02:06:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NDy5L1j1NFeCwxkRreoifiteCmt9uSlmxDgPX55fTNU=; b=rn1tLAMCWtRlYx+ukNHwDCZj515mfgswJ40a7U18/L+lO0lftUle6LtLJeyoL/RR0U RD6fk/Zm9bLDbnBO0SJrf4oNqdRMTWGVuqPjxxWUDrXcf18+rGC76tauOmVJ9qoxL/z+ NJozbTPGz3tExs0djCv+dhNvWukoUPtLIaYGqaG3g85gqbV8ITy3roqwoKTO/axTWtM4 1v3+j1zlAo0EZbXcgWmtPpG3mZ1fAwvb94GZj3fdFF/Pw66G0yQWV6rX8NxIsCCMBGXc x7KzeEnGwSJR0cCmw1TDKcrZd2Wyv/Sz79GkKx6DFIhAjX/CLJ18Taz4eXwCG+2KfLVF mwVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NDy5L1j1NFeCwxkRreoifiteCmt9uSlmxDgPX55fTNU=; b=WhLQMpp7OIQHBXsMowJqVTSIO7QcY5dx+I+GuW+lwEEnIeTXHcnqab4J5AP4GaI932 7S2iXKOlbBn59uyFs40KAqWZAU2MjIRDY7hd0Lb1eN9iZYxJGFU5EA+Dkh5hxWR3meoj R6EhNqaAF2atUNBJmpCJKuVBzyPKczlvM520bqKWkWVcNu0fj+mJ44ZfwcHgfybkM7i3 oaQxm/+zW5gAK9qH8lEQ+Ov/q3e16Ya+bAAbtjK/Hol5NuarvSS1kwybzCS1IpSI4BGL YC9XCiB7KZj2DtxtYkwqULB1sjAi8wpj+5/TPpogKVK57OBVngj9v1FcYh4LFaBob2r1 SodQ== X-Gm-Message-State: AOAM532dr2dVZwx7VrKHUczcnH8slD8ALASykhDSD/wiSom4VY6K/yku qkLPUThqEqUDCl1Fjbv+LkYMKlee3jUhhg== X-Received: by 2002:adf:eccd:0:b0:212:fbbc:79de with SMTP id s13-20020adfeccd000000b00212fbbc79demr35774935wro.520.1654765571489; Thu, 09 Jun 2022 02:06:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/55] target/arm: Move aa32_va_parameters to ptw.c Date: Thu, 9 Jun 2022 10:05:10 +0100 Message-Id: <20220609090537.1971756-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-22-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 3 --- target/arm/helper.c | 64 --------------------------------------------- target/arm/ptw.c | 64 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 67 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index a71161b01bd..9314fb4d23c 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -25,8 +25,5 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); } -ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, - ARMMMUIdx mmu_idx); - #endif /* !CONFIG_USER_ONLY */ #endif /* TARGET_ARM_PTW_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 2526f4c6c4a..f61f1da61e4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10771,70 +10771,6 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, } #ifndef CONFIG_USER_ONLY -ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, - ARMMMUIdx mmu_idx) -{ - uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; - uint32_t el = regime_el(env, mmu_idx); - int select, tsz; - bool epd, hpd; - - assert(mmu_idx != ARMMMUIdx_Stage2_S); - - if (mmu_idx == ARMMMUIdx_Stage2) { - /* VTCR */ - bool sext = extract32(tcr, 4, 1); - bool sign = extract32(tcr, 3, 1); - - /* - * If the sign-extend bit is not the same as t0sz[3], the result - * is unpredictable. Flag this as a guest error. - */ - if (sign != sext) { - qemu_log_mask(LOG_GUEST_ERROR, - "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); - } - tsz = sextract32(tcr, 0, 4) + 8; - select = 0; - hpd = false; - epd = false; - } else if (el == 2) { - /* HTCR */ - tsz = extract32(tcr, 0, 3); - select = 0; - hpd = extract64(tcr, 24, 1); - epd = false; - } else { - int t0sz = extract32(tcr, 0, 3); - int t1sz = extract32(tcr, 16, 3); - - if (t1sz == 0) { - select = va > (0xffffffffu >> t0sz); - } else { - /* Note that we will detect errors later. */ - select = va >= ~(0xffffffffu >> t1sz); - } - if (!select) { - tsz = t0sz; - epd = extract32(tcr, 7, 1); - hpd = extract64(tcr, 41, 1); - } else { - tsz = t1sz; - epd = extract32(tcr, 23, 1); - hpd = extract64(tcr, 42, 1); - } - /* For aarch32, hpd0 is not enabled without t2e as well. */ - hpd &= extract32(tcr, 6, 1); - } - - return (ARMVAParameters) { - .tsz = tsz, - .select = select, - .epd = epd, - .hpd = hpd, - }; -} - hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 525272e99af..427813ea563 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -615,6 +615,70 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, return prot_rw | PAGE_EXEC; } +static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, + ARMMMUIdx mmu_idx) +{ + uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; + uint32_t el = regime_el(env, mmu_idx); + int select, tsz; + bool epd, hpd; + + assert(mmu_idx != ARMMMUIdx_Stage2_S); + + if (mmu_idx == ARMMMUIdx_Stage2) { + /* VTCR */ + bool sext = extract32(tcr, 4, 1); + bool sign = extract32(tcr, 3, 1); + + /* + * If the sign-extend bit is not the same as t0sz[3], the result + * is unpredictable. Flag this as a guest error. + */ + if (sign != sext) { + qemu_log_mask(LOG_GUEST_ERROR, + "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); + } + tsz = sextract32(tcr, 0, 4) + 8; + select = 0; + hpd = false; + epd = false; + } else if (el == 2) { + /* HTCR */ + tsz = extract32(tcr, 0, 3); + select = 0; + hpd = extract64(tcr, 24, 1); + epd = false; + } else { + int t0sz = extract32(tcr, 0, 3); + int t1sz = extract32(tcr, 16, 3); + + if (t1sz == 0) { + select = va > (0xffffffffu >> t0sz); + } else { + /* Note that we will detect errors later. */ + select = va >= ~(0xffffffffu >> t1sz); + } + if (!select) { + tsz = t0sz; + epd = extract32(tcr, 7, 1); + hpd = extract64(tcr, 41, 1); + } else { + tsz = t1sz; + epd = extract32(tcr, 23, 1); + hpd = extract64(tcr, 42, 1); + } + /* For aarch32, hpd0 is not enabled without t2e as well. */ + hpd &= extract32(tcr, 6, 1); + } + + return (ARMVAParameters) { + .tsz = tsz, + .select = select, + .epd = epd, + .hpd = hpd, + }; +} + /* * check_s2_mmu_setup * @cpu: ARMCPU From patchwork Thu Jun 9 09:05:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580259 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp619815max; Thu, 9 Jun 2022 02:58:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwB8UeopYvcL3guzXuTjgQkMNSlNNCmA7zSFsDpqNfnKrcv0rgkY1WnmwSa6I+z73MHzBCM X-Received: by 2002:a05:6214:2a88:b0:464:463a:7a7c with SMTP id jr8-20020a0562142a8800b00464463a7a7cmr28213959qvb.127.1654768701461; Thu, 09 Jun 2022 02:58:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654768701; cv=none; d=google.com; s=arc-20160816; b=QHa1zy9+kourkMPZ4i6vz7TSoxA8l/AeUxPMj8E78fB/f4hJVCsEgL+vw3OcySAMl6 IpVPaW2rJtj/aLSWziDYERPgx6cwnnv2oOT3nMZk64K+fSYqceKmYYG7R2AwtjG/Cnsd D0EkSOwnQSFQ4sBuHDkM6RvHuBT2A56qQIJxJwQi5SePK9vPz40Rjhd9RnNdZC3AaJjc fTOGRs9E46wNJ1+juhHbqqWfO9kjMcr477Vuz6ongfapMWDhyaxrjfqOVwGBVwdHZasB NnjuQCzZspe5tkg71G2s3It9/VjDk8CUcekXy6vp57DkHL4tpuOAFGq3yrqdRrjQNtkR i3eA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rd6uuNfniFNZ5ZxqrHQJZxW1BzKlfPz7FzEjKvWSCtE=; b=eGcVqubhAXIkxo4caTis1GiGqpbmRx9nPBI9LRRMYqXXz8H2Nyxa6V+LNJ4+f/H2Po dQzfBNxOkoYYXGgCjnc4Uf64Z7OLjwNDFEEIWmoQtuKaWItQJRcucccbLJx43Aata0fp XW272Df9EoYNEvF8IbH8crhB5XmaoQeacH4Ll1JVExjgwxMVK21ulEUJqCSV4FaEon/9 t/+uD+P6ortbKS1mxOBKtaBqKP3ggjotZA32iSSISZwWDXIVKCsZ7BWmRobJKZYB7X+s Ohxx/vWigfKWi4kVnMGwxxKoGrlJPXNNXbtu6lJQw3Ie/E+IBIufhcIWt1Do6HQZboxW mRmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ll+e0oo1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id gs15-20020a056214226f00b0046427d2c730si12197122qvb.222.2022.06.09.02.58.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:58:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ll+e0oo1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42984 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEvk-0002Lq-Ri for patch@linaro.org; Thu, 09 Jun 2022 05:58:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39646) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7O-0001Yz-Ba for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:21 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:36483) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7J-00063j-W3 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:17 -0400 Received: by mail-wr1-x42c.google.com with SMTP id o8so3625877wro.3 for ; Thu, 09 Jun 2022 02:06:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rd6uuNfniFNZ5ZxqrHQJZxW1BzKlfPz7FzEjKvWSCtE=; b=Ll+e0oo1jaPvSjSMft05R2FgQe3K2SnfuIImWHyZwiGxoMJItgjYQBROhhOjGG2nqn AYV20Mecjp7DyZRGA+/isTvkovKsTKB2zGYEQMqiN6H67gesoqkMHpUDC+Pw/OkwkapN ZfXMWvvMbTBc0MQ4PQUT12AwQeE4Z1nyfrRbKX84CTq1saP8XfQk51qY7pqFCbwPI/ir Tj2YQHTzfMDzDZqAl2COkOBq+YfvQDjlQuYWaT8cQ2SFu1P1VIkCdTx38I0Fim5bTpvX KOgeyetWNZ+I74gpv53TzEBFr873f70mRJvnVfpajNdlR1k6jrz4U6+43ds11rudXd+9 Ji9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rd6uuNfniFNZ5ZxqrHQJZxW1BzKlfPz7FzEjKvWSCtE=; b=UjQR4uSY0ruf7oMwEV6UyvqmyqDtCkkXVh6lvDrHevG02iuzVQu1u05kRvR5DuBnOX AJaPJfCWQAUW/poTa1k+CRh2BRQ/lxdo33eGKioDcUVUvVS3QtzDlynDCvlCiLSxZlwR RdX17nrIgVmJE6hgTm080WtxC4F1A8iyWZEM2cBEULV6//IVMY2uGQzC3mPJZyBeyDsQ FYwrkPVywU4sd6nV9caTC8AtFLuh2wrV6lVcbYzuYWWwBet7vcrfFioFTCm9LM3xDlvz 9Qkq6qUrlJSQRKzHNp238xCMhNG3BkuwnTmUMA8d/lYPOnEJwVcQm4kXOwmXtDTC+TaZ Pywg== X-Gm-Message-State: AOAM531CEgXAnhSJl3ArALCPrP4jYh4Lelb3G2OQ4PXleX2YuJv3RScy JkG4XHUq3ssku2XXMlxEF8vvyvzAgZ7cNw== X-Received: by 2002:adf:f90f:0:b0:20e:5fd4:5d06 with SMTP id b15-20020adff90f000000b0020e5fd45d06mr37551453wrr.371.1654765572394; Thu, 09 Jun 2022 02:06:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/55] target/arm: Move ap_to_tw_prot etc to ptw.c Date: Thu, 9 Jun 2022 10:05:11 +0100 Message-Id: <20220609090537.1971756-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-23-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 10 ------ target/arm/helper.c | 77 ------------------------------------------ target/arm/ptw.c | 81 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 81 insertions(+), 87 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index 9314fb4d23c..85ad5767944 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -15,15 +15,5 @@ bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx); bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx); uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn); -int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, - int ap, int domain_prot); -int simple_ap_to_rw_prot_is_user(int ap, bool is_user); - -static inline int -simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) -{ - return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); -} - #endif /* !CONFIG_USER_ONLY */ #endif /* TARGET_ARM_PTW_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index f61f1da61e4..e894afcb491 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10537,83 +10537,6 @@ bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) g_assert_not_reached(); } } - -/* Translate section/page access permissions to page - * R/W protection flags - * - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * @ap: The 3-bit access permissions (AP[2:0]) - * @domain_prot: The 2-bit domain access permissions - */ -int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap, int domain_prot) -{ - bool is_user = regime_is_user(env, mmu_idx); - - if (domain_prot == 3) { - return PAGE_READ | PAGE_WRITE; - } - - switch (ap) { - case 0: - if (arm_feature(env, ARM_FEATURE_V7)) { - return 0; - } - switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { - case SCTLR_S: - return is_user ? 0 : PAGE_READ; - case SCTLR_R: - return PAGE_READ; - default: - return 0; - } - case 1: - return is_user ? 0 : PAGE_READ | PAGE_WRITE; - case 2: - if (is_user) { - return PAGE_READ; - } else { - return PAGE_READ | PAGE_WRITE; - } - case 3: - return PAGE_READ | PAGE_WRITE; - case 4: /* Reserved. */ - return 0; - case 5: - return is_user ? 0 : PAGE_READ; - case 6: - return PAGE_READ; - case 7: - if (!arm_feature(env, ARM_FEATURE_V6K)) { - return 0; - } - return PAGE_READ; - default: - g_assert_not_reached(); - } -} - -/* Translate section/page access permissions to page - * R/W protection flags. - * - * @ap: The 2-bit simple AP (AP[2:1]) - * @is_user: TRUE if accessing from PL0 - */ -int simple_ap_to_rw_prot_is_user(int ap, bool is_user) -{ - switch (ap) { - case 0: - return is_user ? 0 : PAGE_READ | PAGE_WRITE; - case 1: - return PAGE_READ | PAGE_WRITE; - case 2: - return is_user ? 0 : PAGE_READ; - case 3: - return PAGE_READ; - default: - g_assert_not_reached(); - } -} #endif /* !CONFIG_USER_ONLY */ int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 427813ea563..9ab77c39980 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -211,6 +211,87 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, return true; } +/* + * Translate section/page access permissions to page R/W protection flags + * @env: CPUARMState + * @mmu_idx: MMU index indicating required translation regime + * @ap: The 3-bit access permissions (AP[2:0]) + * @domain_prot: The 2-bit domain access permissions + */ +static int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, + int ap, int domain_prot) +{ + bool is_user = regime_is_user(env, mmu_idx); + + if (domain_prot == 3) { + return PAGE_READ | PAGE_WRITE; + } + + switch (ap) { + case 0: + if (arm_feature(env, ARM_FEATURE_V7)) { + return 0; + } + switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { + case SCTLR_S: + return is_user ? 0 : PAGE_READ; + case SCTLR_R: + return PAGE_READ; + default: + return 0; + } + case 1: + return is_user ? 0 : PAGE_READ | PAGE_WRITE; + case 2: + if (is_user) { + return PAGE_READ; + } else { + return PAGE_READ | PAGE_WRITE; + } + case 3: + return PAGE_READ | PAGE_WRITE; + case 4: /* Reserved. */ + return 0; + case 5: + return is_user ? 0 : PAGE_READ; + case 6: + return PAGE_READ; + case 7: + if (!arm_feature(env, ARM_FEATURE_V6K)) { + return 0; + } + return PAGE_READ; + default: + g_assert_not_reached(); + } +} + +/* + * Translate section/page access permissions to page R/W protection flags. + * @ap: The 2-bit simple AP (AP[2:1]) + * @is_user: TRUE if accessing from PL0 + */ +static int simple_ap_to_rw_prot_is_user(int ap, bool is_user) +{ + switch (ap) { + case 0: + return is_user ? 0 : PAGE_READ | PAGE_WRITE; + case 1: + return PAGE_READ | PAGE_WRITE; + case 2: + return is_user ? 0 : PAGE_READ; + case 3: + return PAGE_READ; + default: + g_assert_not_reached(); + } +} + +static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) +{ + return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); +} + static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, From patchwork Thu Jun 9 09:05:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580283 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp664047max; Thu, 9 Jun 2022 04:02:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzd+Kkh2BEfVRBv63jgqURL5j7JhcljFnyg0zDacK9JFzIxxKQ6CYQTU+As7V6uCgjDxPcW X-Received: by 2002:a05:622a:24c:b0:304:ed45:d89a with SMTP id c12-20020a05622a024c00b00304ed45d89amr16104128qtx.519.1654772544352; Thu, 09 Jun 2022 04:02:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654772544; cv=none; d=google.com; s=arc-20160816; b=fpGKOlIQG9p1n2f2N+jt1owH33gtsKtSNJ8BbjKiiTCgtI2xpoUa/Y+4XBlnPLY0kg KK9BJzvptwskYiGzitMcppMeeKInazIdiFs/dEJ7m3ds9uGxFIQz2Mv0QHsM84LxxQ7i 9z8qRnNaFWYQqjpytEwiRM17QEhbIJ6Z8fg3B0PTKgy2zzDiZntJvXbzVQN9kMR6bB8p tDU5FmQOkOdVXy1XoSkIPuHCrDEITpAsoIGw/AME5HlZTDQwDo/81fMUC1/cZSeHhmd8 zhMpaHutIl+qZ7sPIMGeKicb4TjY2+4ATTtJ4QiLm9hoqyJo2VLpVpTdpYgGbwYApKt6 a/Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OuhXk6TQyBrgWjcan+zAuS1lnzgYNbegbZMrB1RwcE0=; b=aJYV5JlQIUqXJ7hDhQMkopC+KEC5xsJOhWhcrvfzWjh73sOEfEbdFH8sBBcEt8mkKR ZA2V2hKvJu+WXIKg2gSwyQeA7kZCJljvP3G/A+6X5UhZVjRd/yAg4Nudspye6si3fagd 4JKTpIRVXyicTJ9TpBKbsYoCWSfDF01bki6OqkdkNUFs2sOvsJnW38LZhtBG2oFqF0nO 9VdVfAHSFeeWKQHmH5L9JPG5MPQqziosh8PvZE6g3AiOoBYxPRY5O7ObOn16tVRagWgy SKzWiykaN1ASxyaKuoqL2yFB2AwvT3bIHP4NNmnMEyviP5uxN2jp8tNH0X42yxjwA8k7 bSlw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w2vhU9JB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d15-20020a05622a15cf00b003050059df54si2367167qty.771.2022.06.09.04.02.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 04:02:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w2vhU9JB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54310 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFvj-0002jA-V8 for patch@linaro.org; Thu, 09 Jun 2022 07:02:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39650) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7O-0001Z1-DS for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:21 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:33706) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7K-000640-NK for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:18 -0400 Received: by mail-wr1-x42f.google.com with SMTP id h5so31518518wrb.0 for ; Thu, 09 Jun 2022 02:06:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OuhXk6TQyBrgWjcan+zAuS1lnzgYNbegbZMrB1RwcE0=; b=w2vhU9JBzTbWDw98pfYdxQSWlbErFUebQSWz9iiLuQ3NDfXmJ49hhN63seyjgdEjsx G84r55Pe5sUQ+b2TkRu9/m/vAtu0XfCr7EmORUKufRu31WNLLgvE8gpdNbqARb+lqSEw nit7AaiVRoF2HHqFSczbRSY/qjg4GxbraHgdiJKC7kS868dC/Fi4Xnm6SF4xF0vLBr67 XpIqYMFb738A7814FHw+AnGB5EdCnD2D4BHfDJ9NeRiaF7JgOq1iyBYQFzO0c6auk6aJ FX3TfsCy0nzJHlrRldqgu0uEYHBA/LZFuAE/kRpWhcCYrPKvJ+elU7Gg7m58TFF2fyB5 dnPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OuhXk6TQyBrgWjcan+zAuS1lnzgYNbegbZMrB1RwcE0=; b=bHypYM4ad4WPLQqr0pOYT5kPTFA9WKifYxAIBCBDcHy3IDWUpBX3KDltOcKwUU6L8F js31KwFfbGJ3X9O47+YOUdSE4DmBQImCiF/opjHpXikOHW2JmrANJiqdcNNyauz5fNqi XKU6jGFSNdUgW0XSfwRFP8lzpsdZ+zCcsppPTR3dIJsauXOKTFuTlYlwFhjeWLnkGWFc 7S+0Lb9nNTCPXfpNC3vEIzuXu6hcSAwPf3D7EHJrRBdtnfM1dLrghNnSdNXJer6xWccO WpXi+9egpfUfjGks6jRy2aIutzxwSrw0StQpsISWLFaX5HXNcjVR9R4qxsjqZp5P+Qeb klKg== X-Gm-Message-State: AOAM533wkTds1aMaKZOof50rduSXHl7j6xNHB8ohkuuQlsRA83p+GlXJ WMrb9+4RcK4BML1RJWTXjbmwLDp012QEJA== X-Received: by 2002:a05:6000:1888:b0:218:3fab:c510 with SMTP id a8-20020a056000188800b002183fabc510mr19870503wri.473.1654765573417; Thu, 09 Jun 2022 02:06:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/55] target/arm: Move regime_is_user to ptw.c Date: Thu, 9 Jun 2022 10:05:12 +0100 Message-Id: <20220609090537.1971756-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-24-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 1 - target/arm/helper.c | 24 ------------------------ target/arm/ptw.c | 22 ++++++++++++++++++++++ 3 files changed, 22 insertions(+), 25 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index 85ad5767944..3d3061a4351 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -11,7 +11,6 @@ #ifndef CONFIG_USER_ONLY -bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx); bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx); uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn); diff --git a/target/arm/helper.c b/target/arm/helper.c index e894afcb491..8deb0fa94c1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10515,30 +10515,6 @@ ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) } #endif /* !CONFIG_USER_ONLY */ -#ifndef CONFIG_USER_ONLY -bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_E20_0: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_MUser: - case ARMMMUIdx_MSUser: - case ARMMMUIdx_MUserNegPri: - case ARMMMUIdx_MSUserNegPri: - return true; - default: - return false; - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - g_assert_not_reached(); - } -} -#endif /* !CONFIG_USER_ONLY */ - int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) { if (regime_has_2_ranges(mmu_idx)) { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9ab77c39980..8db4b5edf1a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -53,6 +53,28 @@ static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx) return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; } +static bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_SE10_0: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_SE0: + case ARMMMUIdx_MUser: + case ARMMMUIdx_MSUser: + case ARMMMUIdx_MUserNegPri: + case ARMMMUIdx_MSUserNegPri: + return true; + default: + return false; + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + g_assert_not_reached(); + } +} + static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs) { /* From patchwork Thu Jun 9 09:05:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580279 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp653589max; Thu, 9 Jun 2022 03:47:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwScgvpGS1wqCgb72CCSifMyOhU4UNADLUL4Mo5a9VYV8oChVAISUJ4rCYeQknYm6sJ3I8x X-Received: by 2002:a05:622a:2c3:b0:304:f1ac:cffe with SMTP id a3-20020a05622a02c300b00304f1accffemr14138059qtx.163.1654771654555; Thu, 09 Jun 2022 03:47:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654771654; cv=none; d=google.com; s=arc-20160816; b=HltbYjd4NHZCyxd+2q6D40MS7alPbMLATeCGogEXCJTANceAecOA+YIXn4obc0yJPX grrcDy4FLQ/VwZnt771V7No/zfgyAlRFOnY87jSats9ctgLzxEjl76N0/ms7OY/BHKBe tLe5lvsT73PqHG5haxm7cul8djCErlCNousWMhntxrvd/X4+vnBWSCxdw/zZdWPd+wVG HuuAXzh0CLK6aO8mdUxKbXcaR8l+IimZGJg4DHF0A9g+6zCPr2o3FBP/gg22qN8hhC40 fn+R+I01vOAPn2T9AaRNmeNzm6pq4cz9rUgPhnb7HKlYPQYWd78nRvWPabLAi5NjnqVh 7rpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vssipGCOqEJQNoMsGfFwc+dxYekNW1L8kP+aFic/gt8=; b=WdJinZY14XYwEg4ukTaf2Cbyqtprign8EXQCmHosZX5cdrvgIjJ2b+lsUMF5kAaSB6 8vWqWg8eYVnd8cvbBjtz1qCk3JHA/PFrJNSuyjKEJ9n9ZtxdeABvxvJw7OZqLI8IhYfJ MpKkDBXQ1dykc7mWcpgvghT3y4o2hrqcnvosq6v0omTdE1S5Q5zY1Sd7Jz/ceBDTVQM3 Vkw3Mp8PV26WDeaOvzioaIyd6eRY2r5KhSt1HOCzmsUd11TxWiYTxcO7LK4Ylg69GMkh BvmXEAQerYnom+u9uFTicu9j6HSFy2BvBdo9FivPDx/2p+3RJKDMjDxGICzcRsuJff4G kAig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NCooA6v8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k21-20020a05620a415500b006a042cb4ce7si8578013qko.8.2022.06.09.03.47.34 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:47:34 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NCooA6v8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36728 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFhO-000656-2c for patch@linaro.org; Thu, 09 Jun 2022 06:47:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39652) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7O-0001Z2-Gg for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:21 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:46807) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7L-0005v7-GR for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:18 -0400 Received: by mail-wr1-x429.google.com with SMTP id u8so27137454wrm.13 for ; Thu, 09 Jun 2022 02:06:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vssipGCOqEJQNoMsGfFwc+dxYekNW1L8kP+aFic/gt8=; b=NCooA6v8ACoFTIlVaviEsHeZ6x5CwA1abm6IcfTfPLbyUY/rehr6+Mky2geKX2bbTL Sw3hrEvPORH4NQLaBFL1iDIFNZFuBonXypsLlu4mx0EFTfQ7tTQsoC7pIhKf10dHUnCa B1cKJYA9+BFPewG6hJc6/y6qIMS7yk7b8i3ZPKKuDDJQm2y/fs+ZvoGkyQp21d8BtFFU swyH8niWKdIw9pw5KtmQWB4ID3RCfNXijL8qA7QCO5X77GAijPjw8MFHVrglHkVgrstn R1dXFAOcPNuR/BWlTg1KqtuNsBE4llG0rxWaVMh4aTK+SQCWE0t3wfD+F7sInfQdmzrv xVsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vssipGCOqEJQNoMsGfFwc+dxYekNW1L8kP+aFic/gt8=; b=1OCg6LVlVBHiH/0Vi7uM77hg8C/gReU0thHvtfxVYG78pK0QNEGvbqEabDPJXatiUP Jr3dbtUdRLPq5kJV4B8WWC8rBICBW0zpQnD6D9SJOLz4A/oHYM6VoLOlt2KZC+LtjYFR SjYmmZ61Rp21b6EivS9acq34AnZcyJZyUHiMVlQPHeKYE37QJ7EPrl6t9F9fKKv4l0sO RL+ogFRqWFNLV2SJA/n9L7O44LjGeD2UEhkCCJNZCZv69f1CDADb0sNWYyPK9/A0zHDW 5mcxpvMcGR40XM32BZ2zbr0WvqWT23lbUrn1wbPSq/itGa/cHGi1pRQIOza2PT3E3wFb sgcw== X-Gm-Message-State: AOAM533Mzd75FwrMpbU1s58Q5k/Gg8/oPOCQqf7lwWfxG8BclTTKkZpR RA7mg1d4ouTFTyJYHnQSwZDsMp2vBJkJMw== X-Received: by 2002:a5d:58ed:0:b0:217:dd5:7508 with SMTP id f13-20020a5d58ed000000b002170dd57508mr24330176wrd.606.1654765574388; Thu, 09 Jun 2022 02:06:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/55] target/arm: Move regime_ttbr to ptw.c Date: Thu, 9 Jun 2022 10:05:13 +0100 Message-Id: <20220609090537.1971756-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-25-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 1 - target/arm/helper.c | 16 ---------------- target/arm/ptw.c | 16 ++++++++++++++++ 3 files changed, 16 insertions(+), 17 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index 3d3061a4351..ed152ddaf4e 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -12,7 +12,6 @@ #ifndef CONFIG_USER_ONLY bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx); -uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn); #endif /* !CONFIG_USER_ONLY */ #endif /* TARGET_ARM_PTW_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 8deb0fa94c1..fdda87e87e2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10475,22 +10475,6 @@ bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; } -/* Return the TTBR associated with this translation regime */ -uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) -{ - if (mmu_idx == ARMMMUIdx_Stage2) { - return env->cp15.vttbr_el2; - } - if (mmu_idx == ARMMMUIdx_Stage2_S) { - return env->cp15.vsttbr_el2; - } - if (ttbrn == 0) { - return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; - } else { - return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; - } -} - /* Convert a possible stage1+2 MMU index into the appropriate * stage 1 MMU index */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8db4b5edf1a..dc559e6bdfd 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -75,6 +75,22 @@ static bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) } } +/* Return the TTBR associated with this translation regime */ +static uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) +{ + if (mmu_idx == ARMMMUIdx_Stage2) { + return env->cp15.vttbr_el2; + } + if (mmu_idx == ARMMMUIdx_Stage2_S) { + return env->cp15.vsttbr_el2; + } + if (ttbrn == 0) { + return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; + } else { + return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; + } +} + static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs) { /* From patchwork Thu Jun 9 09:05:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580281 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp659976max; Thu, 9 Jun 2022 03:56:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwz9+DAKR+iS83+I9YXzU1F13T/vKS7WXSEDT9tL/nOLumIRMjn/O3U/TTlMPXai0P6kbWj X-Received: by 2002:a37:a043:0:b0:6a6:a7c9:7e with SMTP id j64-20020a37a043000000b006a6a7c9007emr19765046qke.339.1654772216309; Thu, 09 Jun 2022 03:56:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654772216; cv=none; d=google.com; s=arc-20160816; b=B6wRbC23bH1PwDeMtrXTUo0PSIWg6K8ntB7s2/vzWiGJo1PlqRBZ6DJ0an2pTTcBCR qHrwC4G1Ss0NaC1ewhqItzR7S1IMS9qHApwRigM2d8g9bRVlZ5Q+UMjghPfrxxcb40Yt bmlaU25ALpn+NKsAfj3cf5TGj9uiquR8sUcxo1q2YdUpgpYGnZl02RQBrVrzxtKoOFgH jqEgABz+oN8f0ecQCm4I3NlPQZFAJQGWFONhSyKjr0ZkQ7t9hK+JvMUZPK5Ly1GZIV9u FJec6yqEM0UsdEBnmCnZlik6w6vivk4NfVPXTY8RxkwPCaCqexVSxn1Ji1wuCnrUtFg7 MBfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NqYWQ8l2y3CQlswUgWQkihqe1Lkdxi0y72T5OHE/ZAg=; b=zWPdGz2O2Y+y0FtbcFYt/tV+gU9fUY7JaS4iDc8b1YIfK7Z1QedMDS+7uu0UFA/Zrq mWeahbNQvRiyvpoFl4aaVfoRRIUJleW9OH7Obhgrws1mE6oNWSYC0qsepYvkfBJEn2iM sPblPt3XU/Es/GLWC0nTQtfUrwiI9jPR8qhL0GxcMmPwdiM/zBSLkWd4ueSVUIGprUAk 9vQvZ0FOnesqSd+omEg0lBh7Z04M6/jkgniGeAedriVZnZbqO2PbgAewBc8lcEjQ3+jm jfuDRHIiDVKdMfmJRIBae9K4ML7qTY9mVU+5wEXbC9uHN5mvX0ehPphZ0c6k0yL/kOwA BwyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lXZ8SzMQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d15-20020a05622a100f00b00304fdcd5674si3757130qte.548.2022.06.09.03.56.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:56:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lXZ8SzMQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45710 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFqR-000589-Pd for patch@linaro.org; Thu, 09 Jun 2022 06:56:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39666) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7O-0001Z3-Ud for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:21 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:44816) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7M-00060e-Ft for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:18 -0400 Received: by mail-wr1-x433.google.com with SMTP id q15so23422931wrc.11 for ; Thu, 09 Jun 2022 02:06:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NqYWQ8l2y3CQlswUgWQkihqe1Lkdxi0y72T5OHE/ZAg=; b=lXZ8SzMQuaSIkxttaPcqja1ngEg2kC4C4jnTj25wsXSNAyadt/KJSoB8uTk+71trNh lyMsKokwPfTfS3ET35LbQQIYysiZ+P8um5eZq1cx+ZIJpWtEmo59afB3p81u/ZI9CrtL EThDxu/nzSljgic5GS0+q3D1WeqkdmTvxD/QT8D5VVPI7hAhd8WRBbvGeUgxZsZHAwwf vEZLLUDedkJl1OQAcWMhNJtkthYFoJX7x0qYiJT5KZYhDDgNf3eO8G9YocbQmmCrZSfy H6qp/FFLFnrFmnPxlGvhLSTf9ZbEaBORMz61X1ia5QXZ3abZbnTfp6B19aMrTE8Q0jKi vQAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NqYWQ8l2y3CQlswUgWQkihqe1Lkdxi0y72T5OHE/ZAg=; b=7XWrZwiwGrVCrNXXpQXXVXdqm8/aLvGRKRmqCySWEYpVzX6fCm+axU9eEPCf33y1N7 A3vkTeBEpnYTcgShi4LY1tTEHHBC84LDdsmn7oVKng1Z899ddVB/rSw5dedgefIRi6P3 Flr++gWdweOI4za6mKUBwU4E9ELPQQkLhERBH9DtX7zIo2gkKTLcFJapLkMApwjtG1P2 cAChrgFH0Cn0Sv4kDr2aD4jFj5SzhbeIno74itlxPJiHP71zW1iJJSVbSxzA50pa+8jo Ho3wTWAnDORmgkxuI9+JtsEY9lmV2tBlGCXolm3SicPNkeP2M0srGWlz8+5q+8sIejBY qBZA== X-Gm-Message-State: AOAM532HghF4oujbjge+9nMBjg7hSZuQ0WIJ0WaB4vxQHhpInMk8xCFl BO7C74kShzV36IR9JrrXMBsyjtx3PyuDyA== X-Received: by 2002:a5d:5383:0:b0:211:8d24:8285 with SMTP id d3-20020a5d5383000000b002118d248285mr37600105wrv.681.1654765575792; Thu, 09 Jun 2022 02:06:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/55] target/arm: Move regime_translation_disabled to ptw.c Date: Thu, 9 Jun 2022 10:05:14 +0100 Message-Id: <20220609090537.1971756-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-26-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 17 ---------------- target/arm/helper.c | 47 --------------------------------------------- target/arm/ptw.c | 47 ++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 46 insertions(+), 65 deletions(-) delete mode 100644 target/arm/ptw.h diff --git a/target/arm/ptw.h b/target/arm/ptw.h deleted file mode 100644 index ed152ddaf4e..00000000000 --- a/target/arm/ptw.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * ARM page table walking. - * - * This code is licensed under the GNU GPL v2 or later. - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#ifndef TARGET_ARM_PTW_H -#define TARGET_ARM_PTW_H - -#ifndef CONFIG_USER_ONLY - -bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx); - -#endif /* !CONFIG_USER_ONLY */ -#endif /* TARGET_ARM_PTW_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index fdda87e87e2..69b1c060c1f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -36,7 +36,6 @@ #include "semihosting/common-semi.h" #endif #include "cpregs.h" -#include "ptw.h" #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ @@ -10429,52 +10428,6 @@ uint64_t arm_sctlr(CPUARMState *env, int el) } #ifndef CONFIG_USER_ONLY - -/* Return true if the specified stage of address translation is disabled */ -bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - uint64_t hcr_el2; - - if (arm_feature(env, ARM_FEATURE_M)) { - switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & - (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { - case R_V7M_MPU_CTRL_ENABLE_MASK: - /* Enabled, but not for HardFault and NMI */ - return mmu_idx & ARM_MMU_IDX_M_NEGPRI; - case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: - /* Enabled for all cases */ - return false; - case 0: - default: - /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but - * we warned about that in armv7m_nvic.c when the guest set it. - */ - return true; - } - } - - hcr_el2 = arm_hcr_el2_eff(env); - - if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { - /* HCR.DC means HCR.VM behaves as 1 */ - return (hcr_el2 & (HCR_DC | HCR_VM)) == 0; - } - - if (hcr_el2 & HCR_TGE) { - /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) { - return true; - } - } - - if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { - /* HCR.DC means SCTLR_EL1.M behaves as 0 */ - return true; - } - - return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; -} - /* Convert a possible stage1+2 MMU index into the appropriate * stage 1 MMU index */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index dc559e6bdfd..ec60afd9bff 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -12,7 +12,6 @@ #include "cpu.h" #include "internals.h" #include "idau.h" -#include "ptw.h" static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, @@ -91,6 +90,52 @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) } } +/* Return true if the specified stage of address translation is disabled */ +static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + uint64_t hcr_el2; + + if (arm_feature(env, ARM_FEATURE_M)) { + switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & + (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { + case R_V7M_MPU_CTRL_ENABLE_MASK: + /* Enabled, but not for HardFault and NMI */ + return mmu_idx & ARM_MMU_IDX_M_NEGPRI; + case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: + /* Enabled for all cases */ + return false; + case 0: + default: + /* + * HFNMIENA set and ENABLE clear is UNPREDICTABLE, but + * we warned about that in armv7m_nvic.c when the guest set it. + */ + return true; + } + } + + hcr_el2 = arm_hcr_el2_eff(env); + + if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { + /* HCR.DC means HCR.VM behaves as 1 */ + return (hcr_el2 & (HCR_DC | HCR_VM)) == 0; + } + + if (hcr_el2 & HCR_TGE) { + /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ + if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) { + return true; + } + } + + if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { + /* HCR.DC means SCTLR_EL1.M behaves as 0 */ + return true; + } + + return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; +} + static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs) { /* From patchwork Thu Jun 9 09:05:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580263 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp626255max; Thu, 9 Jun 2022 03:06:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwHU4wGUs+tffwP96PaS07xFHzMKZoXSjKNzoQU7A1FaOcEGa49WU8s/Ioc56b52K9PGlFj X-Received: by 2002:ac8:5b87:0:b0:2f3:cef0:cd7d with SMTP id a7-20020ac85b87000000b002f3cef0cd7dmr30846463qta.428.1654769192177; Thu, 09 Jun 2022 03:06:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654769192; cv=none; d=google.com; s=arc-20160816; b=noP9e3UvqwWszNSQPpeQ7hPA8FLhjJlTa6H1xGIZ4rRH3W7I3pHKyztKiQcJ7BVRns IZJyF01ks35hmZQbzG4nrnu6o8w1jx9VlDCVcQKv6X1pCUpEIwOzWib9r3R+sAsN/qxN FeF07Nn6g2XKGtiLuQxP2sQ0b/x6ghanufHEGYyzyeWdXTKZI0fLFOD6E+r63c30LpSR EGITeC+jUq/0MHkZgBmSr6ZIaL06OdletW6PHj4wpCyPMNH+KWX46mnGagU1yCglWzqp v08nAap8LqvPSRFnb/vp/pTnLKSufxHAw9EDjteaxOYOeMsMMhm8QmmtLH9pFQv8i24h GS0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JfidimcrBCl7Udx4o3Zs0c4uqkOTceip308AFLIscT0=; b=UzDJR0YczEIt000QRIHaSAOxT+4zaG9zVuVJgyzXBg1XzvTkiDxLJprf1cq697QdEB Q3qpWAVw319+xDmB+ObLlYgFMxGcWEA1nixUyr/pN7D/8yTFRV3fBnAdUE2PQq9aXR0Q KcKeuvwQuA4/X7Bik3klm4MrWskViwvGgfn6JWyLZfQi1gnNOCWzP+YPJ71TO7uFadSC 1a3PXz846hg/kqe8DZ5NhxundMLyCkAYGpuSKD7pNQYewuew4X6dSOSnZ5fyQGEppO/R O7zpozg+V8aBMx+dLD8Gtw135RwsOj65MTeYrmmsZaABaVaSJ3rjhooPRNPJo7xeJwJK 4ZhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iORuARJV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a8-20020a05622a02c800b0030511c0bfdesi248303qtx.343.2022.06.09.03.06.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:06:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iORuARJV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51968 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzF3f-0000XZ-Mu for patch@linaro.org; Thu, 09 Jun 2022 06:06:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7Q-0001ZD-Fe for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:22 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:46819) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7O-0005xd-3T for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:19 -0400 Received: by mail-wr1-x435.google.com with SMTP id u8so27137707wrm.13 for ; Thu, 09 Jun 2022 02:06:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JfidimcrBCl7Udx4o3Zs0c4uqkOTceip308AFLIscT0=; b=iORuARJVwwG7cRteZ+Qo+xAm0B1S0qTOkFSIP6hNa+Q/+4XQD1BqHnlgTY6I1Hqn5V NvFBRrtYowDAoCPbjMFu83+vb/URbr42RhRLADK7OuFcMEGrpraphyUonXtKkuW/vOO+ TueQaJJ/ZUtzCgHeNFofW0s7bacFbhfJjulrVRMM2yr34E9dVkvAhISr5CKe7pWPkyiJ spyIgYgh0TSGs+6MWLcSqXQk8KyRNCFUqnoUupUfsmTWG/qajhCGMdCJt+YBGZLb4ORe YUE1sJcLIvC8oL/ou/RfwpmACDszrX3g+sAuq2Tkm972tYWebBCGv52k7r1dDTj716bL 4fGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JfidimcrBCl7Udx4o3Zs0c4uqkOTceip308AFLIscT0=; b=bIf14kmcdpLXwpbqRMnjLMNOFymLt18QJ86AtxqUtmefys/u4L6nM4sV+RbIbDxgwH IK4mycYjBwht8Bjr0d9pS8EZ5UjK8zivDXvrFfSyP+Y0meCxVwiJ/dDgijomWQ95Dif4 K/88Kdnb+RZQ9E1zJMV6oPKh5JsqFxKSMSNmzOnPf/9P7WQmY+jFV833f+yZ7uBqRLRe ED2yS/Nuhv5e9grX8Hguu0WAEZdLvd14p+bIrIbVD4eogSbfNhy0yKP3qSTt92sReYEp ZDnGhIDjoSMIleECNP53ptLIyOKBahmwhAiRTu/zARrKAIi+YTU/G7r5eP0geSe1x5Nz CenQ== X-Gm-Message-State: AOAM533kTccI2d9uUzlmfjy5EHB6RJMmAxPaT+HIE5LJTLPnJo2cgWk7 jvwMvZUl2kAvG2elO+5DYhIPUbkNVurKaA== X-Received: by 2002:a5d:6dd1:0:b0:210:7a1:cda0 with SMTP id d17-20020a5d6dd1000000b0021007a1cda0mr37329039wrz.570.1654765576678; Thu, 09 Jun 2022 02:06:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/55] target/arm: Move arm_cpu_get_phys_page_attrs_debug to ptw.c Date: Thu, 9 Jun 2022 10:05:15 +0100 Message-Id: <20220609090537.1971756-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-27-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 26 -------------------------- target/arm/ptw.c | 24 ++++++++++++++++++++++++ 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 69b1c060c1f..fe1e426f883 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10606,32 +10606,6 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, }; } -#ifndef CONFIG_USER_ONLY -hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, - MemTxAttrs *attrs) -{ - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - hwaddr phys_addr; - target_ulong page_size; - int prot; - bool ret; - ARMMMUFaultInfo fi = {}; - ARMMMUIdx mmu_idx = arm_mmu_idx(env); - ARMCacheAttrs cacheattrs = {}; - - *attrs = (MemTxAttrs) {}; - - ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr, - attrs, &prot, &page_size, &fi, &cacheattrs); - - if (ret) { - return -1; - } - return phys_addr; -} -#endif - /* Note that signed overflow is undefined in C. The following routines are careful to use unsigned types where modulo arithmetic is required. Failure to do so _will_ break on newer gcc. */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ec60afd9bff..e9f6870d0a6 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2491,3 +2491,27 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, phys_ptr, prot, page_size, fi); } } + +hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, + MemTxAttrs *attrs) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + hwaddr phys_addr; + target_ulong page_size; + int prot; + bool ret; + ARMMMUFaultInfo fi = {}; + ARMMMUIdx mmu_idx = arm_mmu_idx(env); + ARMCacheAttrs cacheattrs = {}; + + *attrs = (MemTxAttrs) {}; + + ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr, + attrs, &prot, &page_size, &fi, &cacheattrs); + + if (ret) { + return -1; + } + return phys_addr; +} From patchwork Thu Jun 9 09:05:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580287 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp679990max; Thu, 9 Jun 2022 04:22:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzBy21k78/ucHCtZBDgV2vemjHgBnc3lU3xCjxVeUNjSkb9e8n4FmU91buh/XaAi09/N5gi X-Received: by 2002:a05:622a:110f:b0:2f3:c9f1:ada4 with SMTP id e15-20020a05622a110f00b002f3c9f1ada4mr31086293qty.197.1654773720248; Thu, 09 Jun 2022 04:22:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654773720; cv=none; d=google.com; s=arc-20160816; b=affBus/tDPBePZ7/mhL8wijpKywcDNnJYO45fNKoqA+vrDYw7gfX6uuxWvjKRxPDw8 Vecg7tUjDBL8sJOWGJJu1ftFwnjCLE2KapFU8mSALFo3qKQz0ah9E3zhmqL8Vt8sa/8w UJnH1r5+8WdLUe3YhDBXcR2WU5d5qYZJdaeEwe0UFTxlb9U5ow/c6Tu2KdBa80/Vise5 2+fQESs9HDrIosYXvQFF6ilxV6KR38h3re9Xm5jSKNdXJU9lBoTumkXEqs2Ppo/9RySF OluhEdEwkp3XiQA/pWhwe878c69iod96H18NRQLiGxd9k1+OrF8buYrBe85ufEtl0I3O m1AA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Hig8Fai2F1wZbBshuF8R/7YaHSV9c3nGNPXI/ypkLI4=; b=NXiUH/l8JbSa4h4zcHLAwkptYIQ2QCfWVRJjgZI/yn7PzczwBz0c3GvR9hG03EPWwJ s5tNLx/oCmLw2VKaU/O400+/TyTSgD0IUORrcQuyf2KctyX8nIc3zGS+oxCvlTyztxh7 29uLHjAzQIY9oPgSY1tDrveSFoWbD/BdRn6eO9uOIAA21Jr8FG7dkBozazVFpYqBmWHQ 2DPGKtkkiD0wOAnFxgnMR4B/We7wGA73wjOw7whlmjHjKBN+hTFrZQ2PSKwE/78KqVPO Q/fWzSdDTB9bz5vSUA1LeGy/GVKJfH13ir+bt+EFrjJXLFvbrLyFhIbsqZVBjB3iFP9y brrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="m/4E20ul"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 11-20020ac8594b000000b002f530e47760si12640732qtz.53.2022.06.09.04.22.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 04:22:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="m/4E20ul"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42960 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzGEh-0007t8-Q8 for patch@linaro.org; Thu, 09 Jun 2022 07:21:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39726) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7R-0001ZF-2K for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:22 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:44820) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7P-00064p-0N for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:20 -0400 Received: by mail-wr1-x432.google.com with SMTP id q15so23424549wrc.11 for ; Thu, 09 Jun 2022 02:06:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Hig8Fai2F1wZbBshuF8R/7YaHSV9c3nGNPXI/ypkLI4=; b=m/4E20ulIBpiVB/IMa2AT0nnlThFQOBHtqCJzjlmJp3oFcJcu+Xpy0FTdeWW4zK9ch MNfuszWLqvuUhK5IseecTJff0wmPFASjE1IRsO2ZrCgBs3E0xzXE6gmjrbATr6Mb1dwZ QYRC3a/r2it+xiQq3um2PL0locyGFSGhxdFfJc/kCiPfxMZALgRo94qDtrRQLntdEi1l CzjGR3jUaO58muauouuXb5mZFNpZH+pl+JGL+2papdYTW5nVR17jJMVvsnE21laW2VpE 2cNW27sSBMP3HMIukzTCCpFRto5WRcn7wVu163HBjAknMWwkjyH9CQsaCSWu40vwAHKx eOlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hig8Fai2F1wZbBshuF8R/7YaHSV9c3nGNPXI/ypkLI4=; b=RUCVNJbDhcMlnMtQvR4ky3yU/4VJ+k52H9hd0SHHGTn3iH87KEoVRwJelRlx1UWafh cKvWDeEmf1P8Ki8+HEonLyO8+VpfXebooxAXg5hfC1Lky5ETHguAgyutxvhrUDFGcjBS banWHdoTftO8zyGgAYBxGDbEFWviASovHJgYgyPGdy3N0df2mh3S3DLP/sFUfWQrG8fx j1OMSP7t7zeULpgz1a6OrwgrGcxrr3ZMdWCpjotlkbxv96TQCXxwDM3ZuN8G5HVyaW0C Rys4kQXMYYWP9W8WOedqehO1mC+GJvC2mcQX+rhwNUzvlPYFaidRMYZKnaHUGBxk0FOV /xBQ== X-Gm-Message-State: AOAM532/T5dd5E2AxQ4FdFGtWdUNTmWElHMe4YCGqqJDs59Bd2zTCqr+ 0qSxk6NAXvvvt1dLPQI2+SzWxPp+UvRR6Q== X-Received: by 2002:a5d:4290:0:b0:213:badd:abc5 with SMTP id k16-20020a5d4290000000b00213baddabc5mr32116536wrq.54.1654765577735; Thu, 09 Jun 2022 02:06:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/55] target/arm: Move stage_1_mmu_idx, arm_stage1_mmu_idx to ptw.c Date: Thu, 9 Jun 2022 10:05:16 +0100 Message-Id: <20220609090537.1971756-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-28-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 32 -------------------------------- target/arm/ptw.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 32 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index fe1e426f883..37cf9fa6aba 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10427,31 +10427,6 @@ uint64_t arm_sctlr(CPUARMState *env, int el) return env->cp15.sctlr_el[el]; } -#ifndef CONFIG_USER_ONLY -/* Convert a possible stage1+2 MMU index into the appropriate - * stage 1 MMU index - */ -ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_SE10_0: - return ARMMMUIdx_Stage1_SE0; - case ARMMMUIdx_SE10_1: - return ARMMMUIdx_Stage1_SE1; - case ARMMMUIdx_SE10_1_PAN: - return ARMMMUIdx_Stage1_SE1_PAN; - case ARMMMUIdx_E10_0: - return ARMMMUIdx_Stage1_E0; - case ARMMMUIdx_E10_1: - return ARMMMUIdx_Stage1_E1; - case ARMMMUIdx_E10_1_PAN: - return ARMMMUIdx_Stage1_E1_PAN; - default: - return mmu_idx; - } -} -#endif /* !CONFIG_USER_ONLY */ - int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) { if (regime_has_2_ranges(mmu_idx)) { @@ -11081,13 +11056,6 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) return arm_mmu_idx_el(env, arm_current_el(env)); } -#ifndef CONFIG_USER_ONLY -ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) -{ - return stage_1_mmu_idx(arm_mmu_idx(env)); -} -#endif - static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, CPUARMTBFlags flags) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e9f6870d0a6..49e9a1d108e 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -47,6 +47,34 @@ unsigned int arm_pamax(ARMCPU *cpu) return pamax_map[parange]; } +/* + * Convert a possible stage1+2 MMU index into the appropriate stage 1 MMU index + */ +ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_SE10_0: + return ARMMMUIdx_Stage1_SE0; + case ARMMMUIdx_SE10_1: + return ARMMMUIdx_Stage1_SE1; + case ARMMMUIdx_SE10_1_PAN: + return ARMMMUIdx_Stage1_SE1_PAN; + case ARMMMUIdx_E10_0: + return ARMMMUIdx_Stage1_E0; + case ARMMMUIdx_E10_1: + return ARMMMUIdx_Stage1_E1; + case ARMMMUIdx_E10_1_PAN: + return ARMMMUIdx_Stage1_E1_PAN; + default: + return mmu_idx; + } +} + +ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) +{ + return stage_1_mmu_idx(arm_mmu_idx(env)); +} + static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx) { return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; From patchwork Thu Jun 9 09:05:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580268 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp636079max; Thu, 9 Jun 2022 03:19:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxx5wWsWKdgCg4YrqifZs8BQ6+qnGObfTX/tucVs6jntJFICpzl8NBsKWlYB9yOa7EEMwn6 X-Received: by 2002:a05:620a:410b:b0:6a5:7289:a7a9 with SMTP id j11-20020a05620a410b00b006a57289a7a9mr26149699qko.119.1654769994743; Thu, 09 Jun 2022 03:19:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654769994; cv=none; d=google.com; s=arc-20160816; b=Wf/vWDm9Vj8+scj1jJpK5BqFriRNGPKPufmURYl8nS65KZ0nor3fOkzXv8mg/xA43F 3axd0YDUVE2WIckGLRXeUO7PznwXiFjfSFSuijX5TiLipEXVK1F/rp30I8qmpgOW7Te+ yLrq+e3qbydrSUMn32zKo5CC7tlp1krIh1BMwYjotdYaSkk6rZcopnyeBX90vDTkTOSi SQe7TmWJArKZW3AhRaY57ik4XpN0dXrh+rlaIs6xZD3rdV6FKSUPLieJgdNDJDW+SKh4 4+vpnAsIRDFfaWDtj03eUfv1LdCrr30x48p4cNl4sx8m/bf62IIGLMQRVfSVqzk8y+bV 52pQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vtklS/jBlWBBb7I5PQy1NemEL8fX7OtzLyw/Jsz+ozc=; b=Snm5zCmNqyw1ILQhleg9+87LL209afjelNS8mhS42fMwk25R1ksuRxeEvrSNPqiY3P M82C/qpvbshNZVjHYPSE+eIbR6zKxw8/LUZvyflSXcbFV0zuqLlM1mSrNU5pEnZxiTzD NZcD5dFmEDc3ubprwO49ZSpVc+qodtx/75wLBHnbLrg2jY3G6hCLrX5zdRzrFePYeV6A /b1O9+WLUj+QxeVB3WX8CIRhwAF7e8VMdbyYdbSbq/1DDovbgRTmsvQtKjnHL+6NvNDH 99OeYe84nKqCf62ntmeBcLO+Dov7pVyFKt0IAbvSODFljich+sXSDBDMilybG7mw9C3a wpkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zOs2w1fq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i4-20020a05620a248400b006a3749ae2d6si1236343qkn.215.2022.06.09.03.19.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:19:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zOs2w1fq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37474 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFGc-0002YH-80 for patch@linaro.org; Thu, 09 Jun 2022 06:19:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39736) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7R-0001ZG-BK for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:22 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:36485) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7P-00062j-Aa for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:21 -0400 Received: by mail-wr1-x431.google.com with SMTP id o8so3625311wro.3 for ; Thu, 09 Jun 2022 02:06:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vtklS/jBlWBBb7I5PQy1NemEL8fX7OtzLyw/Jsz+ozc=; b=zOs2w1fq0As+FV5dDTJAxBjv5Jv8AqWDwM0JCrfvo4voWsKiQE9oT281dhoO4Ysevn Gxp3sQ55J70+EQtksSnBfRBnIFdK8ZBqLANhaW60fHcy7DQwX3NdXAmPvRpdfVagnv+K 56UINMHkNh7o+Er0DXHfzcOmhoNoWlkxZ84uhqK/nL6qlj4EqroHl995vuZhF+y1ANgf wi75YBYK6JU2RI38JwYGNxrjeXr0WWJmj9QgV8FyBFXdfs6cv8meyJvNdff4EXk/b37F D2yxhpzyOKWnjOhTIh+AmkGR26UREbIr1X0ik/Kk5EjjclHALfqCTxf6KE5d51vm/rde d6ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vtklS/jBlWBBb7I5PQy1NemEL8fX7OtzLyw/Jsz+ozc=; b=kAj0uBSrldl7pxqI7ryxpoaX05brkEGNvsUqCRW0gUo4tVkiRt2fbstbFOnfb+QUZ1 jnCXIF4kqrglxfxAUfWm8FCFV1m97KMJzWQ826aMf5Tvxx/VtZKX6mW0P/+iMbhX3eRD eS8fQGYOYgu2NWf69n8eLIH9gy6yP7h9i5Lhx3KLi7G2TKrXZpEiNoyA5y732V8R4mpO Y6G+bjLKCQZ+SAeIJ0MOWoa4tsRY+FcXNmvwAdcxmKPDjnMO1wBp5O7CNK9qpN3VddaW thnyV4Za7lxMpktkxxOQSo6jHMa2FoVz0or9fE4H8A19ibdaSTpwT8sI5AQO48LoF4PT YpIg== X-Gm-Message-State: AOAM5323y/Xrvg05hxiLhHcvakrj3JNS2FEkxjykJH2IqD3O0y6tbcaE ZefoU2qweNbVZ9awFr+9BTOV3YfDlIamVQ== X-Received: by 2002:a5d:5222:0:b0:213:b7f7:58fe with SMTP id i2-20020a5d5222000000b00213b7f758femr31628350wra.620.1654765578602; Thu, 09 Jun 2022 02:06:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/55] target/arm: Pass CPUARMState to arm_ld[lq]_ptw Date: Thu, 9 Jun 2022 10:05:17 +0100 Message-Id: <20220609090537.1971756-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The use of ARM_CPU to recover env from cs calls object_class_dynamic_cast, which shows up on the profile. This is pointless, because all callers already have env, and the reverse operation, env_cpu, is only pointer arithmetic. Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-29-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 49e9a1d108e..4d97a248084 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -241,11 +241,10 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, } /* All loads done in the course of a page table walk go through here. */ -static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, +static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUState *cs = env_cpu(env); MemTxAttrs attrs = {}; MemTxResult result = MEMTX_OK; AddressSpace *as; @@ -270,11 +269,10 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, return 0; } -static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, +static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUState *cs = env_cpu(env); MemTxAttrs attrs = {}; MemTxResult result = MEMTX_OK; AddressSpace *as; @@ -409,7 +407,6 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, target_ulong *page_size, ARMMMUFaultInfo *fi) { - CPUState *cs = env_cpu(env); int level = 1; uint32_t table; uint32_t desc; @@ -427,7 +424,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, fi->type = ARMFault_Translation; goto do_fault; } - desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx), mmu_idx, fi); if (fi->type != ARMFault_None) { goto do_fault; @@ -466,7 +463,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, /* Fine pagetable. */ table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); } - desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx), mmu_idx, fi); if (fi->type != ARMFault_None) { goto do_fault; @@ -531,7 +528,6 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, target_ulong *page_size, ARMMMUFaultInfo *fi) { - CPUState *cs = env_cpu(env); ARMCPU *cpu = env_archcpu(env); int level = 1; uint32_t table; @@ -553,7 +549,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, fi->type = ARMFault_Translation; goto do_fault; } - desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx), mmu_idx, fi); if (fi->type != ARMFault_None) { goto do_fault; @@ -607,7 +603,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, ns = extract32(desc, 3, 1); /* Lookup l2 entry. */ table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + desc = arm_ldl_ptw(env, table, regime_is_secure(env, mmu_idx), mmu_idx, fi); if (fi->type != ARMFault_None) { goto do_fault; @@ -973,7 +969,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { ARMCPU *cpu = env_archcpu(env); - CPUState *cs = CPU(cpu); /* Read an LPAE long-descriptor translation table. */ ARMFaultType fault_type = ARMFault_Translation; uint32_t level; @@ -1196,7 +1191,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, descaddr |= (address >> (stride * (4 - level))) & indexmask; descaddr &= ~7ULL; nstable = extract32(tableattrs, 4, 1); - descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi); + descriptor = arm_ldq_ptw(env, descaddr, !nstable, mmu_idx, fi); if (fi->type != ARMFault_None) { goto do_fault; } From patchwork Thu Jun 9 09:05:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580249 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp606279max; Thu, 9 Jun 2022 02:36:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzZBAfpE+8S3quSauRT/CIx0ckTF3hBWh2wC7oqlerR9Q2bTk5HtkQOdrQ0llJXExhkTPna X-Received: by 2002:a05:6214:4101:b0:441:47e5:c718 with SMTP id kc1-20020a056214410100b0044147e5c718mr28897359qvb.12.1654767410253; Thu, 09 Jun 2022 02:36:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654767410; cv=none; d=google.com; s=arc-20160816; b=xmxGHyn8E0bwfMgca2PNH/rYfCpN6vFmfU3ASxeysv7efDLD4OLGkiDRwiSt8JU/E8 k6DKBbfNT6PB1nhGE9coOnXs4GHk+haeZbE/ZrHktG3yB3RWhD80ZjyQxaVUP+FjJPj7 PFvEG1Xvet7/djxfCwRlol5aSTKlDIkIDIAd1fwGBZ+fNUN2OcNWeAWCmcWEPYAwigE6 qDDPtXtcQikCjcfjI8F4XaLGWwdtTbhkrYrVsfKpx/m2VDu90evhZao14ZxwQ8u6z+AL DTR6rNjXnSJzrVkRq0EKRzEyy08wuKkU8iXFauAW8LA9VtsFeCXb7Iq+OWQ5yIxsXwVi Baag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EuesFPP2ejmD1fMqQKFfEmxikNEPVrFLtiBcjEpaFDk=; b=CoZlprVlKchkcxR6axi4bcg6TJk9xWBck1OFlDwqaVM6X8gVpMrC/nS09d5jNXAjrg 47Kj8G6f9vO8Cusz+BvNUtsOiNPke+W2dPBbVXbBdZBP72tYSMwHgCObuuUx4xHoWVjC wsy45U0582Xa6PgVvLzxQxBOiF+1m9UdOlyC9jpamYn9PPsRep4yv15/F3Tbk3hDYA25 8v5KGIdMvoBw6VJsmL7h0VXr33zjTmvvmQoZnHtSwHPGVBiaxPKVDiFFfOm68Sc1Wlcc jI5vkeQ/X7avgx/ICZXPkEaPw3IStmu1Pfr916bh0Ykx35M6ZDToiyN5LhVHWtX940Ux 3Bbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eMZ6cqXE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i12-20020a05620a248c00b006a73211beabsi340682qkn.262.2022.06.09.02.36.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:36:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eMZ6cqXE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEav-0003tW-OG for patch@linaro.org; Thu, 09 Jun 2022 05:36:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39744) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7S-0001ZL-7c for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:22 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:40587) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7Q-0005wl-AN for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:21 -0400 Received: by mail-wr1-x436.google.com with SMTP id k16so31477811wrg.7 for ; Thu, 09 Jun 2022 02:06:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=EuesFPP2ejmD1fMqQKFfEmxikNEPVrFLtiBcjEpaFDk=; b=eMZ6cqXEA7rm1G6az+CJ/89YVforU6AL/xrTqOn7qWmJwniNPn+CQlofDzxNN2gipE AG5aFAwfIqcriNAg+rQc9Ms/vDGMcLiSj5h4wqmenczjxf7MDRBrFmmX6CeO9qXRdddJ okDY+Mn+cNLS6wjXhgz7yZsOHoOvllT7Eb2MOeXHrCP6JIPLkaKgOnQoVFsAjt0HGzo/ zaeTJgtF5XfjUXRzTcm1V4pAV+RiHXVd6QEvjlGEBL02zBmQnk5wJJouZf4+CPpNfni0 Po+tOu/MKA14C/zcl0rJAEXvIuip4uyEWykSrE06CQCeiaKJg6Ma2dlV2FAuJIfegcL4 fusw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EuesFPP2ejmD1fMqQKFfEmxikNEPVrFLtiBcjEpaFDk=; b=Vn0TD4K6+Y8Obbvt7p1p6p0XMHmbZGubdHvzhFnTTEJBXrzGTvIoBVEFHcZAUOWp0V 96ZdlKSpW7MHWr4Pojj/5bJRwso6pZaZug/vANME8qYSfZ31xnOKiJL0aYnS683IcNDx ASZvVhs1/i6P4zVLhOHrs5pouGEp+A9VReAxztNVHtPTn439DjtccoSaCNfVsRjwVwR1 DBrSICvHW7YbYGHu0Ah8hwHIgb07NO5LNXn51iGHliMPVbSeKkEXBfDvSpx+IEolTl02 V+fWsc3r0lUSIkUDIt8GLTiy5X1meRWEP8YivNPbwFxwnGLozclb3waUP2NOueXJo7Ch WiBA== X-Gm-Message-State: AOAM530ruAZXMbj/VO5pnnOa0mH6u/C3DUsYY3ywViDkYjSA/4tPUC34 YHH6Pq4nQCyiwEJlnLl7+bseoBoVUdTiaw== X-Received: by 2002:a05:6000:1547:b0:218:568a:bd2e with SMTP id 7-20020a056000154700b00218568abd2emr10444077wry.716.1654765579600; Thu, 09 Jun 2022 02:06:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/55] target/arm: Rename TBFLAG_A64 ZCR_LEN to VL Date: Thu, 9 Jun 2022 10:05:18 +0100 Message-Id: <20220609090537.1971756-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson With SME, the vector length does not only come from ZCR_ELx. Comment that this is either NVL or SVL, like the pseudocode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 3 ++- target/arm/translate-a64.h | 2 +- target/arm/translate.h | 2 +- target/arm/helper.c | 2 +- target/arm/translate-a64.c | 2 +- target/arm/translate-sve.c | 2 +- 6 files changed, 7 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0ee1705a4fa..e791ffdd6b6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3241,7 +3241,8 @@ FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ */ FIELD(TBFLAG_A64, TBII, 0, 2) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) -FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) +/* The current vector length, either NVL or SVL. */ +FIELD(TBFLAG_A64, VL, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index f2e8ee0ee1f..dbc917ee65b 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -104,7 +104,7 @@ static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno) /* Return the byte size of the "whole" vector register, VL / 8. */ static inline int vec_full_reg_size(DisasContext *s) { - return s->sve_len; + return s->vl; } bool disas_sve(DisasContext *, uint32_t); diff --git a/target/arm/translate.h b/target/arm/translate.h index 9f0bb270c5b..f473a21ed48 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -42,7 +42,7 @@ typedef struct DisasContext { bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; /* SVE exception EL or 0 if enabled */ - int sve_len; /* SVE vector length in bytes */ + int vl; /* current vector length in bytes */ /* Flag indicating that exceptions from secure mode are routed to EL3. */ bool secure_routed_to_el3; bool vfp_enabled; /* FP enabled via FPSCR.EN */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 37cf9fa6aba..c228deca755 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11181,7 +11181,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, zcr_len = sve_zcr_len_for_el(env, el); } DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); - DP_TBFLAG_A64(flags, ZCR_LEN, zcr_len); + DP_TBFLAG_A64(flags, VL, zcr_len); } sctlr = regime_sctlr(env, stage1); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 935e1929bb9..d438fb89e73 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14608,7 +14608,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); - dc->sve_len = (EX_TBFLAG_A64(tb_flags, ZCR_LEN) + 1) * 16; + dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); dc->bt = EX_TBFLAG_A64(tb_flags, BT); dc->btype = EX_TBFLAG_A64(tb_flags, BTYPE); diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 836511d7191..67761bf2cc5 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -111,7 +111,7 @@ static inline int pred_full_reg_offset(DisasContext *s, int regno) /* Return the byte size of the whole predicate register, VL / 64. */ static inline int pred_full_reg_size(DisasContext *s) { - return s->sve_len >> 3; + return s->vl >> 3; } /* Round up the size of a register to a size allowed by From patchwork Thu Jun 9 09:05:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580288 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp689309max; Thu, 9 Jun 2022 04:34:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJymLQ0kujhn/zas4TbQXCNvFVuGgt6t+QJL5kKoTj7vv79yiOesVa2MDP70wd/I80p2Ol2a X-Received: by 2002:ac8:5f91:0:b0:304:df67:c780 with SMTP id j17-20020ac85f91000000b00304df67c780mr26123357qta.248.1654774473524; Thu, 09 Jun 2022 04:34:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654774473; cv=none; d=google.com; s=arc-20160816; b=wjPSvJUCYskNQcbh2qwxbBJU0FZ6PssqMxL4P5nNqPzJIVI4aKJFUGpdH4vc6XyZ2y bmYz8kouGdL+c1mXo7KTybCYXplISZrJvfsJGUxD2myvLBgMgnlqO3xP6mujKQDNdje6 OhA9nRVG0DvQYiPEu5PXB0qWy2PbTxx6lOP3ULNtHYaKT8COt+PYMqG6RRSqLfP4QPI/ tmvb6As3V1N5cXahHQJ/hIFzYUMBC+MZrNTsnS7jZA6jA/bzP3aZyJLgyTEa48h5pzx6 /zvOHhvRys0RX3ffo79gGfresVuFkSKezO4Mnx9Jni3DG2EsvBeZXCyuCARPJWEH2P8v FooQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aIxMiFOj5OlkrMNI1jLiszeJAUOpuEVyCOWF9sP0Y2w=; b=NfuOlHwDaxyuNS379SL+3rsqWOqqtDjjkwz8shvsygQUwUjvw6bHO/8px3L3Qmhr/G JyW5PkjrphDbcmm6rEbryrC53B39/SuWpYWTVAwIV8BKay32kg+mo6/5LlV/AZZGFObl BDUwUE2jPhDMfDI3zSGvhPNXxOrGhIkjdSBVJmrmvUOcs6xq/QxKWMQukt8OslfJTsSi V3LeMWILExWIpzrYXc8vR3iHp7/hA5rYrq5/DwhEsGa8m4fWl2wjgr+rT0WukeQxwU7V 5F7F0bAT5i2Yl8zC9Ts13PUoxq/tYCha/3qax0N2OwvIOBu0059QHYeseAoGaIR2MslX YOgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZC2m5FbC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h17-20020ac85e11000000b00304f6988cd4si4708868qtx.778.2022.06.09.04.34.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 04:34:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZC2m5FbC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51686 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzGQr-00083e-0D for patch@linaro.org; Thu, 09 Jun 2022 07:34:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39806) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7U-0001by-MH for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:24 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:36483) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7S-00063j-WC for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:24 -0400 Received: by mail-wr1-x42c.google.com with SMTP id o8so3625877wro.3 for ; Thu, 09 Jun 2022 02:06:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aIxMiFOj5OlkrMNI1jLiszeJAUOpuEVyCOWF9sP0Y2w=; b=ZC2m5FbCfDchAohCh+UlgwvHp2J/t873YzrMo6IFMAN9+gJvfhwOkbmJ2P0QABjLmY nJOWXN3pusATWYgARANTam9uSrR6CgjXHEf1cRsLX1V2nw2QJgC0yqEVhHXVhVB7UDBN AQ2Zi1Ovk55YuyXHvS7xSav3xNhdu7vDjQGeoB8Um4SAlD2iLvyDrwc7yIuPmcuTxA0A WCc8QjFcUNz/78CVEl9ly1FKvseMuP2teBu6akkxWA7vasDNP9on8bFv0ZTZO2qQjjVr a7RjAmgCZe+E9PDvwSx4vM2JpzKLrelM4oR4mHYWHpl9h1YzsvtxD2b/uKrDc8pLkyCi d+TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aIxMiFOj5OlkrMNI1jLiszeJAUOpuEVyCOWF9sP0Y2w=; b=yuiFcMp9+lnCRhTcJkvtmRouAGLdWvlQPkdsOmNvagGO8q5xK8CkTYp1J+1GHCYSpc FLLdNrtJpmPSP51BITY5QiBSz3mxiRk16TcYYy8yPjqGtRjJtK9zPBQ68+9nLf937Qj9 M4bjW7RuUECdGASkOwcn/wKimgiqcG02OCUK/SnPsIMyccL8I6QiCZ+CX8Ue2VxdzM5+ pu3u+sU4yPnG4lRwF/5rKpmMHK6EEbOXt+8Exb+UUImXJWAWzEOJr5A4EvKvuz5nhMXK l/Mi3IEDBs9CCKtH2mRXkA0Lh0+nFTm9ehYUXCEPrecwyGJYofiQYSiH2clcCqC2cdPG ja0w== X-Gm-Message-State: AOAM532zRD+XeiXPYBUcGiJfM85PlRh7VAYfLLDqUIfec2x8GsBMhsD9 uj7poBVoKb0y8QDLY7EsU4O8TkKrXY6jgw== X-Received: by 2002:a05:6000:1888:b0:218:3fab:c510 with SMTP id a8-20020a056000188800b002183fabc510mr19871078wri.473.1654765580495; Thu, 09 Jun 2022 02:06:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/55] linux-user/aarch64: Introduce sve_vq Date: Thu, 9 Jun 2022 10:05:19 +0100 Message-Id: <20220609090537.1971756-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Add an interface function to extract the digested vector length rather than the raw zcr_el[1] value. This fixes an incorrect return from do_prctl_set_vl where we didn't take into account the set of vector lengths supported by the cpu. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/aarch64/target_prctl.h | 20 +++++++++++++------- target/arm/cpu.h | 11 +++++++++++ linux-user/aarch64/signal.c | 4 ++-- 3 files changed, 26 insertions(+), 9 deletions(-) diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h index 3f5a5d3933a..1d440ffbea4 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -10,7 +10,7 @@ static abi_long do_prctl_get_vl(CPUArchState *env) { ARMCPU *cpu = env_archcpu(env); if (cpu_isar_feature(aa64_sve, cpu)) { - return ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; + return sve_vq(env) * 16; } return -TARGET_EINVAL; } @@ -25,18 +25,24 @@ static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) */ if (cpu_isar_feature(aa64_sve, env_archcpu(env)) && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { - ARMCPU *cpu = env_archcpu(env); uint32_t vq, old_vq; - old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; - vq = MAX(arg2 / 16, 1); - vq = MIN(vq, cpu->sve_max_vq); + old_vq = sve_vq(env); + /* + * Bound the value of arg2, so that we know that it fits into + * the 4-bit field in ZCR_EL1. Rely on the hflags rebuild to + * sort out the length supported by the cpu. + */ + vq = MAX(arg2 / 16, 1); + vq = MIN(vq, ARM_MAX_VQ); + env->vfp.zcr_el[1] = vq - 1; + arm_rebuild_hflags(env); + + vq = sve_vq(env); if (vq < old_vq) { aarch64_sve_narrow_vq(env, vq); } - env->vfp.zcr_el[1] = vq - 1; - arm_rebuild_hflags(env); return vq * 16; } return -TARGET_EINVAL; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e791ffdd6b6..f5af88b686d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3286,6 +3286,17 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) return EX_TBFLAG_ANY(env->hflags, MMUIDX); } +/** + * sve_vq + * @env: the cpu context + * + * Return the VL cached within env->hflags, in units of quadwords. + */ +static inline int sve_vq(CPUARMState *env) +{ + return EX_TBFLAG_A64(env->hflags, VL) + 1; +} + static inline bool bswap_code(bool sctlr_b) { #ifdef CONFIG_USER_ONLY diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 7de4c96eb9d..7da0e36c6d4 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -315,7 +315,7 @@ static int target_restore_sigframe(CPUARMState *env, case TARGET_SVE_MAGIC: if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq = (env->vfp.zcr_el[1] & 0xf) + 1; + vq = sve_vq(env); sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); if (!sve && size == sve_size) { sve = (struct target_sve_context *)ctx; @@ -434,7 +434,7 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, /* SVE state needs saving only if it exists. */ if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq = (env->vfp.zcr_el[1] & 0xf) + 1; + vq = sve_vq(env); sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); sve_ofs = alloc_sigframe_space(sve_size, &layout); } From patchwork Thu Jun 9 09:05:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580267 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp632917max; Thu, 9 Jun 2022 03:15:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJym51DVFHdyEaON5GTQ0bvVXj38PeiLMgjzrz7ntVKmsCcS7m1IqjeqbAWztGBW3ulu1pdT X-Received: by 2002:a05:620a:27c2:b0:6a7:1db:a6e2 with SMTP id i2-20020a05620a27c200b006a701dba6e2mr5126502qkp.150.1654769717038; Thu, 09 Jun 2022 03:15:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654769717; cv=none; d=google.com; s=arc-20160816; b=rlVucBVIJotAp5jeOHGQTWDeoBTAVwm5Ojml8YOYsalpxXVMHfgNddkaS0meC3okzd Wf9WBChjtbxxqRrHSTwsSTJpsqB9FKo17PQK8Pmr/2ZYJDs1dsI5wA6CrPhcKma4Dr/g VMxq73aNKxZ+U7tyx3N5poP+6w9qEr7NaVPJYF2xE1ylfsaheexFi76jWvvydZ1C2+75 xhl/xM35SY4p8jgjuY57y4URVScIBTfRWEbwFywfoJ0onLllzLkG+Y+D/2jqI+ZCGLlY 0ZO74V6kBYXGUFTaMr63MVPiZR54nl4p47YlU139JH73NVh3wAr1sgFkvvXh1J497EM1 TBGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kIvAW33Xnjg8FxQHlUQZrjhFZhed2xMGpf7iSMt46Cs=; b=c9gqzlVbB8E1MTNisFgs5VPUupi9XeSRSYTZ7dCg4G3tOmgjF65+XW8IL8GyhDUFD+ r1WfeNp83AzntX7PKalheZiI+D2ZCCVbj/8yfyR8jM+uj1lBTcMrkP1ajtnbKQqIkcsS QeOVhyds9cTbQqIJMgi5mtfs7DuNtmWPMEMySPAjI/sXlF8LQ6fgeqRuyrYKkjMc98QD lK5YwseDIkejqmxNQN1DUSKwW7DhiV7lCS/1iOwr0G5tKmzmkn1pvzpplJJTOr2NEoGn CBlOBb+pskLUsh1byPZ5hVTZq2UNONig6wsbvLcZkILPJ+fvZv8wtjgpkEGZ6jm/wUBM boGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Tfv6rHlg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s14-20020a05620a29ce00b006a7263f3c0asi954174qkp.757.2022.06.09.03.15.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:15:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Tfv6rHlg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35032 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFC3-0000r3-0C for patch@linaro.org; Thu, 09 Jun 2022 06:15:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39848) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7V-0001cT-U4 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:26 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:40585) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7T-00066W-Dy for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:25 -0400 Received: by mail-wr1-x42d.google.com with SMTP id k16so31480008wrg.7 for ; Thu, 09 Jun 2022 02:06:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kIvAW33Xnjg8FxQHlUQZrjhFZhed2xMGpf7iSMt46Cs=; b=Tfv6rHlgIQ/2qLYdA8pWVP7TGSU4nNZVGiLLKJSm9BEFY4fTJg2KLdNJ0bYdriMPt9 Lg6DO5vuD7SmOw83Pg+urgl7Z6bVayOkOIk8wt0LxFYG6mwXNj2Z69OTtkxF8r0boihL qeysuxJShUZq2lKLkbHTL8qMnSGv7qL+tgvUZPjVezdE1GyGT5PFk7Cwv4tNNG8VWsW5 HTwEM/+VlbYRoZbGTpZYWr40b9gW57czGf02C7Aecezd5euPvhGHDPDJEBQqjCmXDVPz Qgl9MixPO0rhrCvRcY0+bfE22EfNFpJKrFsAWAGx5gXrTVZ/7rqWdVS0mt2YZsdq2iVr YjyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kIvAW33Xnjg8FxQHlUQZrjhFZhed2xMGpf7iSMt46Cs=; b=VL0/XBE0VkT7k1wdb8GSgNCFyqT82/JIrkOh4mJm1euDJyw9pylAmN1NSQpiJ232EK l1M5trT11ladn5eF9v6ZrR1Ffvd8WS6wO26fbvbj530I41vvyajf1gnpbjfbjExOIvGH RC7/jNt44aL/okNMTir0dsCTkPdQcTuQGxKl0t/tubIyV1hkmIA3fI1Axkm8G0dPeCJj f62NjcCqGgSkehcgigKhmlUknJgxJvIh2P5cH7H9b1THHnTQn7U9j+FZnPXFwztOCNBP zhQ5dk8vJmR4ycxfDUjDfEJMN2BnvKOxyZZSkhCCz+KKjnhJJt20jxZnyN4BPMo4wOE9 jpig== X-Gm-Message-State: AOAM533ocCqU7tpvdSZfy+C1ZnRITn/XJF7Vz6up/yiEN1rA3mTHHIMF 5lDWg+4wOt+KL4Hb3tdlU4CFfG+6PxZXSw== X-Received: by 2002:a5d:6945:0:b0:211:7de7:7247 with SMTP id r5-20020a5d6945000000b002117de77247mr37017126wrw.169.1654765581358; Thu, 09 Jun 2022 02:06:21 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/55] target/arm: Remove route_to_el2 check from sve_exception_el Date: Thu, 9 Jun 2022 10:05:20 +0100 Message-Id: <20220609090537.1971756-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We handle this routing in raise_exception. Promoting the value early means that we can't directly compare FPEXC_EL and SVEEXC_EL. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c228deca755..1bd77af7e50 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6149,8 +6149,7 @@ int sve_exception_el(CPUARMState *env, int el) /* fall through */ case 0: case 2: - /* route_to_el2 */ - return hcr_el2 & HCR_TGE ? 2 : 1; + return 1; } /* Check CPACR.FPEN. */ From patchwork Thu Jun 9 09:05:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580253 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp613923max; Thu, 9 Jun 2022 02:49:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyaX21/gh3pW8rfuiCZw1tlo/I4AcmmbxsEOXTO+KSj5nWzCcR+5m5Zaus7CEsJJ8uGQyM0 X-Received: by 2002:a05:622a:130a:b0:304:f156:ec9 with SMTP id v10-20020a05622a130a00b00304f1560ec9mr13867663qtk.226.1654768161527; Thu, 09 Jun 2022 02:49:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654768161; cv=none; d=google.com; s=arc-20160816; b=smf6tHKZk/uU5g4omXKd3x12LovYf+TDXuN4/Y5udnfRjYioh4JHVwJts2UdDb2ECg TCDc57jn6YkTsaiOCzWsdgDsT3ce7tOQLWUMD6J7nwZEu8o75wudA2AhG4dFe55LhkQ9 7hEiNVScF6z5CsIgg8VOnodcFy4mazbQQRxjBtfIn5OojU7cssDPUrJfiAW09TXce9gR rkZsb789RuTJcgNB3DR3vSCfqtWLYLq+U6KLqGuHb3F2XDQISJsP/e+QBHvRYRhK7VPJ BLGbAz86WUs/TAJnez2Ir1uVlD0kGpNL4ANjHbV4QAaW5BHhNKMulhZ5gZ09zNpB3gES PuuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=biefxwiMWkFplUNyCYS3rTOiD6++qV4YkTvNGi9PTWE=; b=eK6RPDEEmwnFQRkbOq1gdxZFOuFgXXakqlbEhNav454kXEJADttnHKLtJRUWsqmU6q bWbskT4RzPkXlFZSlF0TBv1DnXXUmrQRXj0EuSfJI3YalK+HndtWX8Brm9qKkg9o0hcn YW5pg/eQW0oPBYZdVadNdgW1L9q6wW3jcH9QSP+gO9ZeZ9GKw9E/tNBk8qHyeS/gzg/l Oue8fAfFWCYyfLZtazfhdLlHV01AAe2eSBl9xSIQdYcJ50k+l8EhcAi/0yBVgBt13l+o ZefyZo3e4ra53+m3gcKgVSy81/hgkKIhiYv37YzSUh8xOIcGJwbF3venY837V8MHtQUb YgFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CImkj7Cc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ke1-20020a056214300100b004644918d50bsi11946469qvb.148.2022.06.09.02.49.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 02:49:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CImkj7Cc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzEn3-00025q-1L for patch@linaro.org; Thu, 09 Jun 2022 05:49:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7V-0001cB-S1 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:26 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:43557) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7T-00062u-40 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:24 -0400 Received: by mail-wr1-x42e.google.com with SMTP id d14so22478158wra.10 for ; Thu, 09 Jun 2022 02:06:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=biefxwiMWkFplUNyCYS3rTOiD6++qV4YkTvNGi9PTWE=; b=CImkj7CcSzsMXUFeUgr4OgjlVtoTEaUrxxXD1UxdxuMTBDPNY7KSZC9J2nQWZBpt2k AyCywy2PkhKYOMmNXD4p+bbpHrTAiMbc0Uus7iSejXEQKXJh86oLwi3owSaQcKM/ZViW abc8KSlz7HB/POQDmTkRlEYGZ33reKuv6bhKHWSgS3WOFoFP7dyEKc9ff/V9xmh1X8D0 r3fonp6SyqK10HTOuhTNTritWpI02Rl6ihch2CEQ15YaRjrjIoFWC0wQAkaKpdVeghOF aw6dkMN6m9oLNE/I8Tyku9Szvsgg+jAmORHnOYDkpz0yRQXe159Xl8rp13yxCF+fnN5r CXcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=biefxwiMWkFplUNyCYS3rTOiD6++qV4YkTvNGi9PTWE=; b=qRSejLiOANJZNK/BxElUlyufP9EvXeSojt26AFDoZlsQ5XEQB9hh/Z0kFK52czHKZ8 MbJZ32J17zotJg5yND+9GQxRsWH4qtzAMgfin2WylOENKjYgC1BjXDDMXpT1ub3fjTq2 dfivAbPXcNDosSl//xTBTt0DPlMvIejz6MtaWpzBU1O6B1weh5B1yMro3FfTWiKjPQ12 ELiGdUC0Er0G+7DvGlmLUlN0sD0ik0/flPp3/9o47npwr5RWMFd5Extl5HaUB8fXUG7Y 907S93EX7dWhp/o4qIT5Y+vQD9gOHSOuYBv3XtxJ+ayZ3F4gvxVrPKrKxdKs4OANOXAj /HUw== X-Gm-Message-State: AOAM532twcXasMADxcQPrMO2mH3vQXxKNHacxrKSzTsoCUZoYeGKTCrG Li4eINAxyV1qNQNjd9w8NQpnYZSI1irlJg== X-Received: by 2002:a05:6000:152:b0:216:160:2e60 with SMTP id r18-20020a056000015200b0021601602e60mr27315852wrx.663.1654765582316; Thu, 09 Jun 2022 02:06:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/55] target/arm: Remove fp checks from sve_exception_el Date: Thu, 9 Jun 2022 10:05:21 +0100 Message-Id: <20220609090537.1971756-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Instead of checking these bits in fp_exception_el and also in sve_exception_el, document that we must compare the results. The only place where we have not already checked that FP EL is zero is in rebuild_hflags_a64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 58 +++++++++++++++------------------------------ 1 file changed, 19 insertions(+), 39 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1bd77af7e50..4f4044c688d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6129,11 +6129,15 @@ static const ARMCPRegInfo minimal_ras_reginfo[] = { .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) }, }; -/* Return the exception level to which exceptions should be taken - * via SVEAccessTrap. If an exception should be routed through - * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should - * take care of raising that exception. - * C.f. the ARM pseudocode function CheckSVEEnabled. +/* + * Return the exception level to which exceptions should be taken + * via SVEAccessTrap. This excludes the check for whether the exception + * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily + * be found by testing 0 < fp_exception_el < sve_exception_el. + * + * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the + * pseudocode does *not* separate out the FP trap checks, but has them + * all in one function. */ int sve_exception_el(CPUARMState *env, int el) { @@ -6151,18 +6155,6 @@ int sve_exception_el(CPUARMState *env, int el) case 2: return 1; } - - /* Check CPACR.FPEN. */ - switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN)) { - case 1: - if (el != 0) { - break; - } - /* fall through */ - case 0: - case 2: - return 0; - } } /* @@ -6180,24 +6172,10 @@ int sve_exception_el(CPUARMState *env, int el) case 2: return 2; } - - switch (FIELD_EX32(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { - case 1: - if (el == 2 || !(hcr_el2 & HCR_TGE)) { - break; - } - /* fall through */ - case 0: - case 2: - return 0; - } } else if (arm_is_el2_enabled(env)) { if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { return 2; } - if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { - return 0; - } } } @@ -11168,19 +11146,21 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { int sve_el = sve_exception_el(env, el); - uint32_t zcr_len; /* - * If SVE is disabled, but FP is enabled, - * then the effective len is 0. + * If either FP or SVE are disabled, translator does not need len. + * If SVE EL > FP EL, FP exception has precedence, and translator + * does not need SVE EL. Save potential re-translations by forcing + * the unneeded data to zero. */ - if (sve_el != 0 && fp_el == 0) { - zcr_len = 0; - } else { - zcr_len = sve_zcr_len_for_el(env, el); + if (fp_el != 0) { + if (sve_el > fp_el) { + sve_el = 0; + } + } else if (sve_el == 0) { + DP_TBFLAG_A64(flags, VL, sve_zcr_len_for_el(env, el)); } DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); - DP_TBFLAG_A64(flags, VL, zcr_len); } sctlr = regime_sctlr(env, stage1); From patchwork Thu Jun 9 09:05:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580282 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp660344max; Thu, 9 Jun 2022 03:57:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzgDsaGB+jwLktL7NjEeHQ+FEg2FUwENvAjlR927O817VjPH32q/OkmAcTerjK6Cee6fqU1 X-Received: by 2002:a05:620a:4111:b0:6a7:102e:f5d3 with SMTP id j17-20020a05620a411100b006a7102ef5d3mr4196104qko.140.1654772245056; Thu, 09 Jun 2022 03:57:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654772245; cv=none; d=google.com; s=arc-20160816; b=Oyr3ootivyOhtM3vpSvkt6YAsiaCKufiDlRIw0gwYDQw6FahQ79q2YcmLqW0+5xoXc 46rgH0gUje/dlmTH/dZWM97howpDFgY/cfEr5+eqc6GaC/6LGgn999ugGrlHSJESZwLg bSalFDC9H4M/lpxLKAa4iPiZeuUa91MCVovgIda3qIV9ya7psGYrPsBeWFZ8mlwJPa2f VFQku8KBQhxeGmudPyIUEOgLV4zdFTY5D/UhhUDC5ono3htfTl0AGIirytwtSmr231Tv knL0xSENwJ2+oghJUpiX4YpBhZVNhK3o7S4XfsntyRR7OhzFb/iNsLmQKtXiwA2J1arB xsmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OrRqWRQp9nOhwyO9OA3TSRIbMZMtkcOgDSH8VMFZG2E=; b=aj9ziL3SVUKR4EYUnaLe5SeHkHuNCHMAeCNXf/rnbP5nuuTmqJwobgnBDF5hKK3Hte NH6ShFjV0ReMJI/60NOy1sOGK6Trr6wJ5ij9A3z4WGJqH73z4aKJA76I+i8JAeWaiFKe HYdDGS2MlCmRR4CHc5srmUlsSVamAFu46rkWmLHmemhTfsqne1Pwr7ToVq5/9pkt+/Qs 8tJFpLhcb6TlVmCWb8977zyWXwqcRKRDyOz2A4yGRryvFQwmXxGgQMFTVX4nYTIpGCYX 7Gixefn1xo5YRotn82hC+0kkdDoMK61WSoU0cdWh06FOicL5Gr5Kji0hjm5GgOz4bCka H4Fg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SxV8Gfp4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ed2-20020ad44ea2000000b0046451324ac6si12737622qvb.435.2022.06.09.03.57.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:57:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SxV8Gfp4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFqu-0005za-EU for patch@linaro.org; Thu, 09 Jun 2022 06:57:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40084) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7j-0001oY-Qd for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:40 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:51890) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7U-000638-17 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:39 -0400 Received: by mail-wm1-x331.google.com with SMTP id z17so7275188wmi.1 for ; Thu, 09 Jun 2022 02:06:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OrRqWRQp9nOhwyO9OA3TSRIbMZMtkcOgDSH8VMFZG2E=; b=SxV8Gfp4Wp7VVIZr1yL5BVHOPT6Ya4UDxFBBrDHQugd19quJmIS0Vpk4f5+KRahsix gW2p/+C2ywCZzUVbx2+K07xciYAujlijQwd30zlw4jDZkkmqDq1yrfvRvddB1g2YB8uz L9NKIxGZ1pyz54Y9J3RSOVVDhy73KUu+QI+bLikJ7bx1d9BQPTNBIuWVwnQVEgSXJxYM 64IdaARQw0MPXKkz9+f7yoTm1oZekOxq0st5KIP39QM+CHXeP9uqtEr4AB3NRbQGwuZ5 c08vT8h4x0DpWdmJsHhS/Bc+CSOK0fjFKz5Ru7dOP8pbwt9amTK+L6yS4pSNYr/nSW1t 2xLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OrRqWRQp9nOhwyO9OA3TSRIbMZMtkcOgDSH8VMFZG2E=; b=nlF981IbsNvQ+UCxwF688XjqQuqoDq96lzw0EvlVpCYEfc29djuWDSIFm/YfJkPYQX hl0TWj/i7mG0iV/HGzrdQe4LWqZbDhnHpfVUp/RqdO6r00gDAJv9b4jtX85I7wWV6mEv 0RGgfvKWJMvt4R5FegGn2I+AfVMe8BDiATEb0W2FBgr5znwzQS+n8n5xLHEZ2BI1K0rb FSwhN2UyCIAY0ncAkuGVRyOs9+IQEkV13EN7v2+3gJC+/2tt2IOjVsr/Q5TVNJmn11o5 LmzcC8pwlXATWz5+PXTCFGw1adbxdzrImTLFW+hDKy2ryiInltN74up4n7o2ZV0Uwv3b AaMg== X-Gm-Message-State: AOAM532GY1JrEhBs3aVPWUTY/s9YzSkXFZq9QNpo8/KDuQ+tjIWFWhpP N1kbQIgMHUST2APNYfxPUMo1Gifu5Ilwjw== X-Received: by 2002:a05:600c:3845:b0:39c:6ea9:ed34 with SMTP id s5-20020a05600c384500b0039c6ea9ed34mr1403163wmr.175.1654765583187; Thu, 09 Jun 2022 02:06:23 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/55] target/arm: Add el_is_in_host Date: Thu, 9 Jun 2022 10:05:22 +0100 Message-Id: <20220609090537.1971756-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This (newish) ARM pseudocode function is easier to work with than open-coded tests for HCR_E2H etc. Use of the function will be staged into the code base in parts. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 2 ++ target/arm/helper.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1d83146d565..ceaddcbfd6e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1347,6 +1347,8 @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); #endif +bool el_is_in_host(CPUARMState *env, int el); + void aa32_max_features(ARMCPU *cpu); #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 4f4044c688d..322508170e3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5282,6 +5282,34 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) return ret; } +/* + * Corresponds to ARM pseudocode function ELIsInHost(). + */ +bool el_is_in_host(CPUARMState *env, int el) +{ + uint64_t mask; + + /* + * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff(). + * Perform the simplest bit tests first, and validate EL2 afterward. + */ + if (el & 1) { + return false; /* EL1 or EL3 */ + } + + /* + * Note that hcr_write() checks isar_feature_aa64_vh(), + * aka HaveVirtHostExt(), in allowing HCR_E2H to be set. + */ + mask = el ? HCR_E2H : HCR_E2H | HCR_TGE; + if ((env->cp15.hcr_el2 & mask) != mask) { + return false; + } + + /* TGE and/or E2H set: double check those bits are currently legal. */ + return arm_is_el2_enabled(env) && arm_el_is_aa64(env, 2); +} + static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { From patchwork Thu Jun 9 09:05:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580289 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp696640max; Thu, 9 Jun 2022 04:44:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy1yakL35NFFtD28aGfVHVf7pdlL55cXVMxL9ITuXWKT/rE66cxukfifHDw6SVrNCndpmr1 X-Received: by 2002:ac8:5a11:0:b0:304:bab8:66f3 with SMTP id n17-20020ac85a11000000b00304bab866f3mr30876329qta.388.1654775061518; Thu, 09 Jun 2022 04:44:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654775061; cv=none; d=google.com; s=arc-20160816; b=ab/frO25CVA2Ou8OxvSQKJgjtHgvX6Bby6oLV23REy/23NaNhZxx+YF7327RIf2pv7 eHlvuXwpgWYJyHgiDXM2Zda6EkxEmrfIihccBH53Mx3d/+/ZxZKh4Awg3MoD/dkZA+y7 N5YgDvgVFB6fQ63P3Q35Mx6RjlOJK0xk682t51KSVML6F9qs16H9nwFMfdoUmNaLKtmZ 8/hPVaiy72uvFjoWUZxMVO5pys52U53Rv6IsDj09D90/wBlQHssUVSvHbslTMhGIR9j2 Wark3Pk9q+Lobx2iAQaL4YSSLZiUhIKvngn2pR8Xd2h6uR09pc6eK9uKLAbAO5sGayjL 5Fww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lq+u7f2f7YE5vmdKlLixcNnaKlj2/xU4nnWKz5bhpYE=; b=f+Kes3p9VqJ118mGt+H/+HMA0humsSBAy5FRvu5+nOZt6Ysefc4tT7DTgisp/sVNVJ K+JNYJzXxjg5nLmjnLSwMGiXNI1KsFI8noV9xq+nkXz6Lw3vCa2MVpd1wjswHyhsxKnX DDjSEeXnuPeSRuY+DIRs/HqJXKCksiO8vxxK/R/x22vOqp8XT6WR/pap5o4fHOzcqCW1 PI/mDQBEP4pfrtepCUJaxFx2M63VPvUOYKjUJBJ2YZT8Au7g11nZMbKGvATobhdURE3C 8+Db/P/+hqNqQBXKLyvcz7C3anb2N8N8WwPg1wSLe1ysR9E/Qdo6zKk4Lov+XQ6cqvEn Efeg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MUrD7RXv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y19-20020a05622a121300b002f944144f7bsi6475219qtx.283.2022.06.09.04.44.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 04:44:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MUrD7RXv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60202 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzGaL-0005eX-24 for patch@linaro.org; Thu, 09 Jun 2022 07:44:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39870) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7W-0001cl-Q9 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:28 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:53919) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7V-00067I-Ao for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:26 -0400 Received: by mail-wm1-x331.google.com with SMTP id z9so5330339wmf.3 for ; Thu, 09 Jun 2022 02:06:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=lq+u7f2f7YE5vmdKlLixcNnaKlj2/xU4nnWKz5bhpYE=; b=MUrD7RXva30XHSMxqFTV9lc8x1KlHVijSZRf+PibyhYch/MRfG/ERrlbrAMa5K7Lbi Zh0hCq8gpwkTmWCCAEoIwIa/YBKI+MJsBSdTRikbaHwPDzOHrSci16Y27NIGCezsFy17 1lDwisM/ONvYtEi0W+U6a4Y2FxskNC1W5x5DaHm1u1AFO3WSeqjYNxIjWoWulRmdwoXc U7axr4SlRTm0QDriWRDmArFhMgsXjN5hCxhyIatTPpERVJo68ecmxRtH373ThXDxLM/+ xS6UMNisK67Tsm07sZkl+t5muA0hOT2q8Y9L9oRDBEcCsr1ngmMVPZbIj6k4D0+2RSB+ BgVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lq+u7f2f7YE5vmdKlLixcNnaKlj2/xU4nnWKz5bhpYE=; b=1Gneaqf0TGKtLDPRQIEPtsTrtedTTu6DjzUILgmn8QsQix8vg/kgNqnnMFJQ29H9/W 1vjD54e2jovsTiKfbLcuQzP2chLBFIqmL56VAzMiPqLyjQI86bqGW/s6wM29H7zmRkru +cU4KNpnS6CXOYY92dTI8I2XrwCuqU3bqvrVryR04RGLYbiurPOrdTNW5DrxidhiuvDW QsVoiy5JxFZzrd2Jlc/6Btd8SvqeHjvQcKILHhR6dGM46BLy5l4XBg5iHx6NPrRtnjd/ JNCLVAtgGTVNpiI8HhPywjbyv7tLyT8ZWPaBQPnf+/LzJEccRhGsQ9ZkMBK1KVFZCSL7 AWVQ== X-Gm-Message-State: AOAM530gua54tczfeA2qlyqeoH9hSSzm7uPt5EN+Ru2IqpP1IUjcRY43 TO5/5dZm1KcAbgrYVpO+JfvH1iGY82n3aQ== X-Received: by 2002:a05:600c:a42:b0:393:d831:bf05 with SMTP id c2-20020a05600c0a4200b00393d831bf05mr2190206wmq.187.1654765583991; Thu, 09 Jun 2022 02:06:23 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/55] target/arm: Use el_is_in_host for sve_zcr_len_for_el Date: Thu, 9 Jun 2022 10:05:23 +0100 Message-Id: <20220609090537.1971756-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The ARM pseudocode function NVL uses this predicate now, and I think it's a bit clearer. Simplify the pseudocode condition by noting that IsInHost is always false for EL1. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 322508170e3..6b17c0f507f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6238,8 +6238,7 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) ARMCPU *cpu = env_archcpu(env); uint32_t zcr_len = cpu->sve_max_vq - 1; - if (el <= 1 && - (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { + if (el <= 1 && !el_is_in_host(env, el)) { zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); } if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { From patchwork Thu Jun 9 09:05:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580290 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp702972max; Thu, 9 Jun 2022 04:53:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx2nMZUO6tAyJhqDQr3byok+w2WUkIjeogJ9XufWPkVBXgJ3tIg5cL6BVWvoQ8DAs1ojuRQ X-Received: by 2002:a05:622a:1b91:b0:304:ff21:288e with SMTP id bp17-20020a05622a1b9100b00304ff21288emr8261767qtb.397.1654775637667; Thu, 09 Jun 2022 04:53:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654775637; cv=none; d=google.com; s=arc-20160816; b=swCYSDU+aJcHeWMnQ14UHS2IkBkbWSx4GYSer0b407+Wz0e8kpIV88WwsKqnTJV8EZ IRrZ+NEoDVcGALR/rqdVb5c1Aha1TsGtwhGfHQ96Fyp6vH3Oub4H221KgA4p7SaqoQ0V IyuZIwtZPUYfTRRq+LmqZD+In7jeFwE2UDJbsLAvNGdTgw8i3PuqMD5e2AwdwAwFh+03 UXzrOqU1iHRc0Dr8Cy+KPeaZd5NCKcyhT/nWvdRl2/ywk/U7j1VXse5DL903AAxR+4R3 gkK5TlXuyiIEtoOXzPP+hppSoT/paQDrYicQQYFx5rYF2ZFyIN+EIh7O5xIRiGN0wOvX e5IQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tECKDbH/4mwcOqBc4mXupaexcp4butR2eX7BFSU01YQ=; b=PZ+zFfy9vtyN4l7rBMBHMQqTpkmcQ3sQ6gch2EGQHCKsf/0wN1z3GnjoaKhc3rKsoQ L0c/UBZAcxKWz+gEs529Hcvl6S8gqorXsI4O1wh7BbW5lVfDwnQxaEe7IhBF3xSsPmBm ax3F3uUT2p3ZTCngjTBQHGtAmxVCTvDmeEIKLxvrxxTzepCVD0uSqHeiF0TFYzUFISL6 lZa7KJPrxhuz1B76EmX49c0oeK0733elsUjzRmFeinzkhm6dRCOiIhtKYwhe/J0uLL/k vP4zkLKPNz0jexn/ScjLNmy59536C6jmdCvALQAmot23+RRF1Ru1tIkcqh+MCkU38w5f Fahg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mTxweZhm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j3-20020ac85c43000000b002f91176c27esi12136562qtj.10.2022.06.09.04.53.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 04:53:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mTxweZhm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40606 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzGjd-0003hE-7r for patch@linaro.org; Thu, 09 Jun 2022 07:53:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7X-0001d7-TT for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:28 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:34251) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7W-00067c-98 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:27 -0400 Received: by mail-wm1-x332.google.com with SMTP id p6-20020a05600c1d8600b0039c630b8d96so432920wms.1 for ; Thu, 09 Jun 2022 02:06:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=tECKDbH/4mwcOqBc4mXupaexcp4butR2eX7BFSU01YQ=; b=mTxweZhmwelgUUrFdCBV+SagYHBM8i4WTuasMM088/5EVcGSTkyBfhyKnikeGxOG5e UcWljrSt/086LLSCVRM6WmJqGzO+VrGvDqTC5AfSDiKQrET5aqtk7JtOpHqpfp/jXI0h FHzhhdHk1wuNx5UCr7zHFTvTs+QzB6+yc6QMNnfj/D6Aulu017huSaBKRI6VDyaGKMoq gTZRu3mnWse40o5ZkEOA8yYJAl4cwPwl6xRqcvWbr+G5HSWjYcPyWwtA73rNeTkCVaMY /WiErQbLBNgGmWNYrTuCnSgdhB5UJ+vNStObQlJqGV+fwtYUF+0whTc/KeIiFKupUl3e Gmzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tECKDbH/4mwcOqBc4mXupaexcp4butR2eX7BFSU01YQ=; b=scDD3HchEvW4aKE444YvGKq8YebopU2fa980I7DfnfgKGakIntp0VhOeTKd9iyuMPS rLMQRzTHH7sGcTp5nymdZ6XA0Ck6uQApRcqRLoxvBEA4en0LbS1gp4qS7SQmjLNc705S asOK6vhzwqojS60SNJSt0LdI5u9c62gTNxfg24615GEj/X/q6R3z5Xno0OWuPTvOpbO8 C0HyqKaXxnCT7acgbBGimpqrgxkYWxVGZGiV5z5pJr7/M1EpDhy666a+tRRbJQPRSPUO LZtbsCgRRhoyJGmkFrDL1J3zMQ/7EIyEKEBpxwr/22QKg2OKYFJ1zFhoTj8aBPXYD76v yDFQ== X-Gm-Message-State: AOAM532CmSvuNnd+znAxiCRlNbqTyb2TsCb1NBSZIyK5nzgEN7f9R5rh 8moV+EGpbfpjYx7lwLYA6dFJGoPvD7JZTg== X-Received: by 2002:a7b:c31a:0:b0:39c:4783:385e with SMTP id k26-20020a7bc31a000000b0039c4783385emr2248879wmj.185.1654765584789; Thu, 09 Jun 2022 02:06:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/55] target/arm: Use el_is_in_host for sve_exception_el Date: Thu, 9 Jun 2022 10:05:24 +0100 Message-Id: <20220609090537.1971756-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The ARM pseudocode function CheckNormalSVEEnabled uses this predicate now, and I think it's a bit clearer. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6b17c0f507f..40b60b1eea2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6170,9 +6170,7 @@ static const ARMCPRegInfo minimal_ras_reginfo[] = { int sve_exception_el(CPUARMState *env, int el) { #ifndef CONFIG_USER_ONLY - uint64_t hcr_el2 = arm_hcr_el2_eff(env); - - if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { + if (el <= 1 && !el_is_in_host(env, el)) { switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) { case 1: if (el != 0) { @@ -6189,6 +6187,7 @@ int sve_exception_el(CPUARMState *env, int el) * CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ if (el <= 2) { + uint64_t hcr_el2 = arm_hcr_el2_eff(env); if (hcr_el2 & HCR_E2H) { switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { case 1: From patchwork Thu Jun 9 09:05:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580272 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp646534max; Thu, 9 Jun 2022 03:35:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyCOJ2UzjEWg5f+Th1FYzCh/oVeJ2Mlkzb5+wmY9FehGvjFax9oTlV9WjhUZz2EJjy4VkFb X-Received: by 2002:a05:622a:589:b0:305:7d5:4a4f with SMTP id c9-20020a05622a058900b0030507d54a4fmr4748876qtb.0.1654770944056; Thu, 09 Jun 2022 03:35:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654770944; cv=none; d=google.com; s=arc-20160816; b=OK+vZKx76kKD3Iqt4jts0wMSZ4CJ7laSr9RH0LMD4j2jNuqlNQ8L3Oi3QKAfACeJkC /0AcLC0Fbc8Ev1ug3XoyNnAvvQ0IkaJm869sASCJTlNkS7VslHo04cakgZewJii/vj+d Egu7G3LFSqisVR4VubgOO1DLA11mqjtPKXaGlwtEk1Mufm/sx8tKR4TrKoUr/E/dN2zw 0sB0s8o77vXSThLY+Xe02qhVB5W+uGyGDMpsY9bOIh7zZWAt/6oXo5rDiab5CbocbIbN RQO1NXgFngY1fmELfj5W0XL6Fb8Hz4Aj0khS7WX6R5UU5LluIRomdl8LruEVqPpQDs8Y 2SOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mf8AdCDhGe88lxvbihB81XSJ6frI4E36LSXViphWNvA=; b=qgp+0rNzC/35X89mAbfyX2+0aTPajqKVpzKAvCJSPsFiu77Tyl6N1ZxM1I5OHaa6ba O/TuIT2YwWo9a0+Sw8mS9uGB+tTO13azVmLFoAbNlAWU2v6Q6lfq10PxlDhGCmx0VM5r Ufzheh2CJvvEj+gzY7eMGbMUm79IZQWB6f4DCF7gKIMOxphEBXuiqScFPnJQEJlnpIM6 Fe/8cG0BQdaDvMnNwALkZ4ylBVxSEHkYOe5Ls4TwzB4U3hsnbjCKwDyapiMXXG5jdUW1 VEF4GB1KEOMdTw5SBRutyNbrB/evtZBAq2peH92GQUsjUotyr6eIW4rWpcDOtq5d1p5a 3y+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fhkawx0V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c19-20020a05622a025300b00304e7fb9337si7171811qtx.127.2022.06.09.03.35.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:35:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fhkawx0V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46188 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFVv-0001Bh-HH for patch@linaro.org; Thu, 09 Jun 2022 06:35:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7Y-0001d9-4O for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:28 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:36485) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7W-00062j-Lu for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:27 -0400 Received: by mail-wr1-x431.google.com with SMTP id o8so3625311wro.3 for ; Thu, 09 Jun 2022 02:06:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mf8AdCDhGe88lxvbihB81XSJ6frI4E36LSXViphWNvA=; b=fhkawx0VuNJ92c0NYT4sqHx/3AXzhkL7Hbw0A1MglNgQ8isWqSEmJhaINdD6x7rub5 mOj+N9+CgBavt8uNwB9c8hvRJhosjKKpx59/M8HPwCmWFlpnSMEveEH+Gkm4YznUOTVl gDmJ9YLUcsGjeTnW/Dx420CvYgOKuozhI1nFzhsHRmhJyWJDj4JKfcAnmksAJN4pGvk+ e7E6DqGd5y3Y9BOzszfcduHFTes1YOI3PsGWBAdPoSNziupslK00tC2RCd01Nnr7t95N 9s1wiAmNY+epPeUyQOGr5TxYnkrL+319uGtTnfz8u5+QdGDriy0XhyF31zkCgeUI6coz dEwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mf8AdCDhGe88lxvbihB81XSJ6frI4E36LSXViphWNvA=; b=HTpt/jVwCtUhQuKdQ+mpKa8QLTwhMCzbjjWMZ4K/TNuotydz7cOsr5bJlqnilE4dfz 0O3KwfNViTB3ztEWmnRguq37fp1HwihtSUf4x9klf+ga1Bx+cxDMpuc3rzoic0eLb8dt 4R6H50cv2lo3IjlzpCFfBVz/l6QrxB+Aej6cn0eZAU03ArsFZ3Nx03s8XAdc4bjKSxOX LUg+3W4dyA0OjCEpextdxyscTLcwznRzbtG/XTIGc/bcKOWyos1IVpdVmm0MbLOSwG4K yaNXDdJQ2W/t0ZbqgRytY3Nb4kBIOIXv26Lhg01Gd7amG9+Z/HN1XwR5JVSihe0v2k2o haSw== X-Gm-Message-State: AOAM5313zIwUxqb6g5yxg4S6kif9rQu9q8zM7lEDijooRwh+kkkkns19 J8SpkckTnSdbQGDaRWN/LZYKZ9cs5vhV6A== X-Received: by 2002:a5d:4344:0:b0:20c:cad4:9e9b with SMTP id u4-20020a5d4344000000b0020ccad49e9bmr36843473wrr.187.1654765585953; Thu, 09 Jun 2022 02:06:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/55] target/arm: Hoist arm_is_el2_enabled check in sve_exception_el Date: Thu, 9 Jun 2022 10:05:25 +0100 Message-Id: <20220609090537.1971756-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This check is buried within arm_hcr_el2_eff(), but since we have to have the explicit check for CPTR_EL2.TZ, we might as well just check it once at the beginning of the block. Once this is done, we can test HCR_EL2.{E2H,TGE} directly, rather than going through arm_hcr_el2_eff(). Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 40b60b1eea2..61e8026d0e3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6183,15 +6183,12 @@ int sve_exception_el(CPUARMState *env, int el) } } - /* - * CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). - */ - if (el <= 2) { - uint64_t hcr_el2 = arm_hcr_el2_eff(env); - if (hcr_el2 & HCR_E2H) { + if (el <= 2 && arm_is_el2_enabled(env)) { + /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ + if (env->cp15.hcr_el2 & HCR_E2H) { switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { case 1: - if (el != 0 || !(hcr_el2 & HCR_TGE)) { + if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { break; } /* fall through */ @@ -6199,7 +6196,7 @@ int sve_exception_el(CPUARMState *env, int el) case 2: return 2; } - } else if (arm_is_el2_enabled(env)) { + } else { if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { return 2; } From patchwork Thu Jun 9 09:05:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580261 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp623655max; Thu, 9 Jun 2022 03:03:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzgU8UZ+2TYaooyh8nLUbTw+CFnnSweA9AsXCife9p3clPWFZ0GJh0OgiGBbsHNMSGI/qVh X-Received: by 2002:ac8:7c56:0:b0:2fb:8075:4755 with SMTP id o22-20020ac87c56000000b002fb80754755mr30668797qtv.403.1654768991169; Thu, 09 Jun 2022 03:03:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654768991; cv=none; d=google.com; s=arc-20160816; b=z9qCIKNpFDuHhXysZUFY/8alzj4n3RCJhQ9mJ2Sp4do/a3QinI6Y5i6qFX2tkA6OAR MSur8+PKMq2BJTy7Fed9u3zyoV1XZUB/XC2ToJSu4JTOzpa9yUHoQ7cgdtbu7vWqsDG3 6St8/3zanL9DZ8eFsKdsZqbsEuF7NE9ei2zZAfKzdkN8as31mvfd9eE24kwgbRv0m0Uz HAItj13RzAHWw8kp7pMTSTcAq+T1hu/YfhoNfCmMVT1f8oz5UDtMWguSZLpqFee1ddYk Njj9ClhD3EZcaOQsXZTBU0dcNVVsjFKj4YDZEy0lwS4T2T3N/sEJG3d1spHgOKUboTh2 4usg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1m/UJxXLmktUI528IS17AqpDYaE8Ds5euhmbpvoO2wI=; b=xVLcR1ve1dYrITZFYkVSzcuaiaPPGQERSLln41Ff5zrKasQ9cyFn0ZQSXCVLN+tARs MzQaGfVu4I+VqViRYheCvBC4EW9tGlZ8QMpAPmw3VptCC8u2OFx2Q5KqndHQnAtBuvc0 IRlUpd6j3kV8IPnz3tbCyNkM1R12hdavoZYi2FYcljLDRY0UPRgoDKtyIIZPbgYM/uTk 7+ChEghGoe9tqkR34WTWOck4mC9kw/Ub6X6kZTosWik6ZdJfk2zv2HP+70n8T2au1IM5 w0TjcEo4EshMimaBk5FoAvn3oiNV8jAspaY5Q+rK9wAOHZna5VKvq2ZJyJUeRwKV5p+A UV3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xQFAqMwd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r3-20020a05622a034300b00304fe11548csi3475109qtw.408.2022.06.09.03.03.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:03:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xQFAqMwd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49726 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzF0O-0006zI-UZ for patch@linaro.org; Thu, 09 Jun 2022 06:03:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39912) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7Z-0001e8-IM for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:29 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:55140) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7Y-000687-4S for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:29 -0400 Received: by mail-wm1-x329.google.com with SMTP id n185so12106857wmn.4 for ; Thu, 09 Jun 2022 02:06:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1m/UJxXLmktUI528IS17AqpDYaE8Ds5euhmbpvoO2wI=; b=xQFAqMwdkDeVs1JZLigxCqno2jD16chXRNKDQigIDXF6X461NKYq5Z3DGy25jEnNKt y0t4LtaR0+VtOLKAMfdT0QPfDou1vzp4opggtlMi0Pe0o4BUTmdlR5eYd1ojm4m+6zs+ DCGbilr2gd6Izkawl4sMdM29qU4XNsk8QMcsOXoAPc4NG3ZzYeSsE/T5Rxs/5dOUMe1k Pz9OYnZPwfeyQuTf+f7QWLZ013YcQBjqrkxrcAh+ORTh+vefQhY36CRwu0n43oQZyn9+ H1QgW4NYqjKeX4i5Hcez4LKTqpMn8pvVeDU8ZwvWEv3ib+0O50H3Ouq0KnUwcTzGExeu UqvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1m/UJxXLmktUI528IS17AqpDYaE8Ds5euhmbpvoO2wI=; b=Skq3+rg9Y4KK9UTG/7hyFzZZYlEvBW/J/fFw5bYVa+HTy0ZvOLzIzXBcB0EWs/jDaE qvJcFY9IEoBwmy82AlYNeFswRzDW/FNCAAEhk+t8cVYFUSlAlLENf8jlbKl4ZCZ5PWDg 1hRIo6DusI/PKE9ClOZS51tM2T7iwZi11Xhg4jg7ukSKkvXI874+eQfjAslnfWVS71+e cQQw+t/f6kfanjl4Gj+FJZ77dtFujJR46KHvVmjYsvxZ1bwnO/kaBDL7g+Iif8UgqfK1 W+vG9sDFEwzGjJM1g+VlvXqjQ7+7W5J5CjNOL6kKMP6ZiXv8wfuZ2PwRYCNmo3aNLw+V zZOA== X-Gm-Message-State: AOAM532K/scpHb2RTS7fX/fRstYlP93XfRD5l3+PjxW/kOjszAOzf/3e lRHRDNZ46GodP2hkdHP2zi/VRfnTv9QtXA== X-Received: by 2002:a1c:19c4:0:b0:397:88a6:6 with SMTP id 187-20020a1c19c4000000b0039788a60006mr2265383wmz.138.1654765586789; Thu, 09 Jun 2022 02:06:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 44/55] target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset Date: Thu, 9 Jun 2022 10:05:26 +0100 Message-Id: <20220609090537.1971756-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We don't need to constrain the value set in zcr_el[1], because it will be done by sve_zcr_len_for_el. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d2bd74c2ed4..06219441674 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -208,8 +208,7 @@ static void arm_cpu_reset(DeviceState *dev) CPACR_EL1, ZEN, 3); /* with reasonable vector length */ if (cpu_isar_feature(aa64_sve, cpu)) { - env->vfp.zcr_el[1] = - aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); + env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; } /* * Enable 48-bit address space (TODO: take reserved_va into account). From patchwork Thu Jun 9 09:05:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580265 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp630988max; Thu, 9 Jun 2022 03:12:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx8PrRRfS3rtFVj3HB3BBsVRdGEh1xdr9S2WCCWQ0HzV1qWNSCS5u3zsAd+Re4bvJXvsG4B X-Received: by 2002:a05:622a:201:b0:2f9:3dbf:669c with SMTP id b1-20020a05622a020100b002f93dbf669cmr31838703qtx.3.1654769561822; Thu, 09 Jun 2022 03:12:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654769561; cv=none; d=google.com; s=arc-20160816; b=Hitfx5YX/ggdShEhv5lvavqZ0go61sBgdhd6rcEePlBe1XYfo1JkPItuiaeHBqkJzn WNJ2EPSXD0W3BonZmfmDIFe5N2l5wE7Lq1l030oAMpkaCnCej6ygJuh01EjHpNFyQeH6 5xvtwdEAjVPgfsS2mu/y1qaTRJZhU9yrcL2wAE/l49NEugx5jNIkkq6uptjL1AzP4RKq IwxaYjEY44DF3xu8Gfraqz8W71oJVk+lRkUzHDgv1h24ltJa5F+1jS6GcRrAKjKc7mY3 HOAEUylVtESm2W2EX8X3kBdia68xXQuZlj2w0EjqAlSKMNjIxd7mCXYkfR52nO8K+lx3 aydA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PRXhDDaF6nWlyfN7Oj+HymEa8eenhGrZqsYAZ8IODjs=; b=caXS6Nqt91jS+Uo7LAKWnPGSBIfhXQXpxVH1xHbqdi+dxmRjrrDQvX1S9rDva1bYfD ddSKqQ2Tk3KZgN8k3+49NK1VDlPumlBkAG96N6aXTppJ82cgAt78bqezJGtYK0W2VSSh doqtvdN7wehC8SbnxTRdI04rlgZ+oKgfJ1YPDIhaLHQfxMOshGn4vo8h+e4SU0lVAuGV mAWc2mCvr82/3774mEAU1RCAVepAxxytZMNNS4glXTJ+e1yD1QShJhpJrMBmmjP/j4yt D9zalyXv+b56oltOmKz7BVXYoxkvcvY7ZuD3YWmCVdy1Y2lVCV6vtQbQSSicdVTf28Bj IVTQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="fffEUXh/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 128-20020a370686000000b006a6f997f186si2487488qkg.392.2022.06.09.03.12.41 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:12:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="fffEUXh/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzF9d-0005ee-9j for patch@linaro.org; Thu, 09 Jun 2022 06:12:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7a-0001fC-OE for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:31 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:44678) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7Z-00068P-4T for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:30 -0400 Received: by mail-wm1-x334.google.com with SMTP id m32-20020a05600c3b2000b0039756bb41f2so12273407wms.3 for ; Thu, 09 Jun 2022 02:06:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PRXhDDaF6nWlyfN7Oj+HymEa8eenhGrZqsYAZ8IODjs=; b=fffEUXh/hJhdqrF8+T1jEgSi9J+q5yChQeC/OqTRpmM4N8M+grQe6+yIRPW70ArkSK IwEK336e8n8lRdpWpByvEnqZtY6N982J0rfuF0nmJiQ3OxRN2wwsa4B0X0pEGzBeJ8rr P/jy62ELv96VdWew9N8HeT9zy/RtHx6I8Z93DAa31xigxUts1CpAyCLeJcUk0nLbMKp2 yvnVWxEryN534kZDNgz4tHkZE6UTBT21fOM5QfLWeyiQOndzbXW757doMbiPLO79J+eK sbmHYv51GWjoaUs7JMOBo2GkADQuJlh2HzaCNGVA/mVOYGwWRy29ug9ZsfyZHyUi0orE 5/0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PRXhDDaF6nWlyfN7Oj+HymEa8eenhGrZqsYAZ8IODjs=; b=m/Gjxvi0Zl18af9NTiyBipL/haC/NN2q83j+VP1M/9hhmHREFZtriYQXPH47ussaXT 7Q0evKiI6VOG+ytRkTMu9Ssv1euVOydLizCqzaB4+VPgzZR8GpsdJfVpGM9Xexk4z13t tSLaf3QEnu+BZiVI6P2Vsk7nbuq/5PXIFLCLdNB2lq2XVDoZZitPlVIhO+LWJfjXY9ZQ vLZXmJkfKB5YmSoz9YEkGOD1uQ46p+3uTpx5d/w0vJvY3W2ZdsI0gKyLW5TuAEdN9+VY F4wqJMIJ+MgjnrSc4SgO8ulXL4Jwh1L/pgQ+QHR+d6Mf52NBzL0bopQzy/ZRIo+XdDxQ cOSA== X-Gm-Message-State: AOAM5328pEs5wIYPZcCzhPFw3hWI6ivJi13Fhj9uBUokEETUenE7j4br fqp3H8FVmy2hF+fG+mT6vhIh+hPwvjt/ng== X-Received: by 2002:a7b:ce8c:0:b0:39c:5bf4:abc0 with SMTP id q12-20020a7bce8c000000b0039c5bf4abc0mr2225808wmj.135.1654765587745; Thu, 09 Jun 2022 02:06:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 45/55] target/arm: Merge aarch64_sve_zcr_get_valid_len into caller Date: Thu, 9 Jun 2022 10:05:27 +0100 Message-Id: <20220609090537.1971756-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This function is used only once, and will need modification for Streaming SVE mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 11 ----------- target/arm/helper.c | 30 +++++++++++------------------- 2 files changed, 11 insertions(+), 30 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index ceaddcbfd6e..79eb4637538 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -189,17 +189,6 @@ void arm_translate_init(void); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ -/** - * aarch64_sve_zcr_get_valid_len: - * @cpu: cpu context - * @start_len: maximum len to consider - * - * Return the maximum supported sve vector length <= @start_len. - * Note that both @start_len and the return value are in units - * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128. - */ -uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len); - enum arm_fprounding { FPROUNDING_TIEEVEN, FPROUNDING_POSINF, diff --git a/target/arm/helper.c b/target/arm/helper.c index 61e8026d0e3..de159c644cd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6212,39 +6212,31 @@ int sve_exception_el(CPUARMState *env, int el) return 0; } -uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) -{ - uint32_t end_len; - - start_len = MIN(start_len, ARM_MAX_VQ - 1); - end_len = start_len; - - if (!test_bit(start_len, cpu->sve_vq_map)) { - end_len = find_last_bit(cpu->sve_vq_map, start_len); - assert(end_len < start_len); - } - return end_len; -} - /* * Given that SVE is enabled, return the vector length for EL. */ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) { ARMCPU *cpu = env_archcpu(env); - uint32_t zcr_len = cpu->sve_max_vq - 1; + uint32_t len = cpu->sve_max_vq - 1; + uint32_t end_len; if (el <= 1 && !el_is_in_host(env, el)) { - zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); + len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[1]); } if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { - zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); + len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[2]); } if (arm_feature(env, ARM_FEATURE_EL3)) { - zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); + len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } - return aarch64_sve_zcr_get_valid_len(cpu, zcr_len); + end_len = len; + if (!test_bit(len, cpu->sve_vq_map)) { + end_len = find_last_bit(cpu->sve_vq_map, len); + assert(end_len < len); + } + return end_len; } static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, From patchwork Thu Jun 9 09:05:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580271 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp644175max; Thu, 9 Jun 2022 03:32:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwGh3OPtY0XrHGySAZCWe0BlGZ6MrqwslSF+S5SbZhnbPRR/2AOh5VY0maLVwk1yqWXv79K X-Received: by 2002:ac8:7f52:0:b0:305:8c5:2f5d with SMTP id g18-20020ac87f52000000b0030508c52f5dmr4387310qtk.577.1654770751287; Thu, 09 Jun 2022 03:32:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654770751; cv=none; d=google.com; s=arc-20160816; b=xGeuUCTE3ey9Su430pXvV55f89RaXO0tgf+RAJXf4aYG2LfvKfUfZCRdf9QMTSw0+2 4ZvHTdGXmQJBegqqBdVd73DwSxnsjDSkc+0Aano0xJTp5UXj5XDGL0+gEhGW2qCpDpwa Px0+JHUm4C9IHJ2lWE0o03Me4QmVGcykL7ekWRlO70CL0ntz6ZVUEV/T6VR1UalF7KoF CrMUFSry/PO1pSnY8jjmzBL2LoW38vhkL2fDd7T6Upe6+swPj2ko5OW5dHt3YmRBzf92 XxljL4Q7fQH37ezxFo7h4ju9hzm6pRNMzE43g+EWVV4BrrQWvW3aABDszRzGy3uwm/Mu ouZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RzISLAIsm/HQUCbU5drdl/7AuVQMoSI54OKREy/L1no=; b=UCI/ixwM/2Y5DRW3YB3Q2O5zN2MCTR44yH7QQlKNScZ1C2iSUElVXaaZgh3Pnr7EuW sIrGwYD+zw0IyneKk72kLYu6xvBuMgb3gxxzzk+KimGOMIl99l94Itd78v6a/9c0aPaM TfWJV46ruvP66ZMArA3y5HuIpb0c+ni1kq9kHSuJK2hiBtPQaaSyH4xhpuRknQZ0nN5T D5qPHnjX3WVrM7f2iUw6Vx6PiqpCOK2sDGkqSLCQ1uy2cS0Mw/kw/GFxORdHdqrBg2X1 qScVU6A53Oo8YP6ckSZ0K2+f9jbsN0ZcAWb2dmgHKRDbVxuT5GQr7lUxsuCiGti6VYDG U3aA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pdT8R7UO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d6-20020a05622a05c600b00300c8625c9asi12873374qtb.238.2022.06.09.03.32.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:32:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pdT8R7UO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43426 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFSo-0007C6-Pq for patch@linaro.org; Thu, 09 Jun 2022 06:32:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39980) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7d-0001hH-UD for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:34 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:51017) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7a-00068f-K9 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:32 -0400 Received: by mail-wm1-x32c.google.com with SMTP id e5so5272909wma.0 for ; Thu, 09 Jun 2022 02:06:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=RzISLAIsm/HQUCbU5drdl/7AuVQMoSI54OKREy/L1no=; b=pdT8R7UOBjH98ntFTJOA7FaJDD6BEFL5G79O1tegmwEz6IqpA2E4Oiiry7DFGrsTwA QH8dPxU6xbWjiG6+HZUsTqUr7xGMjng9pUbU+VHramWqxsD+S6rsLBOTkVNGiVLCPNCJ kg/Us/yjM7z5zBNyVLk+9fmqllesCGQdCKytrFeh5rMFZhAHi4fevbAE+ygjAOlXmarU xE2wI+lfTnUcVZ2rkJRE6kuP3QvAPPBhGC6tJpKWLOd6Jv1Af/gJVFjHt5sNMPfY80tr ma8kyagHy6kAh9mprQ0k4oWW3JQyJtx0FVZQ2Y57hCgjreB7CRpTr8fmYD0i/6k7A0Qm TIQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RzISLAIsm/HQUCbU5drdl/7AuVQMoSI54OKREy/L1no=; b=W13HTntDtOrrFRpKWGX/NOm9eGA5oWrRkclJ3ScCu6DM+RWBrQB8lUj3OYorodrsEC Jr6ADiEgBklqzd38ZYze/jTlJlLGSqdNAmUPKixRUZIP4tzvk8AX2DdRAQHgQGteUvLM Dg+J4HD9iUPtrnpz3M9dm1VTqsz6Wkd2pGkt7hOFtwWuW9MMdqLeOTME0Tnnb24DtEHt Clg2du58sjc4Dm9BJAjeMPGoOiFiE6Wa86hZnFUNwi84wZoBbnmQKsqfVrIA9qzyKH80 /VWHBZ+OmPkKh+nGMRP0MfZcmpWDuqpRuu3h4t3cx/+JSV3Z9auqXlKOdiduUT/rdGud +5Uw== X-Gm-Message-State: AOAM532LKONF2qITHCZZHlJOExbR1frzRjBCo0bgVzCu8HEZLxbayeez qLvfO7XlsBT5aBsZNkYa1rVlB3//NnZMgg== X-Received: by 2002:a1c:4682:0:b0:39c:4459:6a84 with SMTP id t124-20020a1c4682000000b0039c44596a84mr2213102wma.167.1654765589048; Thu, 09 Jun 2022 02:06:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 46/55] target/arm: Use uint32_t instead of bitmap for sve vq's Date: Thu, 9 Jun 2022 10:05:28 +0100 Message-Id: <20220609090537.1971756-47-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The bitmap need only hold 15 bits; bitmap is over-complicated. We can simplify operations quite a bit with plain logical ops. The introduction of SVE_VQ_POW2_MAP eliminates the need for looping in order to search for powers of two. Simply perform the logical ops and use count leading or trailing zeros as required to find the result. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 6 +-- target/arm/internals.h | 5 ++ target/arm/kvm_arm.h | 7 ++- target/arm/cpu64.c | 117 ++++++++++++++++++++--------------------- target/arm/helper.c | 9 +--- target/arm/kvm64.c | 36 +++---------- 6 files changed, 75 insertions(+), 105 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f5af88b686d..73f24a57603 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1041,9 +1041,9 @@ struct ArchCPU { * Bits set in sve_vq_supported represent valid vector lengths for * the CPU type. */ - DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); - DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); - DECLARE_BITMAP(sve_vq_supported, ARM_MAX_VQ); + uint32_t sve_vq_map; + uint32_t sve_vq_init; + uint32_t sve_vq_supported; /* Generic timer counter frequency, in Hz */ uint64_t gt_cntfrq_hz; diff --git a/target/arm/internals.h b/target/arm/internals.h index 79eb4637538..a1bae4588ae 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1340,4 +1340,9 @@ bool el_is_in_host(CPUARMState *env, int el); void aa32_max_features(ARMCPU *cpu); +/* Powers of 2 for sve_vq_map et al. */ +#define SVE_VQ_POW2_MAP \ + ((1 << (1 - 1)) | (1 << (2 - 1)) | \ + (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1))) + #endif diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index b7f78b52154..99017b635ce 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -239,13 +239,12 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf); /** * kvm_arm_sve_get_vls: * @cs: CPUState - * @map: bitmap to fill in * * Get all the SVE vector lengths supported by the KVM host, setting * the bits corresponding to their length in quadwords minus one - * (vq - 1) in @map up to ARM_MAX_VQ. + * (vq - 1) up to ARM_MAX_VQ. Return the resulting map. */ -void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map); +uint32_t kvm_arm_sve_get_vls(CPUState *cs); /** * kvm_arm_set_cpu_features_from_host: @@ -439,7 +438,7 @@ static inline void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) g_assert_not_reached(); } -static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) +static inline uint32_t kvm_arm_sve_get_vls(CPUState *cs) { g_assert_not_reached(); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index cce68dd82a2..15665c962b2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -355,8 +355,11 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * any of the above. Finally, if SVE is not disabled, then at least one * vector length must be enabled. */ - DECLARE_BITMAP(tmp, ARM_MAX_VQ); - uint32_t vq, max_vq = 0; + uint32_t vq_map = cpu->sve_vq_map; + uint32_t vq_init = cpu->sve_vq_init; + uint32_t vq_supported; + uint32_t vq_mask = 0; + uint32_t tmp, vq, max_vq = 0; /* * CPU models specify a set of supported vector lengths which are @@ -364,10 +367,16 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * in the supported bitmap results in an error. When KVM is enabled we * fetch the supported bitmap from the host. */ - if (kvm_enabled() && kvm_arm_sve_supported()) { - kvm_arm_sve_get_vls(CPU(cpu), cpu->sve_vq_supported); - } else if (kvm_enabled()) { - assert(!cpu_isar_feature(aa64_sve, cpu)); + if (kvm_enabled()) { + if (kvm_arm_sve_supported()) { + cpu->sve_vq_supported = kvm_arm_sve_get_vls(CPU(cpu)); + vq_supported = cpu->sve_vq_supported; + } else { + assert(!cpu_isar_feature(aa64_sve, cpu)); + vq_supported = 0; + } + } else { + vq_supported = cpu->sve_vq_supported; } /* @@ -375,8 +384,9 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * From the properties, sve_vq_map implies sve_vq_init. * Check first for any sve enabled. */ - if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) { - max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1; + if (vq_map != 0) { + max_vq = 32 - clz32(vq_map); + vq_mask = MAKE_64BIT_MASK(0, max_vq); if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { error_setg(errp, "cannot enable sve%d", max_vq * 128); @@ -392,15 +402,10 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * For KVM we have to automatically enable all supported unitialized * lengths, even when the smaller lengths are not all powers-of-two. */ - bitmap_andnot(tmp, cpu->sve_vq_supported, cpu->sve_vq_init, max_vq); - bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); + vq_map |= vq_supported & ~vq_init & vq_mask; } else { /* Propagate enabled bits down through required powers-of-two. */ - for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { - if (!test_bit(vq - 1, cpu->sve_vq_init)) { - set_bit(vq - 1, cpu->sve_vq_map); - } - } + vq_map |= SVE_VQ_POW2_MAP & ~vq_init & vq_mask; } } else if (cpu->sve_max_vq == 0) { /* @@ -413,25 +418,18 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) if (kvm_enabled()) { /* Disabling a supported length disables all larger lengths. */ - for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { - if (test_bit(vq - 1, cpu->sve_vq_init) && - test_bit(vq - 1, cpu->sve_vq_supported)) { - break; - } - } + tmp = vq_init & vq_supported; } else { /* Disabling a power-of-two disables all larger lengths. */ - for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) { - if (test_bit(vq - 1, cpu->sve_vq_init)) { - break; - } - } + tmp = vq_init & SVE_VQ_POW2_MAP; } + vq = ctz32(tmp) + 1; max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; - bitmap_andnot(cpu->sve_vq_map, cpu->sve_vq_supported, - cpu->sve_vq_init, max_vq); - if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) { + vq_mask = MAKE_64BIT_MASK(0, max_vq); + vq_map = vq_supported & ~vq_init & vq_mask; + + if (max_vq == 0 || vq_map == 0) { error_setg(errp, "cannot disable sve%d", vq * 128); error_append_hint(errp, "Disabling sve%d results in all " "vector lengths being disabled.\n", @@ -441,7 +439,8 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) return; } - max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1; + max_vq = 32 - clz32(vq_map); + vq_mask = MAKE_64BIT_MASK(0, max_vq); } /* @@ -451,9 +450,9 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) */ if (cpu->sve_max_vq != 0) { max_vq = cpu->sve_max_vq; + vq_mask = MAKE_64BIT_MASK(0, max_vq); - if (!test_bit(max_vq - 1, cpu->sve_vq_map) && - test_bit(max_vq - 1, cpu->sve_vq_init)) { + if (vq_init & ~vq_map & (1 << (max_vq - 1))) { error_setg(errp, "cannot disable sve%d", max_vq * 128); error_append_hint(errp, "The maximum vector length must be " "enabled, sve-max-vq=%d (%d bits)\n", @@ -462,8 +461,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) } /* Set all bits not explicitly set within sve-max-vq. */ - bitmap_complement(tmp, cpu->sve_vq_init, max_vq); - bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); + vq_map |= ~vq_init & vq_mask; } /* @@ -472,13 +470,14 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * are clear, just in case anybody looks. */ assert(max_vq != 0); - bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq); + assert(vq_mask != 0); + vq_map &= vq_mask; /* Ensure the set of lengths matches what is supported. */ - bitmap_xor(tmp, cpu->sve_vq_map, cpu->sve_vq_supported, max_vq); - if (!bitmap_empty(tmp, max_vq)) { - vq = find_last_bit(tmp, max_vq) + 1; - if (test_bit(vq - 1, cpu->sve_vq_map)) { + tmp = vq_map ^ (vq_supported & vq_mask); + if (tmp) { + vq = 32 - clz32(tmp); + if (vq_map & (1 << (vq - 1))) { if (cpu->sve_max_vq) { error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq); error_append_hint(errp, "This CPU does not support " @@ -502,15 +501,15 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) return; } else { /* Ensure all required powers-of-two are enabled. */ - for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { - if (!test_bit(vq - 1, cpu->sve_vq_map)) { - error_setg(errp, "cannot disable sve%d", vq * 128); - error_append_hint(errp, "sve%d is required as it " - "is a power-of-two length smaller " - "than the maximum, sve%d\n", - vq * 128, max_vq * 128); - return; - } + tmp = SVE_VQ_POW2_MAP & vq_mask & ~vq_map; + if (tmp) { + vq = 32 - clz32(tmp); + error_setg(errp, "cannot disable sve%d", vq * 128); + error_append_hint(errp, "sve%d is required as it " + "is a power-of-two length smaller " + "than the maximum, sve%d\n", + vq * 128, max_vq * 128); + return; } } } @@ -530,6 +529,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) /* From now on sve_max_vq is the actual maximum supported length. */ cpu->sve_max_vq = max_vq; + cpu->sve_vq_map = vq_map; } static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, @@ -590,7 +590,7 @@ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, if (!cpu_isar_feature(aa64_sve, cpu)) { value = false; } else { - value = test_bit(vq - 1, cpu->sve_vq_map); + value = extract32(cpu->sve_vq_map, vq - 1, 1); } visit_type_bool(v, name, &value, errp); } @@ -612,12 +612,8 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, return; } - if (value) { - set_bit(vq - 1, cpu->sve_vq_map); - } else { - clear_bit(vq - 1, cpu->sve_vq_map); - } - set_bit(vq - 1, cpu->sve_vq_init); + cpu->sve_vq_map = deposit32(cpu->sve_vq_map, vq - 1, 1, value); + cpu->sve_vq_init |= 1 << (vq - 1); } static bool cpu_arm_get_sve(Object *obj, Error **errp) @@ -979,7 +975,7 @@ static void aarch64_max_initfn(Object *obj) cpu->dcz_blocksize = 7; /* 512 bytes */ #endif - bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ); + cpu->sve_vq_supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); aarch64_add_pauth_properties(obj); aarch64_add_sve_properties(obj); @@ -1026,12 +1022,11 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->gic_vprebits = 5; cpu->gic_pribits = 5; - /* Suppport of A64FX's vector length are 128,256 and 512bit only */ + /* The A64FX supports only 128, 256 and 512 bit vector lengths */ aarch64_add_sve_properties(obj); - bitmap_zero(cpu->sve_vq_supported, ARM_MAX_VQ); - set_bit(0, cpu->sve_vq_supported); /* 128bit */ - set_bit(1, cpu->sve_vq_supported); /* 256bit */ - set_bit(3, cpu->sve_vq_supported); /* 512bit */ + cpu->sve_vq_supported = (1 << 0) /* 128bit */ + | (1 << 1) /* 256bit */ + | (1 << 3); /* 512bit */ cpu->isar.reset_pmcr_el0 = 0x46014040; diff --git a/target/arm/helper.c b/target/arm/helper.c index de159c644cd..90aac6bc12d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6219,7 +6219,6 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) { ARMCPU *cpu = env_archcpu(env); uint32_t len = cpu->sve_max_vq - 1; - uint32_t end_len; if (el <= 1 && !el_is_in_host(env, el)) { len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[1]); @@ -6231,12 +6230,8 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } - end_len = len; - if (!test_bit(len, cpu->sve_vq_map)) { - end_len = find_last_bit(cpu->sve_vq_map, len); - assert(end_len < len); - } - return end_len; + len = 31 - clz32(cpu->sve_vq_map & MAKE_64BIT_MASK(0, len + 1)); + return len; } static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 363032da903..b3f635fc952 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -760,15 +760,13 @@ bool kvm_arm_steal_time_supported(void) QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); -void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) +uint32_t kvm_arm_sve_get_vls(CPUState *cs) { /* Only call this function if kvm_arm_sve_supported() returns true. */ static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; static bool probed; uint32_t vq = 0; - int i, j; - - bitmap_zero(map, ARM_MAX_VQ); + int i; /* * KVM ensures all host CPUs support the same set of vector lengths. @@ -809,46 +807,24 @@ void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) if (vq > ARM_MAX_VQ) { warn_report("KVM supports vector lengths larger than " "QEMU can enable"); + vls[0] &= MAKE_64BIT_MASK(0, ARM_MAX_VQ); } } - for (i = 0; i < KVM_ARM64_SVE_VLS_WORDS; ++i) { - if (!vls[i]) { - continue; - } - for (j = 1; j <= 64; ++j) { - vq = j + i * 64; - if (vq > ARM_MAX_VQ) { - return; - } - if (vls[i] & (1UL << (j - 1))) { - set_bit(vq - 1, map); - } - } - } + return vls[0]; } static int kvm_arm_sve_set_vls(CPUState *cs) { - uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = {0}; + ARMCPU *cpu = ARM_CPU(cs); + uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq_map }; struct kvm_one_reg reg = { .id = KVM_REG_ARM64_SVE_VLS, .addr = (uint64_t)&vls[0], }; - ARMCPU *cpu = ARM_CPU(cs); - uint32_t vq; - int i, j; assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX); - for (vq = 1; vq <= cpu->sve_max_vq; ++vq) { - if (test_bit(vq - 1, cpu->sve_vq_map)) { - i = (vq - 1) / 64; - j = (vq - 1) % 64; - vls[i] |= 1UL << j; - } - } - return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); } From patchwork Thu Jun 9 09:05:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580275 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp649915max; Thu, 9 Jun 2022 03:41:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzRhVy3T5PDaOC0S0JFrsbhs68q8CQh0gxCx4poYAFl7LoALCD9xtxPWc3cDKKNYnz3cbbH X-Received: by 2002:ac8:5a8b:0:b0:304:ef1f:b725 with SMTP id c11-20020ac85a8b000000b00304ef1fb725mr14795861qtc.57.1654771261885; Thu, 09 Jun 2022 03:41:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654771261; cv=none; d=google.com; s=arc-20160816; b=AHrtq3gwEDT4WliNwsOc0p9wlZQRwPufnOQ/2ym/si86Wc97Qur42PrBoAEaFHvhcZ jFt+Rx6eoIyABrKDdW5SGpU4ypi6zU+02uE4AxG5rIYNPapzZJJbTsrSASli7B0jiSRz p1pt3MnSac+YGvyQo7cahE30joiaYkXN3q3Fkq6BS/enxxam9L8s74eUBlrm6gdEFQOV RzhzJSuHw4hIxaD8NTShdI6LPhMMngh9rYoH6qAqlRwpZGaTHbdto07DK0X4Zzh/GCAP 72Y3qCu38N88odneSBXkx+A/wtH5zZRvor1+PYozp8NobLWX4rI/43RTVLRqMzDlAwyo dGHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ln4NarpB9GXHE3SSoQy0ZUBfyqzyJv95N2jOXflbDEs=; b=P7U8lbgiFlyHvnhnsEVgb8irFGEWHVFREADXB77pTEyP+FVqWgAlc9NvDTP6Ihxd9z 7PJ3WAfs6KnWUTSVXd80iPW9LV9z4SRUQR6a/RBakku3N57FY5kYth0AQWszFcG9UaFn w5A9Ou9m/6PvT6BKAh8qGxnDfDumttOC+9PNOZNuk0JoXmR7rcjFl8044c2bAqpWzT+V YVilsmQCjQ5R97pjkJzty3OcWx6b21TaOSC5FX+0fklhHWrHOJKX/x5/+l8IxSuZ84Ed fz9gjeSxJlDnItxm/DDOvgo6sHCSEHoj9sYr8guRGVq56dYpPIsyY9vI/mRl7IL3+tud wBDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EWhynYWP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k2-20020a05620a142200b006a6af3fb622si7239752qkj.416.2022.06.09.03.41.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:41:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EWhynYWP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52298 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFb3-0005hJ-AM for patch@linaro.org; Thu, 09 Jun 2022 06:41:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39960) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7d-0001gU-SN for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:34 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:47100) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7b-00061B-0P for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:32 -0400 Received: by mail-wm1-x32e.google.com with SMTP id r123-20020a1c2b81000000b0039c1439c33cso12264463wmr.5 for ; Thu, 09 Jun 2022 02:06:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ln4NarpB9GXHE3SSoQy0ZUBfyqzyJv95N2jOXflbDEs=; b=EWhynYWPJGb3hPXk6/XiW86PShAFbDRSonRdil7h/KJulzf3n5xajMNv53PEghwhkt dRdoIRJ3sguC+yM90+usvvuEVq5U+DTx2ocWe1d40gye0vruVZjEcQ0R9Z1jfaKo/ib5 KWokqu8v4tm0mjmz9ag+9xtqn3zXncCU68EuqDX4RfmseW5QXeh76HswJCQSB/PQCWXQ VjmGThLOM27jEaYTs6fHqXxUPgkjMp1e559531OqscmuHMdtc2qts5JIaydoogrTKLUY 4e31FtyZzgw3swherBq0jjOVJzDp8LzUs1ntwlmiUYesaXihwM88PZhG89NE00Y5wdRI lPnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ln4NarpB9GXHE3SSoQy0ZUBfyqzyJv95N2jOXflbDEs=; b=Zeb3ERLV9o2CH3wPOry2sn5UXTv+WSJhWjTiC0ivXe2DPr5ERUpxdQhjW8eq/nxmu3 IGU+ZdoSLFXAchdp/LCiTiuBfZlor/0h9l2Ia5c2dnQvVnl+uhyT6TVIMDx+gCzu8/+n Rxxzl2SBojWxxp9o9u8yI9olYXOETMRCq44RAx/ID0O+reoy+wQKUScbjkQXPC4bBQSQ h9FHRKwLhpbeuBcjBu0ufUxrjvZMwKBx3ptHyhm0mRX+9226Cq8Eros95I/MPoBAXIAG Ob5+Trs2vK46WoBvMS+iQATOmW8sPHjBIvRoRUz/m1W2/fyQoUHJncUuBVkjEMl7J6XR FDkw== X-Gm-Message-State: AOAM531HZcXhUim1h/8BV7MqUPkg4LfT3XAKz0YmN1Eq3eZd8HUhCtcj K1Ms4lvuvp2KYapw1YHFZxJm/f0jZOQYBg== X-Received: by 2002:a05:600c:4fd2:b0:39b:893e:ff79 with SMTP id o18-20020a05600c4fd200b0039b893eff79mr2295531wmq.73.1654765590191; Thu, 09 Jun 2022 02:06:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 47/55] target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el Date: Thu, 9 Jun 2022 10:05:29 +0100 Message-Id: <20220609090537.1971756-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This will be used for both Normal and Streaming SVE, and the value does not necessarily come from ZCR_ELx. While we're at it, emphasize the units in which the value is returned. Patch produced by git grep -l sve_zcr_len_for_el | \ xargs -n1 sed -i 's/sve_zcr_len_for_el/sve_vqm1_for_el/g' and then adding a function comment. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 11 ++++++++++- target/arm/arch_dump.c | 2 +- target/arm/cpu.c | 2 +- target/arm/gdbstub64.c | 2 +- target/arm/helper.c | 12 ++++++------ 5 files changed, 19 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 73f24a57603..e45b5cb7fe1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1132,7 +1132,16 @@ void aarch64_sync_64_to_32(CPUARMState *env); int fp_exception_el(CPUARMState *env, int cur_el); int sve_exception_el(CPUARMState *env, int cur_el); -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); + +/** + * sve_vqm1_for_el: + * @env: CPUARMState + * @el: exception level + * + * Compute the current SVE vector length for @el, in units of + * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. + */ +uint32_t sve_vqm1_for_el(CPUARMState *env, int el); static inline bool is_a64(CPUARMState *env) { diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 01848453109..b1f040e69f2 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -166,7 +166,7 @@ static off_t sve_fpcr_offset(uint32_t vq) static uint32_t sve_current_vq(CPUARMState *env) { - return sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + return sve_vqm1_for_el(env, arm_current_el(env)) + 1; } static size_t sve_size_vq(uint32_t vq) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 06219441674..1b5d5357880 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -925,7 +925,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) vfp_get_fpcr(env), vfp_get_fpsr(env)); if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { - int j, zcr_len = sve_zcr_len_for_el(env, el); + int j, zcr_len = sve_vqm1_for_el(env, el); for (i = 0; i <= FFR_PRED_NUM; i++) { bool eol; diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 596878666d7..07a6746944d 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -152,7 +152,7 @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) * We report in Vector Granules (VG) which is 64bit in a Z reg * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. */ - int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + int vq = sve_vqm1_for_el(env, arm_current_el(env)) + 1; return gdb_get_reg64(buf, vq * 2); } default: diff --git a/target/arm/helper.c b/target/arm/helper.c index 90aac6bc12d..400f7cd1dba 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6215,7 +6215,7 @@ int sve_exception_el(CPUARMState *env, int el) /* * Given that SVE is enabled, return the vector length for EL. */ -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) +uint32_t sve_vqm1_for_el(CPUARMState *env, int el) { ARMCPU *cpu = env_archcpu(env); uint32_t len = cpu->sve_max_vq - 1; @@ -6238,7 +6238,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { int cur_el = arm_current_el(env); - int old_len = sve_zcr_len_for_el(env, cur_el); + int old_len = sve_vqm1_for_el(env, cur_el); int new_len; /* Bits other than [3:0] are RAZ/WI. */ @@ -6249,7 +6249,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, * Because we arrived here, we know both FP and SVE are enabled; * otherwise we would have trapped access to the ZCR_ELn register. */ - new_len = sve_zcr_len_for_el(env, cur_el); + new_len = sve_vqm1_for_el(env, cur_el); if (new_len < old_len) { aarch64_sve_narrow_vq(env, new_len + 1); } @@ -11168,7 +11168,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, sve_el = 0; } } else if (sve_el == 0) { - DP_TBFLAG_A64(flags, VL, sve_zcr_len_for_el(env, el)); + DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el)); } DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); } @@ -11534,10 +11534,10 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, */ old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; old_len = (old_a64 && !sve_exception_el(env, old_el) - ? sve_zcr_len_for_el(env, old_el) : 0); + ? sve_vqm1_for_el(env, old_el) : 0); new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; new_len = (new_a64 && !sve_exception_el(env, new_el) - ? sve_zcr_len_for_el(env, new_el) : 0); + ? sve_vqm1_for_el(env, new_el) : 0); /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { From patchwork Thu Jun 9 09:05:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580269 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp637106max; Thu, 9 Jun 2022 03:21:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyftvz1EglVE16HRmmhrUsZlieJ8DgQHhLa2lPAJIC9arhYii3/pJimC7B024QaFVvkefn+ X-Received: by 2002:a05:6214:32d:b0:467:da90:d8b6 with SMTP id j13-20020a056214032d00b00467da90d8b6mr25262138qvu.95.1654770093901; Thu, 09 Jun 2022 03:21:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654770093; cv=none; d=google.com; s=arc-20160816; b=dl9Nx+MXVYxflHn/zrirP/SLLm6p1Px7R7HBsJiFHDBwUKqUJB9v+IdInKkBk0q9lT 41zL4QO0ZNdSBngErkPZsrC6dhB4W7T6LSG5qA86Te6w0Q9OU8VBX86ZnScvNiBFhlTh S1gbfo78AkZ1UdiVVZTBWfkdGlt+gP5sH7Vrzk9oXCySNqrYfYegaQidbMpj3I7oZkVl BCVhkiMzBIWx1SQyewjMeyZIKUy8eR0RKUzdpH7VHUqdjP+cCA/Pky9FHTA4owY0cTtn 0ZxT37U5UmHCJ6pQvdzV9cZhNTNr0yHjVULQ2Y0O85Grwx0i79AKQD70YDKQwXuTxQD2 o4tA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Y6NKzjmohrdzTWz249bQwDudC0VH9aW6QTVdwHDMnIc=; b=nlNdG0Kmux2up+xPXI3TVOUksq2aboTksGt7ZM22CqtLi7ZCqcaraygRaPVDhyh/Xx Aq2UwyE3+a3XgXgGUzLpkqy5lsBq129oyOQYz0btPE60P/Li+dnPpPK/Gkk6qmAysbRg BW9BdQqyh58vx/I29Y8aBLdap3XHhGcagDPQ+Tu8jhTFXyGqrfIs4+VEfDTdPlVE+t33 pAnecfop7ETmSBOJnYhy4WivXOIUPe/BeT4uYW0uwPAriSof4Q+P+C/1NQglBWg2fujb 69teju+rH03zcxuME/QXMlPnpOF4RCI2jvZAqBySoHtl6WCxROw/391BhjJMZlKRDmPK /3+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R0faIh7x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d17-20020a05622a15d100b0030509130c55si1549142qty.219.2022.06.09.03.21.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:21:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R0faIh7x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38236 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFID-00034d-8R for patch@linaro.org; Thu, 09 Jun 2022 06:21:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7e-0001jh-W7 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:35 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:43563) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7c-00063C-2Z for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:34 -0400 Received: by mail-wr1-x433.google.com with SMTP id d14so22478436wra.10 for ; Thu, 09 Jun 2022 02:06:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Y6NKzjmohrdzTWz249bQwDudC0VH9aW6QTVdwHDMnIc=; b=R0faIh7xeFaIzB1VOYAgdfpPLOHHAYna+UOAAyvxW/w11AmltFCmelBXLEUA+IrHBj 4F+NiBeU9u4HxJ9X3owYxm1Srfc5DpSH+nbjlDUg1OyDzDTEoYefWgq6b4Lbx9WR+f1u hTLInLscWUUJku+wN7O1x3yeOwkMRO8QResv2grWibNziF7gzUf4f0+ZVQIehLPuXE1j 3+Sy7tTuJ67og+JTJvAFqx0Cu+/PGhyEReAh65BleCMYJ9wp9CocD5MygDMk2qip0WbV B4QKq1jaBEQdK/oHh0IE9gkPh38xAHssTwCr3omOEhILEBmaBYZS5qzSoPp8gQoQDQwG Mi1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y6NKzjmohrdzTWz249bQwDudC0VH9aW6QTVdwHDMnIc=; b=Tw0no7GwgvaB0raIsMj/HzxjbAPk/W4DGEcYSkBqHkyTSAFqIzjMU3V+mTdJI6ubDH vtyfukLmnGoVrureoNP3TOB5wpu+433u0tBJ50/yYLkuW/JGv+pHIGjmK/nHVElb8Z2s M4Z2/HvJ26AJMwZL5bfk2zuue9hOOyoyBYRSNm7an7tbzO91odO++ImljwoL5omhbiTg 8Qd4r+zb6GO7De3fQ4vWfVN7qT+qYyxYq21pSdonhnNdBXtnKyUvhL9aVJstgCzADpA6 /MRV6Mt0pdjCTYLYUt9IFmnu3fMtFiXbMvw90Mi5/1Ks+IP4l/gBHcVcJSDRnCPZcvTS twmA== X-Gm-Message-State: AOAM530Bc/mzsRECd3TGjuAhW1QlJxbDhZJsRZDnOQozAs56Yuc2Gstg K/vg+Bs3Au48hYzuHsRDD12V3FB08nxfyQ== X-Received: by 2002:adf:b644:0:b0:210:1fde:a513 with SMTP id i4-20020adfb644000000b002101fdea513mr39475679wre.604.1654765591286; Thu, 09 Jun 2022 02:06:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 48/55] target/arm: Split out load/store primitives to sve_ldst_internal.h Date: Thu, 9 Jun 2022 10:05:30 +0100 Message-Id: <20220609090537.1971756-49-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Begin creation of sve_ldst_internal.h by moving the primitives that access host and tlb memory. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/sve_ldst_internal.h | 127 +++++++++++++++++++++++++++++++++ target/arm/sve_helper.c | 107 +-------------------------- 2 files changed, 128 insertions(+), 106 deletions(-) create mode 100644 target/arm/sve_ldst_internal.h diff --git a/target/arm/sve_ldst_internal.h b/target/arm/sve_ldst_internal.h new file mode 100644 index 00000000000..ef9117e84c1 --- /dev/null +++ b/target/arm/sve_ldst_internal.h @@ -0,0 +1,127 @@ +/* + * ARM SVE Load/Store Helpers + * + * Copyright (c) 2018-2022 Linaro + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARM_SVE_LDST_INTERNAL_H +#define TARGET_ARM_SVE_LDST_INTERNAL_H + +#include "exec/cpu_ldst.h" + +/* + * Load one element into @vd + @reg_off from @host. + * The controlling predicate is known to be true. + */ +typedef void sve_ldst1_host_fn(void *vd, intptr_t reg_off, void *host); + +/* + * Load one element into @vd + @reg_off from (@env, @vaddr, @ra). + * The controlling predicate is known to be true. + */ +typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off, + target_ulong vaddr, uintptr_t retaddr); + +/* + * Generate the above primitives. + */ + +#define DO_LD_HOST(NAME, H, TYPEE, TYPEM, HOST) \ +static inline void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \ +{ TYPEM val = HOST(host); *(TYPEE *)(vd + H(reg_off)) = val; } + +#define DO_ST_HOST(NAME, H, TYPEE, TYPEM, HOST) \ +static inline void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \ +{ TYPEM val = *(TYPEE *)(vd + H(reg_off)); HOST(host, val); } + +#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \ +static inline void sve_##NAME##_tlb(CPUARMState *env, void *vd, \ + intptr_t reg_off, target_ulong addr, uintptr_t ra) \ +{ \ + TYPEM val = TLB(env, useronly_clean_ptr(addr), ra); \ + *(TYPEE *)(vd + H(reg_off)) = val; \ +} + +#define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \ +static inline void sve_##NAME##_tlb(CPUARMState *env, void *vd, \ + intptr_t reg_off, target_ulong addr, uintptr_t ra) \ +{ \ + TYPEM val = *(TYPEE *)(vd + H(reg_off)); \ + TLB(env, useronly_clean_ptr(addr), val, ra); \ +} + +#define DO_LD_PRIM_1(NAME, H, TE, TM) \ + DO_LD_HOST(NAME, H, TE, TM, ldub_p) \ + DO_LD_TLB(NAME, H, TE, TM, cpu_ldub_data_ra) + +DO_LD_PRIM_1(ld1bb, H1, uint8_t, uint8_t) +DO_LD_PRIM_1(ld1bhu, H1_2, uint16_t, uint8_t) +DO_LD_PRIM_1(ld1bhs, H1_2, uint16_t, int8_t) +DO_LD_PRIM_1(ld1bsu, H1_4, uint32_t, uint8_t) +DO_LD_PRIM_1(ld1bss, H1_4, uint32_t, int8_t) +DO_LD_PRIM_1(ld1bdu, H1_8, uint64_t, uint8_t) +DO_LD_PRIM_1(ld1bds, H1_8, uint64_t, int8_t) + +#define DO_ST_PRIM_1(NAME, H, TE, TM) \ + DO_ST_HOST(st1##NAME, H, TE, TM, stb_p) \ + DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra) + +DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t) +DO_ST_PRIM_1(bh, H1_2, uint16_t, uint8_t) +DO_ST_PRIM_1(bs, H1_4, uint32_t, uint8_t) +DO_ST_PRIM_1(bd, H1_8, uint64_t, uint8_t) + +#define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \ + DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p) \ + DO_LD_HOST(ld1##NAME##_le, H, TE, TM, LD##_le_p) \ + DO_LD_TLB(ld1##NAME##_be, H, TE, TM, cpu_##LD##_be_data_ra) \ + DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra) + +#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \ + DO_ST_HOST(st1##NAME##_be, H, TE, TM, ST##_be_p) \ + DO_ST_HOST(st1##NAME##_le, H, TE, TM, ST##_le_p) \ + DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \ + DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra) + +DO_LD_PRIM_2(hh, H1_2, uint16_t, uint16_t, lduw) +DO_LD_PRIM_2(hsu, H1_4, uint32_t, uint16_t, lduw) +DO_LD_PRIM_2(hss, H1_4, uint32_t, int16_t, lduw) +DO_LD_PRIM_2(hdu, H1_8, uint64_t, uint16_t, lduw) +DO_LD_PRIM_2(hds, H1_8, uint64_t, int16_t, lduw) + +DO_ST_PRIM_2(hh, H1_2, uint16_t, uint16_t, stw) +DO_ST_PRIM_2(hs, H1_4, uint32_t, uint16_t, stw) +DO_ST_PRIM_2(hd, H1_8, uint64_t, uint16_t, stw) + +DO_LD_PRIM_2(ss, H1_4, uint32_t, uint32_t, ldl) +DO_LD_PRIM_2(sdu, H1_8, uint64_t, uint32_t, ldl) +DO_LD_PRIM_2(sds, H1_8, uint64_t, int32_t, ldl) + +DO_ST_PRIM_2(ss, H1_4, uint32_t, uint32_t, stl) +DO_ST_PRIM_2(sd, H1_8, uint64_t, uint32_t, stl) + +DO_LD_PRIM_2(dd, H1_8, uint64_t, uint64_t, ldq) +DO_ST_PRIM_2(dd, H1_8, uint64_t, uint64_t, stq) + +#undef DO_LD_TLB +#undef DO_ST_TLB +#undef DO_LD_HOST +#undef DO_LD_PRIM_1 +#undef DO_ST_PRIM_1 +#undef DO_LD_PRIM_2 +#undef DO_ST_PRIM_2 + +#endif /* TARGET_ARM_SVE_LDST_INTERNAL_H */ diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 3bdcd4ce9d0..0c6dde00aa6 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -21,12 +21,12 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" #include "vec_internal.h" +#include "sve_ldst_internal.h" /* Return a value for NZCV as per the ARM PredTest pseudofunction. @@ -5301,111 +5301,6 @@ void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va, * Load contiguous data, protected by a governing predicate. */ -/* - * Load one element into @vd + @reg_off from @host. - * The controlling predicate is known to be true. - */ -typedef void sve_ldst1_host_fn(void *vd, intptr_t reg_off, void *host); - -/* - * Load one element into @vd + @reg_off from (@env, @vaddr, @ra). - * The controlling predicate is known to be true. - */ -typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off, - target_ulong vaddr, uintptr_t retaddr); - -/* - * Generate the above primitives. - */ - -#define DO_LD_HOST(NAME, H, TYPEE, TYPEM, HOST) \ -static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \ -{ \ - TYPEM val = HOST(host); \ - *(TYPEE *)(vd + H(reg_off)) = val; \ -} - -#define DO_ST_HOST(NAME, H, TYPEE, TYPEM, HOST) \ -static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \ -{ HOST(host, (TYPEM)*(TYPEE *)(vd + H(reg_off))); } - -#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \ -static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \ - target_ulong addr, uintptr_t ra) \ -{ \ - *(TYPEE *)(vd + H(reg_off)) = \ - (TYPEM)TLB(env, useronly_clean_ptr(addr), ra); \ -} - -#define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \ -static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \ - target_ulong addr, uintptr_t ra) \ -{ \ - TLB(env, useronly_clean_ptr(addr), \ - (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); \ -} - -#define DO_LD_PRIM_1(NAME, H, TE, TM) \ - DO_LD_HOST(NAME, H, TE, TM, ldub_p) \ - DO_LD_TLB(NAME, H, TE, TM, cpu_ldub_data_ra) - -DO_LD_PRIM_1(ld1bb, H1, uint8_t, uint8_t) -DO_LD_PRIM_1(ld1bhu, H1_2, uint16_t, uint8_t) -DO_LD_PRIM_1(ld1bhs, H1_2, uint16_t, int8_t) -DO_LD_PRIM_1(ld1bsu, H1_4, uint32_t, uint8_t) -DO_LD_PRIM_1(ld1bss, H1_4, uint32_t, int8_t) -DO_LD_PRIM_1(ld1bdu, H1_8, uint64_t, uint8_t) -DO_LD_PRIM_1(ld1bds, H1_8, uint64_t, int8_t) - -#define DO_ST_PRIM_1(NAME, H, TE, TM) \ - DO_ST_HOST(st1##NAME, H, TE, TM, stb_p) \ - DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra) - -DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t) -DO_ST_PRIM_1(bh, H1_2, uint16_t, uint8_t) -DO_ST_PRIM_1(bs, H1_4, uint32_t, uint8_t) -DO_ST_PRIM_1(bd, H1_8, uint64_t, uint8_t) - -#define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \ - DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p) \ - DO_LD_HOST(ld1##NAME##_le, H, TE, TM, LD##_le_p) \ - DO_LD_TLB(ld1##NAME##_be, H, TE, TM, cpu_##LD##_be_data_ra) \ - DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra) - -#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \ - DO_ST_HOST(st1##NAME##_be, H, TE, TM, ST##_be_p) \ - DO_ST_HOST(st1##NAME##_le, H, TE, TM, ST##_le_p) \ - DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \ - DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra) - -DO_LD_PRIM_2(hh, H1_2, uint16_t, uint16_t, lduw) -DO_LD_PRIM_2(hsu, H1_4, uint32_t, uint16_t, lduw) -DO_LD_PRIM_2(hss, H1_4, uint32_t, int16_t, lduw) -DO_LD_PRIM_2(hdu, H1_8, uint64_t, uint16_t, lduw) -DO_LD_PRIM_2(hds, H1_8, uint64_t, int16_t, lduw) - -DO_ST_PRIM_2(hh, H1_2, uint16_t, uint16_t, stw) -DO_ST_PRIM_2(hs, H1_4, uint32_t, uint16_t, stw) -DO_ST_PRIM_2(hd, H1_8, uint64_t, uint16_t, stw) - -DO_LD_PRIM_2(ss, H1_4, uint32_t, uint32_t, ldl) -DO_LD_PRIM_2(sdu, H1_8, uint64_t, uint32_t, ldl) -DO_LD_PRIM_2(sds, H1_8, uint64_t, int32_t, ldl) - -DO_ST_PRIM_2(ss, H1_4, uint32_t, uint32_t, stl) -DO_ST_PRIM_2(sd, H1_8, uint64_t, uint32_t, stl) - -DO_LD_PRIM_2(dd, H1_8, uint64_t, uint64_t, ldq) -DO_ST_PRIM_2(dd, H1_8, uint64_t, uint64_t, stq) - -#undef DO_LD_TLB -#undef DO_ST_TLB -#undef DO_LD_HOST -#undef DO_LD_PRIM_1 -#undef DO_ST_PRIM_1 -#undef DO_LD_PRIM_2 -#undef DO_ST_PRIM_2 - /* * Skip through a sequence of inactive elements in the guarding predicate @vg, * beginning at @reg_off bounded by @reg_max. Return the offset of the active From patchwork Thu Jun 9 09:05:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580278 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp652195max; Thu, 9 Jun 2022 03:45:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxRx+FXPWlPaGxlSvzc75dFo+hmMx1nOEKMY5+yEXUacPxQ1DEe1s5VdsMP8qVtKuMlfgTX X-Received: by 2002:ac8:7e83:0:b0:304:b3c4:b297 with SMTP id w3-20020ac87e83000000b00304b3c4b297mr30930663qtj.668.1654771503070; Thu, 09 Jun 2022 03:45:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654771503; cv=none; d=google.com; s=arc-20160816; b=EDIQAcCgJ2jWHZ6uineEwABOc6ZvfXqB9wBUlTHp3SnKTfZVXG5yWBZP/Mkm/uZijw A/uT7xDos7JQcMV1bdQg0HKedLXLVwxmMYeHGwAz3MueD4Bedz6849Y+xb2ldff6unog PFcb5q9JGuc5Dt0LDkwwyHmRfR8VQjCpLFBv/RrAGsKppCifnrgfSYuBg5eyFzdBd1pP kPlY7nHJqkA8mTuskEholN3VyN55HEgtgTbJRm0XR8XowM3wRbCkeqCQ4WhLLdihykO/ 7u7Ig5b9YNAG/U/3PLs/TuXf6L/GC8njbYge0RhW1cLV/nSKqjNTcaI0Aax7qmQdkszK zqhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=F9/bTgmopMaBQ0OD2oJr6RwZaHaOzv4367oHJLRZpW4=; b=CyQlsSYmQxLKulyCiC+uyZwpG2poiKuwmQQD3ZQrq0LzvMKuBGKA3vQj3amGKIthqc Uaj3BPIITzz7qwqMBciL+ifHgXNnYIyeD11+z5MrNRSotTQjquX8AQnqVAazX87FUsks Veaq7lrVGUz2Wn9vEvZwGleL/HFGLv8kzXvO9XdTLcLtR+jVSyXANeIDfLtflOUtNFOP 0sfy05Ht9nEKfMxsOs7MQr+Cd5cTzQIm87mU+OzUlGBu8y4v6rfFgiFTx0YBFnsbYj0A qoGNlM/2i8fXXsyDlReiiSZB8EqQeha9EjjCFkIBRJN9wF9zkCor8qszODCe6Q9PUXGw 1+bA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OJEvjqJy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t9-20020a05622a148900b002f381e22b22si12525781qtx.365.2022.06.09.03.45.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:45:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OJEvjqJy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60898 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFew-0003Gj-JK for patch@linaro.org; Thu, 09 Jun 2022 06:45:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40024) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7i-0001lt-E0 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:38 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:53919) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7d-00067I-9J for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:37 -0400 Received: by mail-wm1-x331.google.com with SMTP id z9so5330339wmf.3 for ; Thu, 09 Jun 2022 02:06:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=F9/bTgmopMaBQ0OD2oJr6RwZaHaOzv4367oHJLRZpW4=; b=OJEvjqJyKIiIBkJceysPIhW243YMUSKb6cTvXTQeY+PLTvgSfIboX35HdPDqA9KKFn GMYBGIW8O0Kg8r/0pRN/EXOubKbX+A6XBBkaXn2ZNYbzbcKIFj8TGWL2VzycdHIEH8rF oq5XkxqxlqUySs3deCbiQgRQc8H+oggTjaeDk8lxqyMIgF4c0oNa8ypttrxoMJtbj/K/ 7rcPvlouKGdPhM3943JNs5uD10SS522tvtY8G984X05S4Ng/u3boe/nRKOK1Msdp01N1 LCziZQBiA/nr1I1z54ZqC3DyMaOjJptTHZQyq/m/fEQKXdBEXwwR7dyyELx4iqLd20It 0oMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F9/bTgmopMaBQ0OD2oJr6RwZaHaOzv4367oHJLRZpW4=; b=c+tnp+hVgFK0gLCMrRdkgkKxUMa5IigJSXOtlSWo5pgQDYzMBQMQXc9ICbBAoKyIjK ZV7bdWmtte9MTbAvLigLZ7Wl5kUOO/bV2yBzh2MvsLh3bUTPMakKllmXk1PLYmog/yYo zEAquOrSbVL7HX7ZZ85cJ00xi5mrc1Jisj1vRNPQVX2AmbI8GNNm0N5xBtBuNPbSbM37 sVJH/cRDzIGFPUcwmDQlP1SkMJ3d93ymVyyQ43rzCZXtX9Hr/59WzbcM6ba5dnNAVvIl 4SPm1WGoGsFXWiGmHuLB5l2+wxqVU6FQ2LtlUI+BcCpVQJY5Bmt7jYEp1xP3v15/Jtb1 wu+Q== X-Gm-Message-State: AOAM532GmZTfIcq/ptgbWYStzbUxM3pP/OFidb6FB6CNpxa2tUdO3nNi J2dJaA6TBZoo5oIdloRAcUCGzv5WBgxicQ== X-Received: by 2002:a05:600c:2e14:b0:39c:58c4:c6ed with SMTP id o20-20020a05600c2e1400b0039c58c4c6edmr2308116wmf.156.1654765592275; Thu, 09 Jun 2022 02:06:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 49/55] target/arm: Export sve contiguous ldst support functions Date: Thu, 9 Jun 2022 10:05:31 +0100 Message-Id: <20220609090537.1971756-50-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Export all of the support functions for performing bulk fault analysis on a set of elements at contiguous addresses controlled by a predicate. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/sve_ldst_internal.h | 94 ++++++++++++++++++++++++++++++++++ target/arm/sve_helper.c | 87 ++++++------------------------- 2 files changed, 111 insertions(+), 70 deletions(-) diff --git a/target/arm/sve_ldst_internal.h b/target/arm/sve_ldst_internal.h index ef9117e84c1..b5c473fc48b 100644 --- a/target/arm/sve_ldst_internal.h +++ b/target/arm/sve_ldst_internal.h @@ -124,4 +124,98 @@ DO_ST_PRIM_2(dd, H1_8, uint64_t, uint64_t, stq) #undef DO_LD_PRIM_2 #undef DO_ST_PRIM_2 +/* + * Resolve the guest virtual address to info->host and info->flags. + * If @nofault, return false if the page is invalid, otherwise + * exit via page fault exception. + */ + +typedef struct { + void *host; + int flags; + MemTxAttrs attrs; +} SVEHostPage; + +bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, + target_ulong addr, int mem_off, MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); + +/* + * Analyse contiguous data, protected by a governing predicate. + */ + +typedef enum { + FAULT_NO, + FAULT_FIRST, + FAULT_ALL, +} SVEContFault; + +typedef struct { + /* + * First and last element wholly contained within the two pages. + * mem_off_first[0] and reg_off_first[0] are always set >= 0. + * reg_off_last[0] may be < 0 if the first element crosses pages. + * All of mem_off_first[1], reg_off_first[1] and reg_off_last[1] + * are set >= 0 only if there are complete elements on a second page. + * + * The reg_off_* offsets are relative to the internal vector register. + * The mem_off_first offset is relative to the memory address; the + * two offsets are different when a load operation extends, a store + * operation truncates, or for multi-register operations. + */ + int16_t mem_off_first[2]; + int16_t reg_off_first[2]; + int16_t reg_off_last[2]; + + /* + * One element that is misaligned and spans both pages, + * or -1 if there is no such active element. + */ + int16_t mem_off_split; + int16_t reg_off_split; + + /* + * The byte offset at which the entire operation crosses a page boundary. + * Set >= 0 if and only if the entire operation spans two pages. + */ + int16_t page_split; + + /* TLB data for the two pages. */ + SVEHostPage page[2]; +} SVEContLdSt; + +/* + * Find first active element on each page, and a loose bound for the + * final element on each page. Identify any single element that spans + * the page boundary. Return true if there are any active elements. + */ +bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg, + intptr_t reg_max, int esz, int msize); + +/* + * Resolve the guest virtual addresses to info->page[]. + * Control the generation of page faults with @fault. Return false if + * there is no work to do, which can only happen with @fault == FAULT_NO. + */ +bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, + CPUARMState *env, target_ulong addr, + MMUAccessType access_type, uintptr_t retaddr); + +#ifdef CONFIG_USER_ONLY +static inline void +sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, uint64_t *vg, + target_ulong addr, int esize, int msize, + int wp_access, uintptr_t retaddr) +{ } +#else +void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, + uint64_t *vg, target_ulong addr, + int esize, int msize, int wp_access, + uintptr_t retaddr); +#endif + +void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env, uint64_t *vg, + target_ulong addr, int esize, int msize, + uint32_t mtedesc, uintptr_t ra); + #endif /* TARGET_ARM_SVE_LDST_INTERNAL_H */ diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 0c6dde00aa6..8cd371e3e37 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5341,16 +5341,9 @@ static intptr_t find_next_active(uint64_t *vg, intptr_t reg_off, * exit via page fault exception. */ -typedef struct { - void *host; - int flags; - MemTxAttrs attrs; -} SVEHostPage; - -static bool sve_probe_page(SVEHostPage *info, bool nofault, - CPUARMState *env, target_ulong addr, - int mem_off, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, + target_ulong addr, int mem_off, MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) { int flags; @@ -5406,59 +5399,13 @@ static bool sve_probe_page(SVEHostPage *info, bool nofault, return true; } - -/* - * Analyse contiguous data, protected by a governing predicate. - */ - -typedef enum { - FAULT_NO, - FAULT_FIRST, - FAULT_ALL, -} SVEContFault; - -typedef struct { - /* - * First and last element wholly contained within the two pages. - * mem_off_first[0] and reg_off_first[0] are always set >= 0. - * reg_off_last[0] may be < 0 if the first element crosses pages. - * All of mem_off_first[1], reg_off_first[1] and reg_off_last[1] - * are set >= 0 only if there are complete elements on a second page. - * - * The reg_off_* offsets are relative to the internal vector register. - * The mem_off_first offset is relative to the memory address; the - * two offsets are different when a load operation extends, a store - * operation truncates, or for multi-register operations. - */ - int16_t mem_off_first[2]; - int16_t reg_off_first[2]; - int16_t reg_off_last[2]; - - /* - * One element that is misaligned and spans both pages, - * or -1 if there is no such active element. - */ - int16_t mem_off_split; - int16_t reg_off_split; - - /* - * The byte offset at which the entire operation crosses a page boundary. - * Set >= 0 if and only if the entire operation spans two pages. - */ - int16_t page_split; - - /* TLB data for the two pages. */ - SVEHostPage page[2]; -} SVEContLdSt; - /* * Find first active element on each page, and a loose bound for the * final element on each page. Identify any single element that spans * the page boundary. Return true if there are any active elements. */ -static bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, - uint64_t *vg, intptr_t reg_max, - int esz, int msize) +bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg, + intptr_t reg_max, int esz, int msize) { const int esize = 1 << esz; const uint64_t pg_mask = pred_esz_masks[esz]; @@ -5548,9 +5495,9 @@ static bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, * Control the generation of page faults with @fault. Return false if * there is no work to do, which can only happen with @fault == FAULT_NO. */ -static bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, - CPUARMState *env, target_ulong addr, - MMUAccessType access_type, uintptr_t retaddr) +bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, + CPUARMState *env, target_ulong addr, + MMUAccessType access_type, uintptr_t retaddr) { int mmu_idx = cpu_mmu_index(env, false); int mem_off = info->mem_off_first[0]; @@ -5606,12 +5553,12 @@ static bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, return have_work; } -static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, - uint64_t *vg, target_ulong addr, - int esize, int msize, int wp_access, - uintptr_t retaddr) -{ #ifndef CONFIG_USER_ONLY +void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, + uint64_t *vg, target_ulong addr, + int esize, int msize, int wp_access, + uintptr_t retaddr) +{ intptr_t mem_off, reg_off, reg_last; int flags0 = info->page[0].flags; int flags1 = info->page[1].flags; @@ -5667,12 +5614,12 @@ static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, } while (reg_off & 63); } while (reg_off <= reg_last); } -#endif } +#endif -static void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env, - uint64_t *vg, target_ulong addr, int esize, - int msize, uint32_t mtedesc, uintptr_t ra) +void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env, + uint64_t *vg, target_ulong addr, int esize, + int msize, uint32_t mtedesc, uintptr_t ra) { intptr_t mem_off, reg_off, reg_last; From patchwork Thu Jun 9 09:05:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580273 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp647061max; Thu, 9 Jun 2022 03:36:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyffkAKtLkV6+Hf47qaiptlbktnjz51QSaCN1nwnWYqLIStQUfWtRn0ISNcV6+UCwzOIbMM X-Received: by 2002:a05:620a:2947:b0:6a3:a317:fa08 with SMTP id n7-20020a05620a294700b006a3a317fa08mr26245593qkp.746.1654770997302; Thu, 09 Jun 2022 03:36:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654770997; cv=none; d=google.com; s=arc-20160816; b=y4HcgljkUegBJn9Qe2pGzS81L3T700tFoG2k7HmSi48aQW0CnGiYd9madkiv0iBIY3 PbsQumCESQQ7sqTLW8dQzPEvh/giy6m907oPILG6muiq0/51t4q5yiO+tvS00IgAFqoU 9TFKqnHqjjCDpcRhkoBGdMK6MvmEcRbzDF28fAfIcyCQXwvi2pcX5I6VHQCqVCebO+3+ L/zcXE2F5RWAQxAHH8XLQDpVB/9evKVLCmwIcG0QPgqoJkalvpEScn7YLBGPvh+xyYhj GtKLwyuy6ww0PrxVI+jp/x937LjlUnF6Ag1KGA/BLSrmDOjvSuW96YlkMbd3TC74O2Hl gNrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=A14QxFs16bLONsVCSDgKLzSud5B5D6SZ03whQ20bd3w=; b=tbNB+YZg1i3I+KkIFWHrN2DJbXGpd2eY4W1xld6sUDTTMGl51nETQ473uGlxDREVbs Cw6DAauOY0iG+HheB4I/Qq6+O36qhwgk1z4a8Gf6q8pxMDj0JKA/aDZhL46w/h06rk4u ErL2AUcgmUc5E5zRYMsRNhxH5jDC0lApvtWdyNIxtiRF6y0cqoiBaj22qwjh96++LyfA u4Gej7er2szHSbirLJPagwcfgQheWn/gT13FQRUlV9/X/JKC3iFWSV7f71AqDd/e1tMN h2+oSbZ/DbCNjRpFf+Rm5r9uVapQWMg3dAmyTaN3ZPOGqLvr0bQQBjLsYCc5ZMjtJvqs /qsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CggcEqGc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id bq34-20020a05620a46a200b006a7316a3b30si415608qkb.373.2022.06.09.03.36.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:36:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CggcEqGc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46988 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFWm-0001wS-R3 for patch@linaro.org; Thu, 09 Jun 2022 06:36:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40014) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7f-0001k9-Jm for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:35 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:43557) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7d-00062u-O4 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:35 -0400 Received: by mail-wr1-x42e.google.com with SMTP id d14so22478158wra.10 for ; Thu, 09 Jun 2022 02:06:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=A14QxFs16bLONsVCSDgKLzSud5B5D6SZ03whQ20bd3w=; b=CggcEqGcQmo4V+zqyGuGh0OrHns6C2kvXM732Ca0W6lPCoxIM0XF/QQTx7orla1dlS iCoI3LkbK2LHZ0m5gV8v7aNMmxnw//aJPYJwS7dc9f8KvDYNGWl87EFFQWNrbYL4NEk3 wOCHGZCWYAKB460pdWCn2tqhrz9096rmLXlnld4yDryeW3+fiH1TdaS205ubXCPd4Y0Z Li9exE0QUcRS8VnhJYCgz6hZUJtapy/c5UkH7+iT5rDzTAcfs3DQ/XG8wV/H+HyE3LxK B8VvPMV2ut3xKAYncRBmWpnUXIKNa8DGV5oRswrhwzOn4toKTsHtKPhLu+1Ak4NaCJMD JWRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A14QxFs16bLONsVCSDgKLzSud5B5D6SZ03whQ20bd3w=; b=rAKucWDceyQ9uWls2Fdv+ng9pciwjYgmj1uXYA+Rjy38qJLqI4KrOQiK576jA9OX8O 9P3M3p/neetcPUYzcU9hukL3/FxNpLH1dix9I0sTV3ZBIjkcMBTEfkiJwp0tB6w1wWzQ netDeqK+YgMd3ihIcx+jBjQbQ5XDdIlpR1//tq2iPfeCZ7cwHnwPPXospzT/btZCYHo/ 6vAYqGLwd+EXhVRj7s1N5WeRzIwYfd4LGX202U/RWaX77QzDyhLi7vWhMVFw8pW9ODfc 7L6XzOIZEVCre71pyhe6JhbvrTjKskHnkAVwrLtm6Gk1eCrW9i/mY8OZikVhOSPFSwO9 7G5Q== X-Gm-Message-State: AOAM533gXK/ogNfgMMHnJHn16K8xA9Zc4bCoGNnjvnnQp+WtuGGQ8VoX hb5Ol0Fyza4/NnUri4A3JCQMbzyeKhBMuA== X-Received: by 2002:a05:6000:168c:b0:218:4523:c975 with SMTP id y12-20020a056000168c00b002184523c975mr17911740wrd.23.1654765593007; Thu, 09 Jun 2022 02:06:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 50/55] target/arm: Move expand_pred_b to vec_internal.h Date: Thu, 9 Jun 2022 10:05:32 +0100 Message-Id: <20220609090537.1971756-51-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Put the inline function near the array declaration. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/vec_internal.h | 8 +++++++- target/arm/sve_helper.c | 9 --------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h index 1d63402042f..d1a1ea4a668 100644 --- a/target/arm/vec_internal.h +++ b/target/arm/vec_internal.h @@ -50,8 +50,14 @@ #define H8(x) (x) #define H1_8(x) (x) -/* Data for expanding active predicate bits to bytes, for byte elements. */ +/* + * Expand active predicate bits to bytes, for byte elements. + */ extern const uint64_t expand_pred_b_data[256]; +static inline uint64_t expand_pred_b(uint8_t byte) +{ + return expand_pred_b_data[byte]; +} static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) { diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 8cd371e3e37..e865c125273 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -103,15 +103,6 @@ uint32_t HELPER(sve_predtest)(void *vd, void *vg, uint32_t words) return flags; } -/* - * Expand active predicate bits to bytes, for byte elements. - * (The data table itself is in vec_helper.c as MVE also needs it.) - */ -static inline uint64_t expand_pred_b(uint8_t byte) -{ - return expand_pred_b_data[byte]; -} - /* Similarly for half-word elements. * for (i = 0; i < 256; ++i) { * unsigned long m = 0; From patchwork Thu Jun 9 09:05:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580286 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp672310max; Thu, 9 Jun 2022 04:12:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxa++Yg/OHYyoqHIEfGCetp7sByzt1jVN6y9MDU2TaRz9rZKHN2ETAFEQAkE+JjvTIw4xbZ X-Received: by 2002:a05:6214:2589:b0:464:69ea:771c with SMTP id fq9-20020a056214258900b0046469ea771cmr33391512qvb.41.1654773147171; Thu, 09 Jun 2022 04:12:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654773147; cv=none; d=google.com; s=arc-20160816; b=wg1MDoF7yB3Ux4giir3+fAisuPz7q5yJAC5D97x4kd/4tDNKYm3Ac7W1gjMovS373c tnh2IL3Q2+MG0tHK8RwITeme4xgLPI1C1KYAxQSwI3rpRBWENLCDVa+TswHIzN+ovlFG P0grJGllxbzGgWDz/7jo+88EJ0m+6cUiShKVg6GJvv4yf5uR6Yl7GBXnnBwAWyQuoWVx XDLAd72MkUXesnn7267t1fXgnbkTagDWw0OqRkB1RcVan1EpHSdFNTwxeSGmoBVpKrGt htWyuJutmCV5gWpdQWFsEMq9A842EvwxAk1+eYCJkwuXIPyMuAFBvzxKN4b25dHipVb8 tWwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cex5x9L9Gl/d10/8cuiaJvgz9NAjknIKjSgIAlTWGEg=; b=fQjIX/SPpZBb0oBcYXhCWxXstOk8lLbjh9lr+3re2VhRwMtGVskPjOqovODwcBlrNy 8KFUcm5rDjmWw+5fZZqC5ZlYlDafqez2JS00hAwUr6DlGI/utFPmKOp2LTEx/74t82kw ewSet3lO9N0wTW9BA/8+N0DBNSVN4/iMlgBW7bOjZ3uMQca8RcskCGf3FIuD0Lst/QdE cJVoO6wQ5PCEIKgltSUzTACwhaz6WLdPX/BMegUBGKx+ysjVuF26J53PmSw0KnWzw6wL l1zRYPHsTBnQwEpWAbZ6tttq/WPIp0cR2jAu+KqjwMMEAZn2epxv/XWjaPcgr/qxrKXv VyLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UO2hkPRO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id bq14-20020a05620a468e00b006a6c5527372si4858598qkb.761.2022.06.09.04.12.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 04:12:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UO2hkPRO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35476 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzG5R-0001l8-3u for patch@linaro.org; Thu, 09 Jun 2022 07:12:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40108) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7r-0001sd-4j for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:48 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:42899) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7e-00060y-O5 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:46 -0400 Received: by mail-wr1-x432.google.com with SMTP id s1so8358409wra.9 for ; Thu, 09 Jun 2022 02:06:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cex5x9L9Gl/d10/8cuiaJvgz9NAjknIKjSgIAlTWGEg=; b=UO2hkPROv7vuihUX1utcuWVxNMFTDbgBcFfusZtlQkk/9VhAHIEPABTXoV/A5CdH/D xNSeL/bjHkW+0kDIXRX//0+CLnXbOUuB2k+E6XPdtgdr5yvVUlrshc9QSsZ2/pFhn+DU GlXdGda5k3fB3/hMbhImuDEcy0Ms3m+dKl+xxKABfbrdOgQQhlpJ0YVyI4herbssA5SW fkaJUmAdR5gQcLYKjb4DCshJAapMuVKAsX+UljFmxD6phzkNV5WVAGFg6G/ZUsja7uD/ w5qWP2gmUCsGD/H14t6ZuO3+ilobOvLwpiRZJCeNvtN6P1tIOz/xxfdLIxBVCSXXDean C6QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cex5x9L9Gl/d10/8cuiaJvgz9NAjknIKjSgIAlTWGEg=; b=GFOM9rLypc2/QpYdnYgPq7GaC/vMpd1xXezbyOEOFCnDUAnHVTxK0sRoCt+fRIJ79L XzlOiYuZ4AzRN/23qrbO+LwrN0Wlfza7Saun7PEV2fpR7fWyO5F5SL0V1/4DMQMtx5tG 7fvjQWar7DjbI1xigE789KZqX91NZio+FsymP4DaNeo2jyM4NrBMpqR17vm6nl58rGzt 0OYXMBRkSQO1vYe3qmwOl1iRx3klNW63dP37FUoZxnnuaY3aD/WTj5xmlv+eTDTKqD3b /FQZMW/3+aiB1h9vGNYISak+zZMFy1EwXuMfPGdMg+HWYMF7uxWkSJRqXbK6Rjy6h9dT N1HA== X-Gm-Message-State: AOAM532cg53Y0Uv6tQNvZIGXTo+fL+mmc9IgdQ4ovchzyT+Lf3jdNYLg l2k1fl8gFIdYXvrjn/p2AxLEDdjAmyForQ== X-Received: by 2002:a5d:5222:0:b0:213:b7f7:58fe with SMTP id i2-20020a5d5222000000b00213b7f758femr31629529wra.620.1654765593905; Thu, 09 Jun 2022 02:06:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 51/55] target/arm: Use expand_pred_b in mve_helper.c Date: Thu, 9 Jun 2022 10:05:33 +0100 Message-Id: <20220609090537.1971756-52-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Use the function instead of the array directly. Because the function performs its own masking, via the uint8_t parameter, we need to do nothing extra within the users: the bits above the first 2 (_uh) or 4 (_uw) will be discarded by assignment to the local bmask variables, and of course _uq uses the entire uint64_t result. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/mve_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 846962bf4c5..403b345ea3b 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -726,7 +726,7 @@ static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask) static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) { - uint16_t bmask = expand_pred_b_data[mask & 3]; + uint16_t bmask = expand_pred_b(mask); *d = (*d & ~bmask) | (r & bmask); } @@ -737,7 +737,7 @@ static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask) static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) { - uint32_t bmask = expand_pred_b_data[mask & 0xf]; + uint32_t bmask = expand_pred_b(mask); *d = (*d & ~bmask) | (r & bmask); } @@ -748,7 +748,7 @@ static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask) static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) { - uint64_t bmask = expand_pred_b_data[mask & 0xff]; + uint64_t bmask = expand_pred_b(mask); *d = (*d & ~bmask) | (r & bmask); } From patchwork Thu Jun 9 09:05:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580277 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp651160max; Thu, 9 Jun 2022 03:43:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwMQqQ4wvw7CvC5df2vSSFW9FFHWcDx9t6zMKrN46gwYsUfPOaSkR79xPIV7fcY3SjmZ/HP X-Received: by 2002:ac8:5fd5:0:b0:305:115a:93e with SMTP id k21-20020ac85fd5000000b00305115a093emr909338qta.623.1654771387938; Thu, 09 Jun 2022 03:43:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654771387; cv=none; d=google.com; s=arc-20160816; b=EUn8hnwPk7CvKEAJEyopdWdAbBYpt7pafi8p0HuB74LQ76a7/iHAN6r6u2BY6bKRjy wvV8S1sHK4zIECMnr3yLeWBH1cw8WlVUxPtge5faVmXzZ2G9aECtsH8H4q8o2ro6hGkC 2Km1u6kk5vOZ6J4nEIei7CCmrLiFVsSe3vUsJwUb5TC7ObbrNbuB0YhDXCtF1tFHCL/J QEfTole8gtuLK9kEpkxBFcfCfqm0rvgcCQ6eqmklu3qovSATFevsERVgY7zR4FDOGgFN a2N6pnexc/4LXJXUJdPY5/M2l5ICjweItARVS/buzk5VIocm1vH1wlOOczmd3d2PXVL+ uA7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4FBoJtD8BnTfjL+tOQoIkqKssw+9QYDFG8qS913t+NY=; b=Fp/q4Rc7Y83DCB7W+/gtMilI+fL9KXHZObqqUJ7OkveqpWOr5vrTsHlXsu3JiunNnz Cf61jBcYuO8wEYpLJXzffziRBq3//Jco2rvN2NYmsy00VSTQJF7/lGpTu3O1kNdlLrqi wUf2kpFUqXDl0Me2L0bGtDytlJlof0UepTyTiUpgw+6HeMymLys0xwZvyAZSPwej/HBe 0o1a/iW/7tZJWXRKKLKD0hMMDXdtQHGoy6hDcdkwMC9p8Huma4H+JO0/be0rGnev7/wp VehltlxAMbVMpYWmer0NqttLICv/HRQjDEbXtll5LjTJokApLDsgNolBpObjl1XvC0XW sdbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xKIotShL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v20-20020a05620a441400b006a5f604640bsi13678612qkp.224.2022.06.09.03.43.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:43:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xKIotShL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57888 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFd5-0001D0-EV for patch@linaro.org; Thu, 09 Jun 2022 06:43:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40058) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7i-0001n7-Rz for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:39 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:37403) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7h-0006Ag-7h for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:38 -0400 Received: by mail-wr1-x431.google.com with SMTP id m26so20034092wrb.4 for ; Thu, 09 Jun 2022 02:06:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4FBoJtD8BnTfjL+tOQoIkqKssw+9QYDFG8qS913t+NY=; b=xKIotShL64D8PEfdIrqMlXsxd5HmVnVtykYliXYfUptdaBS5C2G+PJcnwQT3o4HdnA TOLKDotN64G8hWxzR+6zCYOcMDzDZF4hSqgDO3F3+yAP4KmWfmDlsuJ4/I9uoJEKV3hs OfvhY+1ntTTHd8J0WB0ewXowOnBtNL2XupBc0MZtGesLUZIjTvbR6f/fq8WT6n0cA1Wx U72jhl/nv6eZbrzooxp4SMpIX7A3ICIjUahCTDlycPJEqoBLeA7Fc9diAJ3OunYPaWtJ IAmDIZdK/JGvyLqX2cp6QqbGSj5kg05DW8I9YguJodcnt4wXRJVNfaNAhAJtJ6U0jluJ jcMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4FBoJtD8BnTfjL+tOQoIkqKssw+9QYDFG8qS913t+NY=; b=Zq9KgKP6VC3eR7Y2PyrgtQHSwcrNiCQU80685YqYvq46dk1Kjmdc/AaOGZTn1K6C8u rupHY5lzMWlUR4+sNGh2dI1pjTsnYCdUQnNJc2UUa949s+BAFQ5wysOtwXGOpOG1p7K4 PIaOoAewVCynaD6rKse/PwLVl9D3/k56rfrMQVeWiW7WautTeAEGjpP3Alnz6ufEp2u/ PH+Nw5onCu97RUWA9fXVyjZrviAhOSeJV3uZrg3uQhOuj1ae0RqiOaSi8FdrWL8fOQiM SGAkeg1rcRSNw4W4bWUinst5MziVMmkeEOPrINHow0ywm3b/4ys7vXakD2TrDrzv/d0N sY4A== X-Gm-Message-State: AOAM5316xU6gvErNZ9AWE/5NeTn6aqi+0/xR7jZLFs9kd0ZJibsKkCMm FkcSVZ4gg3vL92FNVnI4K8PaDwEWvlNoZQ== X-Received: by 2002:adf:c64c:0:b0:20f:e8f0:be4c with SMTP id u12-20020adfc64c000000b0020fe8f0be4cmr37253756wrg.614.1654765594780; Thu, 09 Jun 2022 02:06:34 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 52/55] target/arm: Move expand_pred_h to vec_internal.h Date: Thu, 9 Jun 2022 10:05:34 +0100 Message-Id: <20220609090537.1971756-53-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Move the data to vec_helper.c and the inline to vec_internal.h. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/vec_internal.h | 7 +++++++ target/arm/sve_helper.c | 29 ----------------------------- target/arm/vec_helper.c | 26 ++++++++++++++++++++++++++ 3 files changed, 33 insertions(+), 29 deletions(-) diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h index d1a1ea4a668..1d527fadac1 100644 --- a/target/arm/vec_internal.h +++ b/target/arm/vec_internal.h @@ -59,6 +59,13 @@ static inline uint64_t expand_pred_b(uint8_t byte) return expand_pred_b_data[byte]; } +/* Similarly for half-word elements. */ +extern const uint64_t expand_pred_h_data[0x55 + 1]; +static inline uint64_t expand_pred_h(uint8_t byte) +{ + return expand_pred_h_data[byte & 0x55]; +} + static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) { uint64_t *d = vd + opr_sz; diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index e865c125273..1654c0bbf9e 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -103,35 +103,6 @@ uint32_t HELPER(sve_predtest)(void *vd, void *vg, uint32_t words) return flags; } -/* Similarly for half-word elements. - * for (i = 0; i < 256; ++i) { - * unsigned long m = 0; - * if (i & 0xaa) { - * continue; - * } - * for (j = 0; j < 8; j += 2) { - * if ((i >> j) & 1) { - * m |= 0xfffful << (j << 3); - * } - * } - * printf("[0x%x] = 0x%016lx,\n", i, m); - * } - */ -static inline uint64_t expand_pred_h(uint8_t byte) -{ - static const uint64_t word[] = { - [0x01] = 0x000000000000ffff, [0x04] = 0x00000000ffff0000, - [0x05] = 0x00000000ffffffff, [0x10] = 0x0000ffff00000000, - [0x11] = 0x0000ffff0000ffff, [0x14] = 0x0000ffffffff0000, - [0x15] = 0x0000ffffffffffff, [0x40] = 0xffff000000000000, - [0x41] = 0xffff00000000ffff, [0x44] = 0xffff0000ffff0000, - [0x45] = 0xffff0000ffffffff, [0x50] = 0xffffffff00000000, - [0x51] = 0xffffffff0000ffff, [0x54] = 0xffffffffffff0000, - [0x55] = 0xffffffffffffffff, - }; - return word[byte & 0x55]; -} - /* Similarly for single word elements. */ static inline uint64_t expand_pred_s(uint8_t byte) { diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 17fb1583622..26c373e522f 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -127,6 +127,32 @@ const uint64_t expand_pred_b_data[256] = { 0xffffffffffffffff, }; +/* + * Similarly for half-word elements. + * for (i = 0; i < 256; ++i) { + * unsigned long m = 0; + * if (i & 0xaa) { + * continue; + * } + * for (j = 0; j < 8; j += 2) { + * if ((i >> j) & 1) { + * m |= 0xfffful << (j << 3); + * } + * } + * printf("[0x%x] = 0x%016lx,\n", i, m); + * } + */ +const uint64_t expand_pred_h_data[0x55 + 1] = { + [0x01] = 0x000000000000ffff, [0x04] = 0x00000000ffff0000, + [0x05] = 0x00000000ffffffff, [0x10] = 0x0000ffff00000000, + [0x11] = 0x0000ffff0000ffff, [0x14] = 0x0000ffffffff0000, + [0x15] = 0x0000ffffffffffff, [0x40] = 0xffff000000000000, + [0x41] = 0xffff00000000ffff, [0x44] = 0xffff0000ffff0000, + [0x45] = 0xffff0000ffffffff, [0x50] = 0xffffffff00000000, + [0x51] = 0xffffffff0000ffff, [0x54] = 0xffffffffffff0000, + [0x55] = 0xffffffffffffffff, +}; + /* Signed saturating rounding doubling multiply-accumulate high half, 8-bit */ int8_t do_sqrdmlah_b(int8_t src1, int8_t src2, int8_t src3, bool neg, bool round) From patchwork Thu Jun 9 09:05:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580280 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp653822max; Thu, 9 Jun 2022 03:47:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyWnQaoIXucSKnaxgL15sPSviOjTJQOgYvy4DJ/MTNTgXX6zOLzsrOz8kjqkUuCeAEvjACe X-Received: by 2002:a05:6214:27e2:b0:468:bc97:8cba with SMTP id jt2-20020a05621427e200b00468bc978cbamr23104241qvb.57.1654771677650; Thu, 09 Jun 2022 03:47:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654771677; cv=none; d=google.com; s=arc-20160816; b=xgBULfZwrVFvs7bTw68ZeRMiiwl8FPqvo/S7Fc5r4/Cfd+eVT1z/PqN/tq9EdAo8/I pWfkOVplSgaFgqHjHVMlz/WzrX6Z7cEdZHprR5f6fAN4ypop8m7fl9rmt6Kcea7p7ozn f8a1bDqnukEwDq8ll5nIifpaPWj6/Xq7ns/2XS7bOcSuuNJbYPVG/Ha16TY7GkM1q/pE DEBIVgJMHyOCgkzdo1H+1jlWN2mykSfWwCyBxl7CGMXb0pV0tjd/g1mg3kKz3UsnM/+h GpYw2rlz+js1OEh1B91w9x8M2hOJIElzNSGsHboaCqH48JAQ0w1j70VUeutEZhXwPjXS CyXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=O7gtIRaRwJ71mlo9jIWS+jCv56ddk4eH5DIeQnFasaQ=; b=tDAw/RN4GcroA5KGVMkj1ZExlARe+HQqz1YCaGJN+kkX+ES4PTRmy45WdcxlR/vtmC jZF0vYKKr/wqcpIiWNFpZ1GFj36uZYfFo5xoeHXFzOc2dJWD7Ui4IH8lpPcPEEt5nu4b kr6mj4k9JR3SCOJL6pjEN2EohZMbL6Abe+dglSaWWl6OBdXeQYDtjSYN7AMfvrmUHDSE /beSX+BMk0gGixaX2vpGUguzCrpadw2xKYeZXx7aUA7L4IPg88kX8z3VObpo2BVJjf3G /2JRAWfyc8l+YLfVDMp5EmgIymx1uMhOBSXSow2BBI8q3o9E8B6jK+92R06cT/UD6jLv 7yuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KzIbGgrv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p18-20020a05622a00d200b002f3df2ef3b3si13514581qtw.370.2022.06.09.03.47.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 03:47:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KzIbGgrv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38076 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFhk-00072G-Ul for patch@linaro.org; Thu, 09 Jun 2022 06:47:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40068) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7j-0001oG-D9 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:39 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:37679) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7h-0006Aw-U3 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:39 -0400 Received: by mail-wm1-x32c.google.com with SMTP id o37-20020a05600c512500b0039c4ba4c64dso6599170wms.2 for ; Thu, 09 Jun 2022 02:06:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=O7gtIRaRwJ71mlo9jIWS+jCv56ddk4eH5DIeQnFasaQ=; b=KzIbGgrv+MHSOzOSIpha96OMEANSnHNIm24FO600IBYEUbg0anhsRIar2ylD9x1A7s 6M7cENNhORciRZZxn46A/ievk+fjUzkvKbaqmRNa6raQF93ZQUDvvHApiJkcNgmcQ6q5 itqJjiYv3vmTl3Pw5c1+hKtYWxIEPUzT/9EBkIFLrCiBegFbxMi4K//RUmABfsv2gkxJ pfN9BTFn3sSwRkw+e5pkPpJB2wKvCHZjb+82NjfjTLYUzJhKbhm+BVqFbxC8AtgRccnA J3LC+c7E/fwsjTgimgEac0pf2T6vMDB4AN2J0PTwooGWd3SmGbrF9gUWhmYOsCVHXLEu yGnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O7gtIRaRwJ71mlo9jIWS+jCv56ddk4eH5DIeQnFasaQ=; b=TQ0a0mys14iihJ5Avf5Y6QG4eA3HjIsfIfYhJPzHLJKthAxgN3/KnfGhPCPNbvxnih 5URLIVU1DqssPqGxLmzLODh4eA8jMokFl+a5w5A7aM7rYVV3oPwnyCWHHFrUQgRdXy2p Tnwca94tb6TdDqEtdzqos4uDeXgvt1/jUAudWCdV/jM0rOQtJFHkdHBJRNLXRmtw7U/N DUd2orQLqs0Ejag4iPMFbPpVY/0d00lOzbvFuJZjsDefrA6OcWm9hR3phlckhPPVetNE 7CMHf2zTeEMj2WUHxcVTE9/zPhxHmbLHMb9PKvVe01ngRKh7yiBtVJUkE5V9FmOXeijZ Wddw== X-Gm-Message-State: AOAM533AwYkRoLOgkjzXoi8ZEXQJnpKAYUJdddN1q5nT81HJ4flMqtXG JFW66IZLFSiRSOymwyjjq1ser2myFS5Mxg== X-Received: by 2002:a05:600c:3503:b0:39c:65e0:c070 with SMTP id h3-20020a05600c350300b0039c65e0c070mr2227755wmq.161.1654765595611; Thu, 09 Jun 2022 02:06:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 53/55] target/arm: Export bfdotadd from vec_helper.c Date: Thu, 9 Jun 2022 10:05:35 +0100 Message-Id: <20220609090537.1971756-54-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We will need this over in sme_helper.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/vec_internal.h | 13 +++++++++++++ target/arm/vec_helper.c | 2 +- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h index 1d527fadac1..1f4ed80ff76 100644 --- a/target/arm/vec_internal.h +++ b/target/arm/vec_internal.h @@ -230,4 +230,17 @@ uint64_t pmull_h(uint64_t op1, uint64_t op2); */ uint64_t pmull_w(uint64_t op1, uint64_t op2); +/** + * bfdotadd: + * @sum: addend + * @e1, @e2: multiplicand vectors + * + * BFloat16 2-way dot product of @e1 & @e2, accumulating with @sum. + * The @e1 and @e2 operands correspond to the 32-bit source vector + * slots and contain two Bfloat16 values each. + * + * Corresponds to the ARM pseudocode function BFDotAdd. + */ +float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2); + #endif /* TARGET_ARM_VEC_INTERNAL_H */ diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 26c373e522f..9a9c034e36f 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -2557,7 +2557,7 @@ DO_MMLA_B(gvec_usmmla_b, do_usmmla_b) * BFloat16 Dot Product */ -static float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2) +float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2) { /* FPCR is ignored for BFDOT and BFMMLA. */ float_status bf_status = { From patchwork Thu Jun 9 09:05:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580284 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp666732max; Thu, 9 Jun 2022 04:05:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxi6+8ng2s3LWYSK44hJofpvlVEidhc4pAQcLpfWHNuJn3ASI5qNOvvErquf7KA+ZOLBpkG X-Received: by 2002:a05:6214:c26:b0:464:3fdd:a3e6 with SMTP id a6-20020a0562140c2600b004643fdda3e6mr46629889qvd.113.1654772724800; Thu, 09 Jun 2022 04:05:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654772724; cv=none; d=google.com; s=arc-20160816; b=1GVP8xTyvMEciV0PY5jeplwqV1NIl61HAjWFao4SuAG4AhMAyswisgP5/BOu96/8L/ m7dqMivlSpR3nDMqHLsOrlNM/kVEyXCUWpBq8THrZx6BS9jbf6hA1AMf6uxDaRXUJgL5 2F3jYMFx0q1P5zKFsHGzirDnEVxmuDAuEAbCeyN67JP5NW/NgNdv7Rtw7F68p3pwFWkI wlVnZN33IZg5qqnwpWka1UfzNxRyj2aFnNLxrROpLhLYCLaozYoju/kLZzXvEh3C40QV e6+rZGeMVIilDmgbncAejj7adj5SwPs0QhGzfwYgZUhlvS7C0RLWo7DLBFchSfbwpSZc gW3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZDzwoFqQkyUODGOZytKyrO2zzhN95wbOXNg0vdTc5XQ=; b=jB5J/d1l809ilxxdIx/Kr2ZErcPtXHGj6pF2ltW78x/u30mjhnfeifk6RNwZCH8mhY Qo9Ehew82mOQnZUNYjM95El1rd2/ygXy8DNzg+L4OUbscCQZSGHav1BQOWproAItpVwE T2V+eOIoPUID27J7SguiKMAs2aA6SYvYM7NXfN1ROyJ7HmxI5JTsFqG3a9KN66agkoha +yox/Y/q/iaCEQ7+GEa43JB5ibg+9I6jddQGvbny2Q6X/fpSB8D1tRTbb+3Jf79zjhwK 0DDacBcxvF16uUp2o/BcukvbK/iMnZMhSbJCTeRqgPcpeUzoZnX2VL3M9nYIGOSybGaJ 210g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="MObO/wfY"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h27-20020a05620a13fb00b006a6b1513084si6872868qkl.140.2022.06.09.04.05.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 04:05:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="MObO/wfY"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55348 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzFye-0003Vi-CR for patch@linaro.org; Thu, 09 Jun 2022 07:05:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40092) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7o-0001rX-50 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:44 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:53920) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7i-0006BK-O3 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:43 -0400 Received: by mail-wm1-x331.google.com with SMTP id z9so5330625wmf.3 for ; Thu, 09 Jun 2022 02:06:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZDzwoFqQkyUODGOZytKyrO2zzhN95wbOXNg0vdTc5XQ=; b=MObO/wfYFRd9V8SBfrCe3zeKzYWbPisVcnsfpRig3h/RGW2oxZ5pibjqvHuZEw5POB L7/KfM2jso5mszakTB80q3fPOPbyb8ZNuWiJ1mT63JqkAvIsZMp7/oJcq5VhMQVSupuj SVpGUs2WmKlrzSeodFPYvbFrjgKgEP6YIEhtDDutU05xRdzApX+boWSoDcSWbn2f8I+w bugYye20JucZiKZqfUrdK4NPxAnCWguYbAINx77iYjpx/r9ck+F9BUVkpGh2SxxSUx2B 27DQf3ObZ1TxkeBIvzwQHXaw7cixqriVOsEK7wi/OuJ0EfPX/v+n0uyGbyOfuMn9RmQO pQUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZDzwoFqQkyUODGOZytKyrO2zzhN95wbOXNg0vdTc5XQ=; b=k89JxNRW/le4Jhe5f+Q5oXqceypxD5YJEW08XssPsIX0piLi7kDbDvpTthLUSHtIoW TIyegCx8oADD0TOjY/o8zPnd2nXDAwk9vwX0A3jUjOtoceFd+GKAk7/HTtwEc15fLUA6 vdtiFyVPriJgmbeHwlpR2E1ZHeh1YjuM//cD/VHfeUW9Zcu2ZFxu+4O1z41e//k41vqb 6Bib1F4Ia9gIG5RJFJWNBcE8lTfq+k+bwqyGXCCeBjtoL05pCYBX+qcUivSHy5Ju9nVP viRifefHwEVW1PaNnFQ4biIEtZIEo86BhcYlbKknYItALS67v/Iez4f1PXQ8hxMYJVF+ m+7Q== X-Gm-Message-State: AOAM530aVCtAQsLJYSGYV7w0y83F4AG0EFI4cX2yLQQXwd/qWeGRB6pO +D5agPbUtlqFd6WIpMQdxt91iknH+PDsrA== X-Received: by 2002:a05:600c:1ca5:b0:39b:a66b:7805 with SMTP id k37-20020a05600c1ca500b0039ba66b7805mr2143187wms.87.1654765596499; Thu, 09 Jun 2022 02:06:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 54/55] target/arm: Add isar_feature_aa64_sme Date: Thu, 9 Jun 2022 10:05:36 +0100 Message-Id: <20220609090537.1971756-55-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This will be used for implementing FEAT_SME. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e45b5cb7fe1..2e6153c5409 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4048,6 +4048,11 @@ static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; } +static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; +} + static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && From patchwork Thu Jun 9 09:05:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 580291 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp708873max; Thu, 9 Jun 2022 05:02:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzbGlARZm4xsBSNTUP/X6KeEkj2SAC7OIrTReRcTETVUEbPe2fVIzKwiKavhDBnw7fpOtNy X-Received: by 2002:a05:6214:1c4e:b0:464:527c:2981 with SMTP id if14-20020a0562141c4e00b00464527c2981mr28783492qvb.39.1654776122574; Thu, 09 Jun 2022 05:02:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654776122; cv=none; d=google.com; s=arc-20160816; b=nlOru40Wr1aBKYT6sAz+MltHpR+hbDzbvkIujqHCmrItqwswEva4YI2wLxt4+JVb2w AWdwUOLPqIQep4xTAeZ0dga/510axEfS1G6xQ3vC4qFayWyOcp1iQTB9N4Zc+eMvJDHW zKGO6d/Dbke0koNkct6EwaXXIZBY4LfxnMDk3BMc7ufktjT/E7NYbV9EbH8yQ7NCI80T 9T+9AGl+dXnqC2r6QC+X+a6TzRtsHc1JOIC3xXWdVUWGRURelV9yTC3K/PLBpnX1yHGR 1x4V8s8/b75xsB8a1/TVelrpN+inj34BI9EPc+LXk6qvS7oMdje7SV1dtkmuDeQ5Z5Ba wA7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AJUvIhNABE7+bpF4sZrKJZdKNVK1oDZ/5Hrds64VDKo=; b=UtO/6oT87cO98a0Ue0bRByy0LV8eY+Q3LatyM1G80OO51d+UyVE3PDY7jDfFMPU6OZ HiCaFlaCzmKR9t+UX1vVv59xkV6OAjLeDSUpctuSe5Fcmrx7GAuVjiKCkqI9D/IEK01A 1tOEEL9IY1kZrsPZiV8b6GZeiaktEODaIDcV/So0iR1tVBMvEHrsMsgWvlAMx0T4c5EO 4SyC0xf0vdLuqwJuyagHhvOV65zoaijRHqUk+ik0+yrwPE3EEaqjY9SWUFYAgFbrlwfT zg1DQDQRsQdY+mv5gfAv3mUu/4Uc1haWOc+5Z9fFqmi/mbA/P5PKdAo/cDQ8dYF+B/IP ZDmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yCJDWWLB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id hu2-20020a056214234200b00461eff5f9b8si9240464qvb.250.2022.06.09.05.02.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jun 2022 05:02:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yCJDWWLB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzGrR-0001ms-TZ for patch@linaro.org; Thu, 09 Jun 2022 08:02:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40086) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzE7k-0001oz-A9 for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:40 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:33709) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzE7i-00063a-9r for qemu-devel@nongnu.org; Thu, 09 Jun 2022 05:06:40 -0400 Received: by mail-wr1-x433.google.com with SMTP id h5so31518410wrb.0 for ; Thu, 09 Jun 2022 02:06:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=AJUvIhNABE7+bpF4sZrKJZdKNVK1oDZ/5Hrds64VDKo=; b=yCJDWWLBX8grHJ4kdbYX8pcy0jMpbW6pyqvqAWJedSJ+mPEfUKYOEH1kqqbSNGVx4T xwxRPLIvaRUibpw9yCDXsHI/pB6kqmsqsvVosbZcF0WnG6vIdfeoLuKs4qxL9Np0VVC9 IRcYo2C1b3keoWXeTMdLPcTX4acK3xdxO6lzy1Avubv7vLUfxve+DMC0lNjEqNEmucYU LXXJRZpVnUi9t9vFnoS480ZM0iyua1Fzx7aInfz3sVpe90n6bvvuGC+EkMry04G4g2V+ mBFv+IfaRRsivsiFlrgARm4PhEzPJGMDResMrgeNStsMCZIz6RbGeMRs1OPMRPjD1k/h 6+yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AJUvIhNABE7+bpF4sZrKJZdKNVK1oDZ/5Hrds64VDKo=; b=ErzC7E2acdr1kCcFD6MkpZdWIqs2ETLDHTbbW19oIp4HuI9IJSsKbe/9fa+YKPYd4H LPxw4e874y/jLJqh/j630ZUMN9ORV/R5WwwBcEWFJCCrGrVh0njAt/q6nQJLp+tTI8ed uyf4pCs2SJPgSOHBQ6wPuSuTsFK6ELFIyrpR34iA7b+Oo1mkj3v2plyu2so4R0mXLcMa jUbCYXKB/7R/qZFYB4mT5zfbotPvSOxofnST8t0WgzH+CsR2jmT9llHLNIrtNzFK6rDF ZiJILsWLxQ+0FMudoYoOZ3IcNB1weKSS8DgXuZ82YYg5+rI6g2VYWfuvL28DBWMz5ykF Wr4g== X-Gm-Message-State: AOAM532CQk/GTTC0cA4OSgecFXaQ+PtVKEpCPA8Tz0UCqveVs0B3dKH/ jeir+FYuiO8+jKW4/yFHWABbTgejxR1cUg== X-Received: by 2002:adf:eccd:0:b0:212:fbbc:79de with SMTP id s13-20020adfeccd000000b00212fbbc79demr35777097wro.520.1654765597488; Thu, 09 Jun 2022 02:06:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 55/55] target/arm: Add ID_AA64SMFR0_EL1 Date: Thu, 9 Jun 2022 10:05:37 +0100 Message-Id: <20220609090537.1971756-56-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220609090537.1971756-1-peter.maydell@linaro.org> References: <20220609090537.1971756-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This register is allocated from the existing block of id registers, so it is already RES0 for cpus that do not implement SME. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220607203306.657998-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 25 +++++++++++++++++++++++++ target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 11 +++++++---- 3 files changed, 34 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2e6153c5409..78dbcb5592c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -966,6 +966,7 @@ struct ArchCPU { uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; uint64_t id_aa64zfr0; + uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; } isar; uint64_t midr; @@ -2190,6 +2191,15 @@ FIELD(ID_AA64ZFR0, I8MM, 44, 4) FIELD(ID_AA64ZFR0, F32MM, 52, 4) FIELD(ID_AA64ZFR0, F64MM, 56, 4) +FIELD(ID_AA64SMFR0, F32F32, 32, 1) +FIELD(ID_AA64SMFR0, B16F32, 34, 1) +FIELD(ID_AA64SMFR0, F16F32, 35, 1) +FIELD(ID_AA64SMFR0, I8I32, 36, 4) +FIELD(ID_AA64SMFR0, F64F64, 48, 1) +FIELD(ID_AA64SMFR0, I16I64, 52, 4) +FIELD(ID_AA64SMFR0, SMEVER, 56, 4) +FIELD(ID_AA64SMFR0, FA64, 63, 1) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) @@ -4195,6 +4205,21 @@ static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; } +static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); +} + +static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf; +} + +static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 400f7cd1dba..ac9942d750d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7722,11 +7722,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, .resetvalue = cpu->isar.id_aa64zfr0 }, - { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64SMFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64smfr0 }, { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index b3f635fc952..ff8f65da22f 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -574,6 +574,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) } else { err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, ARM64_SYS_REG(3, 0, 0, 4, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, + ARM64_SYS_REG(3, 0, 0, 4, 5)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, ARM64_SYS_REG(3, 0, 0, 5, 0)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, @@ -682,10 +684,11 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ahcf->isar.id_aa64pfr0 = t; /* - * Before v5.1, KVM did not support SVE and did not expose - * ID_AA64ZFR0_EL1 even as RAZ. After v5.1, KVM still does - * not expose the register to "user" requests like this - * unless the host supports SVE. + * There is a range of kernels between kernel commit 73433762fcae + * and f81cb2c3ad41 which have a bug where the kernel doesn't expose + * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled + * SVE support, so we only read it here, rather than together with all + * the other ID registers earlier. */ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, ARM64_SYS_REG(3, 0, 0, 4, 4));