From patchwork Wed Jun 8 10:22:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC8D6C433EF for ; Wed, 8 Jun 2022 10:30:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236786AbiFHKaY (ORCPT ); Wed, 8 Jun 2022 06:30:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238194AbiFHK35 (ORCPT ); Wed, 8 Jun 2022 06:29:57 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86B0AA3C32 for ; Wed, 8 Jun 2022 03:22:13 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id u26so31774659lfd.8 for ; Wed, 08 Jun 2022 03:22:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JPW5UrM16VIb0V7/sU8bftbljN5lwsuQwzROP9bFs3c=; b=WwR9ZBulDvF+VzUXyjppAsv7PC22ucgd6TMWxnl6ilFGusLm+jcBOi/++JDfNsXyWt gLDmO+Hyj+lCM6MXA/YQTr/ewf84Wt4TqA9JDcQT5g6kYfjHWKR5rXeT1H3lUpRFKdkM ThIQui1BPduLWKjrX+8agPCVKtIlA7KFOSpE8CzGL1gkfRT+LaDhDMzebB6DoOZ7E4NA 0eNvsMPqW1aPB1TXsTvtx0ErwYqUxjeIWN4Qh6oWaBVaB8BEU6PYFAsp9MdD9xXPfToK q8+W8+vIK6SJRDTg51FcKTFRSULwsvFXdxBeh6y1ythTSpMwrONFcSbYRLbj6riT0+EI CwDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JPW5UrM16VIb0V7/sU8bftbljN5lwsuQwzROP9bFs3c=; b=Q3sE95PPzyG7hpL5Th8PrDnGBsV5P4N/lkM99BVpxnBjtI/oA/iaCuIPy2l3mD2EwI ViEklCfjXiW88HnIdzKNLmflrZOY+IufBFs+T6kfkXSnlQWNY08rSHZkb9cuhClLyqST YE1ZdikJ8S0IsK0DCWqOuf+AHC3PyQI+5QhnvSnwLfr+yY1z8MoAdYXv/Fx94JOvNga9 m7ygvTZYxANjjbSFH0w/0TLjJVC1C7S5GWqPFRRzh3uu7qkkm1fILbNSjBbmdSbuNaqp ELAidP2pU5pzogJlg6C50aRR4GZZdpvRvsOzGxLruzbjaIxuD/mbbRyx76oufJElSLRM 4G0w== X-Gm-Message-State: AOAM531CgvO/a9pL5GiXWSrtWvogcTeFOfbn6lhKBMU/Z5UjSkvEMLY9 2a9FVpaVQCeC+3w9XYyDFVmqcg== X-Google-Smtp-Source: ABdhPJwbkYmZfTV4CYj1/ovm9TEu6RD3OSam5XSvUY2TsC3JKBp7hCKz+V63+800AMNjAKutM3YZPQ== X-Received: by 2002:a05:6512:2286:b0:479:7a60:5e42 with SMTP id f6-20020a056512228600b004797a605e42mr1568944lfu.625.1654683731603; Wed, 08 Jun 2022 03:22:11 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v1-20020ac25601000000b00478fe3327aasm3642934lfd.217.2022.06.08.03.22.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 03:22:11 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Johan Hovold , Rob Herring , Johan Hovold Subject: [PATCH v14 1/7] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Date: Wed, 8 Jun 2022 13:22:02 +0300 Message-Id: <20220608102208.2967438-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608102208.2967438-1-dmitry.baryshkov@linaro.org> References: <20220608102208.2967438-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The subdrivers pass -ESOMETHING if they do not want the core to touch MSI IRQ. dw_pcie_host_init() also checks if (msi_irq > 0) rather than just if (msi_irq). So let's make dw_pcie_free_msi() also check that msi_irq is greater than zero. Reviewed-by: Rob Herring Reviewed-by: Johan Hovold Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-designware-host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 9979302532b7..af91fe69f542 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -257,7 +257,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) static void dw_pcie_free_msi(struct pcie_port *pp) { - if (pp->msi_irq) + if (pp->msi_irq > 0) irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL); irq_domain_remove(pp->msi_domain); From patchwork Wed Jun 8 10:22:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579978 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96022CCA485 for ; Wed, 8 Jun 2022 10:30:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237245AbiFHKan (ORCPT ); Wed, 8 Jun 2022 06:30:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238188AbiFHK34 (ORCPT ); Wed, 8 Jun 2022 06:29:56 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5682195910 for ; Wed, 8 Jun 2022 03:22:15 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id y15so16787153ljc.0 for ; Wed, 08 Jun 2022 03:22:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PAZRY+9de/r/pRtDdwgg/SxpOS6YpBHgoxmPS8uwmeY=; b=bRXPsxn8jK6DstsXeLEpTv79XjGtFN/b+yIy0griFq1V4aggDfXVpLvd/cJCTqnymd 3DlZBDVZQJktWgvo6NCLVE4DdSXbH5YcIBhBTxphdxgZS1eQBsB0k/t1Xc//60M7omF5 XlZrCMzd4s/axItdIekwrKOfna6sNguSUCrGc/2HU2jcUZo+zIVJjQ7eCdoQQw6YqmQ4 l3bJ2kQML4B9zrJDxGUNIrgawcmT2WtSZ/vNO1fEntK7SmfHK4nICcnT9RMTYWrLxiHt 1L7fFTyNzk0hyqNp6Z4v2NC7h7hRgaqVP4hgt+RslNuyxII5oxg/wt26w41yompGSDI+ g/Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PAZRY+9de/r/pRtDdwgg/SxpOS6YpBHgoxmPS8uwmeY=; b=YIl8NgQdda8E0w3J97ua+McMUttLWmT1+58nyhITz1NA4xvWK6YQqt3x8GVPobKLK4 RN7hGn/BAibhJb5DZzZxUBoZdV3LaUZYD5mdiW+z+nkSS6hbQNSxAhSqljvBtXYcNy8J XNhB4S9a3q0zf95bDy6fEp3mxkWk62LdxbffCH1zMmARjf9AGyeSG3JYOkRBieee7AVv /t1kdJZHhx67O1bKQ9lXLGwO4d95n7Cv3c6c5peqI8FhPEb2KjQrltPwqL0dH9W6sW5q mU2pr+38+AyTi9TIzjfeK8WZyI0syIXAXWV6R+CQPk0n2AjniRv6dNJFr6ve7USzHDRa D1iw== X-Gm-Message-State: AOAM530EQN354p9JRa3Gcbsp4CcCc803Df0CvkCfNShSHapIhSZVWIk/ VXA0uNBc0DNSJVGH55ZtBx6uYQ== X-Google-Smtp-Source: ABdhPJzXjRXru7y049FWjmAalRSo/l4qehPqqPUWUsQ62KGTO0RfO+JmFt2PeclHDP26OdCVJzzyVg== X-Received: by 2002:a05:651c:101:b0:250:896d:f870 with SMTP id a1-20020a05651c010100b00250896df870mr55894808ljb.235.1654683733975; Wed, 08 Jun 2022 03:22:13 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v1-20020ac25601000000b00478fe3327aasm3642934lfd.217.2022.06.08.03.22.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 03:22:13 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Johan Hovold , Rob Herring , Johan Hovold Subject: [PATCH v14 3/7] PCI: dwc: split MSI IRQ parsing/allocation to a separate function Date: Wed, 8 Jun 2022 13:22:04 +0300 Message-Id: <20220608102208.2967438-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608102208.2967438-1-dmitry.baryshkov@linaro.org> References: <20220608102208.2967438-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Split handling of MSI host IRQs to a separate dw_pcie_msi_host_init() function. The code is complex enough to warrant a separate function. Reviewed-by: Rob Herring Reviewed-by: Johan Hovold Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 100 ++++++++++-------- 1 file changed, 57 insertions(+), 43 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 96b6196f870b..85c1160792e1 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -289,6 +289,61 @@ static void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); } +static int dw_pcie_msi_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + struct platform_device *pdev = to_platform_device(dev); + int ret; + u32 ctrl, num_ctrls; + + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + for (ctrl = 0; ctrl < num_ctrls; ctrl++) + pp->irq_mask[ctrl] = ~0; + + if (!pp->msi_irq[0]) { + int irq = platform_get_irq_byname_optional(pdev, "msi"); + + if (irq < 0) { + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + } + pp->msi_irq[0] = irq; + } + + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + + ret = dw_pcie_allocate_domains(pp); + if (ret) + return ret; + + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { + if (pp->msi_irq[ctrl] > 0) + irq_set_chained_handler_and_data(pp->msi_irq[ctrl], + dw_chained_msi_isr, + pp); + } + + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); + if (ret) + dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); + + pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, + sizeof(pp->msi_msg), + DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC); + ret = dma_mapping_error(pci->dev, pp->msi_data); + if (ret) { + dev_err(pci->dev, "Failed to map MSI data\n"); + pp->msi_data = 0; + dw_pcie_free_msi(pp); + return ret; + } + + return 0; +} + int dw_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -366,50 +421,9 @@ int dw_pcie_host_init(struct pcie_port *pp) if (ret < 0) return ret; } else if (pp->has_msi_ctrl) { - u32 ctrl, num_ctrls; - - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - for (ctrl = 0; ctrl < num_ctrls; ctrl++) - pp->irq_mask[ctrl] = ~0; - - if (!pp->msi_irq[0]) { - int irq = platform_get_irq_byname_optional(pdev, "msi"); - - if (irq < 0) { - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - } - pp->msi_irq[0] = irq; - } - - pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; - - ret = dw_pcie_allocate_domains(pp); - if (ret) + ret = dw_pcie_msi_host_init(pp); + if (ret < 0) return ret; - - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { - if (pp->msi_irq[ctrl] > 0) - irq_set_chained_handler_and_data(pp->msi_irq[ctrl], - dw_chained_msi_isr, - pp); - } - - ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); - if (ret) - dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); - - pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, - sizeof(pp->msi_msg), - DMA_FROM_DEVICE, - DMA_ATTR_SKIP_CPU_SYNC); - ret = dma_mapping_error(pci->dev, pp->msi_data); - if (ret) { - dev_err(pci->dev, "Failed to map MSI data\n"); - pp->msi_data = 0; - goto err_free_msi; - } } } From patchwork Wed Jun 8 10:22:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDEF3C433EF for ; Wed, 8 Jun 2022 10:30:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237338AbiFHKau (ORCPT ); Wed, 8 Jun 2022 06:30:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238224AbiFHK35 (ORCPT ); Wed, 8 Jun 2022 06:29:57 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C46350078 for ; Wed, 8 Jun 2022 03:22:17 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id t25so32474185lfg.7 for ; Wed, 08 Jun 2022 03:22:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2by5Bt/vQS1TmQjI5mkgsiE5z/umI6jxynKNxO746d4=; b=PHXZX+uJzXSI2P0g9qdj0yl8r21DoGlyFIX+fPxSmmmP8lX6TenY95q3PC2GoBzSzm GYKb9Mf8lV4PTevXPA+KPmjn3XoFhNl9MI192oEqZurSf07DATQZjYkzc9wHAjeUejFC 1mZdLcbW2/NzI4mYPQ2RnzNQcme+iClMyiM0ihKVMpaNbOwYo+grZbULFb8SkqwKdHTE 7SgnsHoB29UBTzquF9p+8s1C84I/h2P7VBF4s9AV0ovPxY7s3czL3uZkI+YwpGs7/jN5 SkuoeuIiknz2aqv3gnjmCBKxaff8gvG4xPT2+Ku9B4O110jNCTHoRhFe7eOYN1lDAn1y pPiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2by5Bt/vQS1TmQjI5mkgsiE5z/umI6jxynKNxO746d4=; b=z5u8lKtRxo7NQbf7ANbIgrs8Ar6j+oSbJGteI69hkCLhSlXjj/eR4KClWxhdFVt1ks c0MoPkdMc3Hpo+Mty9Azer6tISY6L9JH80u7cCfUdr7zEqX08YGEEArEmDHWj40ruOV8 rjW2gybiysmNl73vdjXHeE0z85EMWLG2QY0JVjrHZLQNI/37owGm0BLPWxB/vvuTUQZx hxzO/CCax/43LS+ON5rE/rJkReD5pRT/Tp39y9282JiQsxlvvXkStW5gbvGYvQMs6Xgu 69DbcA27A4eZtsj0QcPeZWt5N535N2D4FpO7MJqofrUawOwfyJn+QRZRV1/G8Xfgdnhz EpSA== X-Gm-Message-State: AOAM5304ZXk4wlj0dduBbXnmYREtmtx18O5krClvEVNeeD7sTR4xVUHE EmCyOqzednSncfdw9JmN8f/54w== X-Google-Smtp-Source: ABdhPJwhtC3H5Wj5I+u/XLrk1Qz7bQ74NSxgJqoQjbuFMOax0L6gS7S8ndUbXXP9jZI2munGntDkaw== X-Received: by 2002:a05:6512:c04:b0:478:f837:d813 with SMTP id z4-20020a0565120c0400b00478f837d813mr22338524lfu.17.1654683735150; Wed, 08 Jun 2022 03:22:15 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v1-20020ac25601000000b00478fe3327aasm3642934lfd.217.2022.06.08.03.22.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 03:22:14 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Johan Hovold , Rob Herring , Johan Hovold Subject: [PATCH v14 4/7] PCI: dwc: Handle MSIs routed to multiple GIC interrupts Date: Wed, 8 Jun 2022 13:22:05 +0300 Message-Id: <20220608102208.2967438-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608102208.2967438-1-dmitry.baryshkov@linaro.org> References: <20220608102208.2967438-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On some of Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Implement support for such configurations by parsing "msi0" ... "msiN" interrupts and attaching them to the chained handler. Note, that if DT doesn't list an array of MSI interrupts and uses single "msi" IRQ, the driver will limit the amount of supported MSI vectors accordingly (to 32). Reviewed-by: Rob Herring Reviewed-by: Johan Hovold Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 63 +++++++++++++++++-- 1 file changed, 59 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 85c1160792e1..26b50948d6fc 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -289,6 +289,46 @@ static void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); } +static int dw_pcie_parse_split_msi_irq(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + struct platform_device *pdev = to_platform_device(dev); + int irq; + u32 ctrl, max_vectors; + + /* Parse as many IRQs as described in the devicetree. */ + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) { + char msi_name[] = "msiX"; + + msi_name[3] = '0' + ctrl; + irq = platform_get_irq_byname_optional(pdev, msi_name); + if (irq == -ENXIO) + break; + if (irq < 0) + return dev_err_probe(dev, irq, + "Failed to parse MSI IRQ '%s'\n", + msi_name); + + pp->msi_irq[ctrl] = irq; + } + + /* If there were no "msiN" IRQs at all, fallback to the standard "msi" IRQ. */ + if (ctrl == 0) + return -ENXIO; + + max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL; + if (pp->num_vectors > max_vectors) { + dev_warn(dev, "Exceeding number of MSI vectors, limiting to %u\n", + max_vectors); + pp->num_vectors = max_vectors; + } + if (!pp->num_vectors) + pp->num_vectors = max_vectors; + + return 0; +} + static int dw_pcie_msi_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -297,21 +337,32 @@ static int dw_pcie_msi_host_init(struct pcie_port *pp) int ret; u32 ctrl, num_ctrls; - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - for (ctrl = 0; ctrl < num_ctrls; ctrl++) + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) pp->irq_mask[ctrl] = ~0; + if (!pp->msi_irq[0]) { + ret = dw_pcie_parse_split_msi_irq(pp); + if (ret < 0 && ret != -ENXIO) + return ret; + } + + if (!pp->num_vectors) + pp->num_vectors = MSI_DEF_NUM_VECTORS; + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + if (!pp->msi_irq[0]) { int irq = platform_get_irq_byname_optional(pdev, "msi"); if (irq < 0) { irq = platform_get_irq(pdev, 0); if (irq < 0) - return irq; + return dev_err_probe(dev, irq, "Failed to parse MSI irq\n"); } pp->msi_irq[0] = irq; } + dev_dbg(dev, "Using %d MSI vectors\n", pp->num_vectors); + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; ret = dw_pcie_allocate_domains(pp); @@ -409,7 +460,11 @@ int dw_pcie_host_init(struct pcie_port *pp) of_property_read_bool(np, "msi-parent") || of_property_read_bool(np, "msi-map")); - if (!pp->num_vectors) { + /* + * For the has_msi_ctrl case the default assignment is handled + * in the dw_pcie_msi_host_init(). + */ + if (!pp->has_msi_ctrl && !pp->num_vectors) { pp->num_vectors = MSI_DEF_NUM_VECTORS; } else if (pp->num_vectors > MAX_MSI_IRQS) { dev_err(dev, "Invalid number of vectors\n");