From patchwork Mon Jan 14 13:24:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155463 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3655041jaa; Mon, 14 Jan 2019 05:25:25 -0800 (PST) X-Google-Smtp-Source: ALg8bN7Dw/rrOauSjSzeOMTr23cFg/xMugt17hwR07N6AMznsevfXmRkXQrDVw7ziCET+uR1qx7T X-Received: by 2002:a17:902:47aa:: with SMTP id r39mr25223234pld.219.1547472325709; Mon, 14 Jan 2019 05:25:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472325; cv=none; d=google.com; s=arc-20160816; b=yv44pUOJKZ+2sAp4XbYevjc5XiKifAp50BH19+ZN+w5dzh33d9a+gECF6GH4WuPvC9 BjywS2JJp4bPt0j3KLwvNWXjMlYsPtcBfA1XA4wM5rpg6flakkS2YMLmpIwilJc9kv/J gZXU5Z/g2GuhJVN+eOGYxS/Q8RdeppdNLX9JNGJ113fQSGE+XC/YL8m8eO7XVIYJWQXQ IQN0S9qaCf460eWctPtjY4XFayJaa1Er8ofKSQoQioR4pGzf+e0D5SLBTk7WzK55QY1U L5dNQEPH2yWElO5zWzIOW0RYDdzNhsSy6tnLRprPKbhI1Rccnsjq4VM8wo7isjDOv3NY 0RnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=NtKe2jericu7SZi4WCZJdZomxBVNvIwuxybIlJmjYW0=; b=FNOE5PgwbeZdGmJ4BavYzqUgZ5ty/uTFiv+pD6NqR+AiRPmbje+Qia7CEfkNgPDeeX 5VFRWq1A3m71NeL1ZExi3YTxX+q6RYuA3Rq/6llNP/+C3BMmA2R8qDf/CVGNODK4/aYC 0jaCwn8tNq2m5S2eEVraPANJOcClnJ8j6H80pfwgAAvaJwTbSMXCA29SUqP8u1u4U5vd wvUSQLVhUR6YS+/ENRhafZd8l1TqW9NjTa00i3pDeeAXMxuneVrnUrWjqt6M78hTrR0R Hm4yAXFNF9cc/w00uPOF0Aybw1qnXJIvrnkBCNbcW3aBNVsYhkeVfsfmRVX11meorggU yl+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ZoJMJ1UD; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 97si330416plm.312.2019.01.14.05.25.25; Mon, 14 Jan 2019 05:25:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ZoJMJ1UD; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726675AbfANNZY (ORCPT + 7 others); Mon, 14 Jan 2019 08:25:24 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:40920 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726525AbfANNZY (ORCPT ); Mon, 14 Jan 2019 08:25:24 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDP6Tn019195; Mon, 14 Jan 2019 07:25:06 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472306; bh=NtKe2jericu7SZi4WCZJdZomxBVNvIwuxybIlJmjYW0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZoJMJ1UDlKF49D1BkkOd3yN5yxSOPLnDFdTCZvitzuZ3lbqbVPhY8qraal+Ibh0FB YKnssgPPzJ7jk1v07k28HhwQ+x20X5X/kGi57IjFmM2HFOGGYGyZmL/OY/XUAYHTe+ KRtGGo488jF/peCKVIAtRre590cFDMVj0GsQLAyw= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDP5j9088411 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:25:06 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:25:05 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:25:05 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWO028516; Mon, 14 Jan 2019 07:25:01 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 02/24] PCI: keystone: Cleanup error_irq configuration Date: Mon, 14 Jan 2019 18:54:02 +0530 Message-ID: <20190114132424.6445-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org pci-keystone driver uses irq_of_parse_and_map to get irq number of error_irq. Use platform_get_irq instead and move platform_get_irq() and request_irq() of error_irq from ks_pcie_add_pcie_port to ks_pcie_probe since error_irq is common to both RC mode and EP mode. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 43 +++++++++-------------- 1 file changed, 17 insertions(+), 26 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 24c38ae570b5..f63268aee2de 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -97,8 +97,6 @@ struct keystone_pcie { struct irq_domain *legacy_irq_domain; struct device_node *np; - int error_irq; - /* Application register space */ void __iomem *va_app_base; /* DT 1st resource */ struct resource app; @@ -726,12 +724,6 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) return ret; } -static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie) -{ - if (ks_pcie->error_irq > 0) - ks_pcie_enable_error_irq(ks_pcie); -} - /* * When a PCI device does not exist during config cycles, keystone host gets a * bus error instead of returning 0xffffffff. This handler always returns 0 @@ -793,7 +785,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) ks_pcie_stop_link(pci); ks_pcie_setup_rc_app_regs(ks_pcie); - ks_pcie_setup_interrupts(ks_pcie); writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), pci->dbi_base + PCI_IO_BASE); @@ -837,23 +828,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct device *dev = &pdev->dev; int ret; - /* - * Index 0 is the platform interrupt for error interrupt - * from RC. This is optional. - */ - ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0); - if (ks_pcie->error_irq <= 0) - dev_info(dev, "no error IRQ defined\n"); - else { - ret = request_irq(ks_pcie->error_irq, ks_pcie_err_irq_handler, - IRQF_SHARED, "pcie-error-irq", ks_pcie); - if (ret < 0) { - dev_err(dev, "failed to request error IRQ %d\n", - ks_pcie->error_irq); - return ret; - } - } - pp->ops = &ks_pcie_host_ops; ret = ks_pcie_dw_host_init(ks_pcie); if (ret) { @@ -929,6 +903,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) u32 num_lanes; char name[10]; int ret; + int irq; int i; ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); @@ -948,6 +923,20 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return ret; } + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "missing IRQ resource: %d\n", irq); + return irq; + } + + ret = request_irq(irq, ks_pcie_err_irq_handler, IRQF_SHARED, + "ks-pcie-error-irq", ks_pcie); + if (ret < 0) { + dev_err(dev, "failed to request error IRQ %d\n", + irq); + return ret; + } + ret = of_property_read_u32(np, "num-lanes", &num_lanes); if (ret) num_lanes = 1; @@ -1003,6 +992,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) if (ret < 0) goto err_get_sync; + ks_pcie_enable_error_irq(ks_pcie); + return 0; err_get_sync: From patchwork Mon Jan 14 13:24:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155474 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3656693jaa; Mon, 14 Jan 2019 05:26:50 -0800 (PST) X-Google-Smtp-Source: ALg8bN6/GSABwofTqJPeoG8PzGLl5LBFO5Fci2nhi2IDNfefqyo2j/M4WCFpBCT0AkPkih0XRpu4 X-Received: by 2002:a62:8d4f:: with SMTP id z76mr26123747pfd.2.1547472410377; Mon, 14 Jan 2019 05:26:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547472410; cv=none; d=google.com; s=arc-20160816; b=XC+GAqQxSkvD5Re1UTE4OpJUrWsdb90usCVeHLrbyJe125nuw8yY50yW+XytKJg82D 7W7l6cLnRuLLtqnDCrRLo+9Ki7gDU9T6uAxdilD8D+nWR17vW56wiH3L1Ue9/hbfCpVC iJzm4PnyAX0hzpDvG65h/Cg/5nEi7F7sZPvTBQc17sjU1vjHyXbCV3DQJ/p8fWRuzm9P sosgvrhQm449VA0KNuj4UboWODxI0+SJZwhTfz1uYeu1iUTRjMyHJazwbabMYW73fuGr QLNMXhK7zXr38gJjf9ffF/cevdSG6jbK0ahZslgNXNAp4DmJjplmZW8GwYf8jIt4S6eJ ocXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=JBZ+KApRI2tD19Gjs/0efSSSLgbMPMBQuRhTfDhOm2w=; b=Wb03Ml14/mwso1tpK/7KzEBhnACRm3HTUR39LIQlj3QbzV/m+ToIsp1hAWHRg3xAjd XtxOSbJqNcBs4i+eGmU4QXV9LGGy562cqL2rG0jmLQFEi4Cz6Toye3euLeBKoSgbUl/F oEp3hvFnpOt6C5suMLzIxYp56IT7fh5oAJaJ0EpUx6/cRY1flqPN1POiJlZ0rTp9+1tW dUH0KhUIE1ArfsqZohjYhMR6vi/4oGDc9mJJD/sjPZmV9zfJpGXhK2f/kYD5FMjCsoOF 3WNN9URD1yGpV/s+3PlwzI0R79uMWYWB/kdQw/dmennTCsXlvxC+XS8NPJprPKIFjdb0 lqXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=az+c5PAy; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o13si319419pgp.540.2019.01.14.05.26.50; Mon, 14 Jan 2019 05:26:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=az+c5PAy; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726652AbfANN0s (ORCPT + 7 others); Mon, 14 Jan 2019 08:26:48 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37462 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726899AbfANN0s (ORCPT ); Mon, 14 Jan 2019 08:26:48 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQEa8098245; Mon, 14 Jan 2019 07:26:14 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472374; bh=JBZ+KApRI2tD19Gjs/0efSSSLgbMPMBQuRhTfDhOm2w=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=az+c5PAyuQYI/R4OJ6Yb4NImGUbk5jupD15MptWEu+9jq8Vjepl8fvI5GhZ1VDFtN 0JBWxlxcCdNaFAo0lsw1aXpSFqGOMvp4NY2uqZGX2+fQHS3qFXPyDTuI4BO1JRlt9B ieAwuUla1SUZN6P/xy1KzbzAtIDHBP37WeZD57bc= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQExh057326 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:14 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:13 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:12 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWc028516; Mon, 14 Jan 2019 07:26:09 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 16/24] PCI: endpoint: Add support to allocate aligned buffers to be mapped in BARs Date: Mon, 14 Jan 2019 18:54:16 +0530 Message-ID: <20190114132424.6445-17-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Modify pci_epf_alloc_space API to take alignment size as argument in order to argument in order to allocate aligned buffers to be mapped to BARs. Add 'align' parameter to epc_features which can be used by platform drivers to specifiy the BAR allocation alignment requirements and use this while invoking pci_epf_alloc_space. This is mainly required for Synopsys Designware PCIe core which masks the lower bits based on the BAR size (See "I/O and MEM Match Modes" section in DesignWare Cores PCI Express Controller Databook version 4.90a). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/functions/pci-epf-test.c | 5 +++-- drivers/pci/endpoint/pci-epf-core.c | 10 ++++++++-- include/linux/pci-epc.h | 2 ++ include/linux/pci-epf.h | 3 ++- 4 files changed, 15 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index 2e0fb231ce0c..faffae2551ed 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -438,7 +438,7 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf) epc_features = epf_test->epc_features; base = pci_epf_alloc_space(epf, sizeof(struct pci_epf_test_reg), - test_reg_bar); + test_reg_bar, epc_features->align); if (!base) { dev_err(dev, "Failed to allocated register space\n"); return -ENOMEM; @@ -453,7 +453,8 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf) if (!!(epc_features->reserved_bar & (1 << bar))) continue; - base = pci_epf_alloc_space(epf, bar_size[bar], bar); + base = pci_epf_alloc_space(epf, bar_size[bar], bar, + epc_features->align); if (!base) dev_err(dev, "Failed to allocate space for BAR%d\n", bar); diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index 8bfdcd291196..fb1306de8f40 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -109,10 +109,12 @@ EXPORT_SYMBOL_GPL(pci_epf_free_space); * pci_epf_alloc_space() - allocate memory for the PCI EPF register space * @size: the size of the memory that has to be allocated * @bar: the BAR number corresponding to the allocated register space + * @align: alignment size for the allocation region * * Invoke to allocate memory for the PCI EPF register space. */ -void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar) +void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, + size_t align) { void *space; struct device *dev = epf->epc->dev.parent; @@ -120,7 +122,11 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar) if (size < 128) size = 128; - size = roundup_pow_of_two(size); + + if (align) + size = ALIGN(size, align); + else + size = roundup_pow_of_two(size); space = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL); if (!space) { diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index c3ffa3917f88..f641badc2c61 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -109,6 +109,7 @@ struct pci_epc { * @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver * @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs * @bar_fixed_size: Array specifying the size supported by each BAR + * @align: alignment size required for BAR buffer allocation */ struct pci_epc_features { unsigned int linkup_notifier : 1; @@ -117,6 +118,7 @@ struct pci_epc_features { u8 reserved_bar; u8 bar_fixed_64bit; u64 bar_fixed_size[BAR_5 + 1]; + size_t align; }; #define to_pci_epc(device) container_of((device), struct pci_epc, dev) diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index ec02f58758c8..2d6f07556682 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -149,7 +149,8 @@ void pci_epf_destroy(struct pci_epf *epf); int __pci_epf_register_driver(struct pci_epf_driver *driver, struct module *owner); void pci_epf_unregister_driver(struct pci_epf_driver *driver); -void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar); +void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, + size_t align); void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar); int pci_epf_bind(struct pci_epf *epf); void pci_epf_unbind(struct pci_epf *epf); From patchwork Mon Jan 14 13:24:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 155484 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3657835jaa; Mon, 14 Jan 2019 05:27:49 -0800 (PST) X-Google-Smtp-Source: ALg8bN70AUe8P69zn+RCcsp1K4W7MOJAz761OjwxYde9+SFap0EQXNbBGMb2wiCfiaGyYZcrhkEn X-Received: by 2002:a63:6103:: with SMTP id v3mr12066959pgb.75.1547472469539; Mon, 14 Jan 2019 05:27:49 -0800 (PST) ARC-Seal: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id t20si331011pgl.211.2019.01.14.05.27.49; Mon, 14 Jan 2019 05:27:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=tk77drck; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726826AbfANN1s (ORCPT + 7 others); Mon, 14 Jan 2019 08:27:48 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:41154 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726717AbfANN1r (ORCPT ); Mon, 14 Jan 2019 08:27:47 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0EDQh1v041581; Mon, 14 Jan 2019 07:26:43 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1547472403; bh=CF5ivThAeVhsXGcV5WpV6w68ilrQQqK8YE1SR4Z9I10=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tk77drck6OKnLY9dkDBCKf0sySURytF9x0xxMOPFRCwcQZacNAStG107CmJDsQSmR r9+a5K2+EQ8KCsvpdbW4C/MY0hSXsdSyzqEbAPOAFj0g958OSBIGxdAPUCIUsSc3kt WtPG9Dy6s5YO1Q06AsX4zxT97WE4I625be1FHFCQ= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0EDQhtG089758 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 14 Jan 2019 07:26:43 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 14 Jan 2019 07:26:42 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 14 Jan 2019 07:26:42 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0EDOoWi028516; Mon, 14 Jan 2019 07:26:38 -0600 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Rob Herring , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , Mark Rutland , Arnd Bergmann , Greg Kroah-Hartman , Murali Karicheri , Jesper Nilsson , , , , , , Subject: [PATCH 22/24] PCI: designware-ep: Use aligned ATU window for raising MSI interrupts Date: Mon, 14 Jan 2019 18:54:22 +0530 Message-ID: <20190114132424.6445-23-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190114132424.6445-1-kishon@ti.com> References: <20190114132424.6445-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Certain platforms like K2G reguires the outbound ATU window to be aligned. The alignment size is already present in mem->page_size. Use the alignment size present in mem->page_size to configre a aligned ATU window. In order to raise an interrupt, CPU has to write to address offset from the start of the window unlike before where writes were always to the beginning of the ATU window. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 47cc06bac91f..f557e83bc34c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -397,6 +397,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct pci_epc *epc = ep->epc; + unsigned int aligned_offset; u16 msg_ctrl, msg_data; u32 msg_addr_lower, msg_addr_upper, reg; u64 msg_addr; @@ -422,13 +423,15 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, reg = ep->msi_cap + PCI_MSI_DATA_32; msg_data = dw_pcie_readw_dbi(pci, reg); } - msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower; + aligned_offset = msg_addr_lower & (epc->mem->page_size - 1); + msg_addr = ((u64)msg_addr_upper) << 32 | + (msg_addr_lower & ~aligned_offset); ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, epc->mem->page_size); if (ret) return ret; - writel(msg_data | (interrupt_num - 1), ep->msi_mem); + writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset); dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);