From patchwork Wed Jun 8 12:07:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E40ECCCA47E for ; Wed, 8 Jun 2022 12:07:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238667AbiFHMHd (ORCPT ); Wed, 8 Jun 2022 08:07:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238653AbiFHMHc (ORCPT ); Wed, 8 Jun 2022 08:07:32 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D30821B9A48 for ; Wed, 8 Jun 2022 05:07:27 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id c2so13469926lfk.0 for ; Wed, 08 Jun 2022 05:07:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VePBzYxQZCMYmePlwL3wtl0+0lRocvRBaNXocWAt7M4=; b=Ihtmv3hVfP8GlQ2ZrJSp5zl353vJCWBqL1/l/4ND1iPexqM6TZN8CHdn0PLPDkZ6Y5 PpJ0xj6EPXULKS1+y82qB+sVgA8XmiGOGzxiIo17eBnnFmCIP0gNlGzcQA/HROlnsEAu kREMad9Hct2zAIW4uDxvSLOJ3hz/TNQUIU+z26NlaI3rAcIwqJQKjUAm5JUSUzDnRbUg rS96RWLgSRAYYuJLtKXq1vIReiv8A+cRcLisSWlbJsFgC59xE1DZQ/nRfCMa2IF2e1UE uUAmzhLODSrsD+YByd3/M5xAzYsDtDIjOCtBdUu6FcbKc387A8infuIrr46BHNSVJ8Ov eBQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VePBzYxQZCMYmePlwL3wtl0+0lRocvRBaNXocWAt7M4=; b=s2flWyHn4skOfI0mvgjACPqC4/T1UaWeWMIe1a9hJBdu7yMawR+NwN/1s/2eFk9HCn SFYI3iMqMNCURh0G1wxBfGzr8m1RnJU9xChWTQwLAauQ+qWs3gfINCSQFbBLNbzGcemH W3c4cFJlYlNTD3l0cWI6CTuYJNFoIpcCP7qB8Wo1hMyw6SuV9BjubNSRLLiMZu6BsJYP e61kryknZ6PeljGAcvlLZ1uFZEGD6KfNXPvrM3xrRA/m7CNsKINTvIWWTLTvi7rB3abW 4zEBJIIuClbMlBITefKhcPTQ/A1LNEhIiNmubcRMV5mLXYKtlPNKy8kXpkH+QiBnK7W9 WJDA== X-Gm-Message-State: AOAM530XaPwnVMnuO+sSoa/AFLvWTrhtOynGzZteQEKPtsrKjBrG7bKM ZYNVTgdOcT7P0mvG1uYIeMa7qw== X-Google-Smtp-Source: ABdhPJynsH9N/Lo36AZTRYTbNatxhuHKEw2yG+X4/bzegyagfUFhMjpfdgQ63ZCEXTGcBKnpbe5hhA== X-Received: by 2002:a05:6512:ac9:b0:479:5b66:e9e9 with SMTP id n9-20020a0565120ac900b004795b66e9e9mr6684404lfu.581.1654690046115; Wed, 08 Jun 2022 05:07:26 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id 4-20020ac25f04000000b0047b0f2d7650sm52049lfq.271.2022.06.08.05.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 05:07:25 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, David Heidelberg Subject: [PATCH v2 01/12] dt-bindings: display/msm: hdmi: split and convert to yaml Date: Wed, 8 Jun 2022 15:07:12 +0300 Message-Id: <20220608120723.2987843-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608120723.2987843-1-dmitry.baryshkov@linaro.org> References: <20220608120723.2987843-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert Qualcomm HDMI binding into HDMI TX and PHY yaml bindings. Changes to schema: HDMI: - fixed reg-names numbering to match 0..3 instead 0,1,3,4 - dropped qcom,tx-ddc-* from example, they were not documented PHY: - moved into phy/ directory - split into QMP and non-QMP PHY schemas Co-developed-by: David Heidelberg Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/hdmi.txt | 99 -------- .../devicetree/bindings/display/msm/hdmi.yaml | 230 ++++++++++++++++++ .../bindings/phy/qcom,hdmi-phy-other.yaml | 103 ++++++++ .../bindings/phy/qcom,hdmi-phy-qmp.yaml | 83 +++++++ 4 files changed, 416 insertions(+), 99 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/msm/hdmi.txt create mode 100644 Documentation/devicetree/bindings/display/msm/hdmi.yaml create mode 100644 Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml create mode 100644 Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.txt b/Documentation/devicetree/bindings/display/msm/hdmi.txt deleted file mode 100644 index 5f90a40da51b..000000000000 --- a/Documentation/devicetree/bindings/display/msm/hdmi.txt +++ /dev/null @@ -1,99 +0,0 @@ -Qualcomm adreno/snapdragon hdmi output - -Required properties: -- compatible: one of the following - * "qcom,hdmi-tx-8996" - * "qcom,hdmi-tx-8994" - * "qcom,hdmi-tx-8084" - * "qcom,hdmi-tx-8974" - * "qcom,hdmi-tx-8660" - * "qcom,hdmi-tx-8960" -- reg: Physical base address and length of the controller's registers -- reg-names: "core_physical" -- interrupts: The interrupt signal from the hdmi block. -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: device clocks - See ../clocks/clock-bindings.txt for details. -- core-vdda-supply: phandle to supply regulator -- hdmi-mux-supply: phandle to mux regulator -- phys: the phandle for the HDMI PHY device -- phy-names: the name of the corresponding PHY device - -Optional properties: -- hpd-gpios: hpd pin -- qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin -- qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin -- qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin -- power-domains: reference to the power domain(s), if available. -- pinctrl-names: the pin control state names; should contain "default" -- pinctrl-0: the default pinctrl state (active) -- pinctrl-1: the "sleep" pinctrl state - -HDMI PHY: -Required properties: -- compatible: Could be the following - * "qcom,hdmi-phy-8660" - * "qcom,hdmi-phy-8960" - * "qcom,hdmi-phy-8974" - * "qcom,hdmi-phy-8084" - * "qcom,hdmi-phy-8996" -- #phy-cells: Number of cells in a PHY specifier; Should be 0. -- reg: Physical base address and length of the registers of the PHY sub blocks. -- reg-names: The names of register regions. The following regions are required: - * "hdmi_phy" - * "hdmi_pll" - For HDMI PHY on msm8996, these additional register regions are required: - * "hdmi_tx_l0" - * "hdmi_tx_l1" - * "hdmi_tx_l3" - * "hdmi_tx_l4" -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- core-vdda-supply: phandle to vdda regulator device node - -Example: - -/ { - ... - - hdmi: hdmi@4a00000 { - compatible = "qcom,hdmi-tx-8960"; - reg-names = "core_physical"; - reg = <0x04a00000 0x2f0>; - interrupts = ; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = - "core", - "master_iface", - "slave_iface"; - clocks = - <&mmcc HDMI_APP_CLK>, - <&mmcc HDMI_M_AHB_CLK>, - <&mmcc HDMI_S_AHB_CLK>; - qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>; - qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>; - qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>; - core-vdda-supply = <&pm8921_hdmi_mvs>; - hdmi-mux-supply = <&ext_3p3v>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hpd_active &ddc_active &cec_active>; - pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; - - phys = <&hdmi_phy>; - phy-names = "hdmi_phy"; - }; - - hdmi_phy: phy@4a00400 { - compatible = "qcom,hdmi-phy-8960"; - reg-names = "hdmi_phy", - "hdmi_pll"; - reg = <0x4a00400 0x60>, - <0x4a00500 0x100>; - #phy-cells = <0>; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = "slave_iface"; - clocks = <&mmcc HDMI_S_AHB_CLK>; - core-vdda-supply = <&pm8921_hdmi_mvs>; - }; -}; diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.yaml b/Documentation/devicetree/bindings/display/msm/hdmi.yaml new file mode 100644 index 000000000000..ef425c649ead --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/hdmi.yaml @@ -0,0 +1,230 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/display/msm/hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Adreno/Snapdragon HDMI output + +maintainers: + - Rob Clark + +properties: + compatible: + enum: + - qcom,hdmi-tx-8084 + - qcom,hdmi-tx-8660 + - qcom,hdmi-tx-8960 + - qcom,hdmi-tx-8974 + - qcom,hdmi-tx-8994 + - qcom,hdmi-tx-8996 + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + reg: + minItems: 1 + maxItems: 3 + + reg-names: + minItems: 1 + items: + - const: core_physical + - const: qfprom_physical + - const: hdcp_physical + + interrupts: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + enum: + - hdmi_phy + - hdmi-phy + + core-vdda-supply: + description: phandle to VDDA supply regulator + + hdmi-mux-supply: + description: phandle to mux regulator + + core-vcc-supply: + description: phandle to VCC supply regulator + + hpd-gpios: + maxItems: 1 + description: hpd pin + + qcom,hdmi-tx-mux-en-gpios: + maxItems: 1 + description: HDMI mux enable pin + + qcom,hdmi-tx-mux-sel-gpios: + maxItems: 1 + description: HDMI mux select pin + + qcom,hdmi-tx-mux-lpm-gpios: + maxItems: 1 + description: HDMI mux lpm pin + + '#sound-dai-cells': + const: 1 + + ports: + type: object + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + description: | + Input endpoints of the controller. + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + description: | + Output endpoints of the controller. + + required: + - port@0 + +required: + - compatible + - clocks + - clock-names + - reg + - reg-names + - interrupts + - phys + - phy-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,hdmi-tx-8960 + - qcom,hdmi-tx-8660 + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: core + - const: master_iface + - const: slave_iface + core-vcc-supplies: false + + - if: + properties: + compatible: + contains: + enum: + - qcom,hdmi-tx-8974 + - qcom,hdmi-tx-8084 + - qcom,hdmi-tx-8994 + - qcom,hdmi-tx-8996 + then: + properties: + clocks: + minItems: 5 + clock-names: + items: + - const: mdp_core + - const: iface + - const: core + - const: alt_iface + - const: extp + hdmi-mux-supplies: false + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmi: hdmi@4a00000 { + compatible = "qcom,hdmi-tx-8960"; + reg-names = "core_physical"; + reg = <0x04a00000 0x2f0>; + interrupts = ; + clock-names = "core", + "master_iface", + "slave_iface"; + clocks = <&clk 61>, + <&clk 72>, + <&clk 98>; + hpd-gpios = <&msmgpio 72 GPIO_ACTIVE_HIGH>; + core-vdda-supply = <&pm8921_hdmi_mvs>; + hdmi-mux-supply = <&ext_3p3v>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hpd_active &ddc_active &cec_active>; + pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; + + phys = <&hdmi_phy>; + phy-names = "hdmi_phy"; + }; + - | + #include + #include + #include + #include + #include + hdmi@9a0000 { + compatible = "qcom,hdmi-tx-8996"; + reg = <0x009a0000 0x50c>, + <0x00070000 0x6158>, + <0x009e0000 0xfff>; + reg-names = "core_physical", + "qfprom_physical", + "hdcp_physical"; + + interrupt-parent = <&mdss>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_HDMI_CLK>, + <&mmcc MDSS_HDMI_AHB_CLK>, + <&mmcc MDSS_EXTPCLK_CLK>; + clock-names = "mdp_core", + "iface", + "core", + "alt_iface", + "extp"; + + phys = <&hdmi_phy>; + phy-names = "hdmi_phy"; + #sound-dai-cells = <1>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; + pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; + + core-vdda-supply = <&vreg_l12a_1p8>; + core-vcc-supply = <&vreg_s4a_1p8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&mdp5_intf3_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml new file mode 100644 index 000000000000..3a6128d8f6fd --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-other.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Adreno/Snapdragon HDMI phy + +maintainers: + - Rob Clark + +properties: + compatible: + enum: + - qcom,hdmi-phy-8660 + - qcom,hdmi-phy-8960 + - qcom,hdmi-phy-8974 + - qcom,hdmi-phy-8084 + + reg: + maxItems: 2 + + reg-names: + items: + - const: hdmi_phy + - const: hdmi_pll + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + + power-domains: + maxItems: 1 + + core-vdda-supply: + description: phandle to VDDA supply regulator + vddio-supply: + description: phandle to VDD I/O supply regulator + + '#phy-cells': + const: 0 + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,hdmi-phy-8660 + - qcom,hdmi-phy-8960 + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: slave_iface + vddio-supply: false + + - if: + properties: + compatible: + contains: + enum: + - qcom,hdmi-phy-8084 + - qcom,hdmi-phy-8974 + then: + properties: + clocks: + maxItems: 2 + clock-names: + items: + - const: iface + - const: alt_iface + +required: + - compatible + - clocks + - reg + - reg-names + - '#phy-cells' + +additionalProperties: false + +examples: + - | + hdmi_phy: phy@4a00400 { + compatible = "qcom,hdmi-phy-8960"; + reg-names = "hdmi_phy", + "hdmi_pll"; + reg = <0x4a00400 0x60>, + <0x4a00500 0x100>; + #phy-cells = <0>; + power-domains = <&mmcc 1>; + clock-names = "slave_iface"; + clocks = <&clk 21>; + core-vdda-supply = <&pm8921_hdmi_mvs>; + }; diff --git a/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml new file mode 100644 index 000000000000..3784e11bf2ef --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-qmp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Adreno/Snapdragon QMP HDMI phy + +maintainers: + - Rob Clark + +properties: + compatible: + enum: + - qcom,hdmi-phy-8996 + + reg: + maxItems: 6 + + reg-names: + items: + - const: hdmi_pll + - const: hdmi_tx_l0 + - const: hdmi_tx_l1 + - const: hdmi_tx_l2 + - const: hdmi_tx_l3 + - const: hdmi_phy + + clocks: + maxItems: 2 + + clock-names: + items: + - const: iface + - const: ref + + power-domains: + maxItems: 1 + + vcca-supply: true + + vddio-supply: true + + '#phy-cells': + const: 0 + +required: + - compatible + - clocks + - clock-names + - reg + - reg-names + - '#phy-cells' + +additionalProperties: false + +examples: + - | + hdmi-phy@9a0600 { + compatible = "qcom,hdmi-phy-8996"; + reg = <0x009a0600 0x1c4>, + <0x009a0a00 0x124>, + <0x009a0c00 0x124>, + <0x009a0e00 0x124>, + <0x009a1000 0x124>, + <0x009a1200 0x0c8>; + reg-names = "hdmi_pll", + "hdmi_tx_l0", + "hdmi_tx_l1", + "hdmi_tx_l2", + "hdmi_tx_l3", + "hdmi_phy"; + + clocks = <&mmcc 116>, + <&gcc 214>; + clock-names = "iface", + "ref"; + #phy-cells = <0>; + + vddio-supply = <&vreg_l12a_1p8>; + vcca-supply = <&vreg_l28a_0p925>; + }; From patchwork Wed Jun 8 12:07:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D528EC43334 for ; Wed, 8 Jun 2022 12:07:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238689AbiFHMHi (ORCPT ); Wed, 8 Jun 2022 08:07:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238683AbiFHMHh (ORCPT ); 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Wed, 08 Jun 2022 05:07:28 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 03/12] dt-bindings: display/msm: hdmi: mark hdmi-mux-supply as deprecated Date: Wed, 8 Jun 2022 15:07:14 +0300 Message-Id: <20220608120723.2987843-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608120723.2987843-1-dmitry.baryshkov@linaro.org> References: <20220608120723.2987843-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org hdmi-mux-supply is not used by the SoC's HDMI block, it is thought to power up the external logic. Thus it should not be a part of HDMI bindings, but it should be declared at some other device in the DT (like HDMI mux, bridge, etc). Mark it as deprecated. Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd --- Documentation/devicetree/bindings/display/msm/hdmi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.yaml b/Documentation/devicetree/bindings/display/msm/hdmi.yaml index 81997759584c..3f703d737ca7 100644 --- a/Documentation/devicetree/bindings/display/msm/hdmi.yaml +++ b/Documentation/devicetree/bindings/display/msm/hdmi.yaml @@ -55,6 +55,7 @@ properties: hdmi-mux-supply: description: phandle to mux regulator + deprecated: true core-vcc-supply: description: phandle to VCC supply regulator From patchwork Wed Jun 8 12:07:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70998C433EF for ; Wed, 8 Jun 2022 12:07:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238683AbiFHMHj (ORCPT ); Wed, 8 Jun 2022 08:07:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238688AbiFHMHh (ORCPT ); Wed, 8 Jun 2022 08:07:37 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58ADC17DDEE for ; Wed, 8 Jun 2022 05:07:32 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id a2so26768533lfg.5 for ; Wed, 08 Jun 2022 05:07:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ywZDJVrp0n0IRRgem+yzlly0FGJg2gJ3lpMx4tNxzuM=; b=LhfKofCuo1hI/kyqKa7GESz/tFf5nTTEsRGD1drqYnsDSKTKl7mh7bjqOMVtcPzePR +d8NnY0Em/bybYJK+GfY61r9DoLU1p1HNrb26LJhZb1l4qzE/vnKh11DliTs98bndMU1 pTsHLKiI5PEMWM67FRQLRzblAmmyzZ7aoHhFt1Lfd8j5V1ZF/t+2Bemio1dtTaYNeIoX p6bOhZqVZzeDQ823vnmjyZ4TjXq/nbxO5SulggVBKOmjpPW74XFxZj0H6smDQWLomNRx 7y+etJlIb0WDVgJ8Zs0BMSERlp3ak1aDh258XRSZOhb3fsshb3khdppIYx3qEEv6fEQF +q6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ywZDJVrp0n0IRRgem+yzlly0FGJg2gJ3lpMx4tNxzuM=; b=28pjWuKkYQ08hzf7eLUSoDV2UHUtd6huKO59FfCg1Mc/a5au98KrgsQrh7TGkSeS4a qArOvAN4AjrBPWjvlb7jzf3IPQd1s8OAER1yUS+P8KHl1DBmVF/b2GKrIzzfdpYiA2D6 xdR+xbo/4q9jByDP8W41AAGFnSjXAZfJ2M4jWB7P/TwcaiNSZC2J3ERrq4453PkPYXvN BqpWZYGwhSPvO+OVHkyplC+F3w9RSX0VDfhrM6tLAKB98y2VDG4hsnCC5esgIQJ7nACd aTiLOIL5b4ND3ArhyAUVnm8+rTWVIaQ9XfhBpKzYFpowqnuVgsS3uRzCx8jSW4BN87qj /lhA== X-Gm-Message-State: AOAM530BLaRZm23c5V2jTo9APNewFGStAgweuxynNfVA/wI2jBnen8HU XXAcRAp64k+LorLAC4TSPggKipm4cqzAzqiW X-Google-Smtp-Source: ABdhPJz7tK93EXNnMP55322ciEx1xGXgkiQ6vvmmZXDmFnGwjAV/yE1fK6My8eJe0sLtueQUeBFgxg== X-Received: by 2002:a19:a411:0:b0:478:f29b:e30e with SMTP id q17-20020a19a411000000b00478f29be30emr21631651lfc.334.1654690050658; Wed, 08 Jun 2022 05:07:30 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id 4-20020ac25f04000000b0047b0f2d7650sm52049lfq.271.2022.06.08.05.07.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 05:07:30 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 05/12] drm/msm/hdmi: drop the hdmi-mux support Date: Wed, 8 Jun 2022 15:07:16 +0300 Message-Id: <20220608120723.2987843-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608120723.2987843-1-dmitry.baryshkov@linaro.org> References: <20220608120723.2987843-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org With the last (and only) in-kernel user of hdmi-mux regulator, drop it from the HDMI driver. Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd --- drivers/gpu/drm/msm/hdmi/hdmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index cf24e68864ba..06b44b40ec09 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -358,7 +358,7 @@ static const char *hpd_reg_names_none[] = {}; static struct hdmi_platform_config hdmi_tx_8660_config; -static const char *hpd_reg_names_8960[] = {"core-vdda", "hdmi-mux"}; +static const char *hpd_reg_names_8960[] = {"core-vdda"}; static const char *hpd_clk_names_8960[] = {"core", "master_iface", "slave_iface"}; static struct hdmi_platform_config hdmi_tx_8960_config = { From patchwork Wed Jun 8 12:07:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC680CCA47B for ; Wed, 8 Jun 2022 12:07:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238710AbiFHMHp (ORCPT ); Wed, 8 Jun 2022 08:07:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238692AbiFHMHm (ORCPT ); Wed, 8 Jun 2022 08:07:42 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89E291B9A48 for ; Wed, 8 Jun 2022 05:07:33 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id c4so843988lfj.12 for ; Wed, 08 Jun 2022 05:07:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4SrJn1arQe5FScrXxLtuR+m23ZEehxKPP642iwefF2U=; b=D32dLkFMj5Huf/eK32m65DMwAIugYmaUWWAhSn0LRcjNVz0sFRAUUvax1dNLQTJ2aS QF07/2qtPcCUNRTofjvhIxNI0Fq4zbKC6e9/lihJz69AXnQy600zS2LPPxpoTC6lxhDJ 1SVE5d3dI3C/Z0TGHtfhN45UlMCNlS18wBzlbfe0ZA3CuEkwG9sa5zscaCtOlxYQAEIl e6TX1XMB0Ha9kK71TMqG9DQYaebSlUY8f+kKFlo+Iu/cu1iXma6v2rO1lM7opFloiryu Ht07WlyMPgNAm1fe03Qt4BYUYwcgMlK6S30UTHB1+H1H//WR/vXMk2HI1UnZZYBJk6ba toQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4SrJn1arQe5FScrXxLtuR+m23ZEehxKPP642iwefF2U=; b=0i560RiWMAPPYKYCSWUi4JFe0ka35aVlw60Yy9C5befc6sijHg35i1SFI03zH/4LNM 3pPBOLJuzg/+wMIKasoH9hO4yJaiZ4MerfvO8stgKzH4L6era0ILC+t9af6mHLK6RslI 4ubIyRjzB3PNb7K3bRnTVAycLLREsNb5/7hS76Jvas9gxB9aPCJrKHaZqgoz57sbRjb0 O/1Ed+YjYHmJrJ0fueYSVBcC4EQFURQPiDt1LI262MIcnYWzuMW30DWk6H8AHYQlYxsX 90iK7ufm/kSz1mvhQYRTi09WPhuqCr5sMzBfodFIKy7HYOszC4802ancpyDvg4ct6YIJ yNKg== X-Gm-Message-State: AOAM533JZJ6aUN0YNbbIaKRAygpjDM6oVj0fZ81T3mews9IfTjhsYBPq AIpKLatoYLWnsq6WsXfv+qJzBg== X-Google-Smtp-Source: ABdhPJxToSO3lYbzAtsONtgrwVVkEY6qN0dIHaIp5+s7jCnnpjryrksRVI7QVDGSc/NJ0F0h+DNYbQ== X-Received: by 2002:a05:6512:280b:b0:47b:531:8299 with SMTP id cf11-20020a056512280b00b0047b05318299mr349294lfb.296.1654690051711; Wed, 08 Jun 2022 05:07:31 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id 4-20020ac25f04000000b0047b0f2d7650sm52049lfq.271.2022.06.08.05.07.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 05:07:31 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 06/12] drm/msm/hdmi: drop unused GPIO support Date: Wed, 8 Jun 2022 15:07:17 +0300 Message-Id: <20220608120723.2987843-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608120723.2987843-1-dmitry.baryshkov@linaro.org> References: <20220608120723.2987843-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The HDMI driver has code to configure extra GPIOs, which predates pinctrl support. Nowadays all platforms should use pinctrl instead. Neither of upstreamed Qualcomm pltforms uses these properties, so it's safe to drop them. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi.c | 61 +++++----------------------- drivers/gpu/drm/msm/hdmi/hdmi.h | 13 +----- drivers/gpu/drm/msm/hdmi/hdmi_hpd.c | 62 ++--------------------------- 3 files changed, 17 insertions(+), 119 deletions(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index 06b44b40ec09..7cb687458a56 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -406,20 +406,6 @@ static struct hdmi_platform_config hdmi_tx_8996_config = { .hpd_freq = hpd_clk_freq_8x74, }; -static const struct { - const char *name; - const bool output; - const int value; - const char *label; -} msm_hdmi_gpio_pdata[] = { - { "qcom,hdmi-tx-ddc-clk", true, 1, "HDMI_DDC_CLK" }, - { "qcom,hdmi-tx-ddc-data", true, 1, "HDMI_DDC_DATA" }, - { "qcom,hdmi-tx-hpd", false, 1, "HDMI_HPD" }, - { "qcom,hdmi-tx-mux-en", true, 1, "HDMI_MUX_EN" }, - { "qcom,hdmi-tx-mux-sel", true, 0, "HDMI_MUX_SEL" }, - { "qcom,hdmi-tx-mux-lpm", true, 1, "HDMI_MUX_LPM" }, -}; - /* * HDMI audio codec callbacks */ @@ -531,7 +517,7 @@ static int msm_hdmi_bind(struct device *dev, struct device *master, void *data) struct hdmi_platform_config *hdmi_cfg; struct hdmi *hdmi; struct device_node *of_node = dev->of_node; - int i, err; + int err; hdmi_cfg = (struct hdmi_platform_config *) of_device_get_match_data(dev); @@ -543,41 +529,16 @@ static int msm_hdmi_bind(struct device *dev, struct device *master, void *data) hdmi_cfg->mmio_name = "core_physical"; hdmi_cfg->qfprom_mmio_name = "qfprom_physical"; - for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) { - const char *name = msm_hdmi_gpio_pdata[i].name; - struct gpio_desc *gpiod; - - /* - * We are fetching the GPIO lines "as is" since the connector - * code is enabling and disabling the lines. Until that point - * the power-on default value will be kept. - */ - gpiod = devm_gpiod_get_optional(dev, name, GPIOD_ASIS); - /* This will catch e.g. -PROBE_DEFER */ - if (IS_ERR(gpiod)) - return PTR_ERR(gpiod); - if (!gpiod) { - /* Try a second time, stripping down the name */ - char name3[32]; - - /* - * Try again after stripping out the "qcom,hdmi-tx" - * prefix. This is mainly to match "hpd-gpios" used - * in the upstream bindings. - */ - if (sscanf(name, "qcom,hdmi-tx-%s", name3)) - gpiod = devm_gpiod_get_optional(dev, name3, GPIOD_ASIS); - if (IS_ERR(gpiod)) - return PTR_ERR(gpiod); - if (!gpiod) - DBG("failed to get gpio: %s", name); - } - hdmi_cfg->gpios[i].gpiod = gpiod; - if (gpiod) - gpiod_set_consumer_name(gpiod, msm_hdmi_gpio_pdata[i].label); - hdmi_cfg->gpios[i].output = msm_hdmi_gpio_pdata[i].output; - hdmi_cfg->gpios[i].value = msm_hdmi_gpio_pdata[i].value; - } + hdmi->hpd_gpiod = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); + /* This will catch e.g. -PROBE_DEFER */ + if (IS_ERR(hdmi->hpd_gpiod)) + return PTR_ERR(hdmi->hpd_gpiod); + + if (!hdmi->hpd_gpiod) + DBG("failed to get HPD gpio"); + + if (hdmi->hpd_gpiod) + gpiod_set_consumer_name(hdmi->hpd_gpiod, "HDMI_HPD"); dev->platform_data = hdmi_cfg; diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h index 736f348befb3..a6c88d157bc3 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.h +++ b/drivers/gpu/drm/msm/hdmi/hdmi.h @@ -19,17 +19,9 @@ #include "msm_drv.h" #include "hdmi.xml.h" -#define HDMI_MAX_NUM_GPIO 6 - struct hdmi_phy; struct hdmi_platform_config; -struct hdmi_gpio_data { - struct gpio_desc *gpiod; - bool output; - int value; -}; - struct hdmi_audio { bool enabled; struct hdmi_audio_infoframe infoframe; @@ -61,6 +53,8 @@ struct hdmi { struct clk **hpd_clks; struct clk **pwr_clks; + struct gpio_desc *hpd_gpiod; + struct hdmi_phy *phy; struct device *phy_dev; @@ -109,9 +103,6 @@ struct hdmi_platform_config { /* clks that need to be on for screen pwr (ie pixel clk): */ const char **pwr_clk_names; int pwr_clk_cnt; - - /* gpio's: */ - struct hdmi_gpio_data gpios[HDMI_MAX_NUM_GPIO]; }; struct hdmi_bridge { diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c index 75605ddac7c4..bfa827b47989 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c @@ -60,48 +60,6 @@ static void msm_hdmi_phy_reset(struct hdmi *hdmi) } } -static int gpio_config(struct hdmi *hdmi, bool on) -{ - const struct hdmi_platform_config *config = hdmi->config; - int i; - - if (on) { - for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) { - struct hdmi_gpio_data gpio = config->gpios[i]; - - if (gpio.gpiod) { - if (gpio.output) { - gpiod_direction_output(gpio.gpiod, - gpio.value); - } else { - gpiod_direction_input(gpio.gpiod); - gpiod_set_value_cansleep(gpio.gpiod, - gpio.value); - } - } - } - - DBG("gpio on"); - } else { - for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) { - struct hdmi_gpio_data gpio = config->gpios[i]; - - if (!gpio.gpiod) - continue; - - if (gpio.output) { - int value = gpio.value ? 0 : 1; - - gpiod_set_value_cansleep(gpio.gpiod, value); - } - } - - DBG("gpio off"); - } - - return 0; -} - static void enable_hpd_clocks(struct hdmi *hdmi, bool enable) { const struct hdmi_platform_config *config = hdmi->config; @@ -154,11 +112,8 @@ int msm_hdmi_hpd_enable(struct drm_bridge *bridge) goto fail; } - ret = gpio_config(hdmi, true); - if (ret) { - DRM_DEV_ERROR(dev, "failed to configure GPIOs: %d\n", ret); - goto fail; - } + if (hdmi->hpd_gpiod) + gpiod_set_value_cansleep(hdmi->hpd_gpiod, 1); pm_runtime_get_sync(dev); enable_hpd_clocks(hdmi, true); @@ -207,10 +162,6 @@ void msm_hdmi_hpd_disable(struct hdmi_bridge *hdmi_bridge) enable_hpd_clocks(hdmi, false); pm_runtime_put(dev); - ret = gpio_config(hdmi, false); - if (ret) - dev_warn(dev, "failed to unconfigure GPIOs: %d\n", ret); - ret = pinctrl_pm_select_sleep_state(dev); if (ret) dev_warn(dev, "pinctrl state chg failed: %d\n", ret); @@ -269,10 +220,7 @@ static enum drm_connector_status detect_reg(struct hdmi *hdmi) #define HPD_GPIO_INDEX 2 static enum drm_connector_status detect_gpio(struct hdmi *hdmi) { - const struct hdmi_platform_config *config = hdmi->config; - struct hdmi_gpio_data hpd_gpio = config->gpios[HPD_GPIO_INDEX]; - - return gpiod_get_value(hpd_gpio.gpiod) ? + return gpiod_get_value(hdmi->hpd_gpiod) ? connector_status_connected : connector_status_disconnected; } @@ -282,8 +230,6 @@ enum drm_connector_status msm_hdmi_bridge_detect( { struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); struct hdmi *hdmi = hdmi_bridge->hdmi; - const struct hdmi_platform_config *config = hdmi->config; - struct hdmi_gpio_data hpd_gpio = config->gpios[HPD_GPIO_INDEX]; enum drm_connector_status stat_gpio, stat_reg; int retry = 20; @@ -291,7 +237,7 @@ enum drm_connector_status msm_hdmi_bridge_detect( * some platforms may not have hpd gpio. Rely only on the status * provided by REG_HDMI_HPD_INT_STATUS in this case. */ - if (!hpd_gpio.gpiod) + if (!hdmi->hpd_gpiod) return detect_reg(hdmi); do { From patchwork Wed Jun 8 12:07:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FBA3CCA47E for ; Wed, 8 Jun 2022 12:07:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238732AbiFHMHw (ORCPT ); Wed, 8 Jun 2022 08:07:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238705AbiFHMHr (ORCPT ); Wed, 8 Jun 2022 08:07:47 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A17821D51AD for ; Wed, 8 Jun 2022 05:07:36 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id a15so32880215lfb.9 for ; Wed, 08 Jun 2022 05:07:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ORFFh/OvwkdHyQw6T41fKq8t4AfCf6S/1IDmxoyQ/4c=; b=wDi7mI3wFjv+MqE1wKSSFLB8GGcxe+vfPK0vtxw3GUBXmzYkA/1Ov4rnTQCOrdFvDa WCzA7ufrcjUn0xLCY/pr3hTjPeVdsyGB9vWa5KJgx5aunKyFtxRuLFRTHcfrW8ULQWlQ 4qWFCkoe1mX4vdziltcPI5wegX7NYuzr0s5aOmZ0X1YcuBP6ywgxzn6J7a8glXk2SJFC VYLo348CEhpBzGjZoPACRRXcnYOvnTHSLwmv9sx1zluWS4s0XHjVhVcY2tQ+Y0Onsca+ ZR5pADzA/lyp4L3d9SFlzEi8MQT0ezCXnaBh+C8UeidMrEZfper3ZItUBagrFi3sRMRI pLHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ORFFh/OvwkdHyQw6T41fKq8t4AfCf6S/1IDmxoyQ/4c=; b=5R23DAMp16agSfkXoAirypoW8N4Ev8U8AeyBVqYG/Axo3b6cTVJDo+BqsDnBoa17Ih TNhbLbfVyBijUq3ZR4h40O5lvirncIq2y847ys8h+P+Nih6hk4mcdFojBPsp6UTl9Re9 TEVsSsAVlaunke7QrY44fDbltDWTIy+JgW2WwpaGLC1iBZ1PH2Eu0L/Uake2v62RUKWQ njXWm/1bHvZHSiSP0uloI+KBehmYaYY7nHtT5QtYEpVgBWFXvqOBA3FZBc+ERphr4w2h tXSdQlw9pW8P53m45XYygbRumKYFh25XuhfbBXF1PdV3JzWSx4t6Z8KuJAKHv2+Pudlm j63g== X-Gm-Message-State: AOAM531sWujPK3u4L5FUbZBExTivlA3imqqaSHK0uex+ZGZmGY9glJz8 aAZOAUaseGMhdIZaBT4ole4cOA== X-Google-Smtp-Source: ABdhPJy+dxO/IWKY0573dyyNPc6FWVijcUPdMYkPtITz4qJPlvq4+Y19DzS2iPFWw9L8FlKp3vWCTw== X-Received: by 2002:a05:6512:53a:b0:479:1725:51f2 with SMTP id o26-20020a056512053a00b00479172551f2mr18043645lfc.688.1654690054546; Wed, 08 Jun 2022 05:07:34 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id 4-20020ac25f04000000b0047b0f2d7650sm52049lfq.271.2022.06.08.05.07.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 05:07:34 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 09/12] drm/msm/hdmi: drop hpd_regs usage on 8x74/8084 Date: Wed, 8 Jun 2022 15:07:20 +0300 Message-Id: <20220608120723.2987843-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608120723.2987843-1-dmitry.baryshkov@linaro.org> References: <20220608120723.2987843-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The MSM HDMI driver has support for hpd_regs on 8x74/8084: supply regulators that are to be enabled for HPD to work. Currently these regulators contain the hpd_gdsc, which was replaced by the power-domains support and hpd-5v/hpd-5v-en, which are not used by the chip itself. They power up the ESD bridge. However it is a separate device which should be represented separately in the device tree. None of upstreamed devices support these properties. Thus drop support for them from the HDMI driver. Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd --- drivers/gpu/drm/msm/hdmi/hdmi.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index ebc87f2a626c..bc6ec6aa2cb9 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -364,24 +364,19 @@ static struct hdmi_platform_config hdmi_tx_8960_config = { }; static const char *pwr_reg_names_8x74[] = {"core-vdda", "core-vcc"}; -static const char *hpd_reg_names_8x74[] = {"hpd-gdsc", "hpd-5v"}; static const char *pwr_clk_names_8x74[] = {"extp", "alt_iface"}; static const char *hpd_clk_names_8x74[] = {"iface", "core", "mdp_core"}; static unsigned long hpd_clk_freq_8x74[] = {0, 19200000, 0}; static struct hdmi_platform_config hdmi_tx_8974_config = { HDMI_CFG(pwr_reg, 8x74), - HDMI_CFG(hpd_reg, 8x74), HDMI_CFG(pwr_clk, 8x74), HDMI_CFG(hpd_clk, 8x74), .hpd_freq = hpd_clk_freq_8x74, }; -static const char *hpd_reg_names_8084[] = {"hpd-gdsc", "hpd-5v", "hpd-5v-en"}; - static struct hdmi_platform_config hdmi_tx_8084_config = { HDMI_CFG(pwr_reg, 8x74), - HDMI_CFG(hpd_reg, 8084), HDMI_CFG(pwr_clk, 8x74), HDMI_CFG(hpd_clk, 8x74), .hpd_freq = hpd_clk_freq_8x74, From patchwork Wed Jun 8 12:07:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 985EFCCA47B for ; Wed, 8 Jun 2022 12:07:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238718AbiFHMHq (ORCPT ); Wed, 8 Jun 2022 08:07:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238705AbiFHMHo (ORCPT ); Wed, 8 Jun 2022 08:07:44 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DB181207F6 for ; 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Wed, 08 Jun 2022 05:07:35 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id 4-20020ac25f04000000b0047b0f2d7650sm52049lfq.271.2022.06.08.05.07.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 05:07:35 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 10/12] drm/msm/hdmi: merge platform config for 8974/8084/8994/8996 Date: Wed, 8 Jun 2022 15:07:21 +0300 Message-Id: <20220608120723.2987843-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608120723.2987843-1-dmitry.baryshkov@linaro.org> References: <20220608120723.2987843-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since there is no more difference between the HDMI platform data between MSM8974/APQ8084/MSM8994/MSM8996, merge these configs into a single entry. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi.c | 27 +++------------------------ 1 file changed, 3 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index bc6ec6aa2cb9..a718e0ebf6cd 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -375,27 +375,6 @@ static struct hdmi_platform_config hdmi_tx_8974_config = { .hpd_freq = hpd_clk_freq_8x74, }; -static struct hdmi_platform_config hdmi_tx_8084_config = { - HDMI_CFG(pwr_reg, 8x74), - HDMI_CFG(pwr_clk, 8x74), - HDMI_CFG(hpd_clk, 8x74), - .hpd_freq = hpd_clk_freq_8x74, -}; - -static struct hdmi_platform_config hdmi_tx_8994_config = { - HDMI_CFG(pwr_reg, 8x74), - HDMI_CFG(pwr_clk, 8x74), - HDMI_CFG(hpd_clk, 8x74), - .hpd_freq = hpd_clk_freq_8x74, -}; - -static struct hdmi_platform_config hdmi_tx_8996_config = { - HDMI_CFG(pwr_reg, 8x74), - HDMI_CFG(pwr_clk, 8x74), - HDMI_CFG(hpd_clk, 8x74), - .hpd_freq = hpd_clk_freq_8x74, -}; - /* * HDMI audio codec callbacks */ @@ -577,9 +556,9 @@ static int msm_hdmi_dev_remove(struct platform_device *pdev) } static const struct of_device_id msm_hdmi_dt_match[] = { - { .compatible = "qcom,hdmi-tx-8996", .data = &hdmi_tx_8996_config }, - { .compatible = "qcom,hdmi-tx-8994", .data = &hdmi_tx_8994_config }, - { .compatible = "qcom,hdmi-tx-8084", .data = &hdmi_tx_8084_config }, + { .compatible = "qcom,hdmi-tx-8996", .data = &hdmi_tx_8974_config }, + { .compatible = "qcom,hdmi-tx-8994", .data = &hdmi_tx_8974_config }, + { .compatible = "qcom,hdmi-tx-8084", .data = &hdmi_tx_8974_config }, { .compatible = "qcom,hdmi-tx-8974", .data = &hdmi_tx_8974_config }, { .compatible = "qcom,hdmi-tx-8960", .data = &hdmi_tx_8960_config }, { .compatible = "qcom,hdmi-tx-8660", .data = &hdmi_tx_8660_config }, From patchwork Wed Jun 8 12:07:23 2022 Content-Type: text/plain; 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Wed, 08 Jun 2022 05:07:37 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id 4-20020ac25f04000000b0047b0f2d7650sm52049lfq.271.2022.06.08.05.07.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 05:07:37 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 12/12] drm/msm/hdmi-phy: populate 8x60 HDMI PHY requirements Date: Wed, 8 Jun 2022 15:07:23 +0300 Message-Id: <20220608120723.2987843-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608120723.2987843-1-dmitry.baryshkov@linaro.org> References: <20220608120723.2987843-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Declare that 8x60 HDMI PHY uses the core-vdda regulator and slave_iface clock (this is the same config as is used by the 8960). Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c index 95f2928cb2cb..1d97640d8c24 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c @@ -122,8 +122,20 @@ static void hdmi_phy_8x60_powerdown(struct hdmi_phy *phy) HDMI_8x60_PHY_REG2_PD_DESER); } +static const char * const hdmi_phy_8x60_reg_names[] = { + "core-vdda", +}; + +static const char * const hdmi_phy_8x60_clk_names[] = { + "slave_iface", +}; + const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg = { .type = MSM_HDMI_PHY_8x60, .powerup = hdmi_phy_8x60_powerup, .powerdown = hdmi_phy_8x60_powerdown, + .reg_names = hdmi_phy_8x60_reg_names, + .num_regs = ARRAY_SIZE(hdmi_phy_8x60_reg_names), + .clk_names = hdmi_phy_8x60_clk_names, + .num_clks = ARRAY_SIZE(hdmi_phy_8x60_clk_names), };