From patchwork Wed Jun 8 13:49:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 579963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFCD8CCA483 for ; Wed, 8 Jun 2022 13:49:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240565AbiFHNtl (ORCPT ); Wed, 8 Jun 2022 09:49:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240884AbiFHNtk (ORCPT ); Wed, 8 Jun 2022 09:49:40 -0400 Received: from baptiste.telenet-ops.be (baptiste.telenet-ops.be [IPv6:2a02:1800:120:4::f00:13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB26E287F40 for ; Wed, 8 Jun 2022 06:49:37 -0700 (PDT) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed30:243a:e14b:d107:1f56]) by baptiste.telenet-ops.be with bizsmtp id gdpb2700B1qF9lr01dpbFn; Wed, 08 Jun 2022 15:49:35 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1nyw3y-003DB9-Qt; Wed, 08 Jun 2022 15:49:34 +0200 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1nyw3y-008L36-C1; Wed, 08 Jun 2022 15:49:34 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski Cc: Phil Edworthy , Biju Das , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH] dt-bindings: clock: renesas,rzg2l: Simplify header file references Date: Wed, 8 Jun 2022 15:49:33 +0200 Message-ID: X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Message-ID: <20220608134933.9uL_mun1wF4EeNod4WfXS2H6xgg3gsTNnbNEsmTAPvw@z> The bindings already uses to refer to the header files with DT binding definitions for core clocks. Use more wildcards to simplify more references to these files. Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring --- To be queued in renesas-clk-for-v5.20. .../devicetree/bindings/clock/renesas,rzg2l-cpg.yaml | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index 8880b834f264cd9f..d036675e0779addc 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -45,10 +45,9 @@ properties: description: | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" and a core clock reference, as defined in - + , - For module clocks, the two clock specifier cells must be "CPG_MOD" and - a module number, as defined in the or - . + a module number, as defined in . const: 2 '#power-domain-cells': @@ -62,7 +61,7 @@ properties: '#reset-cells': description: The single reset specifier cell must be the module number, as defined in - the or . + . const: 1 required: