From patchwork Tue Jun 7 21:35:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579926 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B1DACCA487 for ; Wed, 8 Jun 2022 01:03:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378913AbiFHA7R (ORCPT ); Tue, 7 Jun 2022 20:59:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1574406AbiFGXZk (ORCPT ); Tue, 7 Jun 2022 19:25:40 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73C37170F2A for ; Tue, 7 Jun 2022 14:35:45 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id i29so13530620lfp.3 for ; Tue, 07 Jun 2022 14:35:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ggI96oh4nmAF7H/TKahQWu836yBK21tCOCTlg3vHU9s=; b=doRCuV5A0DI7BomjV0eVJ7z854H9CJSGK+oVS7Gb2uxhNdE3mf/sH2WURuCFXdizlA KA8aOi/S6SWKYeC6lOEsLTlJ2vL4B8eLJpeIkGlvCK8E381VCwQDsB+qN+eVpvTPTCSf rmGmPrDGWN3xE+njNDL/I4w1yIG44umNul1g7lxCaZFCOoUFfaXq+3DvHXKdXne1/K5A jr55sOGEbA9ar0Z3xJDctl+nxozg/iA7UxFcp40DUEjvzPW7p0q6sUPxfeSVnMTCIwD3 gmpRU1jJOmKrnVc6YtWaQBIAun2Ntq7VQiTAtixX9P2xO39G1HgFmK9miVeYs7ozpoT6 tB7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ggI96oh4nmAF7H/TKahQWu836yBK21tCOCTlg3vHU9s=; b=7DAjgmF7cE4af+fBASpGC6TBhv3W/+M1RE+gQTjYhqGsm/yz6gNYYrRahFPQAfOcbh l5J54kEgV8VYqXs7nmGcT6lv1J4F9QQEyZnPKbkwIOgprCWv6aivOEO0maO9Zj8+bEgG riGFo9l3JWhnejvETiLp4E/uzSm/de28m5ub7aEookzh4ecTRADVdqFjbsvMYzmimj3o Uiwt041HmrnwwKq5ErFQ90BiXL5+mbed639UdgLPKKghrFfrknwsoyzRP5fPReN+W3cb O8h3VtPq8pvGoc6GzL/GSeFfnaEaSFG5dtMCA6/MjjUZpTCGNHbdoR9aElcH68YQecio 3zMw== X-Gm-Message-State: AOAM533STk6iK8ds1xUkixgHTBW+R/p6KKsv/bdb4ipWwBSw7EnQydkl D0rHuxBy1MjTUvmJVay4Ep0n1A== X-Google-Smtp-Source: ABdhPJz1EszLbQUB9ohWH+LJawc4IJSKOyxgeyPazzlOBAh37VNSPWCi0pQAvLUG+1eIa+Dbj97ANw== X-Received: by 2002:ac2:4c50:0:b0:479:4fac:dd8e with SMTP id o16-20020ac24c50000000b004794facdd8emr6556972lfk.678.1654637743812; Tue, 07 Jun 2022 14:35:43 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id 4-20020a2e1644000000b0025552d57beasm2975060ljw.89.2022.06.07.14.35.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 14:35:43 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 01/30] phy: qcom-qmp: create copies of QMP PHY driver Date: Wed, 8 Jun 2022 00:35:32 +0300 Message-Id: <20220607213203.2819885-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In order to split and cleanup the single monstrous QMP PHY driver, create blind copies of the current file. They will be used for: - PCIe (and a separate msm8996 PCIe PHY driver) - UFS - USB - Combo DP + USB Acked-by: Bjorn Andersson Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/{phy-qcom-qmp.c => phy-qcom-qmp-combo.c} | 0 .../phy/qualcomm/{phy-qcom-qmp.c => phy-qcom-qmp-pcie-msm8996.c} | 0 drivers/phy/qualcomm/{phy-qcom-qmp.c => phy-qcom-qmp-pcie.c} | 0 drivers/phy/qualcomm/{phy-qcom-qmp.c => phy-qcom-qmp-ufs.c} | 0 drivers/phy/qualcomm/{phy-qcom-qmp.c => phy-qcom-qmp-usb.c} | 0 5 files changed, 0 insertions(+), 0 deletions(-) copy drivers/phy/qualcomm/{phy-qcom-qmp.c => phy-qcom-qmp-combo.c} (100%) copy drivers/phy/qualcomm/{phy-qcom-qmp.c => phy-qcom-qmp-pcie-msm8996.c} (100%) copy drivers/phy/qualcomm/{phy-qcom-qmp.c => phy-qcom-qmp-pcie.c} (100%) copy drivers/phy/qualcomm/{phy-qcom-qmp.c => phy-qcom-qmp-ufs.c} (100%) copy drivers/phy/qualcomm/{phy-qcom-qmp.c => phy-qcom-qmp-usb.c} (100%) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c similarity index 100% copy from drivers/phy/qualcomm/phy-qcom-qmp.c copy to drivers/phy/qualcomm/phy-qcom-qmp-combo.c diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c similarity index 100% copy from drivers/phy/qualcomm/phy-qcom-qmp.c copy to drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c similarity index 100% copy from drivers/phy/qualcomm/phy-qcom-qmp.c copy to drivers/phy/qualcomm/phy-qcom-qmp-pcie.c diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c similarity index 100% copy from drivers/phy/qualcomm/phy-qcom-qmp.c copy to drivers/phy/qualcomm/phy-qcom-qmp-ufs.c diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c similarity index 100% copy from drivers/phy/qualcomm/phy-qcom-qmp.c copy to drivers/phy/qualcomm/phy-qcom-qmp-usb.c From patchwork Tue Jun 7 21:31:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AE42C43334 for ; Wed, 8 Jun 2022 05:43:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233522AbiFHFm4 (ORCPT ); Wed, 8 Jun 2022 01:42:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233802AbiFHFlR (ORCPT ); Wed, 8 Jun 2022 01:41:17 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F02522C4AF for ; Tue, 7 Jun 2022 14:32:23 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id a29so1774382lfk.2 for ; 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Tue, 07 Jun 2022 14:32:21 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g23-20020ac24d97000000b0047255d21153sm3411343lfe.130.2022.06.07.14.32.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 14:32:20 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 10/30] phy: qcom-qmp-ufs: change symbol prefix to qcom_qmp_phy_ufs Date: Wed, 8 Jun 2022 00:31:43 +0300 Message-Id: <20220607213203.2819885-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> References: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change all symbol names to start with qcom_qmp_phy_ufs_ rather than old qcom_qmp_phy_ Acked-by: Bjorn Andersson Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 158 ++++++++++++------------ 1 file changed, 79 insertions(+), 79 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 4b6ce097d3a7..a8d48c70532c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -950,7 +950,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { .is_dual_lane_phy = true, }; -static void qcom_qmp_phy_configure_lane(void __iomem *base, +static void qcom_qmp_phy_ufs_configure_lane(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], int num, @@ -973,15 +973,15 @@ static void qcom_qmp_phy_configure_lane(void __iomem *base, } } -static void qcom_qmp_phy_configure(void __iomem *base, +static void qcom_qmp_phy_ufs_configure(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], int num) { - qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff); + qcom_qmp_phy_ufs_configure_lane(base, regs, tbl, num, 0xff); } -static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) +static int qcom_qmp_phy_ufs_serdes_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -991,30 +991,30 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy) int serdes_tbl_num = cfg->serdes_tbl_num; int ret; - qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + qcom_qmp_phy_ufs_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); if (cfg->serdes_tbl_sec) - qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, + qcom_qmp_phy_ufs_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, cfg->serdes_tbl_num_sec); if (cfg->type == PHY_TYPE_DP) { switch (dp_opts->link_rate) { case 1620: - qcom_qmp_phy_configure(serdes, cfg->regs, + qcom_qmp_phy_ufs_configure(serdes, cfg->regs, cfg->serdes_tbl_rbr, cfg->serdes_tbl_rbr_num); break; case 2700: - qcom_qmp_phy_configure(serdes, cfg->regs, + qcom_qmp_phy_ufs_configure(serdes, cfg->regs, cfg->serdes_tbl_hbr, cfg->serdes_tbl_hbr_num); break; case 5400: - qcom_qmp_phy_configure(serdes, cfg->regs, + qcom_qmp_phy_ufs_configure(serdes, cfg->regs, cfg->serdes_tbl_hbr2, cfg->serdes_tbl_hbr2_num); break; case 8100: - qcom_qmp_phy_configure(serdes, cfg->regs, + qcom_qmp_phy_ufs_configure(serdes, cfg->regs, cfg->serdes_tbl_hbr3, cfg->serdes_tbl_hbr3_num); break; @@ -1074,7 +1074,7 @@ static int qcom_qmp_dp_phy_calibrate(struct phy *phy) return 0; } -static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) +static int qcom_qmp_phy_ufs_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -1169,7 +1169,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) return ret; } -static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) +static int qcom_qmp_phy_ufs_com_exit(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -1204,7 +1204,7 @@ static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy) return 0; } -static int qcom_qmp_phy_init(struct phy *phy) +static int qcom_qmp_phy_ufs_init(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; @@ -1239,7 +1239,7 @@ static int qcom_qmp_phy_init(struct phy *phy) return ret; } - ret = qcom_qmp_phy_com_init(qphy); + ret = qcom_qmp_phy_ufs_com_init(qphy); if (ret) return ret; @@ -1249,7 +1249,7 @@ static int qcom_qmp_phy_init(struct phy *phy) return 0; } -static int qcom_qmp_phy_power_on(struct phy *phy) +static int qcom_qmp_phy_ufs_power_on(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; @@ -1262,7 +1262,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy) unsigned int mask, val, ready; int ret; - qcom_qmp_phy_serdes_init(qphy); + qcom_qmp_phy_ufs_serdes_init(qphy); if (cfg->has_lane_rst) { ret = reset_control_deassert(qphy->lane_rst); @@ -1280,18 +1280,18 @@ static int qcom_qmp_phy_power_on(struct phy *phy) } /* Tx, Rx, and PCS configurations */ - qcom_qmp_phy_configure_lane(tx, cfg->regs, + qcom_qmp_phy_ufs_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); if (cfg->tx_tbl_sec) - qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, + qcom_qmp_phy_ufs_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, cfg->tx_tbl_num_sec, 1); /* Configuration for other LANE for USB-DP combo PHY */ if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, + qcom_qmp_phy_ufs_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 2); if (cfg->tx_tbl_sec) - qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs, + qcom_qmp_phy_ufs_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl_sec, cfg->tx_tbl_num_sec, 2); } @@ -1300,17 +1300,17 @@ static int qcom_qmp_phy_power_on(struct phy *phy) if (cfg->type == PHY_TYPE_DP) cfg->configure_dp_tx(qphy); - qcom_qmp_phy_configure_lane(rx, cfg->regs, + qcom_qmp_phy_ufs_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); if (cfg->rx_tbl_sec) - qcom_qmp_phy_configure_lane(rx, cfg->regs, + qcom_qmp_phy_ufs_configure_lane(rx, cfg->regs, cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, + qcom_qmp_phy_ufs_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 2); if (cfg->rx_tbl_sec) - qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs, + qcom_qmp_phy_ufs_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 2); } @@ -1319,9 +1319,9 @@ static int qcom_qmp_phy_power_on(struct phy *phy) if (cfg->type == PHY_TYPE_DP) { cfg->configure_dp_phy(qphy); } else { - qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); if (cfg->pcs_tbl_sec) - qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, + qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, cfg->pcs_tbl_num_sec); } @@ -1329,10 +1329,10 @@ static int qcom_qmp_phy_power_on(struct phy *phy) if (ret) goto err_disable_pipe_clk; - qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, + qcom_qmp_phy_ufs_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num); if (cfg->pcs_misc_tbl_sec) - qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, + qcom_qmp_phy_ufs_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, cfg->pcs_misc_tbl_num_sec); /* @@ -1380,7 +1380,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy) return ret; } -static int qcom_qmp_phy_power_off(struct phy *phy) +static int qcom_qmp_phy_ufs_power_off(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -1411,7 +1411,7 @@ static int qcom_qmp_phy_power_off(struct phy *phy) return 0; } -static int qcom_qmp_phy_exit(struct phy *phy) +static int qcom_qmp_phy_ufs_exit(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qphy->cfg; @@ -1419,37 +1419,37 @@ static int qcom_qmp_phy_exit(struct phy *phy) if (cfg->has_lane_rst) reset_control_assert(qphy->lane_rst); - qcom_qmp_phy_com_exit(qphy); + qcom_qmp_phy_ufs_com_exit(qphy); return 0; } -static int qcom_qmp_phy_enable(struct phy *phy) +static int qcom_qmp_phy_ufs_enable(struct phy *phy) { int ret; - ret = qcom_qmp_phy_init(phy); + ret = qcom_qmp_phy_ufs_init(phy); if (ret) return ret; - ret = qcom_qmp_phy_power_on(phy); + ret = qcom_qmp_phy_ufs_power_on(phy); if (ret) - qcom_qmp_phy_exit(phy); + qcom_qmp_phy_ufs_exit(phy); return ret; } -static int qcom_qmp_phy_disable(struct phy *phy) +static int qcom_qmp_phy_ufs_disable(struct phy *phy) { int ret; - ret = qcom_qmp_phy_power_off(phy); + ret = qcom_qmp_phy_ufs_power_off(phy); if (ret) return ret; - return qcom_qmp_phy_exit(phy); + return qcom_qmp_phy_ufs_exit(phy); } -static int qcom_qmp_phy_set_mode(struct phy *phy, +static int qcom_qmp_phy_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) { struct qmp_phy *qphy = phy_get_drvdata(phy); @@ -1459,7 +1459,7 @@ static int qcom_qmp_phy_set_mode(struct phy *phy, return 0; } -static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) +static void qcom_qmp_phy_ufs_enable_autonomous_mode(struct qmp_phy *qphy) { const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *pcs = qphy->pcs; @@ -1488,7 +1488,7 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy) qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); } -static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) +static void qcom_qmp_phy_ufs_disable_autonomous_mode(struct qmp_phy *qphy) { const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *pcs = qphy->pcs; @@ -1506,7 +1506,7 @@ static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy) qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); } -static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) +static int __maybe_unused qcom_qmp_phy_ufs_runtime_suspend(struct device *dev) { struct qcom_qmp *qmp = dev_get_drvdata(dev); struct qmp_phy *qphy = qmp->phys[0]; @@ -1523,7 +1523,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) return 0; } - qcom_qmp_phy_enable_autonomous_mode(qphy); + qcom_qmp_phy_ufs_enable_autonomous_mode(qphy); clk_disable_unprepare(qphy->pipe_clk); clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); @@ -1531,7 +1531,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev) return 0; } -static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) +static int __maybe_unused qcom_qmp_phy_ufs_runtime_resume(struct device *dev) { struct qcom_qmp *qmp = dev_get_drvdata(dev); struct qmp_phy *qphy = qmp->phys[0]; @@ -1560,12 +1560,12 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev) return ret; } - qcom_qmp_phy_disable_autonomous_mode(qphy); + qcom_qmp_phy_ufs_disable_autonomous_mode(qphy); return 0; } -static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qcom_qmp_phy_ufs_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int num = cfg->num_vregs; @@ -1581,7 +1581,7 @@ static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg * return devm_regulator_bulk_get(dev, num, qmp->vregs); } -static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qcom_qmp_phy_ufs_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int i; @@ -1606,7 +1606,7 @@ static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg return 0; } -static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qcom_qmp_phy_ufs_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); int num = cfg->num_clks; @@ -1874,28 +1874,28 @@ static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); } -static const struct phy_ops qcom_qmp_phy_gen_ops = { - .init = qcom_qmp_phy_enable, - .exit = qcom_qmp_phy_disable, - .set_mode = qcom_qmp_phy_set_mode, +static const struct phy_ops qcom_qmp_phy_ufs_gen_ops = { + .init = qcom_qmp_phy_ufs_enable, + .exit = qcom_qmp_phy_ufs_disable, + .set_mode = qcom_qmp_phy_ufs_set_mode, .owner = THIS_MODULE, }; -static const struct phy_ops qcom_qmp_phy_dp_ops = { - .init = qcom_qmp_phy_init, +static const struct phy_ops qcom_qmp_phy_ufs_dp_ops = { + .init = qcom_qmp_phy_ufs_init, .configure = qcom_qmp_dp_phy_configure, - .power_on = qcom_qmp_phy_power_on, + .power_on = qcom_qmp_phy_ufs_power_on, .calibrate = qcom_qmp_dp_phy_calibrate, - .power_off = qcom_qmp_phy_power_off, - .exit = qcom_qmp_phy_exit, - .set_mode = qcom_qmp_phy_set_mode, + .power_off = qcom_qmp_phy_ufs_power_off, + .exit = qcom_qmp_phy_ufs_exit, + .set_mode = qcom_qmp_phy_ufs_set_mode, .owner = THIS_MODULE, }; static const struct phy_ops qcom_qmp_pcie_ufs_ops = { - .power_on = qcom_qmp_phy_enable, - .power_off = qcom_qmp_phy_disable, - .set_mode = qcom_qmp_phy_set_mode, + .power_on = qcom_qmp_phy_ufs_enable, + .power_off = qcom_qmp_phy_ufs_disable, + .set_mode = qcom_qmp_phy_ufs_set_mode, .owner = THIS_MODULE, }; @@ -1905,7 +1905,7 @@ static void qcom_qmp_reset_control_put(void *data) } static -int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, +int qcom_qmp_phy_ufs_create(struct device *dev, struct device_node *np, int id, void __iomem *serdes, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); @@ -2007,9 +2007,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) ops = &qcom_qmp_pcie_ufs_ops; else if (cfg->type == PHY_TYPE_DP) - ops = &qcom_qmp_phy_dp_ops; + ops = &qcom_qmp_phy_ufs_dp_ops; else - ops = &qcom_qmp_phy_gen_ops; + ops = &qcom_qmp_phy_ufs_gen_ops; generic_phy = devm_phy_create(dev, np, ops); if (IS_ERR(generic_phy)) { @@ -2027,7 +2027,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id, return 0; } -static const struct of_device_id qcom_qmp_phy_of_match_table[] = { +static const struct of_device_id qcom_qmp_phy_ufs_of_match_table[] = { { .compatible = "qcom,msm8996-qmp-ufs-phy", .data = &msm8996_ufs_cfg, @@ -2064,14 +2064,14 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }, { }, }; -MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table); +MODULE_DEVICE_TABLE(of, qcom_qmp_phy_ufs_of_match_table); -static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { - SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend, - qcom_qmp_phy_runtime_resume, NULL) +static const struct dev_pm_ops qcom_qmp_phy_ufs_pm_ops = { + SET_RUNTIME_PM_OPS(qcom_qmp_phy_ufs_runtime_suspend, + qcom_qmp_phy_ufs_runtime_resume, NULL) }; -static int qcom_qmp_phy_probe(struct platform_device *pdev) +static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) { struct qcom_qmp *qmp; struct device *dev = &pdev->dev; @@ -2125,15 +2125,15 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) mutex_init(&qmp->phy_mutex); - ret = qcom_qmp_phy_clk_init(dev, cfg); + ret = qcom_qmp_phy_ufs_clk_init(dev, cfg); if (ret) return ret; - ret = qcom_qmp_phy_reset_init(dev, cfg); + ret = qcom_qmp_phy_ufs_reset_init(dev, cfg); if (ret) return ret; - ret = qcom_qmp_phy_vreg_init(dev, cfg); + ret = qcom_qmp_phy_ufs_vreg_init(dev, cfg); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "failed to get regulator supplies: %d\n", @@ -2169,7 +2169,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) } /* Create per-lane phy */ - ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg); + ret = qcom_qmp_phy_ufs_create(dev, child, id, serdes, cfg); if (ret) { dev_err(dev, "failed to create lane%d phy, %d\n", id, ret); @@ -2212,16 +2212,16 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) return ret; } -static struct platform_driver qcom_qmp_phy_driver = { - .probe = qcom_qmp_phy_probe, +static struct platform_driver qcom_qmp_phy_ufs_driver = { + .probe = qcom_qmp_phy_ufs_probe, .driver = { .name = "qcom-qmp-ufs-phy", - .pm = &qcom_qmp_phy_pm_ops, - .of_match_table = qcom_qmp_phy_of_match_table, + .pm = &qcom_qmp_phy_ufs_pm_ops, + .of_match_table = qcom_qmp_phy_ufs_of_match_table, }, }; -module_platform_driver(qcom_qmp_phy_driver); +module_platform_driver(qcom_qmp_phy_ufs_driver); MODULE_AUTHOR("Vivek Gautam "); MODULE_DESCRIPTION("Qualcomm QMP UFS PHY driver"); From patchwork Tue Jun 7 21:31:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E50BDCCA47C for ; Wed, 8 Jun 2022 00:58:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234503AbiFHA63 (ORCPT ); Tue, 7 Jun 2022 20:58:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381015AbiFGXiS (ORCPT ); Tue, 7 Jun 2022 19:38:18 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA6B122CBFE for ; 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Tue, 07 Jun 2022 14:32:27 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g23-20020ac24d97000000b0047255d21153sm3411343lfe.130.2022.06.07.14.32.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 14:32:27 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 15/30] phy: qcom-qmp-pcie: drop support for non-PCIe PHY types Date: Wed, 8 Jun 2022 00:31:48 +0300 Message-Id: <20220607213203.2819885-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> References: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop remaining support for PHY types other than PCIe. Acked-by: Bjorn Andersson Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 528 ++--------------------- 1 file changed, 43 insertions(+), 485 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index eedcf9ccb28c..b780994692b3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1832,7 +1832,6 @@ static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy) struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; int serdes_tbl_num = cfg->serdes_tbl_num; int ret; @@ -1842,35 +1841,6 @@ static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy) qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, cfg->serdes_tbl_num_sec); - if (cfg->type == PHY_TYPE_DP) { - switch (dp_opts->link_rate) { - case 1620: - qcom_qmp_phy_pcie_configure(serdes, cfg->regs, - cfg->serdes_tbl_rbr, - cfg->serdes_tbl_rbr_num); - break; - case 2700: - qcom_qmp_phy_pcie_configure(serdes, cfg->regs, - cfg->serdes_tbl_hbr, - cfg->serdes_tbl_hbr_num); - break; - case 5400: - qcom_qmp_phy_pcie_configure(serdes, cfg->regs, - cfg->serdes_tbl_hbr2, - cfg->serdes_tbl_hbr2_num); - break; - case 8100: - qcom_qmp_phy_pcie_configure(serdes, cfg->regs, - cfg->serdes_tbl_hbr3, - cfg->serdes_tbl_hbr3_num); - break; - default: - /* Other link rates aren't supported */ - return -EINVAL; - } - } - - if (cfg->has_phy_com_ctrl) { void __iomem *status; unsigned int mask, val; @@ -1894,32 +1864,6 @@ static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy) return 0; } -static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) -{ - const struct phy_configure_opts_dp *dp_opts = &opts->dp; - struct qmp_phy *qphy = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qphy->cfg; - - memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); - if (qphy->dp_opts.set_voltages) { - cfg->configure_dp_tx(qphy); - qphy->dp_opts.set_voltages = 0; - } - - return 0; -} - -static int qcom_qmp_dp_phy_calibrate(struct phy *phy) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qphy->cfg; - - if (cfg->calibrate_dp_phy) - return cfg->calibrate_dp_phy(qphy); - - return 0; -} - static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; @@ -2089,9 +2033,6 @@ static int qcom_qmp_phy_pcie_init(struct phy *phy) if (ret) return ret; - if (cfg->type == PHY_TYPE_DP) - cfg->dp_aux_init(qphy); - return 0; } @@ -2142,10 +2083,6 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy) cfg->tx_tbl_num_sec, 2); } - /* Configure special DP tx tunings */ - if (cfg->type == PHY_TYPE_DP) - cfg->configure_dp_tx(qphy); - qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); if (cfg->rx_tbl_sec) @@ -2161,15 +2098,10 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy) cfg->rx_tbl_num_sec, 2); } - /* Configure link rate, swing, etc. */ - if (cfg->type == PHY_TYPE_DP) { - cfg->configure_dp_phy(qphy); - } else { - qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); - if (cfg->pcs_tbl_sec) - qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, - cfg->pcs_tbl_num_sec); - } + qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + if (cfg->pcs_tbl_sec) + qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, + cfg->pcs_tbl_num_sec); ret = reset_control_deassert(qmp->ufs_reset); if (ret) @@ -2185,36 +2117,28 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy) * Pull out PHY from POWER DOWN state. * This is active low enable signal to power-down PHY. */ - if(cfg->type == PHY_TYPE_PCIE) - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); if (cfg->has_pwrdn_delay) usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); - if (cfg->type != PHY_TYPE_DP) { - /* Pull PHY out of reset state */ - if (!cfg->no_pcs_sw_reset) - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); - /* start SerDes and Phy-Coding-Sublayer */ - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - - if (cfg->type == PHY_TYPE_UFS) { - status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; - mask = PCS_READY; - ready = PCS_READY; - } else { - status = pcs + cfg->regs[QPHY_PCS_STATUS]; - mask = cfg->phy_status; - ready = 0; - } + /* Pull PHY out of reset state */ + if (!cfg->no_pcs_sw_reset) + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, - PHY_INIT_COMPLETE_TIMEOUT); - if (ret) { - dev_err(qmp->dev, "phy initialization timed-out\n"); - goto err_disable_pipe_clk; - } + status = pcs + cfg->regs[QPHY_PCS_STATUS]; + mask = cfg->phy_status; + ready = 0; + + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, + PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(qmp->dev, "phy initialization timed-out\n"); + goto err_disable_pipe_clk; } + return 0; err_disable_pipe_clk: @@ -2233,25 +2157,20 @@ static int qcom_qmp_phy_pcie_power_off(struct phy *phy) clk_disable_unprepare(qphy->pipe_clk); - if (cfg->type == PHY_TYPE_DP) { - /* Assert DP PHY power down */ - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); - } else { - /* PHY reset */ - if (!cfg->no_pcs_sw_reset) - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* PHY reset */ + if (!cfg->no_pcs_sw_reset) + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); - /* stop SerDes and Phy-Coding-Sublayer */ - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + /* stop SerDes and Phy-Coding-Sublayer */ + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - /* Put PHY into POWER DOWN state: active low */ - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], - cfg->pwrdn_ctrl); - } else { - qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, - cfg->pwrdn_ctrl); - } + /* Put PHY into POWER DOWN state: active low */ + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + } else { + qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); } return 0; @@ -2305,112 +2224,6 @@ static int qcom_qmp_phy_pcie_set_mode(struct phy *phy, return 0; } -static void qcom_qmp_phy_pcie_enable_autonomous_mode(struct qmp_phy *qphy) -{ - const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; - u32 intr_mask; - - if (qphy->mode == PHY_MODE_USB_HOST_SS || - qphy->mode == PHY_MODE_USB_DEVICE_SS) - intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; - else - intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; - - /* Clear any pending interrupts status */ - qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); - /* Writing 1 followed by 0 clears the interrupt */ - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); - - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], - ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); - - /* Enable required PHY autonomous mode interrupts */ - qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); - - /* Enable i/o clamp_n for autonomous mode */ - if (pcs_misc) - qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); -} - -static void qcom_qmp_phy_pcie_disable_autonomous_mode(struct qmp_phy *qphy) -{ - const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; - - /* Disable i/o clamp_n on resume for normal mode */ - if (pcs_misc) - qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); - - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], - ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); - - qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); - /* Writing 1 followed by 0 clears the interrupt */ - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); -} - -static int __maybe_unused qcom_qmp_phy_pcie_runtime_suspend(struct device *dev) -{ - struct qcom_qmp *qmp = dev_get_drvdata(dev); - struct qmp_phy *qphy = qmp->phys[0]; - const struct qmp_phy_cfg *cfg = qphy->cfg; - - dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); - - /* Supported only for USB3 PHY and luckily USB3 is the first phy */ - if (cfg->type != PHY_TYPE_USB3) - return 0; - - if (!qmp->init_count) { - dev_vdbg(dev, "PHY not initialized, bailing out\n"); - return 0; - } - - qcom_qmp_phy_pcie_enable_autonomous_mode(qphy); - - clk_disable_unprepare(qphy->pipe_clk); - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); - - return 0; -} - -static int __maybe_unused qcom_qmp_phy_pcie_runtime_resume(struct device *dev) -{ - struct qcom_qmp *qmp = dev_get_drvdata(dev); - struct qmp_phy *qphy = qmp->phys[0]; - const struct qmp_phy_cfg *cfg = qphy->cfg; - int ret = 0; - - dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); - - /* Supported only for USB3 PHY and luckily USB3 is the first phy */ - if (cfg->type != PHY_TYPE_USB3) - return 0; - - if (!qmp->init_count) { - dev_vdbg(dev, "PHY not initialized, bailing out\n"); - return 0; - } - - ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); - if (ret) - return ret; - - ret = clk_prepare_enable(qphy->pipe_clk); - if (ret) { - dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); - return ret; - } - - qcom_qmp_phy_pcie_disable_autonomous_mode(qphy); - - return 0; -} - static int qcom_qmp_phy_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); @@ -2528,223 +2341,13 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); } -/* - * Display Port PLL driver block diagram for branch clocks - * - * +------------------------------+ - * | DP_VCO_CLK | - * | | - * | +-------------------+ | - * | | (DP PLL/VCO) | | - * | +---------+---------+ | - * | v | - * | +----------+-----------+ | - * | | hsclk_divsel_clk_src | | - * | +----------+-----------+ | - * +------------------------------+ - * | - * +---------<---------v------------>----------+ - * | | - * +--------v----------------+ | - * | dp_phy_pll_link_clk | | - * | link_clk | | - * +--------+----------------+ | - * | | - * | | - * v v - * Input to DISPCC block | - * for link clk, crypto clk | - * and interface clock | - * | - * | - * +--------<------------+-----------------+---<---+ - * | | | - * +----v---------+ +--------v-----+ +--------v------+ - * | vco_divided | | vco_divided | | vco_divided | - * | _clk_src | | _clk_src | | _clk_src | - * | | | | | | - * |divsel_six | | divsel_two | | divsel_four | - * +-------+------+ +-----+--------+ +--------+------+ - * | | | - * v---->----------v-------------<------v - * | - * +----------+-----------------+ - * | dp_phy_pll_vco_div_clk | - * +---------+------------------+ - * | - * v - * Input to DISPCC block - * for DP pixel clock - * - */ -static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - switch (req->rate) { - case 1620000000UL / 2: - case 2700000000UL / 2: - /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ - return 0; - default: - return -EINVAL; - } -} - -static unsigned long -qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -{ - const struct qmp_phy_dp_clks *dp_clks; - const struct qmp_phy *qphy; - const struct phy_configure_opts_dp *dp_opts; - - dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); - qphy = dp_clks->qphy; - dp_opts = &qphy->dp_opts; - - switch (dp_opts->link_rate) { - case 1620: - return 1620000000UL / 2; - case 2700: - return 2700000000UL / 2; - case 5400: - return 5400000000UL / 4; - case 8100: - return 8100000000UL / 6; - default: - return 0; - } -} - -static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { - .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, - .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, -}; - -static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - switch (req->rate) { - case 162000000: - case 270000000: - case 540000000: - case 810000000: - return 0; - default: - return -EINVAL; - } -} - -static unsigned long -qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -{ - const struct qmp_phy_dp_clks *dp_clks; - const struct qmp_phy *qphy; - const struct phy_configure_opts_dp *dp_opts; - - dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); - qphy = dp_clks->qphy; - dp_opts = &qphy->dp_opts; - - switch (dp_opts->link_rate) { - case 1620: - case 2700: - case 5400: - case 8100: - return dp_opts->link_rate * 100000; - default: - return 0; - } -} - -static const struct clk_ops qcom_qmp_dp_link_clk_ops = { - .determine_rate = qcom_qmp_dp_link_clk_determine_rate, - .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, -}; - -static struct clk_hw * -qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) -{ - struct qmp_phy_dp_clks *dp_clks = data; - unsigned int idx = clkspec->args[0]; - - if (idx >= 2) { - pr_err("%s: invalid index %u\n", __func__, idx); - return ERR_PTR(-EINVAL); - } - - if (idx == 0) - return &dp_clks->dp_link_hw; - - return &dp_clks->dp_pixel_hw; -} - -static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, - struct device_node *np) -{ - struct clk_init_data init = { }; - struct qmp_phy_dp_clks *dp_clks; - char name[64]; - int ret; - - dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); - if (!dp_clks) - return -ENOMEM; - - dp_clks->qphy = qphy; - qphy->dp_clks = dp_clks; - - snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); - init.ops = &qcom_qmp_dp_link_clk_ops; - init.name = name; - dp_clks->dp_link_hw.init = &init; - ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); - if (ret) - return ret; - - snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); - init.ops = &qcom_qmp_dp_pixel_clk_ops; - init.name = name; - dp_clks->dp_pixel_hw.init = &init; - ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); - if (ret) - return ret; - - ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); - if (ret) - return ret; - - /* - * Roll a devm action because the clock provider is the child node, but - * the child node is not actually a device. - */ - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); -} - -static const struct phy_ops qcom_qmp_phy_pcie_gen_ops = { +static const struct phy_ops qcom_qmp_phy_pcie_ops = { .init = qcom_qmp_phy_pcie_enable, .exit = qcom_qmp_phy_pcie_disable, .set_mode = qcom_qmp_phy_pcie_set_mode, .owner = THIS_MODULE, }; -static const struct phy_ops qcom_qmp_phy_pcie_dp_ops = { - .init = qcom_qmp_phy_pcie_init, - .configure = qcom_qmp_dp_phy_configure, - .power_on = qcom_qmp_phy_pcie_power_on, - .calibrate = qcom_qmp_dp_phy_calibrate, - .power_off = qcom_qmp_phy_pcie_power_off, - .exit = qcom_qmp_phy_pcie_exit, - .set_mode = qcom_qmp_phy_pcie_set_mode, - .owner = THIS_MODULE, -}; - -static const struct phy_ops qcom_qmp_pcie_ufs_ops = { - .power_on = qcom_qmp_phy_pcie_enable, - .power_off = qcom_qmp_phy_pcie_disable, - .set_mode = qcom_qmp_phy_pcie_set_mode, - .owner = THIS_MODULE, -}; - static void qcom_qmp_reset_control_put(void *data) { reset_control_put(data); @@ -2757,7 +2360,6 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id, struct qcom_qmp *qmp = dev_get_drvdata(dev); struct phy *generic_phy; struct qmp_phy *qphy; - const struct phy_ops *ops; char prop_name[MAX_PROP_NAME]; int ret; @@ -2850,14 +2452,7 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id, return ret; } - if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) - ops = &qcom_qmp_pcie_ufs_ops; - else if (cfg->type == PHY_TYPE_DP) - ops = &qcom_qmp_phy_pcie_dp_ops; - else - ops = &qcom_qmp_phy_pcie_gen_ops; - - generic_phy = devm_phy_create(dev, np, ops); + generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_ops); if (IS_ERR(generic_phy)) { ret = PTR_ERR(generic_phy); dev_err(dev, "failed to create qphy %d\n", ret); @@ -2915,11 +2510,6 @@ static const struct of_device_id qcom_qmp_phy_pcie_of_match_table[] = { }; MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_of_match_table); -static const struct dev_pm_ops qcom_qmp_phy_pcie_pm_ops = { - SET_RUNTIME_PM_OPS(qcom_qmp_phy_pcie_runtime_suspend, - qcom_qmp_phy_pcie_runtime_resume, NULL) -}; - static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) { struct qcom_qmp *qmp; @@ -2927,12 +2517,7 @@ static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) struct device_node *child; struct phy_provider *phy_provider; void __iomem *serdes; - void __iomem *usb_serdes; - void __iomem *dp_serdes = NULL; - const struct qmp_phy_combo_cfg *combo_cfg = NULL; const struct qmp_phy_cfg *cfg = NULL; - const struct qmp_phy_cfg *usb_cfg = NULL; - const struct qmp_phy_cfg *dp_cfg = NULL; int num, id, expected_phys; int ret; @@ -2949,28 +2534,18 @@ static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) return -EINVAL; /* per PHY serdes; usually located at base address */ - usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); + serdes = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(serdes)) return PTR_ERR(serdes); /* per PHY dp_com; if PHY has dp_com control block */ - if (combo_cfg || cfg->has_phy_dp_com_ctrl) { + if (cfg->has_phy_dp_com_ctrl) { qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(qmp->dp_com)) return PTR_ERR(qmp->dp_com); } - if (combo_cfg) { - /* Only two serdes for combo PHY */ - dp_serdes = devm_platform_ioremap_resource(pdev, 2); - if (IS_ERR(dp_serdes)) - return PTR_ERR(dp_serdes); - - dp_cfg = combo_cfg->dp_cfg; - expected_phys = 2; - } else { - expected_phys = cfg->nlanes; - } + expected_phys = cfg->nlanes; mutex_init(&qmp->phy_mutex); @@ -3009,14 +2584,6 @@ static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) id = 0; for_each_available_child_of_node(dev->of_node, child) { - if (of_node_name_eq(child, "dp-phy")) { - cfg = dp_cfg; - serdes = dp_serdes; - } else if (of_node_name_eq(child, "usb3-phy")) { - cfg = usb_cfg; - serdes = usb_serdes; - } - /* Create per-lane phy */ ret = qcom_qmp_phy_pcie_create(dev, child, id, serdes, cfg); if (ret) { @@ -3029,21 +2596,13 @@ static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) * Register the pipe clock provided by phy. * See function description to see details of this pipe clock. */ - if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { - ret = phy_pipe_clk_register(qmp, child); - if (ret) { - dev_err(qmp->dev, - "failed to register pipe clock source\n"); - goto err_node_put; - } - } else if (cfg->type == PHY_TYPE_DP) { - ret = phy_dp_clks_register(qmp, qmp->phys[id], child); - if (ret) { - dev_err(qmp->dev, - "failed to register DP clock source\n"); - goto err_node_put; - } + ret = phy_pipe_clk_register(qmp, child); + if (ret) { + dev_err(qmp->dev, + "failed to register pipe clock source\n"); + goto err_node_put; } + id++; } @@ -3065,7 +2624,6 @@ static struct platform_driver qcom_qmp_phy_pcie_driver = { .probe = qcom_qmp_phy_pcie_probe, .driver = { .name = "qcom-qmp-pcie-phy", - .pm = &qcom_qmp_phy_pcie_pm_ops, .of_match_table = qcom_qmp_phy_pcie_of_match_table, }, }; From patchwork Tue Jun 7 21:31:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579911 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D4B7C43334 for ; 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Tue, 07 Jun 2022 14:32:28 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 16/30] phy: qcom-qmp-pcie-msm8996: drop support for non-PCIe PHY types Date: Wed, 8 Jun 2022 00:31:49 +0300 Message-Id: <20220607213203.2819885-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> References: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop remaining support for PHY types other than PCIe. Acked-by: Bjorn Andersson Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov --- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 532 ++---------------- 1 file changed, 43 insertions(+), 489 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 1741a5675f9a..02e5ae7fa213 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -510,7 +510,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; int serdes_tbl_num = cfg->serdes_tbl_num; int ret; @@ -520,35 +519,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, cfg->serdes_tbl_num_sec); - if (cfg->type == PHY_TYPE_DP) { - switch (dp_opts->link_rate) { - case 1620: - qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, - cfg->serdes_tbl_rbr, - cfg->serdes_tbl_rbr_num); - break; - case 2700: - qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, - cfg->serdes_tbl_hbr, - cfg->serdes_tbl_hbr_num); - break; - case 5400: - qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, - cfg->serdes_tbl_hbr2, - cfg->serdes_tbl_hbr2_num); - break; - case 8100: - qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, - cfg->serdes_tbl_hbr3, - cfg->serdes_tbl_hbr3_num); - break; - default: - /* Other link rates aren't supported */ - return -EINVAL; - } - } - - if (cfg->has_phy_com_ctrl) { void __iomem *status; unsigned int mask, val; @@ -572,36 +542,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) return 0; } -/* - * We need to calibrate the aux setting here as many times - * as the caller tries - */ -static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) -{ - const struct phy_configure_opts_dp *dp_opts = &opts->dp; - struct qmp_phy *qphy = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qphy->cfg; - - memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); - if (qphy->dp_opts.set_voltages) { - cfg->configure_dp_tx(qphy); - qphy->dp_opts.set_voltages = 0; - } - - return 0; -} - -static int qcom_qmp_dp_phy_calibrate(struct phy *phy) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qphy->cfg; - - if (cfg->calibrate_dp_phy) - return cfg->calibrate_dp_phy(qphy); - - return 0; -} - static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; @@ -771,9 +711,6 @@ static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy) if (ret) return ret; - if (cfg->type == PHY_TYPE_DP) - cfg->dp_aux_init(qphy); - return 0; } @@ -824,10 +761,6 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) cfg->tx_tbl_num_sec, 2); } - /* Configure special DP tx tunings */ - if (cfg->type == PHY_TYPE_DP) - cfg->configure_dp_tx(qphy); - qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); if (cfg->rx_tbl_sec) @@ -843,15 +776,10 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) cfg->rx_tbl_num_sec, 2); } - /* Configure link rate, swing, etc. */ - if (cfg->type == PHY_TYPE_DP) { - cfg->configure_dp_phy(qphy); - } else { - qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); - if (cfg->pcs_tbl_sec) - qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, - cfg->pcs_tbl_num_sec); - } + qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + if (cfg->pcs_tbl_sec) + qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, + cfg->pcs_tbl_num_sec); ret = reset_control_deassert(qmp->ufs_reset); if (ret) @@ -867,36 +795,28 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) * Pull out PHY from POWER DOWN state. * This is active low enable signal to power-down PHY. */ - if(cfg->type == PHY_TYPE_PCIE) - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); if (cfg->has_pwrdn_delay) usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); - if (cfg->type != PHY_TYPE_DP) { - /* Pull PHY out of reset state */ - if (!cfg->no_pcs_sw_reset) - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); - /* start SerDes and Phy-Coding-Sublayer */ - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - - if (cfg->type == PHY_TYPE_UFS) { - status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; - mask = PCS_READY; - ready = PCS_READY; - } else { - status = pcs + cfg->regs[QPHY_PCS_STATUS]; - mask = cfg->phy_status; - ready = 0; - } + /* Pull PHY out of reset state */ + if (!cfg->no_pcs_sw_reset) + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, - PHY_INIT_COMPLETE_TIMEOUT); - if (ret) { - dev_err(qmp->dev, "phy initialization timed-out\n"); - goto err_disable_pipe_clk; - } + status = pcs + cfg->regs[QPHY_PCS_STATUS]; + mask = cfg->phy_status; + ready = 0; + + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, + PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(qmp->dev, "phy initialization timed-out\n"); + goto err_disable_pipe_clk; } + return 0; err_disable_pipe_clk: @@ -915,25 +835,20 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy) clk_disable_unprepare(qphy->pipe_clk); - if (cfg->type == PHY_TYPE_DP) { - /* Assert DP PHY power down */ - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); - } else { - /* PHY reset */ - if (!cfg->no_pcs_sw_reset) - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* PHY reset */ + if (!cfg->no_pcs_sw_reset) + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); - /* stop SerDes and Phy-Coding-Sublayer */ - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + /* stop SerDes and Phy-Coding-Sublayer */ + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - /* Put PHY into POWER DOWN state: active low */ - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], - cfg->pwrdn_ctrl); - } else { - qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, - cfg->pwrdn_ctrl); - } + /* Put PHY into POWER DOWN state: active low */ + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + } else { + qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); } return 0; @@ -987,112 +902,6 @@ static int qcom_qmp_phy_pcie_msm8996_set_mode(struct phy *phy, return 0; } -static void qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(struct qmp_phy *qphy) -{ - const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; - u32 intr_mask; - - if (qphy->mode == PHY_MODE_USB_HOST_SS || - qphy->mode == PHY_MODE_USB_DEVICE_SS) - intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; - else - intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; - - /* Clear any pending interrupts status */ - qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); - /* Writing 1 followed by 0 clears the interrupt */ - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); - - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], - ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); - - /* Enable required PHY autonomous mode interrupts */ - qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); - - /* Enable i/o clamp_n for autonomous mode */ - if (pcs_misc) - qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); -} - -static void qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(struct qmp_phy *qphy) -{ - const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; - - /* Disable i/o clamp_n on resume for normal mode */ - if (pcs_misc) - qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); - - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], - ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); - - qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); - /* Writing 1 followed by 0 clears the interrupt */ - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); -} - -static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_suspend(struct device *dev) -{ - struct qcom_qmp *qmp = dev_get_drvdata(dev); - struct qmp_phy *qphy = qmp->phys[0]; - const struct qmp_phy_cfg *cfg = qphy->cfg; - - dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); - - /* Supported only for USB3 PHY and luckily USB3 is the first phy */ - if (cfg->type != PHY_TYPE_USB3) - return 0; - - if (!qmp->init_count) { - dev_vdbg(dev, "PHY not initialized, bailing out\n"); - return 0; - } - - qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(qphy); - - clk_disable_unprepare(qphy->pipe_clk); - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); - - return 0; -} - -static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_resume(struct device *dev) -{ - struct qcom_qmp *qmp = dev_get_drvdata(dev); - struct qmp_phy *qphy = qmp->phys[0]; - const struct qmp_phy_cfg *cfg = qphy->cfg; - int ret = 0; - - dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); - - /* Supported only for USB3 PHY and luckily USB3 is the first phy */ - if (cfg->type != PHY_TYPE_USB3) - return 0; - - if (!qmp->init_count) { - dev_vdbg(dev, "PHY not initialized, bailing out\n"); - return 0; - } - - ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); - if (ret) - return ret; - - ret = clk_prepare_enable(qphy->pipe_clk); - if (ret) { - dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); - return ret; - } - - qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(qphy); - - return 0; -} - static int qcom_qmp_phy_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); @@ -1210,223 +1019,13 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); } -/* - * Display Port PLL driver block diagram for branch clocks - * - * +------------------------------+ - * | DP_VCO_CLK | - * | | - * | +-------------------+ | - * | | (DP PLL/VCO) | | - * | +---------+---------+ | - * | v | - * | +----------+-----------+ | - * | | hsclk_divsel_clk_src | | - * | +----------+-----------+ | - * +------------------------------+ - * | - * +---------<---------v------------>----------+ - * | | - * +--------v----------------+ | - * | dp_phy_pll_link_clk | | - * | link_clk | | - * +--------+----------------+ | - * | | - * | | - * v v - * Input to DISPCC block | - * for link clk, crypto clk | - * and interface clock | - * | - * | - * +--------<------------+-----------------+---<---+ - * | | | - * +----v---------+ +--------v-----+ +--------v------+ - * | vco_divided | | vco_divided | | vco_divided | - * | _clk_src | | _clk_src | | _clk_src | - * | | | | | | - * |divsel_six | | divsel_two | | divsel_four | - * +-------+------+ +-----+--------+ +--------+------+ - * | | | - * v---->----------v-------------<------v - * | - * +----------+-----------------+ - * | dp_phy_pll_vco_div_clk | - * +---------+------------------+ - * | - * v - * Input to DISPCC block - * for DP pixel clock - * - */ -static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - switch (req->rate) { - case 1620000000UL / 2: - case 2700000000UL / 2: - /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ - return 0; - default: - return -EINVAL; - } -} - -static unsigned long -qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -{ - const struct qmp_phy_dp_clks *dp_clks; - const struct qmp_phy *qphy; - const struct phy_configure_opts_dp *dp_opts; - - dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); - qphy = dp_clks->qphy; - dp_opts = &qphy->dp_opts; - - switch (dp_opts->link_rate) { - case 1620: - return 1620000000UL / 2; - case 2700: - return 2700000000UL / 2; - case 5400: - return 5400000000UL / 4; - case 8100: - return 8100000000UL / 6; - default: - return 0; - } -} - -static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { - .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, - .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, -}; - -static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - switch (req->rate) { - case 162000000: - case 270000000: - case 540000000: - case 810000000: - return 0; - default: - return -EINVAL; - } -} - -static unsigned long -qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -{ - const struct qmp_phy_dp_clks *dp_clks; - const struct qmp_phy *qphy; - const struct phy_configure_opts_dp *dp_opts; - - dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); - qphy = dp_clks->qphy; - dp_opts = &qphy->dp_opts; - - switch (dp_opts->link_rate) { - case 1620: - case 2700: - case 5400: - case 8100: - return dp_opts->link_rate * 100000; - default: - return 0; - } -} - -static const struct clk_ops qcom_qmp_dp_link_clk_ops = { - .determine_rate = qcom_qmp_dp_link_clk_determine_rate, - .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, -}; - -static struct clk_hw * -qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) -{ - struct qmp_phy_dp_clks *dp_clks = data; - unsigned int idx = clkspec->args[0]; - - if (idx >= 2) { - pr_err("%s: invalid index %u\n", __func__, idx); - return ERR_PTR(-EINVAL); - } - - if (idx == 0) - return &dp_clks->dp_link_hw; - - return &dp_clks->dp_pixel_hw; -} - -static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, - struct device_node *np) -{ - struct clk_init_data init = { }; - struct qmp_phy_dp_clks *dp_clks; - char name[64]; - int ret; - - dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); - if (!dp_clks) - return -ENOMEM; - - dp_clks->qphy = qphy; - qphy->dp_clks = dp_clks; - - snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); - init.ops = &qcom_qmp_dp_link_clk_ops; - init.name = name; - dp_clks->dp_link_hw.init = &init; - ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); - if (ret) - return ret; - - snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); - init.ops = &qcom_qmp_dp_pixel_clk_ops; - init.name = name; - dp_clks->dp_pixel_hw.init = &init; - ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); - if (ret) - return ret; - - ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); - if (ret) - return ret; - - /* - * Roll a devm action because the clock provider is the child node, but - * the child node is not actually a device. - */ - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); -} - -static const struct phy_ops qcom_qmp_phy_pcie_msm8996_gen_ops = { +static const struct phy_ops qcom_qmp_phy_pcie_msm8996_ops = { .init = qcom_qmp_phy_pcie_msm8996_enable, .exit = qcom_qmp_phy_pcie_msm8996_disable, .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode, .owner = THIS_MODULE, }; -static const struct phy_ops qcom_qmp_phy_pcie_msm8996_dp_ops = { - .init = qcom_qmp_phy_pcie_msm8996_init, - .configure = qcom_qmp_dp_phy_configure, - .power_on = qcom_qmp_phy_pcie_msm8996_power_on, - .calibrate = qcom_qmp_dp_phy_calibrate, - .power_off = qcom_qmp_phy_pcie_msm8996_power_off, - .exit = qcom_qmp_phy_pcie_msm8996_exit, - .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode, - .owner = THIS_MODULE, -}; - -static const struct phy_ops qcom_qmp_pcie_ufs_ops = { - .power_on = qcom_qmp_phy_pcie_msm8996_enable, - .power_off = qcom_qmp_phy_pcie_msm8996_disable, - .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode, - .owner = THIS_MODULE, -}; - static void qcom_qmp_reset_control_put(void *data) { reset_control_put(data); @@ -1439,7 +1038,6 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, struct qcom_qmp *qmp = dev_get_drvdata(dev); struct phy *generic_phy; struct qmp_phy *qphy; - const struct phy_ops *ops; char prop_name[MAX_PROP_NAME]; int ret; @@ -1532,14 +1130,7 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, return ret; } - if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) - ops = &qcom_qmp_pcie_ufs_ops; - else if (cfg->type == PHY_TYPE_DP) - ops = &qcom_qmp_phy_pcie_msm8996_dp_ops; - else - ops = &qcom_qmp_phy_pcie_msm8996_gen_ops; - - generic_phy = devm_phy_create(dev, np, ops); + generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_msm8996_ops); if (IS_ERR(generic_phy)) { ret = PTR_ERR(generic_phy); dev_err(dev, "failed to create qphy %d\n", ret); @@ -1564,11 +1155,6 @@ static const struct of_device_id qcom_qmp_phy_pcie_msm8996_of_match_table[] = { }; MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_msm8996_of_match_table); -static const struct dev_pm_ops qcom_qmp_phy_pcie_msm8996_pm_ops = { - SET_RUNTIME_PM_OPS(qcom_qmp_phy_pcie_msm8996_runtime_suspend, - qcom_qmp_phy_pcie_msm8996_runtime_resume, NULL) -}; - static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) { struct qcom_qmp *qmp; @@ -1576,12 +1162,7 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) struct device_node *child; struct phy_provider *phy_provider; void __iomem *serdes; - void __iomem *usb_serdes; - void __iomem *dp_serdes = NULL; - const struct qmp_phy_combo_cfg *combo_cfg = NULL; const struct qmp_phy_cfg *cfg = NULL; - const struct qmp_phy_cfg *usb_cfg = NULL; - const struct qmp_phy_cfg *dp_cfg = NULL; int num, id, expected_phys; int ret; @@ -1598,28 +1179,18 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) return -EINVAL; /* per PHY serdes; usually located at base address */ - usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); + serdes = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(serdes)) return PTR_ERR(serdes); /* per PHY dp_com; if PHY has dp_com control block */ - if (combo_cfg || cfg->has_phy_dp_com_ctrl) { + if (cfg->has_phy_dp_com_ctrl) { qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(qmp->dp_com)) return PTR_ERR(qmp->dp_com); } - if (combo_cfg) { - /* Only two serdes for combo PHY */ - dp_serdes = devm_platform_ioremap_resource(pdev, 2); - if (IS_ERR(dp_serdes)) - return PTR_ERR(dp_serdes); - - dp_cfg = combo_cfg->dp_cfg; - expected_phys = 2; - } else { - expected_phys = cfg->nlanes; - } + expected_phys = cfg->nlanes; mutex_init(&qmp->phy_mutex); @@ -1658,14 +1229,6 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) id = 0; for_each_available_child_of_node(dev->of_node, child) { - if (of_node_name_eq(child, "dp-phy")) { - cfg = dp_cfg; - serdes = dp_serdes; - } else if (of_node_name_eq(child, "usb3-phy")) { - cfg = usb_cfg; - serdes = usb_serdes; - } - /* Create per-lane phy */ ret = qcom_qmp_phy_pcie_msm8996_create(dev, child, id, serdes, cfg); if (ret) { @@ -1678,21 +1241,13 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) * Register the pipe clock provided by phy. * See function description to see details of this pipe clock. */ - if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { - ret = phy_pipe_clk_register(qmp, child); - if (ret) { - dev_err(qmp->dev, - "failed to register pipe clock source\n"); - goto err_node_put; - } - } else if (cfg->type == PHY_TYPE_DP) { - ret = phy_dp_clks_register(qmp, qmp->phys[id], child); - if (ret) { - dev_err(qmp->dev, - "failed to register DP clock source\n"); - goto err_node_put; - } + ret = phy_pipe_clk_register(qmp, child); + if (ret) { + dev_err(qmp->dev, + "failed to register pipe clock source\n"); + goto err_node_put; } + id++; } @@ -1714,7 +1269,6 @@ static struct platform_driver qcom_qmp_phy_pcie_msm8996_driver = { .probe = qcom_qmp_phy_pcie_msm8996_probe, .driver = { .name = "qcom-qmp-msm8996-pcie-phy", - .pm = &qcom_qmp_phy_pcie_msm8996_pm_ops, .of_match_table = qcom_qmp_phy_pcie_msm8996_of_match_table, }, }; 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Tue, 07 Jun 2022 14:32:30 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g23-20020ac24d97000000b0047255d21153sm3411343lfe.130.2022.06.07.14.32.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 14:32:29 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 17/30] phy: qcom-qmp-ufs: drop support for non-UFS PHY types Date: Wed, 8 Jun 2022 00:31:50 +0300 Message-Id: <20220607213203.2819885-18-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> References: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop remaining support for PHY types other than UFS. Acked-by: Bjorn Andersson Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 612 ++---------------------- 1 file changed, 35 insertions(+), 577 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index a8d48c70532c..0bf1990651b6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -986,7 +986,6 @@ static int qcom_qmp_phy_ufs_serdes_init(struct qmp_phy *qphy) struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; int serdes_tbl_num = cfg->serdes_tbl_num; int ret; @@ -996,35 +995,6 @@ static int qcom_qmp_phy_ufs_serdes_init(struct qmp_phy *qphy) qcom_qmp_phy_ufs_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, cfg->serdes_tbl_num_sec); - if (cfg->type == PHY_TYPE_DP) { - switch (dp_opts->link_rate) { - case 1620: - qcom_qmp_phy_ufs_configure(serdes, cfg->regs, - cfg->serdes_tbl_rbr, - cfg->serdes_tbl_rbr_num); - break; - case 2700: - qcom_qmp_phy_ufs_configure(serdes, cfg->regs, - cfg->serdes_tbl_hbr, - cfg->serdes_tbl_hbr_num); - break; - case 5400: - qcom_qmp_phy_ufs_configure(serdes, cfg->regs, - cfg->serdes_tbl_hbr2, - cfg->serdes_tbl_hbr2_num); - break; - case 8100: - qcom_qmp_phy_ufs_configure(serdes, cfg->regs, - cfg->serdes_tbl_hbr3, - cfg->serdes_tbl_hbr3_num); - break; - default: - /* Other link rates aren't supported */ - return -EINVAL; - } - } - - if (cfg->has_phy_com_ctrl) { void __iomem *status; unsigned int mask, val; @@ -1048,32 +1018,6 @@ static int qcom_qmp_phy_ufs_serdes_init(struct qmp_phy *qphy) return 0; } -static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) -{ - const struct phy_configure_opts_dp *dp_opts = &opts->dp; - struct qmp_phy *qphy = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qphy->cfg; - - memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); - if (qphy->dp_opts.set_voltages) { - cfg->configure_dp_tx(qphy); - qphy->dp_opts.set_voltages = 0; - } - - return 0; -} - -static int qcom_qmp_dp_phy_calibrate(struct phy *phy) -{ - struct qmp_phy *qphy = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qphy->cfg; - - if (cfg->calibrate_dp_phy) - return cfg->calibrate_dp_phy(qphy); - - return 0; -} - static int qcom_qmp_phy_ufs_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; @@ -1243,9 +1187,6 @@ static int qcom_qmp_phy_ufs_init(struct phy *phy) if (ret) return ret; - if (cfg->type == PHY_TYPE_DP) - cfg->dp_aux_init(qphy); - return 0; } @@ -1296,10 +1237,6 @@ static int qcom_qmp_phy_ufs_power_on(struct phy *phy) cfg->tx_tbl_num_sec, 2); } - /* Configure special DP tx tunings */ - if (cfg->type == PHY_TYPE_DP) - cfg->configure_dp_tx(qphy); - qcom_qmp_phy_ufs_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); if (cfg->rx_tbl_sec) @@ -1315,15 +1252,10 @@ static int qcom_qmp_phy_ufs_power_on(struct phy *phy) cfg->rx_tbl_num_sec, 2); } - /* Configure link rate, swing, etc. */ - if (cfg->type == PHY_TYPE_DP) { - cfg->configure_dp_phy(qphy); - } else { - qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); - if (cfg->pcs_tbl_sec) - qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, - cfg->pcs_tbl_num_sec); - } + qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + if (cfg->pcs_tbl_sec) + qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, + cfg->pcs_tbl_num_sec); ret = reset_control_deassert(qmp->ufs_reset); if (ret) @@ -1335,39 +1267,24 @@ static int qcom_qmp_phy_ufs_power_on(struct phy *phy) qcom_qmp_phy_ufs_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, cfg->pcs_misc_tbl_num_sec); - /* - * Pull out PHY from POWER DOWN state. - * This is active low enable signal to power-down PHY. - */ - if(cfg->type == PHY_TYPE_PCIE) - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); - if (cfg->has_pwrdn_delay) usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); - if (cfg->type != PHY_TYPE_DP) { - /* Pull PHY out of reset state */ - if (!cfg->no_pcs_sw_reset) - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); - /* start SerDes and Phy-Coding-Sublayer */ - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - - if (cfg->type == PHY_TYPE_UFS) { - status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; - mask = PCS_READY; - ready = PCS_READY; - } else { - status = pcs + cfg->regs[QPHY_PCS_STATUS]; - mask = cfg->phy_status; - ready = 0; - } + /* Pull PHY out of reset state */ + if (!cfg->no_pcs_sw_reset) + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* start SerDes and Phy-Coding-Sublayer */ + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, - PHY_INIT_COMPLETE_TIMEOUT); - if (ret) { - dev_err(qmp->dev, "phy initialization timed-out\n"); - goto err_disable_pipe_clk; - } + status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; + mask = PCS_READY; + ready = PCS_READY; + + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, + PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(qmp->dev, "phy initialization timed-out\n"); + goto err_disable_pipe_clk; } return 0; @@ -1387,25 +1304,20 @@ static int qcom_qmp_phy_ufs_power_off(struct phy *phy) clk_disable_unprepare(qphy->pipe_clk); - if (cfg->type == PHY_TYPE_DP) { - /* Assert DP PHY power down */ - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); - } else { - /* PHY reset */ - if (!cfg->no_pcs_sw_reset) - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* PHY reset */ + if (!cfg->no_pcs_sw_reset) + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); - /* stop SerDes and Phy-Coding-Sublayer */ - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); + /* stop SerDes and Phy-Coding-Sublayer */ + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); - /* Put PHY into POWER DOWN state: active low */ - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], - cfg->pwrdn_ctrl); - } else { - qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, - cfg->pwrdn_ctrl); - } + /* Put PHY into POWER DOWN state: active low */ + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + } else { + qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); } return 0; @@ -1459,112 +1371,6 @@ static int qcom_qmp_phy_ufs_set_mode(struct phy *phy, return 0; } -static void qcom_qmp_phy_ufs_enable_autonomous_mode(struct qmp_phy *qphy) -{ - const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; - u32 intr_mask; - - if (qphy->mode == PHY_MODE_USB_HOST_SS || - qphy->mode == PHY_MODE_USB_DEVICE_SS) - intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; - else - intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; - - /* Clear any pending interrupts status */ - qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); - /* Writing 1 followed by 0 clears the interrupt */ - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); - - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], - ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); - - /* Enable required PHY autonomous mode interrupts */ - qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); - - /* Enable i/o clamp_n for autonomous mode */ - if (pcs_misc) - qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); -} - -static void qcom_qmp_phy_ufs_disable_autonomous_mode(struct qmp_phy *qphy) -{ - const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; - - /* Disable i/o clamp_n on resume for normal mode */ - if (pcs_misc) - qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); - - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], - ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); - - qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); - /* Writing 1 followed by 0 clears the interrupt */ - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); -} - -static int __maybe_unused qcom_qmp_phy_ufs_runtime_suspend(struct device *dev) -{ - struct qcom_qmp *qmp = dev_get_drvdata(dev); - struct qmp_phy *qphy = qmp->phys[0]; - const struct qmp_phy_cfg *cfg = qphy->cfg; - - dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); - - /* Supported only for USB3 PHY and luckily USB3 is the first phy */ - if (cfg->type != PHY_TYPE_USB3) - return 0; - - if (!qmp->init_count) { - dev_vdbg(dev, "PHY not initialized, bailing out\n"); - return 0; - } - - qcom_qmp_phy_ufs_enable_autonomous_mode(qphy); - - clk_disable_unprepare(qphy->pipe_clk); - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); - - return 0; -} - -static int __maybe_unused qcom_qmp_phy_ufs_runtime_resume(struct device *dev) -{ - struct qcom_qmp *qmp = dev_get_drvdata(dev); - struct qmp_phy *qphy = qmp->phys[0]; - const struct qmp_phy_cfg *cfg = qphy->cfg; - int ret = 0; - - dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); - - /* Supported only for USB3 PHY and luckily USB3 is the first phy */ - if (cfg->type != PHY_TYPE_USB3) - return 0; - - if (!qmp->init_count) { - dev_vdbg(dev, "PHY not initialized, bailing out\n"); - return 0; - } - - ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); - if (ret) - return ret; - - ret = clk_prepare_enable(qphy->pipe_clk); - if (ret) { - dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); - return ret; - } - - qcom_qmp_phy_ufs_disable_autonomous_mode(qphy); - - return 0; -} - static int qcom_qmp_phy_ufs_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); @@ -1622,277 +1428,7 @@ static int qcom_qmp_phy_ufs_clk_init(struct device *dev, const struct qmp_phy_cf return devm_clk_bulk_get(dev, num, qmp->clks); } -static void phy_clk_release_provider(void *res) -{ - of_clk_del_provider(res); -} - -/* - * Register a fixed rate pipe clock. - * - * The _pipe_clksrc generated by PHY goes to the GCC that gate - * controls it. The _pipe_clk coming out of the GCC is requested - * by the PHY driver for its operations. - * We register the _pipe_clksrc here. The gcc driver takes care - * of assigning this _pipe_clksrc as parent to _pipe_clk. - * Below picture shows this relationship. - * - * +---------------+ - * | PHY block |<<---------------------------------------+ - * | | | - * | +-------+ | +-----+ | - * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ - * clk | +-------+ | +-----+ - * +---------------+ - */ -static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) -{ - struct clk_fixed_rate *fixed; - struct clk_init_data init = { }; - int ret; - - ret = of_property_read_string(np, "clock-output-names", &init.name); - if (ret) { - dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); - return ret; - } - - fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); - if (!fixed) - return -ENOMEM; - - init.ops = &clk_fixed_rate_ops; - - /* controllers using QMP phys use 125MHz pipe clock interface */ - fixed->fixed_rate = 125000000; - fixed->hw.init = &init; - - ret = devm_clk_hw_register(qmp->dev, &fixed->hw); - if (ret) - return ret; - - ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); - if (ret) - return ret; - - /* - * Roll a devm action because the clock provider is the child node, but - * the child node is not actually a device. - */ - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); -} - -/* - * Display Port PLL driver block diagram for branch clocks - * - * +------------------------------+ - * | DP_VCO_CLK | - * | | - * | +-------------------+ | - * | | (DP PLL/VCO) | | - * | +---------+---------+ | - * | v | - * | +----------+-----------+ | - * | | hsclk_divsel_clk_src | | - * | +----------+-----------+ | - * +------------------------------+ - * | - * +---------<---------v------------>----------+ - * | | - * +--------v----------------+ | - * | dp_phy_pll_link_clk | | - * | link_clk | | - * +--------+----------------+ | - * | | - * | | - * v v - * Input to DISPCC block | - * for link clk, crypto clk | - * and interface clock | - * | - * | - * +--------<------------+-----------------+---<---+ - * | | | - * +----v---------+ +--------v-----+ +--------v------+ - * | vco_divided | | vco_divided | | vco_divided | - * | _clk_src | | _clk_src | | _clk_src | - * | | | | | | - * |divsel_six | | divsel_two | | divsel_four | - * +-------+------+ +-----+--------+ +--------+------+ - * | | | - * v---->----------v-------------<------v - * | - * +----------+-----------------+ - * | dp_phy_pll_vco_div_clk | - * +---------+------------------+ - * | - * v - * Input to DISPCC block - * for DP pixel clock - * - */ -static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - switch (req->rate) { - case 1620000000UL / 2: - case 2700000000UL / 2: - /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ - return 0; - default: - return -EINVAL; - } -} - -static unsigned long -qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -{ - const struct qmp_phy_dp_clks *dp_clks; - const struct qmp_phy *qphy; - const struct phy_configure_opts_dp *dp_opts; - - dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); - qphy = dp_clks->qphy; - dp_opts = &qphy->dp_opts; - - switch (dp_opts->link_rate) { - case 1620: - return 1620000000UL / 2; - case 2700: - return 2700000000UL / 2; - case 5400: - return 5400000000UL / 4; - case 8100: - return 8100000000UL / 6; - default: - return 0; - } -} - -static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { - .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, - .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, -}; - -static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - switch (req->rate) { - case 162000000: - case 270000000: - case 540000000: - case 810000000: - return 0; - default: - return -EINVAL; - } -} - -static unsigned long -qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -{ - const struct qmp_phy_dp_clks *dp_clks; - const struct qmp_phy *qphy; - const struct phy_configure_opts_dp *dp_opts; - - dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); - qphy = dp_clks->qphy; - dp_opts = &qphy->dp_opts; - - switch (dp_opts->link_rate) { - case 1620: - case 2700: - case 5400: - case 8100: - return dp_opts->link_rate * 100000; - default: - return 0; - } -} - -static const struct clk_ops qcom_qmp_dp_link_clk_ops = { - .determine_rate = qcom_qmp_dp_link_clk_determine_rate, - .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, -}; - -static struct clk_hw * -qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) -{ - struct qmp_phy_dp_clks *dp_clks = data; - unsigned int idx = clkspec->args[0]; - - if (idx >= 2) { - pr_err("%s: invalid index %u\n", __func__, idx); - return ERR_PTR(-EINVAL); - } - - if (idx == 0) - return &dp_clks->dp_link_hw; - - return &dp_clks->dp_pixel_hw; -} - -static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, - struct device_node *np) -{ - struct clk_init_data init = { }; - struct qmp_phy_dp_clks *dp_clks; - char name[64]; - int ret; - - dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); - if (!dp_clks) - return -ENOMEM; - - dp_clks->qphy = qphy; - qphy->dp_clks = dp_clks; - - snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); - init.ops = &qcom_qmp_dp_link_clk_ops; - init.name = name; - dp_clks->dp_link_hw.init = &init; - ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); - if (ret) - return ret; - - snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); - init.ops = &qcom_qmp_dp_pixel_clk_ops; - init.name = name; - dp_clks->dp_pixel_hw.init = &init; - ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); - if (ret) - return ret; - - ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); - if (ret) - return ret; - - /* - * Roll a devm action because the clock provider is the child node, but - * the child node is not actually a device. - */ - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); -} - -static const struct phy_ops qcom_qmp_phy_ufs_gen_ops = { - .init = qcom_qmp_phy_ufs_enable, - .exit = qcom_qmp_phy_ufs_disable, - .set_mode = qcom_qmp_phy_ufs_set_mode, - .owner = THIS_MODULE, -}; - -static const struct phy_ops qcom_qmp_phy_ufs_dp_ops = { - .init = qcom_qmp_phy_ufs_init, - .configure = qcom_qmp_dp_phy_configure, - .power_on = qcom_qmp_phy_ufs_power_on, - .calibrate = qcom_qmp_dp_phy_calibrate, - .power_off = qcom_qmp_phy_ufs_power_off, - .exit = qcom_qmp_phy_ufs_exit, - .set_mode = qcom_qmp_phy_ufs_set_mode, - .owner = THIS_MODULE, -}; - -static const struct phy_ops qcom_qmp_pcie_ufs_ops = { +static const struct phy_ops qcom_qmp_ufs_ops = { .power_on = qcom_qmp_phy_ufs_enable, .power_off = qcom_qmp_phy_ufs_disable, .set_mode = qcom_qmp_phy_ufs_set_mode, @@ -1911,7 +1447,6 @@ int qcom_qmp_phy_ufs_create(struct device *dev, struct device_node *np, int id, struct qcom_qmp *qmp = dev_get_drvdata(dev); struct phy *generic_phy; struct qmp_phy *qphy; - const struct phy_ops *ops; char prop_name[MAX_PROP_NAME]; int ret; @@ -1968,28 +1503,6 @@ int qcom_qmp_phy_ufs_create(struct device *dev, struct device_node *np, int id, if (!qphy->pcs_misc) dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); - /* - * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 - * based phys, so they essentially have pipe clock. So, - * we return error in case phy is USB3 or PIPE type. - * Otherwise, we initialize pipe clock to NULL for - * all phys that don't need this. - */ - snprintf(prop_name, sizeof(prop_name), "pipe%d", id); - qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); - if (IS_ERR(qphy->pipe_clk)) { - if (cfg->type == PHY_TYPE_PCIE || - cfg->type == PHY_TYPE_USB3) { - ret = PTR_ERR(qphy->pipe_clk); - if (ret != -EPROBE_DEFER) - dev_err(dev, - "failed to get lane%d pipe_clk, %d\n", - id, ret); - return ret; - } - qphy->pipe_clk = NULL; - } - /* Get lane reset, if any */ if (cfg->has_lane_rst) { snprintf(prop_name, sizeof(prop_name), "lane%d", id); @@ -2004,14 +1517,7 @@ int qcom_qmp_phy_ufs_create(struct device *dev, struct device_node *np, int id, return ret; } - if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) - ops = &qcom_qmp_pcie_ufs_ops; - else if (cfg->type == PHY_TYPE_DP) - ops = &qcom_qmp_phy_ufs_dp_ops; - else - ops = &qcom_qmp_phy_ufs_gen_ops; - - generic_phy = devm_phy_create(dev, np, ops); + generic_phy = devm_phy_create(dev, np, &qcom_qmp_ufs_ops); if (IS_ERR(generic_phy)) { ret = PTR_ERR(generic_phy); dev_err(dev, "failed to create qphy %d\n", ret); @@ -2066,11 +1572,6 @@ static const struct of_device_id qcom_qmp_phy_ufs_of_match_table[] = { }; MODULE_DEVICE_TABLE(of, qcom_qmp_phy_ufs_of_match_table); -static const struct dev_pm_ops qcom_qmp_phy_ufs_pm_ops = { - SET_RUNTIME_PM_OPS(qcom_qmp_phy_ufs_runtime_suspend, - qcom_qmp_phy_ufs_runtime_resume, NULL) -}; - static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) { struct qcom_qmp *qmp; @@ -2078,12 +1579,7 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) struct device_node *child; struct phy_provider *phy_provider; void __iomem *serdes; - void __iomem *usb_serdes; - void __iomem *dp_serdes = NULL; - const struct qmp_phy_combo_cfg *combo_cfg = NULL; const struct qmp_phy_cfg *cfg = NULL; - const struct qmp_phy_cfg *usb_cfg = NULL; - const struct qmp_phy_cfg *dp_cfg = NULL; int num, id, expected_phys; int ret; @@ -2100,28 +1596,18 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) return -EINVAL; /* per PHY serdes; usually located at base address */ - usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); + serdes = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(serdes)) return PTR_ERR(serdes); /* per PHY dp_com; if PHY has dp_com control block */ - if (combo_cfg || cfg->has_phy_dp_com_ctrl) { + if (cfg->has_phy_dp_com_ctrl) { qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(qmp->dp_com)) return PTR_ERR(qmp->dp_com); } - if (combo_cfg) { - /* Only two serdes for combo PHY */ - dp_serdes = devm_platform_ioremap_resource(pdev, 2); - if (IS_ERR(dp_serdes)) - return PTR_ERR(dp_serdes); - - dp_cfg = combo_cfg->dp_cfg; - expected_phys = 2; - } else { - expected_phys = cfg->nlanes; - } + expected_phys = cfg->nlanes; mutex_init(&qmp->phy_mutex); @@ -2160,14 +1646,6 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) id = 0; for_each_available_child_of_node(dev->of_node, child) { - if (of_node_name_eq(child, "dp-phy")) { - cfg = dp_cfg; - serdes = dp_serdes; - } else if (of_node_name_eq(child, "usb3-phy")) { - cfg = usb_cfg; - serdes = usb_serdes; - } - /* Create per-lane phy */ ret = qcom_qmp_phy_ufs_create(dev, child, id, serdes, cfg); if (ret) { @@ -2176,25 +1654,6 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) goto err_node_put; } - /* - * Register the pipe clock provided by phy. - * See function description to see details of this pipe clock. - */ - if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { - ret = phy_pipe_clk_register(qmp, child); - if (ret) { - dev_err(qmp->dev, - "failed to register pipe clock source\n"); - goto err_node_put; - } - } else if (cfg->type == PHY_TYPE_DP) { - ret = phy_dp_clks_register(qmp, qmp->phys[id], child); - if (ret) { - dev_err(qmp->dev, - "failed to register DP clock source\n"); - goto err_node_put; - } - } id++; } @@ -2216,7 +1675,6 @@ static struct platform_driver qcom_qmp_phy_ufs_driver = { .probe = qcom_qmp_phy_ufs_probe, .driver = { .name = "qcom-qmp-ufs-phy", - .pm = &qcom_qmp_phy_ufs_pm_ops, .of_match_table = qcom_qmp_phy_ufs_of_match_table, }, }; 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Tue, 07 Jun 2022 14:32:32 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g23-20020ac24d97000000b0047255d21153sm3411343lfe.130.2022.06.07.14.32.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 14:32:31 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 19/30] phy: qcom-qmp-combo: cleanup the driver Date: Wed, 8 Jun 2022 00:31:52 +0300 Message-Id: <20220607213203.2819885-20-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> References: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove the conditionals and options that are not used by any of combo USB+DP PHY devices. Acked-by: Bjorn Andersson Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 169 ++-------------------- 1 file changed, 10 insertions(+), 159 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index fa9565844d8c..86dc400a037e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -616,24 +616,12 @@ struct qmp_phy_cfg { /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes_tbl; int serdes_tbl_num; - const struct qmp_phy_init_tbl *serdes_tbl_sec; - int serdes_tbl_num_sec; const struct qmp_phy_init_tbl *tx_tbl; int tx_tbl_num; - const struct qmp_phy_init_tbl *tx_tbl_sec; - int tx_tbl_num_sec; const struct qmp_phy_init_tbl *rx_tbl; int rx_tbl_num; - const struct qmp_phy_init_tbl *rx_tbl_sec; - int rx_tbl_num_sec; const struct qmp_phy_init_tbl *pcs_tbl; int pcs_tbl_num; - const struct qmp_phy_init_tbl *pcs_tbl_sec; - int pcs_tbl_num_sec; - const struct qmp_phy_init_tbl *pcs_misc_tbl; - int pcs_misc_tbl_num; - const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; - int pcs_misc_tbl_num_sec; /* Init sequence for DP PHY block link rates */ const struct qmp_phy_init_tbl *serdes_tbl_rbr; @@ -666,14 +654,9 @@ struct qmp_phy_cfg { unsigned int start_ctrl; unsigned int pwrdn_ctrl; - unsigned int mask_com_pcs_ready; /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ unsigned int phy_status; - /* true, if PHY has a separate PHY_COM control block */ - bool has_phy_com_ctrl; - /* true, if PHY has a reset for individual lanes */ - bool has_lane_rst; /* true, if PHY needs delay after POWER_DOWN */ bool has_pwrdn_delay; /* power_down delay in usec */ @@ -684,9 +667,6 @@ struct qmp_phy_cfg { bool has_phy_dp_com_ctrl; /* true, if PHY has secondary tx/rx lanes to be configured */ bool is_dual_lane_phy; - - /* true, if PCS block has no separate SW_RESET register */ - bool no_pcs_sw_reset; }; struct qmp_phy_combo_cfg { @@ -1084,18 +1064,13 @@ static void qcom_qmp_phy_combo_configure(void __iomem *base, static int qcom_qmp_phy_combo_serdes_init(struct qmp_phy *qphy) { - struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; int serdes_tbl_num = cfg->serdes_tbl_num; - int ret; qcom_qmp_phy_combo_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); - if (cfg->serdes_tbl_sec) - qcom_qmp_phy_combo_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, - cfg->serdes_tbl_num_sec); if (cfg->type == PHY_TYPE_DP) { switch (dp_opts->link_rate) { @@ -1125,27 +1100,6 @@ static int qcom_qmp_phy_combo_serdes_init(struct qmp_phy *qphy) } } - - if (cfg->has_phy_com_ctrl) { - void __iomem *status; - unsigned int mask, val; - - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], - SERDES_START | PCS_START); - - status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; - mask = cfg->mask_com_pcs_ready; - - ret = readl_poll_timeout(status, val, (val & mask), 10, - PHY_INIT_COMPLETE_TIMEOUT); - if (ret) { - dev_err(qmp->dev, - "phy common block init timed-out\n"); - return ret; - } - } - return 0; } @@ -1630,7 +1584,6 @@ static int qcom_qmp_phy_combo_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *serdes = qphy->serdes; void __iomem *pcs = qphy->pcs; void __iomem *dp_com = qmp->dp_com; int ret, i; @@ -1693,18 +1646,13 @@ static int qcom_qmp_phy_combo_com_init(struct qmp_phy *qphy) qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); } - if (cfg->has_phy_com_ctrl) { - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], - SW_PWRDN); - } else { - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) - qphy_setbits(pcs, - cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], - cfg->pwrdn_ctrl); - else - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, - cfg->pwrdn_ctrl); - } + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) + qphy_setbits(pcs, + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + else + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); mutex_unlock(&qmp->phy_mutex); @@ -1725,7 +1673,6 @@ static int qcom_qmp_phy_combo_com_exit(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *serdes = qphy->serdes; int i = cfg->num_resets; mutex_lock(&qmp->phy_mutex); @@ -1735,14 +1682,6 @@ static int qcom_qmp_phy_combo_com_exit(struct qmp_phy *qphy) } reset_control_assert(qmp->ufs_reset); - if (cfg->has_phy_com_ctrl) { - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], - SERDES_START | PCS_START); - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], - SW_RESET); - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], - SW_PWRDN); - } while (--i >= 0) reset_control_assert(qmp->resets[i]); @@ -1764,33 +1703,6 @@ static int qcom_qmp_phy_combo_init(struct phy *phy) int ret; dev_vdbg(qmp->dev, "Initializing QMP phy\n"); - if (cfg->no_pcs_sw_reset) { - /* - * Get UFS reset, which is delayed until now to avoid a - * circular dependency where UFS needs its PHY, but the PHY - * needs this UFS reset. - */ - if (!qmp->ufs_reset) { - qmp->ufs_reset = - devm_reset_control_get_exclusive(qmp->dev, - "ufsphy"); - - if (IS_ERR(qmp->ufs_reset)) { - ret = PTR_ERR(qmp->ufs_reset); - dev_err(qmp->dev, - "failed to get UFS reset: %d\n", - ret); - - qmp->ufs_reset = NULL; - return ret; - } - } - - ret = reset_control_assert(qmp->ufs_reset); - if (ret) - return ret; - } - ret = qcom_qmp_phy_combo_com_init(qphy); if (ret) return ret; @@ -1809,43 +1721,26 @@ static int qcom_qmp_phy_combo_power_on(struct phy *phy) void __iomem *tx = qphy->tx; void __iomem *rx = qphy->rx; void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; void __iomem *status; unsigned int mask, val, ready; int ret; qcom_qmp_phy_combo_serdes_init(qphy); - if (cfg->has_lane_rst) { - ret = reset_control_deassert(qphy->lane_rst); - if (ret) { - dev_err(qmp->dev, "lane%d reset deassert failed\n", - qphy->index); - return ret; - } - } - ret = clk_prepare_enable(qphy->pipe_clk); if (ret) { dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); - goto err_reset_lane; + return ret; } /* Tx, Rx, and PCS configurations */ qcom_qmp_phy_combo_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); - if (cfg->tx_tbl_sec) - qcom_qmp_phy_combo_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, - cfg->tx_tbl_num_sec, 1); /* Configuration for other LANE for USB-DP combo PHY */ if (cfg->is_dual_lane_phy) { qcom_qmp_phy_combo_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 2); - if (cfg->tx_tbl_sec) - qcom_qmp_phy_combo_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl_sec, - cfg->tx_tbl_num_sec, 2); } /* Configure special DP tx tunings */ @@ -1854,17 +1749,10 @@ static int qcom_qmp_phy_combo_power_on(struct phy *phy) qcom_qmp_phy_combo_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); - if (cfg->rx_tbl_sec) - qcom_qmp_phy_combo_configure_lane(rx, cfg->regs, - cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); if (cfg->is_dual_lane_phy) { qcom_qmp_phy_combo_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 2); - if (cfg->rx_tbl_sec) - qcom_qmp_phy_combo_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl_sec, - cfg->rx_tbl_num_sec, 2); } /* Configure link rate, swing, etc. */ @@ -1872,28 +1760,18 @@ static int qcom_qmp_phy_combo_power_on(struct phy *phy) cfg->configure_dp_phy(qphy); } else { qcom_qmp_phy_combo_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); - if (cfg->pcs_tbl_sec) - qcom_qmp_phy_combo_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, - cfg->pcs_tbl_num_sec); } ret = reset_control_deassert(qmp->ufs_reset); if (ret) goto err_disable_pipe_clk; - qcom_qmp_phy_combo_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, - cfg->pcs_misc_tbl_num); - if (cfg->pcs_misc_tbl_sec) - qcom_qmp_phy_combo_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, - cfg->pcs_misc_tbl_num_sec); - if (cfg->has_pwrdn_delay) usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); if (cfg->type != PHY_TYPE_DP) { /* Pull PHY out of reset state */ - if (!cfg->no_pcs_sw_reset) - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); /* start SerDes and Phy-Coding-Sublayer */ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); @@ -1912,9 +1790,6 @@ static int qcom_qmp_phy_combo_power_on(struct phy *phy) err_disable_pipe_clk: clk_disable_unprepare(qphy->pipe_clk); -err_reset_lane: - if (cfg->has_lane_rst) - reset_control_assert(qphy->lane_rst); return ret; } @@ -1931,8 +1806,7 @@ static int qcom_qmp_phy_combo_power_off(struct phy *phy) writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); } else { /* PHY reset */ - if (!cfg->no_pcs_sw_reset) - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); /* stop SerDes and Phy-Coding-Sublayer */ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); @@ -1953,10 +1827,6 @@ static int qcom_qmp_phy_combo_power_off(struct phy *phy) static int qcom_qmp_phy_combo_exit(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qphy->cfg; - - if (cfg->has_lane_rst) - reset_control_assert(qphy->lane_rst); qcom_qmp_phy_combo_com_exit(qphy); @@ -2431,11 +2301,6 @@ static const struct phy_ops qcom_qmp_phy_combo_dp_ops = { .owner = THIS_MODULE, }; -static void qcom_qmp_reset_control_put(void *data) -{ - reset_control_put(data); -} - static int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id, void __iomem *serdes, const struct qmp_phy_cfg *cfg) @@ -2521,20 +2386,6 @@ int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id qphy->pipe_clk = NULL; } - /* Get lane reset, if any */ - if (cfg->has_lane_rst) { - snprintf(prop_name, sizeof(prop_name), "lane%d", id); - qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); - if (IS_ERR(qphy->lane_rst)) { - dev_err(dev, "failed to get lane%d reset\n", id); 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Tue, 07 Jun 2022 14:32:32 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 20/30] phy: qcom-qmp-pcie: cleanup the driver Date: Wed, 8 Jun 2022 00:31:53 +0300 Message-Id: <20220607213203.2819885-21-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> References: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove the conditionals and options that are not used by any of PCIe PHY devices. Acked-by: Bjorn Andersson Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 213 ++--------------------- 1 file changed, 11 insertions(+), 202 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index b780994692b3..d9e8a3e88890 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1257,22 +1257,6 @@ struct qmp_phy_cfg { const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; int pcs_misc_tbl_num_sec; - /* Init sequence for DP PHY block link rates */ - const struct qmp_phy_init_tbl *serdes_tbl_rbr; - int serdes_tbl_rbr_num; - const struct qmp_phy_init_tbl *serdes_tbl_hbr; - int serdes_tbl_hbr_num; - const struct qmp_phy_init_tbl *serdes_tbl_hbr2; - int serdes_tbl_hbr2_num; - const struct qmp_phy_init_tbl *serdes_tbl_hbr3; - int serdes_tbl_hbr3_num; - - /* DP PHY callbacks */ - int (*configure_dp_phy)(struct qmp_phy *qphy); - void (*configure_dp_tx)(struct qmp_phy *qphy); - int (*calibrate_dp_phy)(struct qmp_phy *qphy); - void (*dp_aux_init)(struct qmp_phy *qphy); - /* clock ids to be requested */ const char * const *clk_list; int num_clks; @@ -1292,28 +1276,14 @@ struct qmp_phy_cfg { /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ unsigned int phy_status; - /* true, if PHY has a separate PHY_COM control block */ - bool has_phy_com_ctrl; - /* true, if PHY has a reset for individual lanes */ - bool has_lane_rst; /* true, if PHY needs delay after POWER_DOWN */ bool has_pwrdn_delay; /* power_down delay in usec */ int pwrdn_delay_min; int pwrdn_delay_max; - /* true, if PHY has a separate DP_COM control block */ - bool has_phy_dp_com_ctrl; /* true, if PHY has secondary tx/rx lanes to be configured */ bool is_dual_lane_phy; - - /* true, if PCS block has no separate SW_RESET register */ - bool no_pcs_sw_reset; -}; - -struct qmp_phy_combo_cfg { - const struct qmp_phy_cfg *usb_cfg; - const struct qmp_phy_cfg *dp_cfg; }; /** @@ -1331,11 +1301,7 @@ struct qmp_phy_combo_cfg { * @pipe_clk: pipe clock * @index: lane index * @qmp: QMP phy to which this lane belongs - * @lane_rst: lane's reset controller * @mode: current PHY mode - * @dp_aux_cfg: Display port aux config - * @dp_opts: Display port optional config - * @dp_clks: Display port clocks */ struct qmp_phy { struct phy *phy; @@ -1350,24 +1316,13 @@ struct qmp_phy { struct clk *pipe_clk; unsigned int index; struct qcom_qmp *qmp; - struct reset_control *lane_rst; enum phy_mode mode; - unsigned int dp_aux_cfg; - struct phy_configure_opts_dp dp_opts; - struct qmp_phy_dp_clks *dp_clks; -}; - -struct qmp_phy_dp_clks { - struct qmp_phy *qphy; - struct clk_hw dp_link_hw; - struct clk_hw dp_pixel_hw; }; /** * struct qcom_qmp - structure holding QMP phy block attributes * * @dev: device - * @dp_com: iomapped memory space for phy's dp_com control block * * @clks: array of clocks required by phy * @resets: array of resets required by phy @@ -1376,11 +1331,9 @@ struct qmp_phy_dp_clks { * @phys: array of per-lane phy descriptors * @phy_mutex: mutex lock for PHY common block initialization * @init_count: phy common block initialization count - * @ufs_reset: optional UFS PHY reset handle */ struct qcom_qmp { struct device *dev; - void __iomem *dp_com; struct clk_bulk_data *clks; struct reset_control **resets; @@ -1390,8 +1343,6 @@ struct qcom_qmp { struct mutex phy_mutex; int init_count; - - struct reset_control *ufs_reset; }; static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -1470,8 +1421,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, - .has_phy_com_ctrl = false, - .has_lane_rst = false, .has_pwrdn_delay = true, .pwrdn_delay_min = 995, /* us */ .pwrdn_delay_max = 1005, /* us */ @@ -1500,8 +1449,6 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { .start_ctrl = SERDES_START | PCS_START, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, - .has_phy_com_ctrl = false, - .has_lane_rst = false, .has_pwrdn_delay = true, .pwrdn_delay_min = 995, /* us */ .pwrdn_delay_max = 1005, /* us */ @@ -1829,38 +1776,16 @@ static void qcom_qmp_phy_pcie_configure(void __iomem *base, static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy) { - struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; int serdes_tbl_num = cfg->serdes_tbl_num; - int ret; qcom_qmp_phy_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); if (cfg->serdes_tbl_sec) qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, cfg->serdes_tbl_num_sec); - if (cfg->has_phy_com_ctrl) { - void __iomem *status; - unsigned int mask, val; - - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], - SERDES_START | PCS_START); - - status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; - mask = cfg->mask_com_pcs_ready; - - ret = readl_poll_timeout(status, val, (val & mask), 10, - PHY_INIT_COMPLETE_TIMEOUT); - if (ret) { - dev_err(qmp->dev, - "phy common block init timed-out\n"); - return ret; - } - } - return 0; } @@ -1868,9 +1793,7 @@ static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *serdes = qphy->serdes; void __iomem *pcs = qphy->pcs; - void __iomem *dp_com = qmp->dp_com; int ret, i; mutex_lock(&qmp->phy_mutex); @@ -1908,41 +1831,13 @@ static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy) if (ret) goto err_assert_reset; - if (cfg->has_phy_dp_com_ctrl) { - qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, - SW_PWRDN); - /* override hardware control for reset of qmp phy */ - qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); - - /* Default type-c orientation, i.e CC1 */ - qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); - - qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, - USB3_MODE | DP_MODE); - - /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ - qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); - - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); - } - - if (cfg->has_phy_com_ctrl) { - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], - SW_PWRDN); - } else { - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) - qphy_setbits(pcs, - cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], - cfg->pwrdn_ctrl); - else - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, - cfg->pwrdn_ctrl); - } + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) + qphy_setbits(pcs, + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + else + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); mutex_unlock(&qmp->phy_mutex); @@ -1963,7 +1858,6 @@ static int qcom_qmp_phy_pcie_com_exit(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *serdes = qphy->serdes; int i = cfg->num_resets; mutex_lock(&qmp->phy_mutex); @@ -1972,16 +1866,6 @@ static int qcom_qmp_phy_pcie_com_exit(struct qmp_phy *qphy) return 0; } - reset_control_assert(qmp->ufs_reset); - if (cfg->has_phy_com_ctrl) { - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], - SERDES_START | PCS_START); - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], - SW_RESET); - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], - SW_PWRDN); - } - while (--i >= 0) reset_control_assert(qmp->resets[i]); @@ -1998,37 +1882,9 @@ static int qcom_qmp_phy_pcie_init(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qphy->cfg; int ret; dev_vdbg(qmp->dev, "Initializing QMP phy\n"); - if (cfg->no_pcs_sw_reset) { - /* - * Get UFS reset, which is delayed until now to avoid a - * circular dependency where UFS needs its PHY, but the PHY - * needs this UFS reset. - */ - if (!qmp->ufs_reset) { - qmp->ufs_reset = - devm_reset_control_get_exclusive(qmp->dev, - "ufsphy"); - - if (IS_ERR(qmp->ufs_reset)) { - ret = PTR_ERR(qmp->ufs_reset); - dev_err(qmp->dev, - "failed to get UFS reset: %d\n", - ret); - - qmp->ufs_reset = NULL; - return ret; - } - } - - ret = reset_control_assert(qmp->ufs_reset); - if (ret) - return ret; - } - ret = qcom_qmp_phy_pcie_com_init(qphy); if (ret) return ret; @@ -2051,19 +1907,10 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy) qcom_qmp_phy_pcie_serdes_init(qphy); - if (cfg->has_lane_rst) { - ret = reset_control_deassert(qphy->lane_rst); - if (ret) { - dev_err(qmp->dev, "lane%d reset deassert failed\n", - qphy->index); - return ret; - } - } - ret = clk_prepare_enable(qphy->pipe_clk); if (ret) { dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); - goto err_reset_lane; + return ret; } /* Tx, Rx, and PCS configurations */ @@ -2103,10 +1950,6 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy) qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, cfg->pcs_tbl_num_sec); - ret = reset_control_deassert(qmp->ufs_reset); - if (ret) - goto err_disable_pipe_clk; - qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num); if (cfg->pcs_misc_tbl_sec) @@ -2123,8 +1966,8 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy) usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); /* Pull PHY out of reset state */ - if (!cfg->no_pcs_sw_reset) - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* start SerDes and Phy-Coding-Sublayer */ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); @@ -2143,9 +1986,6 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy) err_disable_pipe_clk: clk_disable_unprepare(qphy->pipe_clk); -err_reset_lane: - if (cfg->has_lane_rst) - reset_control_assert(qphy->lane_rst); return ret; } @@ -2158,8 +1998,7 @@ static int qcom_qmp_phy_pcie_power_off(struct phy *phy) clk_disable_unprepare(qphy->pipe_clk); /* PHY reset */ - if (!cfg->no_pcs_sw_reset) - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); /* stop SerDes and Phy-Coding-Sublayer */ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); @@ -2179,10 +2018,6 @@ static int qcom_qmp_phy_pcie_power_off(struct phy *phy) static int qcom_qmp_phy_pcie_exit(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qphy->cfg; - - if (cfg->has_lane_rst) - reset_control_assert(qphy->lane_rst); qcom_qmp_phy_pcie_com_exit(qphy); @@ -2348,11 +2183,6 @@ static const struct phy_ops qcom_qmp_phy_pcie_ops = { .owner = THIS_MODULE, }; -static void qcom_qmp_reset_control_put(void *data) -{ - reset_control_put(data); -} - static int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id, void __iomem *serdes, const struct qmp_phy_cfg *cfg) @@ -2438,20 +2268,6 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id, qphy->pipe_clk = NULL; } - /* Get lane reset, if any */ - if (cfg->has_lane_rst) { - snprintf(prop_name, sizeof(prop_name), "lane%d", id); - qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); - if (IS_ERR(qphy->lane_rst)) { - dev_err(dev, "failed to get lane%d reset\n", id); - return PTR_ERR(qphy->lane_rst); - } - ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, - qphy->lane_rst); - if (ret) - return ret; - } - generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_ops); if (IS_ERR(generic_phy)) { ret = PTR_ERR(generic_phy); @@ -2538,13 +2354,6 @@ static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) if (IS_ERR(serdes)) return PTR_ERR(serdes); - /* per PHY dp_com; if PHY has dp_com control block */ - if (cfg->has_phy_dp_com_ctrl) { - qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(qmp->dp_com)) - return PTR_ERR(qmp->dp_com); - } - expected_phys = cfg->nlanes; mutex_init(&qmp->phy_mutex); From patchwork Tue Jun 7 21:31:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579912 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECE8DC43334 for ; Wed, 8 Jun 2022 03:36:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232459AbiFHDgi (ORCPT ); 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Tue, 07 Jun 2022 14:32:34 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 21/30] phy: qcom-qmp-pcie-msm8996: cleanup the driver Date: Wed, 8 Jun 2022 00:31:54 +0300 Message-Id: <20220607213203.2819885-22-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> References: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove the conditionals and options that are not used by the MSM8996 PCIe PHY device. Hardcode has_lane_rst and has_phy_com_ctrl as this is the case for this PHY. Acked-by: Bjorn Andersson Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov --- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 268 +++--------------- 1 file changed, 41 insertions(+), 227 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 02e5ae7fa213..51da3a3a199e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -266,22 +266,6 @@ struct qmp_phy_cfg { const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; int pcs_misc_tbl_num_sec; - /* Init sequence for DP PHY block link rates */ - const struct qmp_phy_init_tbl *serdes_tbl_rbr; - int serdes_tbl_rbr_num; - const struct qmp_phy_init_tbl *serdes_tbl_hbr; - int serdes_tbl_hbr_num; - const struct qmp_phy_init_tbl *serdes_tbl_hbr2; - int serdes_tbl_hbr2_num; - const struct qmp_phy_init_tbl *serdes_tbl_hbr3; - int serdes_tbl_hbr3_num; - - /* DP PHY callbacks */ - int (*configure_dp_phy)(struct qmp_phy *qphy); - void (*configure_dp_tx)(struct qmp_phy *qphy); - int (*calibrate_dp_phy)(struct qmp_phy *qphy); - void (*dp_aux_init)(struct qmp_phy *qphy); - /* clock ids to be requested */ const char * const *clk_list; int num_clks; @@ -301,28 +285,11 @@ struct qmp_phy_cfg { /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ unsigned int phy_status; - /* true, if PHY has a separate PHY_COM control block */ - bool has_phy_com_ctrl; - /* true, if PHY has a reset for individual lanes */ - bool has_lane_rst; /* true, if PHY needs delay after POWER_DOWN */ bool has_pwrdn_delay; /* power_down delay in usec */ int pwrdn_delay_min; int pwrdn_delay_max; - - /* true, if PHY has a separate DP_COM control block */ - bool has_phy_dp_com_ctrl; - /* true, if PHY has secondary tx/rx lanes to be configured */ - bool is_dual_lane_phy; - - /* true, if PCS block has no separate SW_RESET register */ - bool no_pcs_sw_reset; -}; - -struct qmp_phy_combo_cfg { - const struct qmp_phy_cfg *usb_cfg; - const struct qmp_phy_cfg *dp_cfg; }; /** @@ -334,17 +301,12 @@ struct qmp_phy_combo_cfg { * @tx: iomapped memory space for lane's tx * @rx: iomapped memory space for lane's rx * @pcs: iomapped memory space for lane's pcs - * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) - * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) * @pcs_misc: iomapped memory space for lane's pcs_misc * @pipe_clk: pipe clock * @index: lane index * @qmp: QMP phy to which this lane belongs * @lane_rst: lane's reset controller * @mode: current PHY mode - * @dp_aux_cfg: Display port aux config - * @dp_opts: Display port optional config - * @dp_clks: Display port clocks */ struct qmp_phy { struct phy *phy; @@ -353,30 +315,18 @@ struct qmp_phy { void __iomem *tx; void __iomem *rx; void __iomem *pcs; - void __iomem *tx2; - void __iomem *rx2; void __iomem *pcs_misc; struct clk *pipe_clk; unsigned int index; struct qcom_qmp *qmp; struct reset_control *lane_rst; enum phy_mode mode; - unsigned int dp_aux_cfg; - struct phy_configure_opts_dp dp_opts; - struct qmp_phy_dp_clks *dp_clks; -}; - -struct qmp_phy_dp_clks { - struct qmp_phy *qphy; - struct clk_hw dp_link_hw; - struct clk_hw dp_pixel_hw; }; /** * struct qcom_qmp - structure holding QMP phy block attributes * * @dev: device - * @dp_com: iomapped memory space for phy's dp_com control block * * @clks: array of clocks required by phy * @resets: array of resets required by phy @@ -385,11 +335,9 @@ struct qmp_phy_dp_clks { * @phys: array of per-lane phy descriptors * @phy_mutex: mutex lock for PHY common block initialization * @init_count: phy common block initialization count - * @ufs_reset: optional UFS PHY reset handle */ struct qcom_qmp { struct device *dev; - void __iomem *dp_com; struct clk_bulk_data *clks; struct reset_control **resets; @@ -399,8 +347,6 @@ struct qcom_qmp { struct mutex phy_mutex; int init_count; - - struct reset_control *ufs_reset; }; static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -467,8 +413,6 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = { .mask_com_pcs_ready = PCS_READY, .phy_status = PHYSTATUS, - .has_phy_com_ctrl = true, - .has_lane_rst = true, .has_pwrdn_delay = true, .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, @@ -512,6 +456,8 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) void __iomem *serdes = qphy->serdes; const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; int serdes_tbl_num = cfg->serdes_tbl_num; + void __iomem *status; + unsigned int mask, val; int ret; qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); @@ -519,24 +465,20 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy) qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, cfg->serdes_tbl_num_sec); - if (cfg->has_phy_com_ctrl) { - void __iomem *status; - unsigned int mask, val; - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], - SERDES_START | PCS_START); + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], + SERDES_START | PCS_START); - status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; - mask = cfg->mask_com_pcs_ready; + status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; + mask = cfg->mask_com_pcs_ready; - ret = readl_poll_timeout(status, val, (val & mask), 10, - PHY_INIT_COMPLETE_TIMEOUT); - if (ret) { - dev_err(qmp->dev, - "phy common block init timed-out\n"); - return ret; - } + ret = readl_poll_timeout(status, val, (val & mask), 10, + PHY_INIT_COMPLETE_TIMEOUT); + if (ret) { + dev_err(qmp->dev, + "phy common block init timed-out\n"); + return ret; } return 0; @@ -547,8 +489,6 @@ static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy) struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; - void __iomem *pcs = qphy->pcs; - void __iomem *dp_com = qmp->dp_com; int ret, i; mutex_lock(&qmp->phy_mutex); @@ -586,41 +526,8 @@ static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy) if (ret) goto err_assert_reset; - if (cfg->has_phy_dp_com_ctrl) { - qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, - SW_PWRDN); - /* override hardware control for reset of qmp phy */ - qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); - - /* Default type-c orientation, i.e CC1 */ - qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); - - qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, - USB3_MODE | DP_MODE); - - /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ - qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); - - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); - } - - if (cfg->has_phy_com_ctrl) { - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], - SW_PWRDN); - } else { - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) - qphy_setbits(pcs, - cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], - cfg->pwrdn_ctrl); - else - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, - cfg->pwrdn_ctrl); - } + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], + SW_PWRDN); mutex_unlock(&qmp->phy_mutex); @@ -650,15 +557,12 @@ static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy) return 0; } - reset_control_assert(qmp->ufs_reset); - if (cfg->has_phy_com_ctrl) { - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], - SERDES_START | PCS_START); - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], - SW_RESET); - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], - SW_PWRDN); - } + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], + SERDES_START | PCS_START); + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], + SW_RESET); + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], + SW_PWRDN); while (--i >= 0) reset_control_assert(qmp->resets[i]); @@ -676,37 +580,9 @@ static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qphy->cfg; int ret; dev_vdbg(qmp->dev, "Initializing QMP phy\n"); - if (cfg->no_pcs_sw_reset) { - /* - * Get UFS reset, which is delayed until now to avoid a - * circular dependency where UFS needs its PHY, but the PHY - * needs this UFS reset. - */ - if (!qmp->ufs_reset) { - qmp->ufs_reset = - devm_reset_control_get_exclusive(qmp->dev, - "ufsphy"); - - if (IS_ERR(qmp->ufs_reset)) { - ret = PTR_ERR(qmp->ufs_reset); - dev_err(qmp->dev, - "failed to get UFS reset: %d\n", - ret); - - qmp->ufs_reset = NULL; - return ret; - } - } - - ret = reset_control_assert(qmp->ufs_reset); - if (ret) - return ret; - } - ret = qcom_qmp_phy_pcie_msm8996_com_init(qphy); if (ret) return ret; @@ -729,13 +605,11 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) qcom_qmp_phy_pcie_msm8996_serdes_init(qphy); - if (cfg->has_lane_rst) { - ret = reset_control_deassert(qphy->lane_rst); - if (ret) { - dev_err(qmp->dev, "lane%d reset deassert failed\n", - qphy->index); - return ret; - } + ret = reset_control_deassert(qphy->lane_rst); + if (ret) { + dev_err(qmp->dev, "lane%d reset deassert failed\n", + qphy->index); + return ret; } ret = clk_prepare_enable(qphy->pipe_clk); @@ -751,40 +625,17 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, cfg->tx_tbl_num_sec, 1); - /* Configuration for other LANE for USB-DP combo PHY */ - if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 2); - if (cfg->tx_tbl_sec) - qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl_sec, - cfg->tx_tbl_num_sec, 2); - } - qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); if (cfg->rx_tbl_sec) qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); - if (cfg->is_dual_lane_phy) { - qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 2); - if (cfg->rx_tbl_sec) - qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl_sec, - cfg->rx_tbl_num_sec, 2); - } - qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); if (cfg->pcs_tbl_sec) qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, cfg->pcs_tbl_num_sec); - ret = reset_control_deassert(qmp->ufs_reset); - if (ret) - goto err_disable_pipe_clk; - qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num); if (cfg->pcs_misc_tbl_sec) @@ -801,8 +652,8 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); /* Pull PHY out of reset state */ - if (!cfg->no_pcs_sw_reset) - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + /* start SerDes and Phy-Coding-Sublayer */ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); @@ -822,8 +673,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy) err_disable_pipe_clk: clk_disable_unprepare(qphy->pipe_clk); err_reset_lane: - if (cfg->has_lane_rst) - reset_control_assert(qphy->lane_rst); + reset_control_assert(qphy->lane_rst); return ret; } @@ -836,8 +686,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy) clk_disable_unprepare(qphy->pipe_clk); /* PHY reset */ - if (!cfg->no_pcs_sw_reset) - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); /* stop SerDes and Phy-Coding-Sublayer */ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); @@ -857,10 +706,8 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy) static int qcom_qmp_phy_pcie_msm8996_exit(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qphy->cfg; - if (cfg->has_lane_rst) - reset_control_assert(qphy->lane_rst); + reset_control_assert(qphy->lane_rst); qcom_qmp_phy_pcie_msm8996_com_exit(qphy); @@ -1065,31 +912,7 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, if (!qphy->pcs) return -ENOMEM; - /* - * If this is a dual-lane PHY, then there should be registers for the - * second lane. Some old device trees did not specify this, so fall - * back to old legacy behavior of assuming they can be reached at an - * offset from the first lane. - */ - if (cfg->is_dual_lane_phy) { - qphy->tx2 = of_iomap(np, 3); - qphy->rx2 = of_iomap(np, 4); - if (!qphy->tx2 || !qphy->rx2) { - dev_warn(dev, - "Underspecified device tree, falling back to legacy register regions\n"); - - /* In the old version, pcs_misc is at index 3. */ - qphy->pcs_misc = qphy->tx2; - qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; - qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; - - } else { - qphy->pcs_misc = of_iomap(np, 5); - } - - } else { - qphy->pcs_misc = of_iomap(np, 3); - } + qphy->pcs_misc = of_iomap(np, 3); if (!qphy->pcs_misc) dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); @@ -1117,18 +940,16 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, } /* Get lane reset, if any */ - if (cfg->has_lane_rst) { - snprintf(prop_name, sizeof(prop_name), "lane%d", id); - qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); - if (IS_ERR(qphy->lane_rst)) { - dev_err(dev, "failed to get lane%d reset\n", id); - return PTR_ERR(qphy->lane_rst); - } - ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, - qphy->lane_rst); - if (ret) - return ret; + snprintf(prop_name, sizeof(prop_name), "lane%d", id); + qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); + if (IS_ERR(qphy->lane_rst)) { + dev_err(dev, "failed to get lane%d reset\n", id); + return PTR_ERR(qphy->lane_rst); } + ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, + qphy->lane_rst); + if (ret) + return ret; generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_msm8996_ops); if (IS_ERR(generic_phy)) { @@ -1183,13 +1004,6 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev) if (IS_ERR(serdes)) return PTR_ERR(serdes); - /* per PHY dp_com; if PHY has dp_com control block */ - if (cfg->has_phy_dp_com_ctrl) { - qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(qmp->dp_com)) - return PTR_ERR(qmp->dp_com); - } - expected_phys = cfg->nlanes; mutex_init(&qmp->phy_mutex); From patchwork Tue Jun 7 21:31:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579907 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67FCDC433EF for ; Wed, 8 Jun 2022 05:15:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232111AbiFHFPg (ORCPT ); Wed, 8 Jun 2022 01:15:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234617AbiFHFPL (ORCPT ); Wed, 8 Jun 2022 01:15:11 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6CAED374270 for ; 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Tue, 07 Jun 2022 14:32:36 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g23-20020ac24d97000000b0047255d21153sm3411343lfe.130.2022.06.07.14.32.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 14:32:35 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 22/30] phy: qcom-qmp-ufs: cleanup the driver Date: Wed, 8 Jun 2022 00:31:55 +0300 Message-Id: <20220607213203.2819885-23-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> References: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove the conditionals and options that are not used by any of UFS PHY devices. Acked-by: Bjorn Andersson Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 293 +----------------------- 1 file changed, 12 insertions(+), 281 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 0bf1990651b6..e9b32a3d5adb 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -599,47 +599,16 @@ struct qmp_phy_cfg { /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes_tbl; int serdes_tbl_num; - const struct qmp_phy_init_tbl *serdes_tbl_sec; - int serdes_tbl_num_sec; const struct qmp_phy_init_tbl *tx_tbl; int tx_tbl_num; - const struct qmp_phy_init_tbl *tx_tbl_sec; - int tx_tbl_num_sec; const struct qmp_phy_init_tbl *rx_tbl; int rx_tbl_num; - const struct qmp_phy_init_tbl *rx_tbl_sec; - int rx_tbl_num_sec; const struct qmp_phy_init_tbl *pcs_tbl; int pcs_tbl_num; - const struct qmp_phy_init_tbl *pcs_tbl_sec; - int pcs_tbl_num_sec; - const struct qmp_phy_init_tbl *pcs_misc_tbl; - int pcs_misc_tbl_num; - const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; - int pcs_misc_tbl_num_sec; - - /* Init sequence for DP PHY block link rates */ - const struct qmp_phy_init_tbl *serdes_tbl_rbr; - int serdes_tbl_rbr_num; - const struct qmp_phy_init_tbl *serdes_tbl_hbr; - int serdes_tbl_hbr_num; - const struct qmp_phy_init_tbl *serdes_tbl_hbr2; - int serdes_tbl_hbr2_num; - const struct qmp_phy_init_tbl *serdes_tbl_hbr3; - int serdes_tbl_hbr3_num; - - /* DP PHY callbacks */ - int (*configure_dp_phy)(struct qmp_phy *qphy); - void (*configure_dp_tx)(struct qmp_phy *qphy); - int (*calibrate_dp_phy)(struct qmp_phy *qphy); - void (*dp_aux_init)(struct qmp_phy *qphy); /* clock ids to be requested */ const char * const *clk_list; int num_clks; - /* resets to be requested */ - const char * const *reset_list; - int num_resets; /* regulators to be requested */ const char * const *vreg_list; int num_vregs; @@ -649,22 +618,9 @@ struct qmp_phy_cfg { unsigned int start_ctrl; unsigned int pwrdn_ctrl; - unsigned int mask_com_pcs_ready; /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ unsigned int phy_status; - /* true, if PHY has a separate PHY_COM control block */ - bool has_phy_com_ctrl; - /* true, if PHY has a reset for individual lanes */ - bool has_lane_rst; - /* true, if PHY needs delay after POWER_DOWN */ - bool has_pwrdn_delay; - /* power_down delay in usec */ - int pwrdn_delay_min; - int pwrdn_delay_max; - - /* true, if PHY has a separate DP_COM control block */ - bool has_phy_dp_com_ctrl; /* true, if PHY has secondary tx/rx lanes to be configured */ bool is_dual_lane_phy; @@ -672,11 +628,6 @@ struct qmp_phy_cfg { bool no_pcs_sw_reset; }; -struct qmp_phy_combo_cfg { - const struct qmp_phy_cfg *usb_cfg; - const struct qmp_phy_cfg *dp_cfg; -}; - /** * struct qmp_phy - per-lane phy descriptor * @@ -689,14 +640,9 @@ struct qmp_phy_combo_cfg { * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) * @pcs_misc: iomapped memory space for lane's pcs_misc - * @pipe_clk: pipe clock * @index: lane index * @qmp: QMP phy to which this lane belongs - * @lane_rst: lane's reset controller * @mode: current PHY mode - * @dp_aux_cfg: Display port aux config - * @dp_opts: Display port optional config - * @dp_clks: Display port clocks */ struct qmp_phy { struct phy *phy; @@ -708,27 +654,15 @@ struct qmp_phy { void __iomem *tx2; void __iomem *rx2; void __iomem *pcs_misc; - struct clk *pipe_clk; unsigned int index; struct qcom_qmp *qmp; - struct reset_control *lane_rst; enum phy_mode mode; - unsigned int dp_aux_cfg; - struct phy_configure_opts_dp dp_opts; - struct qmp_phy_dp_clks *dp_clks; -}; - -struct qmp_phy_dp_clks { - struct qmp_phy *qphy; - struct clk_hw dp_link_hw; - struct clk_hw dp_pixel_hw; }; /** * struct qcom_qmp - structure holding QMP phy block attributes * * @dev: device - * @dp_com: iomapped memory space for phy's dp_com control block * * @clks: array of clocks required by phy * @resets: array of resets required by phy @@ -741,10 +675,8 @@ struct qmp_phy_dp_clks { */ struct qcom_qmp { struct device *dev; - void __iomem *dp_com; struct clk_bulk_data *clks; - struct reset_control **resets; struct regulator_bulk_data *vregs; struct qmp_phy **phys; @@ -871,7 +803,6 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { .start_ctrl = SERDES_START, .pwrdn_ctrl = SW_PWRDN, - .is_dual_lane_phy = false, .no_pcs_sw_reset = true, }; @@ -983,37 +914,12 @@ static void qcom_qmp_phy_ufs_configure(void __iomem *base, static int qcom_qmp_phy_ufs_serdes_init(struct qmp_phy *qphy) { - struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; int serdes_tbl_num = cfg->serdes_tbl_num; - int ret; qcom_qmp_phy_ufs_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); - if (cfg->serdes_tbl_sec) - qcom_qmp_phy_ufs_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, - cfg->serdes_tbl_num_sec); - - if (cfg->has_phy_com_ctrl) { - void __iomem *status; - unsigned int mask, val; - - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], - SERDES_START | PCS_START); - - status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; - mask = cfg->mask_com_pcs_ready; - - ret = readl_poll_timeout(status, val, (val & mask), 10, - PHY_INIT_COMPLETE_TIMEOUT); - if (ret) { - dev_err(qmp->dev, - "phy common block init timed-out\n"); - return ret; - } - } return 0; } @@ -1022,10 +928,8 @@ static int qcom_qmp_phy_ufs_com_init(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *serdes = qphy->serdes; void __iomem *pcs = qphy->pcs; - void __iomem *dp_com = qmp->dp_com; - int ret, i; + int ret; mutex_lock(&qmp->phy_mutex); if (qmp->init_count++) { @@ -1040,71 +944,22 @@ static int qcom_qmp_phy_ufs_com_init(struct qmp_phy *qphy) goto err_unlock; } - for (i = 0; i < cfg->num_resets; i++) { - ret = reset_control_assert(qmp->resets[i]); - if (ret) { - dev_err(qmp->dev, "%s reset assert failed\n", - cfg->reset_list[i]); - goto err_disable_regulators; - } - } - - for (i = cfg->num_resets - 1; i >= 0; i--) { - ret = reset_control_deassert(qmp->resets[i]); - if (ret) { - dev_err(qmp->dev, "%s reset deassert failed\n", - qphy->cfg->reset_list[i]); - goto err_assert_reset; - } - } - ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); if (ret) - goto err_assert_reset; - - if (cfg->has_phy_dp_com_ctrl) { - qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, - SW_PWRDN); - /* override hardware control for reset of qmp phy */ - qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); - - /* Default type-c orientation, i.e CC1 */ - qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); - - qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, - USB3_MODE | DP_MODE); + goto err_disable_regulators; - /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ - qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); - - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); - } - - if (cfg->has_phy_com_ctrl) { - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], - SW_PWRDN); - } else { - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) - qphy_setbits(pcs, - cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], - cfg->pwrdn_ctrl); - else - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, - cfg->pwrdn_ctrl); - } + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) + qphy_setbits(pcs, + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + cfg->pwrdn_ctrl); + else + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, + cfg->pwrdn_ctrl); mutex_unlock(&qmp->phy_mutex); return 0; -err_assert_reset: - while (++i < cfg->num_resets) - reset_control_assert(qmp->resets[i]); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); err_unlock: @@ -1117,8 +972,6 @@ static int qcom_qmp_phy_ufs_com_exit(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *serdes = qphy->serdes; - int i = cfg->num_resets; mutex_lock(&qmp->phy_mutex); if (--qmp->init_count) { @@ -1127,17 +980,6 @@ static int qcom_qmp_phy_ufs_com_exit(struct qmp_phy *qphy) } reset_control_assert(qmp->ufs_reset); - if (cfg->has_phy_com_ctrl) { - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], - SERDES_START | PCS_START); - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], - SW_RESET); - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], - SW_PWRDN); - } - - while (--i >= 0) - reset_control_assert(qmp->resets[i]); clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); @@ -1198,77 +1040,35 @@ static int qcom_qmp_phy_ufs_power_on(struct phy *phy) void __iomem *tx = qphy->tx; void __iomem *rx = qphy->rx; void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; void __iomem *status; unsigned int mask, val, ready; int ret; qcom_qmp_phy_ufs_serdes_init(qphy); - if (cfg->has_lane_rst) { - ret = reset_control_deassert(qphy->lane_rst); - if (ret) { - dev_err(qmp->dev, "lane%d reset deassert failed\n", - qphy->index); - return ret; - } - } - - ret = clk_prepare_enable(qphy->pipe_clk); - if (ret) { - dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); - goto err_reset_lane; - } - /* Tx, Rx, and PCS configurations */ qcom_qmp_phy_ufs_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); - if (cfg->tx_tbl_sec) - qcom_qmp_phy_ufs_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, - cfg->tx_tbl_num_sec, 1); /* Configuration for other LANE for USB-DP combo PHY */ if (cfg->is_dual_lane_phy) { qcom_qmp_phy_ufs_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 2); - if (cfg->tx_tbl_sec) - qcom_qmp_phy_ufs_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl_sec, - cfg->tx_tbl_num_sec, 2); } qcom_qmp_phy_ufs_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); - if (cfg->rx_tbl_sec) - qcom_qmp_phy_ufs_configure_lane(rx, cfg->regs, - cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); if (cfg->is_dual_lane_phy) { qcom_qmp_phy_ufs_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 2); - if (cfg->rx_tbl_sec) - qcom_qmp_phy_ufs_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl_sec, - cfg->rx_tbl_num_sec, 2); } qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); - if (cfg->pcs_tbl_sec) - qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, - cfg->pcs_tbl_num_sec); ret = reset_control_deassert(qmp->ufs_reset); if (ret) - goto err_disable_pipe_clk; - - qcom_qmp_phy_ufs_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, - cfg->pcs_misc_tbl_num); - if (cfg->pcs_misc_tbl_sec) - qcom_qmp_phy_ufs_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, - cfg->pcs_misc_tbl_num_sec); - - if (cfg->has_pwrdn_delay) - usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); + return ret; /* Pull PHY out of reset state */ if (!cfg->no_pcs_sw_reset) @@ -1284,17 +1084,10 @@ static int qcom_qmp_phy_ufs_power_on(struct phy *phy) PHY_INIT_COMPLETE_TIMEOUT); if (ret) { dev_err(qmp->dev, "phy initialization timed-out\n"); - goto err_disable_pipe_clk; + return ret; } - return 0; - -err_disable_pipe_clk: - clk_disable_unprepare(qphy->pipe_clk); -err_reset_lane: - if (cfg->has_lane_rst) - reset_control_assert(qphy->lane_rst); - return ret; + return 0; } static int qcom_qmp_phy_ufs_power_off(struct phy *phy) @@ -1302,8 +1095,6 @@ static int qcom_qmp_phy_ufs_power_off(struct phy *phy) struct qmp_phy *qphy = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qphy->cfg; - clk_disable_unprepare(qphy->pipe_clk); - /* PHY reset */ if (!cfg->no_pcs_sw_reset) qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); @@ -1326,10 +1117,6 @@ static int qcom_qmp_phy_ufs_power_off(struct phy *phy) static int qcom_qmp_phy_ufs_exit(struct phy *phy) { struct qmp_phy *qphy = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qphy->cfg; - - if (cfg->has_lane_rst) - reset_control_assert(qphy->lane_rst); qcom_qmp_phy_ufs_com_exit(qphy); @@ -1387,31 +1174,6 @@ static int qcom_qmp_phy_ufs_vreg_init(struct device *dev, const struct qmp_phy_c return devm_regulator_bulk_get(dev, num, qmp->vregs); } -static int qcom_qmp_phy_ufs_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) -{ - struct qcom_qmp *qmp = dev_get_drvdata(dev); - int i; - - qmp->resets = devm_kcalloc(dev, cfg->num_resets, - sizeof(*qmp->resets), GFP_KERNEL); - if (!qmp->resets) - return -ENOMEM; - - for (i = 0; i < cfg->num_resets; i++) { - struct reset_control *rst; - const char *name = cfg->reset_list[i]; - - rst = devm_reset_control_get_exclusive(dev, name); - if (IS_ERR(rst)) { - dev_err(dev, "failed to get %s reset\n", name); - return PTR_ERR(rst); - } - qmp->resets[i] = rst; - } - - return 0; -} - static int qcom_qmp_phy_ufs_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); @@ -1435,11 +1197,6 @@ static const struct phy_ops qcom_qmp_ufs_ops = { .owner = THIS_MODULE, }; -static void qcom_qmp_reset_control_put(void *data) -{ - reset_control_put(data); -} - static int qcom_qmp_phy_ufs_create(struct device *dev, struct device_node *np, int id, void __iomem *serdes, const struct qmp_phy_cfg *cfg) @@ -1447,7 +1204,6 @@ int qcom_qmp_phy_ufs_create(struct device *dev, struct device_node *np, int id, struct qcom_qmp *qmp = dev_get_drvdata(dev); struct phy *generic_phy; struct qmp_phy *qphy; - char prop_name[MAX_PROP_NAME]; int ret; qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); @@ -1503,20 +1259,6 @@ int qcom_qmp_phy_ufs_create(struct device *dev, struct device_node *np, int id, if (!qphy->pcs_misc) dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); - /* Get lane reset, if any */ - if (cfg->has_lane_rst) { - snprintf(prop_name, sizeof(prop_name), "lane%d", id); - qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); - if (IS_ERR(qphy->lane_rst)) { - dev_err(dev, "failed to get lane%d reset\n", id); - return PTR_ERR(qphy->lane_rst); - } - ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, - qphy->lane_rst); - if (ret) - return ret; - } - generic_phy = devm_phy_create(dev, np, &qcom_qmp_ufs_ops); if (IS_ERR(generic_phy)) { ret = PTR_ERR(generic_phy); @@ -1600,13 +1342,6 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) if (IS_ERR(serdes)) return PTR_ERR(serdes); - /* per PHY dp_com; if PHY has dp_com control block */ - if (cfg->has_phy_dp_com_ctrl) { - qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(qmp->dp_com)) - return PTR_ERR(qmp->dp_com); - } - expected_phys = cfg->nlanes; mutex_init(&qmp->phy_mutex); @@ -1615,10 +1350,6 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) if (ret) return ret; - ret = qcom_qmp_phy_ufs_reset_init(dev, cfg); - if (ret) - return ret; - ret = qcom_qmp_phy_ufs_vreg_init(dev, cfg); if (ret) { if (ret != -EPROBE_DEFER) From patchwork Tue Jun 7 21:31:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 223B5C433EF for ; Wed, 8 Jun 2022 02:16:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233852AbiFHCQq (ORCPT ); Tue, 7 Jun 2022 22:16:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1446309AbiFHCOO (ORCPT ); Tue, 7 Jun 2022 22:14:14 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7424374ED7 for ; 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Tue, 07 Jun 2022 14:32:38 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g23-20020ac24d97000000b0047255d21153sm3411343lfe.130.2022.06.07.14.32.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 14:32:37 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 24/30] phy: qcom-qmp-pcie: drop multi-PHY support Date: Wed, 8 Jun 2022 00:31:57 +0300 Message-Id: <20220607213203.2819885-25-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> References: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Each PCIe QMP PHY device provides just a single PCIe PHY. Drop support for handling multiple child PHYs. Acked-by: Bjorn Andersson Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 33 +++--------------------- 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index d9e8a3e88890..0676b67d3ff6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1329,8 +1329,6 @@ struct qmp_phy { * @vregs: regulator supplies bulk data * * @phys: array of per-lane phy descriptors - * @phy_mutex: mutex lock for PHY common block initialization - * @init_count: phy common block initialization count */ struct qcom_qmp { struct device *dev; @@ -1340,9 +1338,6 @@ struct qcom_qmp { struct regulator_bulk_data *vregs; struct qmp_phy **phys; - - struct mutex phy_mutex; - int init_count; }; static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -1796,17 +1791,11 @@ static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy) void __iomem *pcs = qphy->pcs; int ret, i; - mutex_lock(&qmp->phy_mutex); - if (qmp->init_count++) { - mutex_unlock(&qmp->phy_mutex); - return 0; - } - /* turn on regulator supplies */ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); if (ret) { dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); - goto err_unlock; + return ret; } for (i = 0; i < cfg->num_resets; i++) { @@ -1839,8 +1828,6 @@ static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy) qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); - mutex_unlock(&qmp->phy_mutex); - return 0; err_assert_reset: @@ -1848,8 +1835,6 @@ static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy) reset_control_assert(qmp->resets[i]); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); -err_unlock: - mutex_unlock(&qmp->phy_mutex); return ret; } @@ -1860,12 +1845,6 @@ static int qcom_qmp_phy_pcie_com_exit(struct qmp_phy *qphy) const struct qmp_phy_cfg *cfg = qphy->cfg; int i = cfg->num_resets; - mutex_lock(&qmp->phy_mutex); - if (--qmp->init_count) { - mutex_unlock(&qmp->phy_mutex); - return 0; - } - while (--i >= 0) reset_control_assert(qmp->resets[i]); @@ -1873,8 +1852,6 @@ static int qcom_qmp_phy_pcie_com_exit(struct qmp_phy *qphy) regulator_bulk_disable(cfg->num_vregs, qmp->vregs); - mutex_unlock(&qmp->phy_mutex); - return 0; } @@ -2334,7 +2311,7 @@ static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) struct phy_provider *phy_provider; void __iomem *serdes; const struct qmp_phy_cfg *cfg = NULL; - int num, id, expected_phys; + int num, id; int ret; qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); @@ -2354,10 +2331,6 @@ static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) if (IS_ERR(serdes)) return PTR_ERR(serdes); - expected_phys = cfg->nlanes; - - mutex_init(&qmp->phy_mutex); - ret = qcom_qmp_phy_pcie_clk_init(dev, cfg); if (ret) return ret; @@ -2376,7 +2349,7 @@ static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) num = of_get_available_child_count(dev->of_node); /* do we have a rogue child node ? */ - if (num > expected_phys) + if (num > 1) return -EINVAL; qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); From patchwork Tue Jun 7 21:31:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C03FC433EF for ; Wed, 8 Jun 2022 02:05:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236948AbiFHCDm (ORCPT ); Tue, 7 Jun 2022 22:03:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1442302AbiFHCAI (ORCPT ); Tue, 7 Jun 2022 22:00:08 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4BBD377B17 for ; Tue, 7 Jun 2022 14:32:41 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id be31so30301516lfb.10 for ; Tue, 07 Jun 2022 14:32:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2imGqpmmUYIL/vBXDX4AMR6VhO9AAPmsJkl/66iJTZA=; b=wgyLw1ukIv27Jr7FA2UHBVDIW9I5o/409G8LQ9nro6bXSfsSl/TFXOinq21vCTFEeI cF5dvLd3L6VAc703EkdJdX9GVWHqFj3hZbWFwTQV10hHlty6g3Kaf5fRv3p2xAmVbOrw 3m34tcLZ/6n6kh9uBNEoLUItkQAj1XntUTJosrpGAmypdiNRU5WQxAPtD/8aZpIGbCWH p6euAtnd9cuvFYP557qQBIPPd6kQIsUX3Bk1psVeid/+6UBZPBrasL01eA10tgyJuNxi 6FaktP3dtytm4v/GCTwC1lPhe85rjV+WpRnUyYBwaeP4m+rxv3yyoyJzhPsbyjcOAc/e bTbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2imGqpmmUYIL/vBXDX4AMR6VhO9AAPmsJkl/66iJTZA=; b=B8oolDZDOhC84+ZHNsrLq7Ddy2jgUgdkGHv0dz5rfnrMtvhxYgBab5NENu74xdGI6P HV6MSr5Mer6SqjKHbfmRpVUKtKXpURWCX3LFqnx4GSq1KoMQjGIQvEBxj6E1aVDOWaec +0r2PRsyczUGOSTukkrOIvKvx+D+aPGIDgEuWvFmfrUfj3ImmoCMFLlCH1VgiDGyDL1A 5tyD2YykzHXdcHr7YdO/BRqefoHrVCMd/mrN3DiFxjq4HwyIkAo7X/X+6NuQWyifHm9Z dF6qVBRHUyHI5HBrJziZG4Q4HM8ZWniBcyQigVI6dRjo4H8zoh0ki3F5kYJrwKPu1FTm 0tPQ== X-Gm-Message-State: AOAM532ADbDBoXU6DJOhSs/+ZUFBxRBuaoHEtyw8e/L6KLJoJB5BGQTW hADpemII/qAzoThUCpsUAXQIQw== X-Google-Smtp-Source: ABdhPJwFMyzjnfwFMJTEVGamo8VIoOOTzr7r22uif+Mr+AFqfKxBSwM8n6+HCBp/2K2axHKxLqqKBw== X-Received: by 2002:a05:6512:1052:b0:479:1f92:13b4 with SMTP id c18-20020a056512105200b004791f9213b4mr13089936lfb.200.1654637559197; Tue, 07 Jun 2022 14:32:39 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g23-20020ac24d97000000b0047255d21153sm3411343lfe.130.2022.06.07.14.32.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 14:32:38 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 25/30] phy: qcom-qmp-ufs: drop multi-PHY support Date: Wed, 8 Jun 2022 00:31:58 +0300 Message-Id: <20220607213203.2819885-26-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> References: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Each UFS QMP PHY device provides just a single UFS PHY. Drop support for handling multiple child PHYs. Acked-by: Bjorn Andersson Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 33 +++---------------------- 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index e9b32a3d5adb..a2526068232b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -669,8 +669,6 @@ struct qmp_phy { * @vregs: regulator supplies bulk data * * @phys: array of per-lane phy descriptors - * @phy_mutex: mutex lock for PHY common block initialization - * @init_count: phy common block initialization count * @ufs_reset: optional UFS PHY reset handle */ struct qcom_qmp { @@ -681,9 +679,6 @@ struct qcom_qmp { struct qmp_phy **phys; - struct mutex phy_mutex; - int init_count; - struct reset_control *ufs_reset; }; @@ -931,17 +926,11 @@ static int qcom_qmp_phy_ufs_com_init(struct qmp_phy *qphy) void __iomem *pcs = qphy->pcs; int ret; - mutex_lock(&qmp->phy_mutex); - if (qmp->init_count++) { - mutex_unlock(&qmp->phy_mutex); - return 0; - } - /* turn on regulator supplies */ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); if (ret) { dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); - goto err_unlock; + return ret; } ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); @@ -956,14 +945,10 @@ static int qcom_qmp_phy_ufs_com_init(struct qmp_phy *qphy) qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); - mutex_unlock(&qmp->phy_mutex); - return 0; err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); -err_unlock: - mutex_unlock(&qmp->phy_mutex); return ret; } @@ -973,20 +958,12 @@ static int qcom_qmp_phy_ufs_com_exit(struct qmp_phy *qphy) struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; - mutex_lock(&qmp->phy_mutex); - if (--qmp->init_count) { - mutex_unlock(&qmp->phy_mutex); - return 0; - } - reset_control_assert(qmp->ufs_reset); clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); regulator_bulk_disable(cfg->num_vregs, qmp->vregs); - mutex_unlock(&qmp->phy_mutex); - return 0; } @@ -1322,7 +1299,7 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) struct phy_provider *phy_provider; void __iomem *serdes; const struct qmp_phy_cfg *cfg = NULL; - int num, id, expected_phys; + int num, id; int ret; qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); @@ -1342,10 +1319,6 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) if (IS_ERR(serdes)) return PTR_ERR(serdes); - expected_phys = cfg->nlanes; - - mutex_init(&qmp->phy_mutex); - ret = qcom_qmp_phy_ufs_clk_init(dev, cfg); if (ret) return ret; @@ -1360,7 +1333,7 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) num = of_get_available_child_count(dev->of_node); /* do we have a rogue child node ? */ - if (num > expected_phys) + if (num > 1) return -EINVAL; qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); From patchwork Tue Jun 7 21:32:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 307D7C433EF for ; Wed, 8 Jun 2022 01:03:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1386372AbiFHA7i (ORCPT ); Tue, 7 Jun 2022 20:59:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380158AbiFGXiS (ORCPT ); Tue, 7 Jun 2022 19:38:18 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C41522CBEB for ; Tue, 7 Jun 2022 14:32:44 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id y15so15238839ljc.0 for ; Tue, 07 Jun 2022 14:32:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fF4LijbDfT4JefOzp7UdYAr+EfQ5/5blmMbjsXFHank=; b=NzKE7qkr8gsr/JL7rFgPpeulg+CPzyuP+hY6oa709bKQ++KIdK4fUhE2LIL+mnyxUa D6mVy/+r5k49UN02ZeQLXPmf7vapIERQfwwuhK6Jga3COW0mwzZbzYG+pYaHW0KbG+xS uJcmiR6679vZUunpZWEz4k4JyosPTnhPm/lEkBeXweEodeDsJ0KCak9xAeXUBSI4b7QM mtTAKQ0fCtGY5/ulYgQHXXJykPvq6MKm2EYHUr89HaH+b0G5NZdakXT9XUmA1eF92k1G GYZQfC4z3eXu40mF70KL3RdZavDj9peZ/7mJiRIkoa4IDobsuBguBjyHu5G5VigPqWF+ N+dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fF4LijbDfT4JefOzp7UdYAr+EfQ5/5blmMbjsXFHank=; b=7QKuCsu8q7vRsp8/Lr40loGczKNrC3qSV1cqD9KsbD+/wgdgc7Nqs6avV08sDK0MsS ddnEhWE5TsX22Vl/HW7AOQLUVilgNvVTMW195mdi4pkEN0zl8PcXGidHugLuVsEfAYuk CzFpKHmPy3VBx0jDwzOQX2qHPu+WJHms7+8HHWmXrJyB9zrVYhGFEGY4cd+dKvn/doXE 11x7KrmPpwaYnAHJHqiSjy3nhGRTwnyCbr66n4acypR4x1usE0hectqyRByO5vkTVEvz cloHhueJ0H379Q5+h12hcyqAYSdj9SBu6wOm+rOfUdli1tt3QXSL2x4fZBdjvK4oNlDG nfWw== X-Gm-Message-State: AOAM530e3WNrcWmKgjlooZcKM6zLPgbi7z/LtxHwHM680JVfuC1TuKjb XYc/Muc34KuycwgexvdN2WSN9OZpcQXKvYC/6HaMbA== X-Google-Smtp-Source: ABdhPJzAVAqqy6N+Lvbykyd5AuatgMAfK0/3UNTxy+Tx+koXIo1iO57kMjjoIpRRNCJxtRB2P/aLdQ== X-Received: by 2002:a2e:881a:0:b0:255:7c2c:46d8 with SMTP id x26-20020a2e881a000000b002557c2c46d8mr13961393ljh.364.1654637562750; Tue, 07 Jun 2022 14:32:42 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g23-20020ac24d97000000b0047255d21153sm3411343lfe.130.2022.06.07.14.32.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 14:32:42 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 29/30] phy: qcom-qmp-pcie-msm8996: use bulk reset_control API Date: Wed, 8 Jun 2022 00:32:02 +0300 Message-Id: <20220607213203.2819885-30-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> References: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Switch qcom-qmp-pcie-msm8996 driver to use reset_control_bulk_assert / _deassert functions rather than hardcoding the loops in the driver itself. Acked-by: Bjorn Andersson Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov --- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 49 +++++++------------ 1 file changed, 18 insertions(+), 31 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index 51da3a3a199e..48ea1de81d7c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -340,7 +340,7 @@ struct qcom_qmp { struct device *dev; struct clk_bulk_data *clks; - struct reset_control **resets; + struct reset_control_bulk_data *resets; struct regulator_bulk_data *vregs; struct qmp_phy **phys; @@ -489,7 +489,7 @@ static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy) struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; - int ret, i; + int ret; mutex_lock(&qmp->phy_mutex); if (qmp->init_count++) { @@ -504,22 +504,16 @@ static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy) goto err_unlock; } - for (i = 0; i < cfg->num_resets; i++) { - ret = reset_control_assert(qmp->resets[i]); - if (ret) { - dev_err(qmp->dev, "%s reset assert failed\n", - cfg->reset_list[i]); - goto err_disable_regulators; - } + ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset assert failed\n"); + goto err_disable_regulators; } - for (i = cfg->num_resets - 1; i >= 0; i--) { - ret = reset_control_deassert(qmp->resets[i]); - if (ret) { - dev_err(qmp->dev, "%s reset deassert failed\n", - qphy->cfg->reset_list[i]); - goto err_assert_reset; - } + ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset deassert failed\n"); + goto err_disable_regulators; } ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); @@ -534,8 +528,7 @@ static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy) return 0; err_assert_reset: - while (++i < cfg->num_resets) - reset_control_assert(qmp->resets[i]); + reset_control_bulk_assert(cfg->num_resets, qmp->resets); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); err_unlock: @@ -549,7 +542,6 @@ static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy) struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; - int i = cfg->num_resets; mutex_lock(&qmp->phy_mutex); if (--qmp->init_count) { @@ -564,8 +556,7 @@ static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy) qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], SW_PWRDN); - while (--i >= 0) - reset_control_assert(qmp->resets[i]); + reset_control_bulk_assert(cfg->num_resets, qmp->resets); clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); @@ -769,23 +760,19 @@ static int qcom_qmp_phy_pcie_msm8996_reset_init(struct device *dev, const struct { struct qcom_qmp *qmp = dev_get_drvdata(dev); int i; + int ret; qmp->resets = devm_kcalloc(dev, cfg->num_resets, sizeof(*qmp->resets), GFP_KERNEL); if (!qmp->resets) return -ENOMEM; - for (i = 0; i < cfg->num_resets; i++) { - struct reset_control *rst; - const char *name = cfg->reset_list[i]; + for (i = 0; i < cfg->num_resets; i++) + qmp->resets[i].id = cfg->reset_list[i]; - rst = devm_reset_control_get_exclusive(dev, name); - if (IS_ERR(rst)) { - dev_err(dev, "failed to get %s reset\n", name); - return PTR_ERR(rst); - } - qmp->resets[i] = rst; - } + ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); + if (ret) + return dev_err_probe(dev, ret, "failed to get resets\n"); return 0; } From patchwork Tue Jun 7 21:32:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8C04CCA47C for ; Wed, 8 Jun 2022 01:23:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234996AbiFHBXX (ORCPT ); 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Tue, 07 Jun 2022 14:32:43 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 30/30] phy: qcom-qmp-usb: use bulk reset_control API Date: Wed, 8 Jun 2022 00:32:03 +0300 Message-Id: <20220607213203.2819885-31-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> References: <20220607213203.2819885-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Switch qcom-qmp-usb driver to use reset_control_bulk_assert / _deassert functions rather than hardcoding the loops in the driver itself. Acked-by: Bjorn Andersson Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 49 +++++++++---------------- 1 file changed, 18 insertions(+), 31 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index 969253e7bdd9..aebe5ed4e4e3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -1446,7 +1446,7 @@ struct qcom_qmp { void __iomem *dp_com; struct clk_bulk_data *clks; - struct reset_control **resets; + struct reset_control_bulk_data *resets; struct regulator_bulk_data *vregs; struct qmp_phy **phys; @@ -2009,7 +2009,7 @@ static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy) const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *pcs = qphy->pcs; void __iomem *dp_com = qmp->dp_com; - int ret, i; + int ret; /* turn on regulator supplies */ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); @@ -2018,22 +2018,16 @@ static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy) return ret; } - for (i = 0; i < cfg->num_resets; i++) { - ret = reset_control_assert(qmp->resets[i]); - if (ret) { - dev_err(qmp->dev, "%s reset assert failed\n", - cfg->reset_list[i]); - goto err_disable_regulators; - } + ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset assert failed\n"); + goto err_disable_regulators; } - for (i = cfg->num_resets - 1; i >= 0; i--) { - ret = reset_control_deassert(qmp->resets[i]); - if (ret) { - dev_err(qmp->dev, "%s reset deassert failed\n", - qphy->cfg->reset_list[i]); - goto err_assert_reset; - } + ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); + if (ret) { + dev_err(qmp->dev, "reset deassert failed\n"); + goto err_disable_regulators; } ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); @@ -2074,8 +2068,7 @@ static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy) return 0; err_assert_reset: - while (++i < cfg->num_resets) - reset_control_assert(qmp->resets[i]); + reset_control_bulk_assert(cfg->num_resets, qmp->resets); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); @@ -2086,10 +2079,8 @@ static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy) { struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; - int i = cfg->num_resets; - while (--i >= 0) - reset_control_assert(qmp->resets[i]); + reset_control_bulk_assert(cfg->num_resets, qmp->resets); clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); @@ -2376,23 +2367,19 @@ static int qcom_qmp_phy_usb_reset_init(struct device *dev, const struct qmp_phy_ { struct qcom_qmp *qmp = dev_get_drvdata(dev); int i; + int ret; qmp->resets = devm_kcalloc(dev, cfg->num_resets, sizeof(*qmp->resets), GFP_KERNEL); if (!qmp->resets) return -ENOMEM; - for (i = 0; i < cfg->num_resets; i++) { - struct reset_control *rst; - const char *name = cfg->reset_list[i]; + for (i = 0; i < cfg->num_resets; i++) + qmp->resets[i].id = cfg->reset_list[i]; - rst = devm_reset_control_get_exclusive(dev, name); - if (IS_ERR(rst)) { - dev_err(dev, "failed to get %s reset\n", name); - return PTR_ERR(rst); - } - qmp->resets[i] = rst; - } + ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); + if (ret) + return dev_err_probe(dev, ret, "failed to get resets\n"); return 0; }