From patchwork Wed Jun 8 10:22:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579902 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0349CCA47B for ; Wed, 8 Jun 2022 10:30:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237086AbiFHKaZ (ORCPT ); Wed, 8 Jun 2022 06:30:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238180AbiFHK3z (ORCPT ); Wed, 8 Jun 2022 06:29:55 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C51A7195785 for ; Wed, 8 Jun 2022 03:22:15 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id b7so9670415ljr.6 for ; Wed, 08 Jun 2022 03:22:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PAZRY+9de/r/pRtDdwgg/SxpOS6YpBHgoxmPS8uwmeY=; b=bRXPsxn8jK6DstsXeLEpTv79XjGtFN/b+yIy0griFq1V4aggDfXVpLvd/cJCTqnymd 3DlZBDVZQJktWgvo6NCLVE4DdSXbH5YcIBhBTxphdxgZS1eQBsB0k/t1Xc//60M7omF5 XlZrCMzd4s/axItdIekwrKOfna6sNguSUCrGc/2HU2jcUZo+zIVJjQ7eCdoQQw6YqmQ4 l3bJ2kQML4B9zrJDxGUNIrgawcmT2WtSZ/vNO1fEntK7SmfHK4nICcnT9RMTYWrLxiHt 1L7fFTyNzk0hyqNp6Z4v2NC7h7hRgaqVP4hgt+RslNuyxII5oxg/wt26w41yompGSDI+ g/Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PAZRY+9de/r/pRtDdwgg/SxpOS6YpBHgoxmPS8uwmeY=; b=floi04J8ZRmIZn4tiF6qiUEB1ISeMZAuuXe7DYclKpD11zkQx6J/wKepkXweJKCcda HYAl+820VZNHzWsvecejK0RPnPv+YhHn5Wa+FJzlivzF6d7Bh1fKIUl5HdstR2SScgAc Nrnbzq0HmHqFmAgKieF834DGeS4Od5Fj1RITW/e0M0I6T/2oHfw4Aq4bgSTGu546lMRM ehF8c1dQ5Rbz8U+0H8LTf78kh7Q5qsfQrlr/j6YH74br7YSQKeB3zPJ1pYpEBJSoc5SH NgATWkdiaFDB9o1TNTAKWtkwGy8FNhqwA9BTO4EhLUWNK9SZP1eXOalKO6RujxQDAVcm cwmA== X-Gm-Message-State: AOAM5312eyJNboVWAlLla9H6CpBT22i3htO+XNllVKbavoVClOL9/vJO +YJeIAd8JYO2A+KA6AzZTKklxQ== X-Google-Smtp-Source: ABdhPJzXjRXru7y049FWjmAalRSo/l4qehPqqPUWUsQ62KGTO0RfO+JmFt2PeclHDP26OdCVJzzyVg== X-Received: by 2002:a05:651c:101:b0:250:896d:f870 with SMTP id a1-20020a05651c010100b00250896df870mr55894808ljb.235.1654683733975; Wed, 08 Jun 2022 03:22:13 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v1-20020ac25601000000b00478fe3327aasm3642934lfd.217.2022.06.08.03.22.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 03:22:13 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Johan Hovold , Rob Herring , Johan Hovold Subject: [PATCH v14 3/7] PCI: dwc: split MSI IRQ parsing/allocation to a separate function Date: Wed, 8 Jun 2022 13:22:04 +0300 Message-Id: <20220608102208.2967438-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608102208.2967438-1-dmitry.baryshkov@linaro.org> References: <20220608102208.2967438-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Split handling of MSI host IRQs to a separate dw_pcie_msi_host_init() function. The code is complex enough to warrant a separate function. Reviewed-by: Rob Herring Reviewed-by: Johan Hovold Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 100 ++++++++++-------- 1 file changed, 57 insertions(+), 43 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 96b6196f870b..85c1160792e1 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -289,6 +289,61 @@ static void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); } +static int dw_pcie_msi_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + struct platform_device *pdev = to_platform_device(dev); + int ret; + u32 ctrl, num_ctrls; + + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + for (ctrl = 0; ctrl < num_ctrls; ctrl++) + pp->irq_mask[ctrl] = ~0; + + if (!pp->msi_irq[0]) { + int irq = platform_get_irq_byname_optional(pdev, "msi"); + + if (irq < 0) { + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + } + pp->msi_irq[0] = irq; + } + + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + + ret = dw_pcie_allocate_domains(pp); + if (ret) + return ret; + + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { + if (pp->msi_irq[ctrl] > 0) + irq_set_chained_handler_and_data(pp->msi_irq[ctrl], + dw_chained_msi_isr, + pp); + } + + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); + if (ret) + dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); + + pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, + sizeof(pp->msi_msg), + DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC); + ret = dma_mapping_error(pci->dev, pp->msi_data); + if (ret) { + dev_err(pci->dev, "Failed to map MSI data\n"); + pp->msi_data = 0; + dw_pcie_free_msi(pp); + return ret; + } + + return 0; +} + int dw_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -366,50 +421,9 @@ int dw_pcie_host_init(struct pcie_port *pp) if (ret < 0) return ret; } else if (pp->has_msi_ctrl) { - u32 ctrl, num_ctrls; - - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - for (ctrl = 0; ctrl < num_ctrls; ctrl++) - pp->irq_mask[ctrl] = ~0; - - if (!pp->msi_irq[0]) { - int irq = platform_get_irq_byname_optional(pdev, "msi"); - - if (irq < 0) { - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - } - pp->msi_irq[0] = irq; - } - - pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; - - ret = dw_pcie_allocate_domains(pp); - if (ret) + ret = dw_pcie_msi_host_init(pp); + if (ret < 0) return ret; - - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { - if (pp->msi_irq[ctrl] > 0) - irq_set_chained_handler_and_data(pp->msi_irq[ctrl], - dw_chained_msi_isr, - pp); - } - - ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); - if (ret) - dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); - - pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, - sizeof(pp->msi_msg), - DMA_FROM_DEVICE, - DMA_ATTR_SKIP_CPU_SYNC); - ret = dma_mapping_error(pci->dev, pp->msi_data); - if (ret) { - dev_err(pci->dev, "Failed to map MSI data\n"); - pp->msi_data = 0; - goto err_free_msi; - } } } From patchwork Wed Jun 8 10:22:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 579901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01794CCA487 for ; Wed, 8 Jun 2022 10:30:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237190AbiFHKaj (ORCPT ); Wed, 8 Jun 2022 06:30:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238228AbiFHK36 (ORCPT ); Wed, 8 Jun 2022 06:29:58 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D5F3C9EDE for ; Wed, 8 Jun 2022 03:22:17 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id h23so32498835lfe.4 for ; Wed, 08 Jun 2022 03:22:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2by5Bt/vQS1TmQjI5mkgsiE5z/umI6jxynKNxO746d4=; b=PHXZX+uJzXSI2P0g9qdj0yl8r21DoGlyFIX+fPxSmmmP8lX6TenY95q3PC2GoBzSzm GYKb9Mf8lV4PTevXPA+KPmjn3XoFhNl9MI192oEqZurSf07DATQZjYkzc9wHAjeUejFC 1mZdLcbW2/NzI4mYPQ2RnzNQcme+iClMyiM0ihKVMpaNbOwYo+grZbULFb8SkqwKdHTE 7SgnsHoB29UBTzquF9p+8s1C84I/h2P7VBF4s9AV0ovPxY7s3czL3uZkI+YwpGs7/jN5 SkuoeuIiknz2aqv3gnjmCBKxaff8gvG4xPT2+Ku9B4O110jNCTHoRhFe7eOYN1lDAn1y pPiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2by5Bt/vQS1TmQjI5mkgsiE5z/umI6jxynKNxO746d4=; b=rVA6KTRg9e9ukF0W8/Gef3F3QWzW/hejFRQwqQQtt6dHZc+h2NjdiGcPnMg1O1KEjJ apULfTgwrYN+P0k3LfUFsZgx6Us9IieoSV6Pn+7OfDVMdTy2T5zAXU301fnu8rTHLm9M cqu2+1sxdJv1+1MJm+Ujw52SDoYimKPvQ5SPUoNbswz7JB5vzswyNSL0/PUZ09K+Wy7v AOcwDJSBCfcz3pVI2pbFAnuRU2ojJTTrILlti6hHWEcDeTc0X4p+5T7R6sFBbMwJiuQv t3nNyY+KZ9KIzT0ZRarMiUrGKYjCM/ie9PejqNDT2T1T4jQwyGtvU2t6kpmJ+rbe0vV5 OmGA== X-Gm-Message-State: AOAM532lE2SiMLSFxpVah0SFWMbnd37DTKTvv8iaCCsB/28rkmBJl073 CUnHtC+bWC6f+4ew6Owi/7iBrg== X-Google-Smtp-Source: ABdhPJwhtC3H5Wj5I+u/XLrk1Qz7bQ74NSxgJqoQjbuFMOax0L6gS7S8ndUbXXP9jZI2munGntDkaw== X-Received: by 2002:a05:6512:c04:b0:478:f837:d813 with SMTP id z4-20020a0565120c0400b00478f837d813mr22338524lfu.17.1654683735150; Wed, 08 Jun 2022 03:22:15 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v1-20020ac25601000000b00478fe3327aasm3642934lfd.217.2022.06.08.03.22.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 03:22:14 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Johan Hovold , Rob Herring , Johan Hovold Subject: [PATCH v14 4/7] PCI: dwc: Handle MSIs routed to multiple GIC interrupts Date: Wed, 8 Jun 2022 13:22:05 +0300 Message-Id: <20220608102208.2967438-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608102208.2967438-1-dmitry.baryshkov@linaro.org> References: <20220608102208.2967438-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On some of Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Implement support for such configurations by parsing "msi0" ... "msiN" interrupts and attaching them to the chained handler. Note, that if DT doesn't list an array of MSI interrupts and uses single "msi" IRQ, the driver will limit the amount of supported MSI vectors accordingly (to 32). Reviewed-by: Rob Herring Reviewed-by: Johan Hovold Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 63 +++++++++++++++++-- 1 file changed, 59 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 85c1160792e1..26b50948d6fc 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -289,6 +289,46 @@ static void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); } +static int dw_pcie_parse_split_msi_irq(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + struct platform_device *pdev = to_platform_device(dev); + int irq; + u32 ctrl, max_vectors; + + /* Parse as many IRQs as described in the devicetree. */ + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) { + char msi_name[] = "msiX"; + + msi_name[3] = '0' + ctrl; + irq = platform_get_irq_byname_optional(pdev, msi_name); + if (irq == -ENXIO) + break; + if (irq < 0) + return dev_err_probe(dev, irq, + "Failed to parse MSI IRQ '%s'\n", + msi_name); + + pp->msi_irq[ctrl] = irq; + } + + /* If there were no "msiN" IRQs at all, fallback to the standard "msi" IRQ. */ + if (ctrl == 0) + return -ENXIO; + + max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL; + if (pp->num_vectors > max_vectors) { + dev_warn(dev, "Exceeding number of MSI vectors, limiting to %u\n", + max_vectors); + pp->num_vectors = max_vectors; + } + if (!pp->num_vectors) + pp->num_vectors = max_vectors; + + return 0; +} + static int dw_pcie_msi_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -297,21 +337,32 @@ static int dw_pcie_msi_host_init(struct pcie_port *pp) int ret; u32 ctrl, num_ctrls; - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - for (ctrl = 0; ctrl < num_ctrls; ctrl++) + for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) pp->irq_mask[ctrl] = ~0; + if (!pp->msi_irq[0]) { + ret = dw_pcie_parse_split_msi_irq(pp); + if (ret < 0 && ret != -ENXIO) + return ret; + } + + if (!pp->num_vectors) + pp->num_vectors = MSI_DEF_NUM_VECTORS; + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + if (!pp->msi_irq[0]) { int irq = platform_get_irq_byname_optional(pdev, "msi"); if (irq < 0) { irq = platform_get_irq(pdev, 0); if (irq < 0) - return irq; + return dev_err_probe(dev, irq, "Failed to parse MSI irq\n"); } pp->msi_irq[0] = irq; } + dev_dbg(dev, "Using %d MSI vectors\n", pp->num_vectors); + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; ret = dw_pcie_allocate_domains(pp); @@ -409,7 +460,11 @@ int dw_pcie_host_init(struct pcie_port *pp) of_property_read_bool(np, "msi-parent") || of_property_read_bool(np, "msi-map")); - if (!pp->num_vectors) { + /* + * For the has_msi_ctrl case the default assignment is handled + * in the dw_pcie_msi_host_init(). + */ + if (!pp->has_msi_ctrl && !pp->num_vectors) { pp->num_vectors = MSI_DEF_NUM_VECTORS; } else if (pp->num_vectors > MAX_MSI_IRQS) { dev_err(dev, "Invalid number of vectors\n"); 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Wed, 08 Jun 2022 03:22:15 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v1-20020ac25601000000b00478fe3327aasm3642934lfd.217.2022.06.08.03.22.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 03:22:15 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Johan Hovold , Krzysztof Kozlowski , Rob Herring Subject: [PATCH v14 5/7] dt-bindings: PCI: qcom: Support additional MSI interrupts Date: Wed, 8 Jun 2022 13:22:06 +0300 Message-Id: <20220608102208.2967438-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608102208.2967438-1-dmitry.baryshkov@linaro.org> References: <20220608102208.2967438-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Document mapping of additional interrupts. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/pci/qcom,pcie.yaml | 53 +++++++++++++++++-- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 0b69b12b849e..fe8f9a62a665 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -43,11 +43,12 @@ properties: maxItems: 5 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 8 interrupt-names: - items: - - const: msi + minItems: 1 + maxItems: 8 # Common definitions for clocks, clock-names and reset. # Platform constraints are described later. @@ -623,6 +624,52 @@ allOf: - resets - reset-names + # On newer chipsets support either 1 or 8 msi interrupts + # On older chipsets it's always 1 msi interrupt + - if: + properties: + compatibles: + contains: + enum: + - qcom,pcie-msm8996 + - qcom,pcie-sc7280 + - qcom,pcie-sc8180x + - qcom,pcie-sdm845 + - qcom,pcie-sm8150 + - qcom,pcie-sm8250 + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + then: + oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + maxItems: 1 + items: + - const: msi + - properties: + interrupts: + minItems: 8 + interrupt-names: + minItems: 8 + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + unevaluatedProperties: false examples: