From patchwork Wed Jun 8 05:36:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579820 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp5803841max; Tue, 7 Jun 2022 22:40:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz5hQvFOlJGMrxapVYTCMRec0CMOmkoCz5hoL4ptTdLaetkq6HygFnBakRkJBxF7m7SuaXx X-Received: by 2002:ac8:5847:0:b0:304:bc38:f911 with SMTP id h7-20020ac85847000000b00304bc38f911mr26008279qth.515.1654666814897; Tue, 07 Jun 2022 22:40:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654666814; cv=none; d=google.com; s=arc-20160816; b=BPCJcHUpql0fBkzybD+HM2R+/FYTBfAOcJShkHp1JQQympHA0CK/7N9umoYPgjVJ7N HP/DxnDjwbEzAIQWAe2hSytfIqYBb+IsAgVb7aBOlMmdbkTp9UIPHdlpIdnyxX1NfvtZ mjNF/yR03c0YG/bpgaK2So6TravG2CEszJx7gpq8N5BmHxo5nzRKZHCyoNbbnBdLW5TX 8QFJOz5+6FehaZcLZeT2fzmlS0Uvjfojiv19mgWACHVYdR3IvteUukjuPE4ZRyXZn1zM LN+h7PRzlf+WdzXZqzWj4uwCnn2VPaKlazwZCgDwSOdKrvCL+vRFsAxv3emPEkBvHjWt EqJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gw3n5rkKreQm9gaPqnkkqV9cQuORrGSaBukz3VwVbu8=; b=dIkh7ufNb4ZUHhZE6aeaqL6tPDq8R2zbvMhpP1PxD3nN1oYqwyYsxAF7OjLWdCgfBA c7TuadJkLXZhzUTeQ4OdEE0D9fuA1OcDVu6TTpkko9TYzGJKX/Ev0jjlgEIKVz/5BBtj sAad5tKBz5LEeqopw8RQqvAmWfOvBPgHmDbZ6NFl96zgTy1i7X2+bIpDcRjq7x6z/RiV ZMDvW551cyG7qlU3EDuXN7O2xH/z8aU/tzNP/23j62LZdV535NOBP8AgWXvyg0XrS4Tq xILpLBtUHU++yrBSACxJgLMZHP2lYRGzRs+C/JABoPnjHc/J6nERKeibEYe9PdcKMF1X bqpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WcFrwDDJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p12-20020ad45f4c000000b004646c6546b0si11263573qvg.88.2022.06.07.22.40.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 07 Jun 2022 22:40:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WcFrwDDJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyoQQ-0000jn-Ah for patch@linaro.org; Wed, 08 Jun 2022 01:40:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35750) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyoNT-0000fh-G3 for qemu-devel@nongnu.org; Wed, 08 Jun 2022 01:37:11 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:44697) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyoNE-0004cu-4o for qemu-devel@nongnu.org; Wed, 08 Jun 2022 01:37:11 -0400 Received: by mail-pl1-x635.google.com with SMTP id h1so16679305plf.11 for ; Tue, 07 Jun 2022 22:36:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gw3n5rkKreQm9gaPqnkkqV9cQuORrGSaBukz3VwVbu8=; b=WcFrwDDJIv21OUvC2saeB5b0yar4Nkyr9unf9hGB9JGeTCuKFKQCRUvJ2uwOrQ12mT 0vzdtvKKmDAvK14OXHDuEYHtXwX7tAjbj3MEXCF/e64diYShKUejkqUlkro6ReCXmeIV uCDj7xGHo9CaE4ASnC69v/Ydc1FaFGDHTbpM+RSOvabLzwBPzQgIQZ0mwgKn6wMehA8X ck1EcPF1XHfztJTztuWSORiysB0nGVKopE8auu0yEoczPZL7caRWPxe2q1PwDgReKi87 JGsq0qKKLJL1ZipsUi15HHuugzT6CcFAcpbV19u8YA/G4jPP8C6TWDSpF/I9FOa8UieB iI0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gw3n5rkKreQm9gaPqnkkqV9cQuORrGSaBukz3VwVbu8=; b=7e8LSiD98H0qaJxVW0YATRR1VhcdsebsL0JpFsX+yNR7t9ZPvY681OEpaTP9v402jX u9njjWnpkuqB7rPr07fREEbDQVrr5v3asvgk/sQK6ps8TQFKY0PYmJ2bjnsrGc17iSuf V3BtTyDaShwuSszC7q+XXUr/gHw77nXLF/+NNpaA/DGvP+N0BL+bvrzq+vclATfWNLqy ncxOV0pr3BEhA8Awdx2eFO2VUPURNzrrq7Fg97me1896W8NvC1soMveYpwQUOKkxmUg0 2denDnc/lD44c58OnebmxzS9bXi6hCXhD8cp+Nza6BdUimVkDsrc4bVK8RI0uIxPsxoE w3aw== X-Gm-Message-State: AOAM530udv5ccWtJAknK2BtM+yWqOJgRd4w92yLLzoREQfDz0IpSJfsF +NlDHFdFk3OfR8nmf9I1E85UI2jykfUgag== X-Received: by 2002:a17:90a:fb93:b0:1e8:a809:af4d with SMTP id cp19-20020a17090afb9300b001e8a809af4dmr6627562pjb.7.1654666612413; Tue, 07 Jun 2022 22:36:52 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:c626:2f70:ac99:7c97]) by smtp.gmail.com with ESMTPSA id t6-20020a1709028c8600b001636c0b98a7sm13507703plo.226.2022.06.07.22.36.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 22:36:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: jcmvbkbc@gmail.com Subject: [PATCH v4 1/2] target/xtensa: Use an exception for semihosting Date: Tue, 7 Jun 2022 22:36:49 -0700 Message-Id: <20220608053650.811947-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220608053650.811947-1-richard.henderson@linaro.org> References: <20220608053650.811947-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Within do_interrupt, we hold the iothread lock, which is required for Chardev access for the console, and for the round trip for use_gdb_syscalls(). Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 2 ++ target/xtensa/helper.h | 3 --- target/xtensa/exc_helper.c | 4 ++++ target/xtensa/translate.c | 3 ++- target/xtensa/xtensa-semi.c | 3 +-- 5 files changed, 9 insertions(+), 6 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 579adcb769..ea66895e7f 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -260,6 +260,7 @@ enum { EXC_USER, EXC_DOUBLE, EXC_DEBUG, + EXC_SEMIHOST, EXC_MAX }; @@ -576,6 +577,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); +void xtensa_semihosting(CPUXtensaState *env); #endif void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h index ae938ceedb..531679cd86 100644 --- a/target/xtensa/helper.h +++ b/target/xtensa/helper.h @@ -11,9 +11,6 @@ DEF_HELPER_2(retw, void, env, i32) DEF_HELPER_3(window_check, noreturn, env, i32, i32) DEF_HELPER_1(restore_owb, void, env) DEF_HELPER_2(movsp, void, env, i32) -#ifndef CONFIG_USER_ONLY -DEF_HELPER_1(simcall, void, env) -#endif #ifndef CONFIG_USER_ONLY DEF_HELPER_3(waiti, void, env, i32, i32) diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index d4823a65cd..d54a518875 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -219,6 +219,10 @@ void xtensa_cpu_do_interrupt(CPUState *cs) } switch (cs->exception_index) { + case EXC_SEMIHOST: + xtensa_semihosting(env); + return; + case EXC_WINDOW_OVERFLOW4: case EXC_WINDOW_UNDERFLOW4: case EXC_WINDOW_OVERFLOW8: diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 70e11eeb45..b65c8b8428 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -2377,7 +2377,8 @@ static void translate_simcall(DisasContext *dc, const OpcodeArg arg[], { #ifndef CONFIG_USER_ONLY if (semihosting_enabled()) { - gen_helper_simcall(cpu_env); + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + gen_exception(dc, EXC_SEMIHOST); } #endif } diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c index fa21b7e11f..5375f106fc 100644 --- a/target/xtensa/xtensa-semi.c +++ b/target/xtensa/xtensa-semi.c @@ -28,7 +28,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "chardev/char-fe.h" -#include "exec/helper-proto.h" #include "semihosting/semihost.h" #include "qapi/error.h" #include "qemu/log.h" @@ -188,7 +187,7 @@ void xtensa_sim_open_console(Chardev *chr) sim_console = &console; } -void HELPER(simcall)(CPUXtensaState *env) +void xtensa_semihosting(CPUXtensaState *env) { CPUState *cs = env_cpu(env); uint32_t *regs = env->regs; From patchwork Wed Jun 8 05:36:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 579819 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp5803711max; Tue, 7 Jun 2022 22:40:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz7zv+VCsWATJtf4VybEjWVkpbKWrQjHvhwkdBCcex00jmT5wGLpr6+Edek+T62SLXuKg43 X-Received: by 2002:a05:620a:2699:b0:47d:753c:b8ff with SMTP id c25-20020a05620a269900b0047d753cb8ffmr22298869qkp.763.1654666802762; Tue, 07 Jun 2022 22:40:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654666802; cv=none; d=google.com; s=arc-20160816; b=anGFEEFfRdQLPvRlqdbUR7rWK0qmRT2olyrGW6JgX1skSgauD2gFxDOIafvJA5GRjo B7ZR+I6cMksmkmea0h9wkDXo7HT8hqJI0aWegfI2SxVWjKEWOLA2IQ9VsfzBBdBihzLB MwQ5spcm8NfbIpqJ9LXUmjMp7TwatR0dCIrAzW2m7mA9WqI6os60r0f+7tL55Zg9x/np 1KeNZ9JPRxkbKNyHfZ6cKGj6UJjYoxXExAReVFDVAS2d0yLqPQpHbxk+NrZtZuQaJtqq TL/BMvGKjYbK1VM4BHi2dAWN2oHGD+WHv9UoynjmyG7tAU4KWfwzsDva8BUewHs/HCxc b7kQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LN6FSFXMMMn2KSUZ3W1+m9vPiRjqdOJHE+nC89Sujy0=; b=On6vX3WAWZsX/lHilLW+nhnPjR9MG6q0oQZoEqQJw/wd6f4XcXt69XR9BzJeG/Mu1P 9JRCkxhlbQm6XftfTrW5rkDQ61yX0pNkndNLWPTO1qo6DLFpWZWk3N5VpDIUon9Xx/7c jUQhhYY4QLmx4RWWeuApa+qaNOgiOYbiRju9Li+0+fqCuEpueYpE/J3QLtcx9ieR93WL w1BWahZvOAwIQtXtA6YuMqV4pHP9Ak7kpTlNk/hmMOtjF9S6DeIupamdHlBGxvFbsMh9 t145Alqtcqj1jcdFeghtk25jZGScDnr+WodV7QTb9MAlVZKj5dWNrXmedAiceyz/itwj PRMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vKB3SuOl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ef1-20020a05620a808100b006a6c0ba5579si3793217qkb.310.2022.06.07.22.40.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 07 Jun 2022 22:40:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vKB3SuOl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59766 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyoQE-0000QV-7i for patch@linaro.org; Wed, 08 Jun 2022 01:40:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35732) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyoNH-0000Mx-K7 for qemu-devel@nongnu.org; Wed, 08 Jun 2022 01:36:59 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:40823) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyoNE-0004dD-52 for qemu-devel@nongnu.org; Wed, 08 Jun 2022 01:36:59 -0400 Received: by mail-pj1-x102e.google.com with SMTP id w13-20020a17090a780d00b001e8961b355dso5632016pjk.5 for ; Tue, 07 Jun 2022 22:36:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LN6FSFXMMMn2KSUZ3W1+m9vPiRjqdOJHE+nC89Sujy0=; b=vKB3SuOl4c/5xahRwSCI8f//YSd9j35mEMHF6Lbx5qyLKdCQqp5ijRqXmoVSBk/uvd GKoiOjU8/IF5Ye069GPN+IRxcs2Ng+HshZ5rWISPAm4wod52R9pa8PsfZ6Z7SwBmGZf5 4QNvsJiG9T+oQNd3g1nt6elOINGeip2MJasK87CDPCgSZeTkeFD9j2Rptjhgy04haZQi L1eMewCpT3c6jICG4HZfZP01e3npi0n7d8IQPy+OOsNtYm0wR4AvXr4TtrECTHQ1KCf5 MUsxBNWqzIZ6g5wVHRghVHoaOlh0AKo8OQ6eZ+2a7oEAOZYeQWp+Durc5sYu5CjX0JeV yZvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LN6FSFXMMMn2KSUZ3W1+m9vPiRjqdOJHE+nC89Sujy0=; b=b6JHkoTgHlbDpW7ZTgB9jnai+55cz5sUWh53g89lXJ/u6i92Wh4zAZNFpjwOzkw9Ee RN+Nb2FFL68ABy0hkTI9BW8yqqmwPlvlU+g6Ph4Xbd1LOBeKIs7S/aTRqmDD7xg2wHN+ hVzcrZwJwJcd90wY1YBWwWzGV7lrruIHkLmhaHQ8VTePfWkg569fasgxZbPydgcpHOdt osTNgXFZeUbSxjyP2UQZj9x9crxr5l4EWt5iOsUyINY4Xq81KTyodGZ0gbe+hUtCm/XO DKFyTmX32H4oALkEl3ahWX29MmoHDuzFzc460/9dOi/lT8IW1XDJsWfGPKcRxRtLyrTZ 67LQ== X-Gm-Message-State: AOAM533jjX3gWHOeBHdYAEoljh8337x1Ib7o6wUN5xCH4vdcc1q/GxT8 wNQd/IQccqnRqXIN3H/ayzubZ60y+zDoTA== X-Received: by 2002:a17:902:e88b:b0:166:3f77:eb76 with SMTP id w11-20020a170902e88b00b001663f77eb76mr31200656plg.11.1654666613242; Tue, 07 Jun 2022 22:36:53 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:c626:2f70:ac99:7c97]) by smtp.gmail.com with ESMTPSA id t6-20020a1709028c8600b001636c0b98a7sm13507703plo.226.2022.06.07.22.36.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 22:36:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: jcmvbkbc@gmail.com Subject: [PATCH v4 2/2] target/xtensa: Use semihosting/syscalls.h Date: Tue, 7 Jun 2022 22:36:50 -0700 Message-Id: <20220608053650.811947-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220608053650.811947-1-richard.henderson@linaro.org> References: <20220608053650.811947-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This separates guest file descriptors from host file descriptors, and utilizes shared infrastructure for integration with gdbstub. Remove the xtensa custom console handing and rely on the generic -semihosting-config handling of chardevs. Signed-off-by: Richard Henderson --- target/xtensa/cpu.h | 1 - hw/xtensa/sim.c | 3 - target/xtensa/xtensa-semi.c | 323 +++++++++++------------------------- 3 files changed, 97 insertions(+), 230 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index ea66895e7f..99ac3efd71 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -612,7 +612,6 @@ void xtensa_translate_init(void); void **xtensa_get_regfile_by_name(const char *name, int entries, int bits); void xtensa_breakpoint_handler(CPUState *cs); void xtensa_register_core(XtensaConfigList *node); -void xtensa_sim_open_console(Chardev *chr); void check_interrupts(CPUXtensaState *s); void xtensa_irq_init(CPUXtensaState *env); qemu_irq *xtensa_get_extints(CPUXtensaState *env); diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c index 946c71cb5b..5cca6a170e 100644 --- a/hw/xtensa/sim.c +++ b/hw/xtensa/sim.c @@ -87,9 +87,6 @@ XtensaCPU *xtensa_sim_common_init(MachineState *machine) xtensa_create_memory_regions(&sysram, "xtensa.sysram", get_system_memory()); } - if (serial_hd(0)) { - xtensa_sim_open_console(serial_hd(0)); - } return cpu; } diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c index 5375f106fc..7ef4be353e 100644 --- a/target/xtensa/xtensa-semi.c +++ b/target/xtensa/xtensa-semi.c @@ -27,8 +27,10 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "chardev/char-fe.h" +#include "exec/gdbstub.h" #include "semihosting/semihost.h" +#include "semihosting/syscalls.h" +#include "semihosting/softmmu-uaccess.h" #include "qapi/error.h" #include "qemu/log.h" @@ -92,99 +94,69 @@ enum { TARGET_ELOOP = 92, }; -static uint32_t errno_h2g(int host_errno) +static void xtensa_cb(CPUState *cs, uint64_t ret, int err) { - switch (host_errno) { - case 0: return 0; - case EPERM: return TARGET_EPERM; - case ENOENT: return TARGET_ENOENT; - case ESRCH: return TARGET_ESRCH; - case EINTR: return TARGET_EINTR; - case EIO: return TARGET_EIO; - case ENXIO: return TARGET_ENXIO; - case E2BIG: return TARGET_E2BIG; - case ENOEXEC: return TARGET_ENOEXEC; - case EBADF: return TARGET_EBADF; - case ECHILD: return TARGET_ECHILD; - case EAGAIN: return TARGET_EAGAIN; - case ENOMEM: return TARGET_ENOMEM; - case EACCES: return TARGET_EACCES; - case EFAULT: return TARGET_EFAULT; -#ifdef ENOTBLK - case ENOTBLK: return TARGET_ENOTBLK; -#endif - case EBUSY: return TARGET_EBUSY; - case EEXIST: return TARGET_EEXIST; - case EXDEV: return TARGET_EXDEV; - case ENODEV: return TARGET_ENODEV; - case ENOTDIR: return TARGET_ENOTDIR; - case EISDIR: return TARGET_EISDIR; - case EINVAL: return TARGET_EINVAL; - case ENFILE: return TARGET_ENFILE; - case EMFILE: return TARGET_EMFILE; - case ENOTTY: return TARGET_ENOTTY; -#ifdef ETXTBSY - case ETXTBSY: return TARGET_ETXTBSY; -#endif - case EFBIG: return TARGET_EFBIG; - case ENOSPC: return TARGET_ENOSPC; - case ESPIPE: return TARGET_ESPIPE; - case EROFS: return TARGET_EROFS; - case EMLINK: return TARGET_EMLINK; - case EPIPE: return TARGET_EPIPE; - case EDOM: return TARGET_EDOM; - case ERANGE: return TARGET_ERANGE; - case ENOSYS: return TARGET_ENOSYS; -#ifdef ELOOP - case ELOOP: return TARGET_ELOOP; -#endif - }; + CPUXtensaState *env = cs->env_ptr; - return TARGET_EINVAL; -} +#define E(N) case E##N: err = TARGET_E##N; break -typedef struct XtensaSimConsole { - CharBackend be; - struct { - char buffer[16]; - size_t offset; - } input; -} XtensaSimConsole; - -static XtensaSimConsole *sim_console; - -static IOCanReadHandler sim_console_can_read; -static int sim_console_can_read(void *opaque) -{ - XtensaSimConsole *p = opaque; - - return sizeof(p->input.buffer) - p->input.offset; -} - -static IOReadHandler sim_console_read; -static void sim_console_read(void *opaque, const uint8_t *buf, int size) -{ - XtensaSimConsole *p = opaque; - size_t copy = sizeof(p->input.buffer) - p->input.offset; - - if (size < copy) { - copy = size; + switch (err) { + case 0: + break; + E(PERM); + E(NOENT); + E(SRCH); + E(INTR); + E(IO); + E(NXIO); + E(2BIG); + E(NOEXEC); + E(BADF); + E(CHILD); + E(AGAIN); + E(NOMEM); + E(ACCES); + E(FAULT); + E(NOTBLK); + E(BUSY); + E(EXIST); + E(XDEV); + E(NODEV); + E(NOTDIR); + E(ISDIR); + E(INVAL); + E(NFILE); + E(MFILE); + E(NOTTY); + E(TXTBSY); + E(FBIG); + E(NOSPC); + E(SPIPE); + E(ROFS); + E(MLINK); + E(PIPE); + E(DOM); + E(RANGE); + E(NOSYS); + E(LOOP); + default: + err = TARGET_EINVAL; + break; } - memcpy(p->input.buffer + p->input.offset, buf, copy); - p->input.offset += copy; + + env->regs[3] = err; + env->regs[2] = ret; + +#undef E } -void xtensa_sim_open_console(Chardev *chr) +static void xtensa_select_cb(CPUState *cs, uint64_t ret, int err) { - static XtensaSimConsole console; - - qemu_chr_fe_init(&console.be, chr, &error_abort); - qemu_chr_fe_set_handlers(&console.be, - sim_console_can_read, - sim_console_read, - NULL, NULL, &console, - NULL, true); - sim_console = &console; + if (ret & G_IO_NVAL) { + xtensa_cb(cs, -1, EBADF); + } else { + xtensa_cb(cs, ret != 0, 0); + } } void xtensa_semihosting(CPUXtensaState *env) @@ -194,165 +166,64 @@ void xtensa_semihosting(CPUXtensaState *env) switch (regs[2]) { case TARGET_SYS_exit: + gdb_exit(regs[3]); exit(regs[3]); break; case TARGET_SYS_read: + semihost_sys_read(cs, xtensa_cb, regs[3], regs[4], regs[5]); + break; case TARGET_SYS_write: - { - bool is_write = regs[2] == TARGET_SYS_write; - uint32_t fd = regs[3]; - uint32_t vaddr = regs[4]; - uint32_t len = regs[5]; - uint32_t len_done = 0; - - while (len > 0) { - hwaddr paddr = cpu_get_phys_page_debug(cs, vaddr); - uint32_t page_left = - TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1)); - uint32_t io_sz = page_left < len ? page_left : len; - hwaddr sz = io_sz; - void *buf = cpu_physical_memory_map(paddr, &sz, !is_write); - uint32_t io_done; - bool error = false; - - if (buf) { - vaddr += io_sz; - len -= io_sz; - if (fd < 3 && sim_console) { - if (is_write && (fd == 1 || fd == 2)) { - io_done = qemu_chr_fe_write_all(&sim_console->be, - buf, io_sz); - regs[3] = errno_h2g(errno); - } else if (!is_write && fd == 0) { - if (sim_console->input.offset) { - io_done = sim_console->input.offset; - if (io_sz < io_done) { - io_done = io_sz; - } - memcpy(buf, sim_console->input.buffer, io_done); - memmove(sim_console->input.buffer, - sim_console->input.buffer + io_done, - sim_console->input.offset - io_done); - sim_console->input.offset -= io_done; - qemu_chr_fe_accept_input(&sim_console->be); - } else { - io_done = -1; - regs[3] = TARGET_EAGAIN; - } - } else { - qemu_log_mask(LOG_GUEST_ERROR, - "%s fd %d is not supported with chardev console\n", - is_write ? - "writing to" : "reading from", fd); - io_done = -1; - regs[3] = TARGET_EBADF; - } - } else { - io_done = is_write ? - write(fd, buf, io_sz) : - read(fd, buf, io_sz); - regs[3] = errno_h2g(errno); - } - if (io_done == -1) { - error = true; - io_done = 0; - } - cpu_physical_memory_unmap(buf, sz, !is_write, io_done); - } else { - error = true; - regs[3] = TARGET_EINVAL; - break; - } - if (error) { - if (!len_done) { - len_done = -1; - } - break; - } - len_done += io_done; - if (io_done < io_sz) { - break; - } - } - regs[2] = len_done; - } + semihost_sys_write(cs, xtensa_cb, regs[3], regs[4], regs[5]); break; - case TARGET_SYS_open: - { - char name[1024]; - int rc; - int i; - - for (i = 0; i < ARRAY_SIZE(name); ++i) { - rc = cpu_memory_rw_debug(cs, regs[3] + i, - (uint8_t *)name + i, 1, 0); - if (rc != 0 || name[i] == 0) { - break; - } - } - - if (rc == 0 && i < ARRAY_SIZE(name)) { - regs[2] = open(name, regs[4], regs[5]); - regs[3] = errno_h2g(errno); - } else { - regs[2] = -1; - regs[3] = TARGET_EINVAL; - } - } + semihost_sys_open(cs, xtensa_cb, regs[3], 0, regs[4], regs[5]); break; - case TARGET_SYS_close: - if (regs[3] < 3) { - regs[2] = regs[3] = 0; - } else { - regs[2] = close(regs[3]); - regs[3] = errno_h2g(errno); - } + semihost_sys_close(cs, xtensa_cb, regs[3]); break; - case TARGET_SYS_lseek: - regs[2] = lseek(regs[3], (off_t)(int32_t)regs[4], regs[5]); - regs[3] = errno_h2g(errno); + semihost_sys_lseek(cs, xtensa_cb, regs[3], regs[4], regs[5]); break; case TARGET_SYS_select_one: { - uint32_t fd = regs[3]; - uint32_t rq = regs[4]; - uint32_t target_tv = regs[5]; - uint32_t target_tvv[2]; + int timeout, events; - struct timeval tv = {0}; + if (regs[5]) { + uint32_t tv_sec, tv_usec; + uint64_t msec; - if (target_tv) { - cpu_memory_rw_debug(cs, target_tv, - (uint8_t *)target_tvv, sizeof(target_tvv), 0); - tv.tv_sec = (int32_t)tswap32(target_tvv[0]); - tv.tv_usec = (int32_t)tswap32(target_tvv[1]); - } - if (fd < 3 && sim_console) { - if ((fd == 1 || fd == 2) && rq == SELECT_ONE_WRITE) { - regs[2] = 1; - } else if (fd == 0 && rq == SELECT_ONE_READ) { - regs[2] = sim_console->input.offset > 0; - } else { - regs[2] = 0; + if (get_user_u32(tv_sec, regs[5]) || + get_user_u32(tv_usec, regs[5])) { + xtensa_cb(cs, -1, EFAULT); + return; } - regs[3] = 0; - } else { - fd_set fdset; - FD_ZERO(&fdset); - FD_SET(fd, &fdset); - regs[2] = select(fd + 1, - rq == SELECT_ONE_READ ? &fdset : NULL, - rq == SELECT_ONE_WRITE ? &fdset : NULL, - rq == SELECT_ONE_EXCEPT ? &fdset : NULL, - target_tv ? &tv : NULL); - regs[3] = errno_h2g(errno); + /* Poll timeout is in milliseconds; overflow to infinity. */ + msec = tv_sec * 1000ull + DIV_ROUND_UP(tv_usec, 1000ull); + timeout = msec <= INT32_MAX ? msec : -1; + } else { + timeout = -1; } + + switch (regs[4]) { + case SELECT_ONE_READ: + events = G_IO_IN; + break; + case SELECT_ONE_WRITE: + events = G_IO_OUT; + break; + case SELECT_ONE_EXCEPT: + events = G_IO_PRI; + break; + default: + xtensa_cb(cs, -1, EINVAL); + return; + } + + semihost_sys_poll_one(cs, xtensa_select_cb, + regs[3], events, timeout); } break;