From patchwork Tue Jun 7 06:47:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liang Yang X-Patchwork-Id: 579602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23756C43334 for ; Tue, 7 Jun 2022 06:47:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237220AbiFGGrk (ORCPT ); Tue, 7 Jun 2022 02:47:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237209AbiFGGrj (ORCPT ); Tue, 7 Jun 2022 02:47:39 -0400 Received: from mail-sz.amlogic.com (mail-sz.amlogic.com [211.162.65.117]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0A332B262; Mon, 6 Jun 2022 23:47:38 -0700 (PDT) Received: from droid11-sz.amlogic.com (10.28.8.21) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.2176.2; Tue, 7 Jun 2022 14:47:35 +0800 From: Liang Yang To: Miquel Raynal , CC: Liang Yang , Rob Herring , Rob Herring , Richard Weinberger , Vignesh Raghavendra , Jerome Brunet , Neil Armstrong , Martin Blumenstingl , Kevin Hilman , Jianxin Pan , Victor Wan , XianWei Zhao , Kelvin Zhang , BiChao Zheng , YongHui Yu , , , , Subject: [PATCH v6 1/5] dt-bindings: nand: meson: fix meson nfc clock Date: Tue, 7 Jun 2022 14:47:26 +0800 Message-ID: <20220607064731.13367-2-liang.yang@amlogic.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607064731.13367-1-liang.yang@amlogic.com> References: <20220607064731.13367-1-liang.yang@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.8.21] Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org EMMC and NAND have the same clock control register named 'SD_EMMC_CLOCK' which is defined in EMMC port internally. bit0~5 of 'SD_EMMC_CLOCK' is the divider and bit6~7 is the mux for fix pll and xtal. At the beginning, a common MMC and NAND sub-clock was discussed and planed to be implemented as NFC clock provider, but now this series of patches of a common MMC and NAND sub-clock are never being accepted and the current binding was never valid. the reasons for giving up are: 1. EMMC and NAND, which are mutually exclusive anyway 2. coupling the EMMC and NAND. 3. it seems that a common MMC and NAND sub-clock is over engineered. and let us see the link fot more information: https://lore.kernel.org/all/20220121074508.42168-5-liang.yang@amlogic.com so The meson nfc can't work now, let us rework the clock. Acked-by: Rob Herring Signed-off-by: Liang Yang --- .../bindings/mtd/amlogic,meson-nand.txt | 29 ++++++++----------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt index 5794ab1147c1..5d5cdfef417f 100644 --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt @@ -7,18 +7,19 @@ Required properties: - compatible : contains one of: - "amlogic,meson-gxl-nfc" - "amlogic,meson-axg-nfc" + +- reg : Offset and length of the register set + +- reg-names : "nfc" is the register set for NFC controller and "emmc" + is the register set for MCI controller. + - clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names. - clock-names: Should contain the following: "core" - NFC module gate clock - "device" - device clock from eMMC sub clock controller - "rx" - rx clock phase - "tx" - tx clock phase - -- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC - controller port C + "device" - parent clock for internal NFC Optional children nodes: Children nodes represent the available nand chips. @@ -28,24 +29,18 @@ see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindi Example demonstrate on AXG SoC: - sd_emmc_c_clkc: mmc@7000 { - compatible = "amlogic,meson-axg-mmc-clkc", "syscon"; - reg = <0x0 0x7000 0x0 0x800>; - }; - nand-controller@7800 { compatible = "amlogic,meson-axg-nfc"; - reg = <0x0 0x7800 0x0 0x100>; + reg = <0x0 0x7800 0x0 0x100>, + <0x0 0x7000 0x0 0x800>; + reg-names = "nfc", "emmc"; #address-cells = <1>; #size-cells = <0>; interrupts = ; clocks = <&clkc CLKID_SD_EMMC_C>, - <&sd_emmc_c_clkc CLKID_MMC_DIV>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>; - clock-names = "core", "device", "rx", "tx"; - amlogic,mmc-syscon = <&sd_emmc_c_clkc>; + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "device"; pinctrl-names = "default"; pinctrl-0 = <&nand_pins>;